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  1.  
  2.  
  3. static Bool rhdMapMMIO(RHDPtr rhdPtr)
  4. {
  5.      rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR];
  6.      rhdPtr->MMIOBase = MapIoMem((void*)rhdPtr->memBase[RHD_MMIO_BAR],
  7.                                  rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE);
  8.      if( rhdPtr->MMIOBase==0)
  9.         return 0;
  10.  
  11.      DBG(dbgprintf("Mapped IO at %x (size %x)\n", rhdPtr->MMIOBase, rhdPtr->MMIOMapSize));
  12.      return 1;
  13. }
  14.  
  15. /* Read MC register */
  16. unsigned INMC(RHDPtr info, int addr)
  17. {
  18.     u32_t       data;
  19.  
  20.     if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  21.        (info->ChipFamily == CHIP_FAMILY_RS740)) {
  22.        OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  23.        data = INREG(RS690_MC_DATA);
  24.     } else if (info->ChipFamily == CHIP_FAMILY_RS600) {
  25.        OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK));
  26.        data = INREG(RS600_MC_DATA);
  27.     } else if (IS_AVIVO_VARIANT) {
  28.        OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
  29.        (void)INREG(AVIVO_MC_INDEX);
  30.        data = INREG(AVIVO_MC_DATA);
  31.  
  32.        OUTREG(AVIVO_MC_INDEX, 0);
  33.        (void)INREG(AVIVO_MC_INDEX);
  34.     } else {
  35.        OUTREG(R300_MC_IND_INDEX, addr & 0x3f);
  36.        (void)INREG(R300_MC_IND_INDEX);
  37.        data = INREG(R300_MC_IND_DATA);
  38.  
  39.        OUTREG(R300_MC_IND_INDEX, 0);
  40.        (void)INREG(R300_MC_IND_INDEX);
  41.     }
  42.  
  43.     return data;
  44. }
  45.  
  46.  
  47. #define LOC_FB 0x1
  48. #define LOC_AGP 0x2
  49.  
  50. static void radeon_read_mc_fb_agp_location(RHDPtr info, int mask,
  51.                                 u32_t *fb_loc, u32_t *agp_loc, u32_t *agp_loc_hi)
  52. {
  53.  
  54.     if (info->ChipFamily >= CHIP_FAMILY_RV770) {
  55.        if (mask & LOC_FB)
  56.             *fb_loc = INREG(R700_MC_VM_FB_LOCATION);
  57.         if (mask & LOC_AGP) {
  58.             *agp_loc = INREG(R600_MC_VM_AGP_BOT);
  59.             *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
  60.         }
  61.     } else if (info->ChipFamily >= CHIP_FAMILY_R600) {
  62.         if (mask & LOC_FB)
  63.             *fb_loc = INREG(R600_MC_VM_FB_LOCATION);
  64.         if (mask & LOC_AGP) {
  65.             *agp_loc = INREG(R600_MC_VM_AGP_BOT);
  66.             *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
  67.         }
  68.     } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
  69.         if (mask & LOC_FB)
  70.         *fb_loc = INMC(info, RV515_MC_FB_LOCATION);
  71.         if (mask & LOC_AGP) {
  72.         *agp_loc = INMC(info, RV515_MC_AGP_LOCATION);
  73.             *agp_loc_hi = 0;
  74.         }
  75.     } else if (info->ChipFamily == CHIP_FAMILY_RS600) {
  76.         if (mask & LOC_FB)
  77.         *fb_loc = INMC(info, RS600_MC_FB_LOCATION);
  78.         if (mask & LOC_AGP) {
  79.             *agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION);
  80.             *agp_loc_hi = 0;
  81.         }
  82.     } else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  83.                (info->ChipFamily == CHIP_FAMILY_RS740)) {
  84.         if (mask & LOC_FB)
  85.         *fb_loc = INMC(info, RS690_MC_FB_LOCATION);
  86.         if (mask & LOC_AGP) {
  87.         *agp_loc = INMC(info, RS690_MC_AGP_LOCATION);
  88.             *agp_loc_hi = 0;
  89.         }
  90.     } else if (info->ChipFamily >= CHIP_FAMILY_R520) {
  91.         if (mask & LOC_FB)
  92.         *fb_loc = INMC(info, R520_MC_FB_LOCATION);
  93.         if (mask & LOC_AGP) {
  94.         *agp_loc = INMC(info, R520_MC_AGP_LOCATION);
  95.             *agp_loc_hi = 0;
  96.         }
  97.     } else {
  98.         if (mask & LOC_FB)
  99.             *fb_loc = INREG(RADEON_MC_FB_LOCATION);
  100.         if (mask & LOC_AGP)
  101.             *agp_loc = INREG(RADEON_MC_AGP_LOCATION);
  102.     }
  103. }
  104.  
  105. static void RADEONInitMemoryMap(RHDPtr info)
  106. {
  107.      u32_t       mem_size;
  108.      u32_t       aper_size;
  109.  
  110.      radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location,
  111.                     &info->mc_agp_location, &info->mc_agp_location_hi);
  112.  
  113.      /* We shouldn't use info->videoRam here which might have been clipped
  114.       * but the real video RAM instead
  115.       */
  116.      if (info->ChipFamily >= CHIP_FAMILY_R600){
  117.         mem_size = INREG(R600_CONFIG_MEMSIZE);
  118.         aper_size = INREG(R600_CONFIG_APER_SIZE);
  119.      }
  120.      else {
  121.         mem_size = INREG(RADEON_CONFIG_MEMSIZE);
  122.         aper_size = INREG(RADEON_CONFIG_APER_SIZE);
  123.      }
  124.  
  125.      if (mem_size == 0)
  126.         mem_size = 0x800000;
  127.  
  128.      /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
  129.         Novell bug 204882 + along with lots of ubuntu ones */
  130.      if (aper_size > mem_size)
  131.         mem_size = aper_size;
  132.  
  133.  
  134.      if ( (info->ChipFamily != CHIP_FAMILY_RS600) &&
  135.           (info->ChipFamily != CHIP_FAMILY_RS690) &&
  136.           (info->ChipFamily != CHIP_FAMILY_RS740)) {
  137.         if (info->IsIGP)
  138.            info->mc_fb_location = INREG(RADEON_NB_TOM);
  139.         else
  140.         {
  141.            u32_t aper0_base;
  142.  
  143.            if (info->ChipFamily >= CHIP_FAMILY_R600) {
  144.               aper0_base = INREG(R600_CONFIG_F0_BASE);
  145.            }
  146.            else {
  147.               aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
  148.            }
  149.  
  150.          /* Recent chips have an "issue" with the memory controller, the
  151.           * location must be aligned to the size. We just align it down,
  152.           * too bad if we walk over the top of system memory, we don't
  153.           * use DMA without a remapped anyway.
  154.           * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
  155.           */
  156.            if ( info->ChipFamily == CHIP_FAMILY_RV280 ||
  157.                 info->ChipFamily == CHIP_FAMILY_R300 ||
  158.                 info->ChipFamily == CHIP_FAMILY_R350 ||
  159.                 info->ChipFamily == CHIP_FAMILY_RV350 ||
  160.                 info->ChipFamily == CHIP_FAMILY_RV380 ||
  161.                 info->ChipFamily == CHIP_FAMILY_R420 ||
  162.                 info->ChipFamily == CHIP_FAMILY_RV410)
  163.               aper0_base &= ~(mem_size - 1);
  164.  
  165.            if ( info->ChipFamily >= CHIP_FAMILY_R600) {
  166.               info->mc_fb_location = (aper0_base >> 24) |
  167.               (((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
  168.               dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
  169.            }
  170.            else {
  171.               info->mc_fb_location = (aper0_base >> 16) |
  172.               ((aper0_base + mem_size - 1) & 0xffff0000U);
  173.            }
  174.         }
  175.      }
  176.      if (info->ChipFamily >= CHIP_FAMILY_R600) {
  177.         info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
  178.      }
  179.      else {
  180.         info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
  181.      }
  182.      /* Just disable the damn AGP apertures for now, it may be
  183.       * re-enabled later by the DRM
  184.       */
  185.  
  186.      if (IS_AVIVO_VARIANT) {
  187.         if (info->ChipFamily >= CHIP_FAMILY_R600) {
  188.            OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
  189.      }
  190.      else {
  191.         OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
  192.      }
  193.          info->mc_agp_location = 0x003f0000;
  194.      }
  195.      else
  196.          info->mc_agp_location = 0xffffffc0;
  197.  
  198.       dbgprintf("RADEONInitMemoryMap() : \n");
  199.       dbgprintf("  mem_size         : 0x%08x\n", (unsigned)mem_size);
  200.       dbgprintf("  MC_FB_LOCATION   : 0x%08x\n", (unsigned)info->mc_fb_location);
  201.       dbgprintf("  MC_AGP_LOCATION  : 0x%08x\n", (unsigned)info->mc_agp_location);
  202. }
  203.  
  204. static void RADEONGetVRamType(RHDPtr info)
  205. {
  206.      u32_t tmp;
  207.  
  208.      if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300))
  209.         info->IsDDR = TRUE;
  210.      else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
  211.         info->IsDDR = TRUE;
  212.      else
  213.         info->IsDDR = FALSE;
  214.  
  215.      if ( (info->ChipFamily >= CHIP_FAMILY_R600) &&
  216.           (info->ChipFamily <= CHIP_FAMILY_RV635))
  217.      {
  218.         int chansize;
  219.         /* r6xx */
  220.         tmp = INREG(R600_RAMCFG);
  221.         if (tmp & R600_CHANSIZE_OVERRIDE)
  222.             chansize = 16;
  223.         else if (tmp & R600_CHANSIZE)
  224.             chansize = 64;
  225.         else
  226.             chansize = 32;
  227.         if (info->ChipFamily == CHIP_FAMILY_R600)
  228.             info->RamWidth = 8 * chansize;
  229.         else if (info->ChipFamily == CHIP_FAMILY_RV670)
  230.             info->RamWidth = 4 * chansize;
  231.         else if ((info->ChipFamily == CHIP_FAMILY_RV610) ||
  232.              (info->ChipFamily == CHIP_FAMILY_RV620))
  233.             info->RamWidth = chansize;
  234.         else if ((info->ChipFamily == CHIP_FAMILY_RV630) ||
  235.              (info->ChipFamily == CHIP_FAMILY_RV635))
  236.             info->RamWidth = 2 * chansize;
  237.      }
  238.      else if (info->ChipFamily == CHIP_FAMILY_RV515) {
  239.      /* rv515/rv550 */
  240.         tmp = INMC(info, RV515_MC_CNTL);
  241.         tmp &= RV515_MEM_NUM_CHANNELS_MASK;
  242.         switch (tmp) {
  243.            case 0: info->RamWidth = 64; break;
  244.            case 1: info->RamWidth = 128; break;
  245.            default: info->RamWidth = 128; break;
  246.         }
  247.      }
  248.      else if ((info->ChipFamily >= CHIP_FAMILY_R520) &&
  249.               (info->ChipFamily <= CHIP_FAMILY_RV570)){
  250.      /* r520/rv530/rv560/rv570/r580 */
  251.         tmp = INMC(info, R520_MC_CNTL0);
  252.         switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
  253.            case 0: info->RamWidth = 32; break;
  254.            case 1: info->RamWidth = 64; break;
  255.            case 2: info->RamWidth = 128; break;
  256.            case 3: info->RamWidth = 256; break;
  257.            default: info->RamWidth = 64; break;
  258.         }
  259.         if (tmp & R520_MC_CHANNEL_SIZE) {
  260.            info->RamWidth *= 2;
  261.         }
  262.      }
  263.      else if ((info->ChipFamily >= CHIP_FAMILY_R300) &&
  264.               (info->ChipFamily <= CHIP_FAMILY_RV410)) {
  265.      /* r3xx, r4xx */
  266.         tmp = INREG(RADEON_MEM_CNTL);
  267.         tmp &= R300_MEM_NUM_CHANNELS_MASK;
  268.         switch (tmp) {
  269.            case 0: info->RamWidth = 64; break;
  270.            case 1: info->RamWidth = 128; break;
  271.            case 2: info->RamWidth = 256; break;
  272.            default: info->RamWidth = 128; break;
  273.         }
  274.      }
  275.      else if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
  276.               (info->ChipFamily == CHIP_FAMILY_RS100) ||
  277.               (info->ChipFamily == CHIP_FAMILY_RS200)){
  278.      tmp = INREG(RADEON_MEM_CNTL);
  279.      if (tmp & RV100_HALF_MODE)
  280.         info->RamWidth = 32;
  281.      else
  282.         info->RamWidth = 64;
  283.  
  284. ///    if (!info->HasCRTC2) {
  285. ///        info->RamWidth /= 4;
  286. ///        info->IsDDR = TRUE;
  287. ///    }
  288.      }
  289.      else if (info->ChipFamily <= CHIP_FAMILY_RV280) {
  290.         tmp = INREG(RADEON_MEM_CNTL);
  291.      if (tmp & RADEON_MEM_NUM_CHANNELS_MASK)
  292.         info->RamWidth = 128;
  293.      else
  294.         info->RamWidth = 64;
  295.      } else {
  296.      /* newer IGPs */
  297.         info->RamWidth = 128;
  298.      }
  299.  
  300.      /* This may not be correct, as some cards can have half of channel disabled
  301.       * ToDo: identify these cases
  302.       */
  303. }
  304.  
  305. /*
  306.  * Depending on card genertation, chipset bugs, etc... the amount of vram
  307.  * accessible to the CPU can vary. This function is our best shot at figuring
  308.  * it out. Returns a value in KB.
  309.  */
  310. static u32_t RADEONGetAccessibleVRAM(RHDPtr info)
  311. {
  312.     u32_t       aper_size;
  313.     unsigned char  byte;
  314.  
  315.     if (info->ChipFamily >= CHIP_FAMILY_R600)
  316.        aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
  317.     else
  318.        aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
  319.  
  320.  
  321.     /* Set HDP_APER_CNTL only on cards that are known not to be broken,
  322.      * that is has the 2nd generation multifunction PCI interface
  323.      */
  324.     if (info->ChipFamily == CHIP_FAMILY_RV280 ||
  325.         info->ChipFamily == CHIP_FAMILY_RV350 ||
  326.         info->ChipFamily == CHIP_FAMILY_RV380 ||
  327.         info->ChipFamily == CHIP_FAMILY_R420  ||
  328.         info->ChipFamily == CHIP_FAMILY_RV410 ||
  329.         IS_AVIVO_VARIANT) {
  330.         MASKREG (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
  331.                      ~RADEON_HDP_APER_CNTL);
  332.         dbgprintf("Generation 2 PCI interface, using max accessible memory\n");
  333.             return aper_size * 2;
  334.     }
  335.  
  336.     /* Older cards have all sorts of funny issues to deal with. First
  337.      * check if it's a multifunction card by reading the PCI config
  338.      * header type... Limit those to one aperture size
  339.      */
  340. //    PCI_READ_BYTE(info->PciInfo, &byte, 0xe);
  341. //    if (byte & 0x80) {
  342. //    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
  343. //           "Generation 1 PCI interface in multifunction mode"
  344. //           ", accessible memory limited to one aperture\n");
  345. //    return aper_size;
  346. //    }
  347.  
  348.     /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
  349.      * have set it up. We don't write this as it's broken on some ASICs but
  350.      * we expect the BIOS to have done the right thing (might be too optimistic...)
  351.      */
  352. //    if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
  353. //        return aper_size * 2;
  354.  
  355.     return aper_size;
  356. }
  357.  
  358.  
  359. static Bool RADEONPreInitVRAM(RHDPtr info)
  360. {
  361.      u32_t accessible, bar_size;
  362.  
  363.      if ((!IS_AVIVO_VARIANT) && info->IsIGP)
  364.      {
  365.         u32_t tom = INREG(RADEON_NB_TOM);
  366.  
  367.         info->videoRam = (((tom >> 16) -
  368.                  (tom & 0xffff) + 1) << 6);
  369.  
  370.         OUTREG(RADEON_CONFIG_MEMSIZE, info->videoRam * 1024);
  371.      }
  372.      else
  373.      {
  374.         if (info->ChipFamily >= CHIP_FAMILY_R600)
  375.            info->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
  376.         else
  377.         {
  378.          /* Read VRAM size from card */
  379.            info->videoRam      = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
  380.  
  381.          /* Some production boards of m6 will return 0 if it's 8 MB */
  382.            if (info->videoRam == 0)
  383.            {
  384.               info->videoRam = 8192;
  385.               OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000);
  386.            }
  387.         }
  388.      }
  389.  
  390.      RADEONGetVRamType(info);
  391.  
  392.      /* Get accessible memory */
  393.      accessible = RADEONGetAccessibleVRAM(info);
  394.  
  395.      /* Crop it to the size of the PCI BAR */
  396. //     bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024;
  397.  
  398.      bar_size = 1 << (info->memsize[RHD_FB_BAR] - 10);
  399.  
  400.      if (bar_size == 0)
  401.         bar_size = 0x20000;
  402.      if (accessible > bar_size)
  403.         accessible = bar_size;
  404.  
  405.      dbgprintf("Detected total video RAM=%dK width=%dbit,"
  406.                 "accessible=%uK (PCI BAR=%uK)\n",
  407.                 info->videoRam, info->RamWidth,
  408.                 (unsigned)accessible, (unsigned)bar_size);
  409.  
  410.      if (info->videoRam > accessible)
  411.         info->videoRam = accessible;
  412.  
  413.      if (!IS_AVIVO_VARIANT)
  414.         info->MemCntl            = INREG(RADEON_SDRAM_MODE_REG);
  415.         info->BusCntl            = INREG(RADEON_BUS_CNTL);
  416.  
  417.      info->videoRam  &= ~1023;
  418.      info->FbMapSize  = info->videoRam * 1024;
  419.  
  420.      /* if the card is PCI Express reserve the last 32k for the gart table */
  421.  
  422. //    if (info->cardType == CARD_PCIE )
  423.       /* work out the size of pcie aperture */
  424. //        info->FbSecureSize = RADEONDRIGetPciAperTableSize(info);
  425. //    else
  426. //    info->FbSecureSize = 0;
  427.  
  428.     return TRUE;
  429. }
  430.  
  431. /*
  432.  
  433. #define RADEON_NB_TOM             0x15c
  434.  
  435. static size_t rhdGetVideoRamSize(RHDPtr rhdPtr)
  436. {
  437.   size_t RamSize, BARSize;
  438.  
  439.   if (rhdPtr->ChipFamily == CHIP_FAMILY_RS690)
  440.     RamSize = (_RHDRegRead(rhdPtr, R5XX_CONFIG_MEMSIZE))>>10;
  441.   else
  442.     if (rhdPtr->IsIGP)
  443.     {
  444.       u32_t tom = _RHDRegRead(rhdPtr, RADEON_NB_TOM);
  445.       RamSize = (((tom >> 16) - (tom & 0xffff) + 1) << 6);
  446.       _RHDRegWrite(rhdPtr,R5XX_CONFIG_MEMSIZE, RamSize<<10);
  447.     }
  448.     else
  449.     {
  450.       if (rhdPtr->ChipFamily < CHIP_FAMILY_R600)
  451.       {
  452.         RamSize = (_RHDRegRead(rhdPtr, R5XX_CONFIG_MEMSIZE)) >> 10;
  453.         if(RamSize==0) RamSize=8192;
  454.       }
  455.       else
  456.         RamSize = (_RHDRegRead(rhdPtr, R6XX_CONFIG_MEMSIZE)) >> 10;
  457.     };
  458.  
  459.   BARSize = 1 << (rhdPtr->memsize[RHD_FB_BAR] - 10);
  460.   if(BARSize==0)
  461.     BARSize = 0x20000;
  462.  
  463.   if (RamSize > BARSize) {
  464.     DBG(dbgprintf("The detected amount of videoram"
  465.            " exceeds the PCI BAR aperture.\n"));
  466.     DBG(dbgprintf("Using only %dkB of the total "
  467.            "%dkB.\n", (int) BARSize, (int) RamSize));
  468.     return BARSize;
  469.   }
  470.   else return RamSize;
  471. }
  472. */
  473.  
  474. #if 0
  475. static Bool
  476. rhdMapFB(RHDPtr rhdPtr)
  477. {
  478.   rhdPtr->FbMapSize = 1 << rhdPtr->memsize[RHD_FB_BAR];
  479.   rhdPtr->PhisBase = rhdPtr->memBase[RHD_FB_BAR];
  480.  
  481.  // rhdPtr->FbBase = MapIoMem(rhdPtr->PhisBase, rhdPtr->FbMapSize,PG_SW+PG_NOCACHE);
  482.  
  483.  //  if (!rhdPtr->FbBase)
  484.  //   return FALSE;
  485.  
  486.     /* These devices have an internal address reference, which some other
  487.      * address registers in there also use. This can be different from the
  488.      * address in the BAR */
  489.   if (rhdPtr->ChipFamily < CHIP_FAMILY_R600)
  490.     rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, HDP_FB_LOCATION)<< 16;
  491.   else
  492.     rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, R6XX_CONFIG_FB_BASE);
  493.  
  494. //    rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, 0x6110);
  495. //    dbgprintf("rhdPtr->FbIntAddress %x\n",rhdPtr->FbIntAddress);
  496.  
  497.   if (rhdPtr->FbIntAddress != rhdPtr->PhisBase)
  498.     dbgprintf("PCI FB Address (BAR) is at "
  499.               "0x%08X while card Internal Address is 0x%08X\n",
  500.               (unsigned int) rhdPtr->PhisBase,rhdPtr->FbIntAddress);
  501.  // dbgprintf("Mapped FB at %p (size 0x%08X)\n",rhdPtr->FbBase, rhdPtr->FbMapSize);
  502.   return TRUE;
  503. }
  504. #endif
  505.  
  506. static Bool RADEONPreInitChipType(RHDPtr rhdPtr)
  507. {
  508.      u32_t cmd_stat;
  509.  
  510.      rhdPtr->ChipErrata = 0;
  511.  
  512.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) &&
  513.           ((_RHDRegRead(rhdPtr,RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
  514.            == RADEON_CFG_ATI_REV_A11))
  515.         rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG;
  516.  
  517.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) ||
  518.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
  519.         rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS;
  520.  
  521.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) ||
  522.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
  523.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
  524.         rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY;
  525.  
  526.      rhdPtr->cardType = CARD_PCI;
  527.  
  528.  
  529.      cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG);
  530.  
  531.      if (cmd_stat & RADEON_CAP_LIST)
  532.      {
  533.         u32_t cap_ptr, cap_id;
  534.  
  535.         cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG);
  536.         cap_ptr &= RADEON_CAP_PTR_MASK;
  537.  
  538.         while(cap_ptr != RADEON_CAP_ID_NULL)
  539.         {
  540.            cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr);
  541.            if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
  542.               rhdPtr->cardType = CARD_AGP;
  543.               break;
  544.            }
  545.            if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) {
  546.               rhdPtr->cardType = CARD_PCIE;
  547.               break;
  548.            }
  549.            cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
  550.         }
  551.      }
  552.  
  553.      dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" :
  554.                (rhdPtr->cardType==CARD_PCIE) ? "PCIE" : "AGP");
  555.  
  556.     /* treat PCIE IGP cards as PCI  */
  557.      if (rhdPtr->cardType == CARD_PCIE && rhdPtr->IsIGP)
  558.          rhdPtr->cardType = CARD_PCI;
  559.  
  560.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
  561.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ||
  562.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS300) ||
  563.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS400) ||
  564.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS480) ||
  565.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS600) ||
  566.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS690) ||
  567.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS740))
  568.         rhdPtr->has_tcl = FALSE;
  569.      else {
  570.         rhdPtr->has_tcl = TRUE;
  571.      }
  572.  
  573.      rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR];
  574.  
  575.      return TRUE;
  576. }
  577.  
  578. Bool RHDPreInit()
  579. {
  580.     /* We need access to IO space already */
  581.      if ( !rhdMapMMIO(&rhd) ) {
  582.         dbgprintf("Failed to map MMIO.\n");
  583.         return FALSE;
  584.      };
  585.  
  586.  
  587.      if( !RADEONPreInitChipType(&rhd))
  588.         return FALSE;
  589.  
  590.      if (!RADEONPreInitVRAM(&rhd))
  591.         return FALSE;
  592.  
  593.      RADEONInitMemoryMap(&rhd);
  594.  
  595.      if (!rhd.videoRam)
  596.      {
  597.         dbgprintf("No Video RAM detected.\n");
  598.         goto error1;
  599.      }
  600.      dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam);
  601.  
  602.      rhd.FbFreeStart = 0;
  603.      rhd.FbFreeSize = rhd.videoRam << 10;
  604.  
  605.  // if( !rhdMapFB(&rhd))
  606. //    return FALSE;
  607.  
  608. //  rhd.FbScanoutStart = 0;
  609. //  rhd.FbScanoutSize  = 8*1024*1024;
  610.  
  611.   rhd.FbFreeStart    = 10*1024*1024;
  612.   rhd.FbFreeSize     = rhd.FbMapSize - rhd.FbFreeStart;
  613.  
  614.   rhdInitHeap(&rhd);
  615.   return TRUE;
  616.  
  617. error1:
  618.   return FALSE;
  619. };
  620.  
  621.  
  622.  
  623.