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  1. ; Vendor ids
  2. INTEL_VID      =   0x8086
  3. SIS_VID        =   0x1039
  4. NVIDIA_VID     =   0x10DE
  5. AMD_VID        =   0x1022
  6.  
  7. ; Device ids
  8. ICH_DID        =   0x2415
  9. ICH0_DID       =   0x2425
  10. ICH2_DID       =   0x2445
  11. ICH3_DID       =   0x2485
  12. ICH4_DID       =   0x24C5
  13. ICH5_DID       =   0x24D5
  14. MX440_DID      =   0x7195
  15. SI7012_DID     =   0x7012
  16. NFORCE_DID     =   0x01B1
  17. NFORCE2_DID    =   0x006A
  18. AMD8111_DID    =   0x764D
  19. AMD768_DID     =   0x7445
  20.  
  21. NAMBAR_REG     =   0x10            ; native audio mixer BAR
  22.  NAM_SIZE      =   256             ; 256 bytes required.
  23.  
  24. NABMBAR_REG    =   0x14            ; native audio bus mastering BAR
  25.  NABM_SIZE     =   64              ; 64 bytes
  26.  
  27. IRQ_REG        =   0x3c            ; IRQ holder for PCI
  28. INT_REG        =   0x3d            ; INT pin
  29. ICH4_CFG_REG   =   0x41            ; ICH4 config register
  30.  
  31.  
  32. ; BUS master registers, accessed via NABMBAR+offset
  33.  
  34. ; ICH supports 3 different types of register sets for three types of things
  35. ; it can do, thus:
  36. ;
  37. ; PCM in (for recording) aka PI
  38. ; PCM out (for playback) aka PO
  39. ; MIC in (for recording) aka MC
  40.  
  41. PI_BDBAR_REG            =     0       ; PCM in buffer descriptor BAR
  42. PO_BDBAR_REG            =     10h     ; PCM out buffer descriptor BAR
  43. MC_BDBAR_REG            =     20h     ; MIC in buffer descriptor BAR
  44.  
  45. ; each buffer descriptor BAR holds a pointer which has entries to the buffer
  46. ; contents of the .WAV file we're going to play.  Each entry is 8 bytes long
  47. ; (more on that later) and can contain 32 entries total, so each BAR is
  48. ; 256 bytes in length, thus:
  49.  
  50. BDL_SIZE                =     32*8    ; Buffer Descriptor List size
  51. INDEX_MASK              =     31      ; indexes must be 0-31
  52.  
  53.  
  54.  
  55. PI_CIV_REG              =     4       ; PCM in current Index value (RO)
  56. PO_CIV_REG              =     14h     ; PCM out current Index value (RO)
  57. MC_CIV_REG              =     24h     ; MIC in current Index value (RO)
  58.  
  59. ;8bit read only
  60. ; each current index value is simply a pointer showing us which buffer
  61. ; (0-31) the codec is currently processing.  Once this counter hits 31, it
  62. ; wraps back to 0.
  63. ; this can be handy to know, as once it hits 31, we're almost out of data to
  64. ; play back or room to record!
  65.  
  66.  
  67. PI_LVI_REG              =     5       ; PCM in Last Valid Index
  68. PO_LVI_REG              =     15h     ; PCM out Last Valid Index
  69. MC_LVI_REG              =     25h     ; MIC in Last Valid Index
  70. ;8bit read/write
  71. ; The Last Valid Index is a number (0-31) to let the codec know what buffer
  72. ; number to stop on after processing.  It could be very nasty to play audio
  73. ; from buffers that aren't filled with the audio we want to play.
  74.  
  75.  
  76. PI_SR_REG               =     6       ; PCM in Status register
  77. PO_SR_REG               =     16h     ; PCM out Status register
  78. MC_SR_REG               =     26h     ; MIC in Status register
  79. ;16bit read/write
  80. ; status registers.  Bitfields follow:
  81.  
  82. FIFO_ERR                =     BIT4    ; FIFO Over/Underrun W1TC.
  83.  
  84. BCIS                    =     BIT3    ; buffer completion interrupt status.
  85.                                         ; Set whenever the last sample in ANY
  86.                                         ; buffer is finished.  Bit is only
  87.                                         ; set when the Interrupt on Complete
  88.                                         ; (BIT4 of control reg) is set.
  89.  
  90. LVBCI                   =     BIT2    ; Set whenever the codec has processed
  91.                                         ; the last buffer in the buffer list.
  92.                                         ; Will fire an interrupt if IOC bit is
  93.                                         ; set. Probably set after the last
  94.                                         ; sample in the last buffer is
  95.                                         ; processed.  W1TC
  96.  
  97.  
  98. CELV                    =     BIT1    ; Current buffer == last valid.
  99.                                         ; Bit is RO and remains set until LVI is
  100.                                         ; cleared.  Probably set up the start
  101.                                         ; of processing for the last buffer.
  102.  
  103.  
  104. DCH                     =     BIT0    ; DMA controller halted.
  105.                                         ; set whenever audio stream is stopped
  106.                                         ; or something else goes wrong.
  107.  
  108.  
  109. PI_PICB_REG             =     8       ; PCM in position in current buffer(RO)
  110. PO_PICB_REG             =     18h     ; PCM out position in current buffer(RO)
  111. MC_PICB_REG             =     28h     ; MIC in position in current buffer (RO)
  112. ;16bit read only
  113. ; position in current buffer regs show the number of dwords left to be
  114. ; processed in the current buffer.
  115. ;
  116.  
  117.  
  118.  
  119.  
  120.  
  121. PI_PIV_REG              =     0ah     ; PCM in Prefected index value
  122. PO_PIV_REG              =     1ah     ; PCM out Prefected index value
  123. MC_PIV_REG              =     2ah     ; MIC in Prefected index value
  124. ;8bit, read only
  125. ; Prefetched index value register.
  126. ; tells which buffer number (0-31) has be prefetched.  I'd imagine this
  127. ; value follows the current index value fairly closely. (CIV+1)
  128. ;
  129.  
  130.  
  131. PI_CR_REG               =     0bh     ; PCM in Control Register
  132. PO_CR_REG               =     1bh     ; PCM out Control Register
  133. MC_CR_REG               =     2bh     ; MIC in Control Register
  134. ; 8bit
  135. ; Control register *MUST* only be accessed as an 8bit value.
  136. ; Control register.  See bitfields below.
  137. ;
  138.  
  139.  
  140. IOCE                    =     BIT4    ; interrupt on complete enable.
  141.                                         ; set this bit if you want an intrtpt
  142.                                         ; to fire whenever LVBCI is set.
  143. FEIFE                   =     BIT3    ; set if you want an interrupt to fire
  144.                                         ; whenever there is a FIFO (over or
  145.                                         ; under) error.
  146. LVBIE                   =     BIT2    ; last valid buffer interrupt enable.
  147.                                         ; set if you want an interrupt to fire
  148.                                         ; whenever the completion of the last
  149.                                         ; valid buffer.
  150. RR                      =     BIT1    ; reset registers.  Nukes all regs
  151.                                         ; except bits 4:2 of this register.
  152.                                         ; Only set this bit if BIT 0 is 0
  153. RPBM                    =     BIT0    ; Run/Pause
  154.                                         ; set this bit to start the codec!
  155.  
  156.  
  157. GLOB_CNT_REG            =     2ch     ; Global control register
  158. SEC_RES_EN              =     BIT5    ; secondary codec resume event
  159.                                         ; interrupt enable.  Not used here.
  160. PRI_RES_EN              =     BIT4    ; ditto for primary. Not used here.
  161. ACLINK_OFF              =     BIT3    ; Turn off the AC97 link
  162. ACWARM_RESET            =     BIT2    ; Awaken the AC97 link from sleep.
  163.                                         ; registers preserved, bit self clears
  164. ACCOLD_RESET            =     BIT1    ; Reset everything in the AC97 and
  165.                                         ; reset all registers.  Not self clearin
  166. ;g
  167.  
  168. GPIIE                   =     BIT0    ; GPI Interrupt enable.
  169.                                         ; set if you want an interrupt to
  170.                                         ; fire upon ANY of the bits in the
  171.                                         ; GPI (general pursose inputs?) not used
  172. ;.
  173.  
  174. GLOB_STS_REG            =     30h     ; Global Status register (RO)
  175.  
  176. MD3                     =     BIT17   ; modem powerdown status (yawn)
  177. AD3                     =     BIT16   ; Audio powerdown status (yawn)
  178. RD_COMPLETE_STS         =     BIT15   ; Codec read timed out. 0=normal
  179. BIT3SLOT12              =     BIT14   ; shadowed status of bit 3 in slot 12
  180. BIT2SLOT12              =     BIT13   ; shadowed status of bit 2 in slot 12
  181. BIT1SLOT12              =     BIT12   ; shadowed status of bit 1 in slot 12
  182. SEC_RESUME_STS          =     BIT11   ; secondary codec has resumed (and irqed)
  183. PRI_RESUME_STS          =     BIT10   ; primary codec has resumed (and irqed)
  184. SEC_CODEC_RDY           =     BIT9    ; secondary codec is ready for action
  185. PRI_CODEC_RDY           =     BIT8    ; Primary codec is ready for action
  186.                                         ; software must check these bits before
  187.                                         ; starting the codec!
  188. MIC_IN_IRQ              =     BIT7    ; MIC in caused an interrupt
  189. PCM_OUT_IRQ             =     BIT6    ; One of the PCM out channels IRQed
  190. PCM_IN_IRQ              =     BIT5    ; One of the PCM in channels IRQed
  191. MODEM_OUT_IRQ           =     BIT2    ; modem out channel IRQed
  192. MODEM_IN_IRQ            =     BIT1    ; modem in channel IRQed
  193. GPI_STS_CHANGE          =     BIT0    ; set whenever GPI's have changed.
  194.                                         ; BIT0 of slot 12 also reflects this.
  195.  
  196.  
  197. ACC_SEMA_REG            =     34h     ; Codec write semiphore register
  198. CODEC_BUSY              =     BIT0    ; codec register I/O is happening
  199.                                         ; self clearing
  200.  
  201.  
  202.  
  203. ;
  204. ; Buffer Descriptors List
  205. ; As stated earlier, each buffer descriptor list is a set of (up to) 32
  206. ; descriptors, each 8 bytes in length.  Bytes 0-3 of a descriptor entry point
  207. ; to a chunk of memory to either play from or record to.  Bytes 4-7 of an
  208. ; entry describe various control things detailed below.
  209. ;
  210. ; Buffer pointers must always be aligned on a Dword boundry.
  211. ;
  212. ;
  213.  
  214. IOC                     =     BIT31   ; Fire an interrupt whenever this
  215.                                         ; buffer is complete.
  216.  
  217. BUP                     =     BIT30   ; Buffer Underrun Policy.
  218.                                         ; if this buffer is the last buffer
  219.                                         ; in a playback, fill the remaining
  220.                                         ; samples with 0 (silence) or not.
  221.                                         ; It's a good idea to set this to 1
  222.                                         ; for the last buffer in playback,
  223.                                         ; otherwise you're likely to get a lot
  224.                                         ; of noise at the end of the sound.
  225.  
  226. ;
  227. ; Bits 15:0 contain the length of the buffer, in number of samples, which
  228. ; are 16 bits each, coupled in left and right pairs, or 32bits each.
  229. ; Luckily for us, that's the same format as .wav files.
  230. ;
  231. ; A value of FFFF is 65536 samples.  Running at 44.1Khz, that's just about
  232. ; 1.5 seconds of sample time.  FFFF * 32bits is 1FFFFh bytes or 128k of data.
  233. ;
  234. ; A value of 0 in these bits means play no samples.
  235. ;
  236.  
  237.  
  238. ;*****************************************************************************
  239. ;* AC97 Codec registers include (based on Jeff Leyda AC97 wav player SDK :-)
  240. ;*****************************************************************************
  241.  
  242. ; Not all codecs are created =al. Refer to the spec for your specific codec.
  243. ; All registers are 16bits wide.  Access to codec registers over the AC97 link
  244. ; is defined by the OEM.
  245. ; Secondary codec's are accessed by ORing in BIT7 of all register accesses.
  246.  
  247.  
  248. ; each codec/mixer register is 16bits
  249.  
  250. CODEC_RESET_REG                 =     00      ; reset codec
  251. CODEC_MASTER_VOL_REG            =     02      ; master volume
  252. CODEC_HP_VOL_REG                =     04      ; headphone volume
  253. CODEC_MASTER_MONO_VOL_REG       =     06      ; master mono volume
  254. CODEC_MASTER_TONE_REG           =     08      ; master tone (R+L)
  255. CODEC_PCBEEP_VOL_REG            =     0ah     ; PC beep volume
  256. CODEC_PHONE_VOL_REG             =     0ch     ; phone volume
  257. CODEC_MIC_VOL_REG               =     0eh     ; MIC volume
  258. CODEC_LINE_IN_VOL_REG           =     10h     ; line input volume
  259. CODEC_CD_VOL_REG                =     12h     ; CD volume
  260. CODEC_VID_VOL_REG               =     14h     ; video volume
  261. CODEC_AUX_VOL_REG               =     16h     ; aux volume
  262. CODEC_PCM_OUT_REG               =     18h     ; PCM output volume
  263. CODEC_RECORD_SELECT_REG         =     1ah     ; record select input
  264. CODEC_RECORD_VOL_REG            =     1ch     ; record volume
  265. CODEC_RECORD_MIC_VOL_REG        =     1eh     ; record mic volume
  266. CODEC_GP_REG                    =     20h     ; general purpose
  267. CODEC_3D_CONTROL_REG            =     22h     ; 3D control
  268. ; 24h is reserved
  269. CODEC_POWER_CTRL_REG            =     26h     ; powerdown control
  270. CODEC_EXT_AUDIO_REG             =     28h     ; extended audio
  271. CODEC_EXT_AUDIO_CTRL_REG        =     2ah     ; extended audio control
  272. CODEC_PCM_FRONT_DACRATE_REG     =     2ch     ; PCM out sample rate
  273. CODEC_PCM_SURND_DACRATE_REG     =     2eh     ; surround sound sample rate
  274. CODEC_PCM_LFE_DACRATE_REG       =     30h     ; LFE sample rate
  275. CODEC_LR_ADCRATE_REG            =     32h     ; PCM in sample rate
  276. CODEC_MIC_ADCRATE_REG           =     34h     ; mic in sample rate
  277.  
  278.  
  279. ; registers 36-7a are reserved on the ICH
  280.  
  281. CODEC_VENDORID1_REG             =     7ch     ; codec vendor ID 1
  282. CODEC_VENDORID2_REG             =     7eh     ; codec vendor ID 2
  283.  
  284.  
  285. ; When 2 codecs are present in the system, use BIT7 to access the 2nd
  286. ; set of registers, ie 80h-feh
  287.  
  288. SECONDARY_CODEC                 =     BIT7    ; 80-8f registers for 2nda