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  1. /*
  2.  * Copyright 2006-2007 Advanced Micro Devices, Inc.  
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice shall be included in
  12.  * all copies or substantial portions of the Software.
  13.  *
  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20.  * OTHER DEALINGS IN THE SOFTWARE.
  21.  */
  22.  
  23.  
  24. /****************************************************************************/ 
  25. /*Portion I: Definitions  shared between VBIOS and Driver                   */
  26. /****************************************************************************/
  27.  
  28.  
  29. #ifndef _ATOMBIOS_H
  30. #define _ATOMBIOS_H
  31.  
  32. #define ATOM_VERSION_MAJOR                   0x00020000
  33. #define ATOM_VERSION_MINOR                   0x00000002
  34.  
  35. #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
  36.  
  37.  
  38. #ifdef _H2INC
  39.   #ifndef ULONG
  40.     typedef unsigned long ULONG;
  41.   #endif
  42.  
  43.   #ifndef UCHAR
  44.     typedef unsigned char UCHAR;
  45.   #endif
  46.  
  47.   #ifndef USHORT
  48.     typedef unsigned short USHORT;
  49.   #endif
  50. #endif
  51.      
  52. #define ATOM_DAC_A            0
  53. #define ATOM_DAC_B            1
  54. #define ATOM_EXT_DAC          2
  55.  
  56. #define ATOM_CRTC1            0
  57. #define ATOM_CRTC2            1
  58.  
  59. #define ATOM_DIGA             0
  60. #define ATOM_DIGB             1
  61.  
  62. #define ATOM_PPLL1            0
  63. #define ATOM_PPLL2            1
  64.  
  65. #define ATOM_SCALER1          0
  66. #define ATOM_SCALER2          1
  67.  
  68. #define ATOM_SCALER_DISABLE   0  
  69. #define ATOM_SCALER_CENTER    1  
  70. #define ATOM_SCALER_EXPANSION 2  
  71. #define ATOM_SCALER_MULTI_EX  3  
  72.  
  73. #define ATOM_DISABLE          0
  74. #define ATOM_ENABLE           1
  75. #define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)
  76. #define ATOM_LCD_BLON                           (ATOM_ENABLE+2)
  77. #define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)
  78. #define ATOM_LCD_SELFTEST_START                                                                 (ATOM_DISABLE+5)
  79. #define ATOM_LCD_SELFTEST_STOP                                                                  (ATOM_ENABLE+5)
  80. #define ATOM_ENCODER_INIT                                         (ATOM_DISABLE+7)
  81.  
  82. #define ATOM_BLANKING         1
  83. #define ATOM_BLANKING_OFF     0
  84.  
  85. #define ATOM_CURSOR1          0
  86. #define ATOM_CURSOR2          1
  87.  
  88. #define ATOM_ICON1            0
  89. #define ATOM_ICON2            1
  90.  
  91. #define ATOM_CRT1             0
  92. #define ATOM_CRT2             1
  93.  
  94. #define ATOM_TV_NTSC          1
  95. #define ATOM_TV_NTSCJ         2
  96. #define ATOM_TV_PAL           3
  97. #define ATOM_TV_PALM          4
  98. #define ATOM_TV_PALCN         5
  99. #define ATOM_TV_PALN          6
  100. #define ATOM_TV_PAL60         7
  101. #define ATOM_TV_SECAM         8
  102. #define ATOM_TV_CV            16
  103.  
  104. #define ATOM_DAC1_PS2         1
  105. #define ATOM_DAC1_CV          2
  106. #define ATOM_DAC1_NTSC        3
  107. #define ATOM_DAC1_PAL         4
  108.  
  109. #define ATOM_DAC2_PS2         ATOM_DAC1_PS2
  110. #define ATOM_DAC2_CV          ATOM_DAC1_CV
  111. #define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC
  112. #define ATOM_DAC2_PAL         ATOM_DAC1_PAL
  113.  
  114. #define ATOM_PM_ON            0
  115. #define ATOM_PM_STANDBY       1
  116. #define ATOM_PM_SUSPEND       2
  117. #define ATOM_PM_OFF           3
  118.  
  119. /* Bit0:{=0:single, =1:dual},
  120.    Bit1 {=0:666RGB, =1:888RGB},
  121.    Bit2:3:{Grey level}
  122.    Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
  123.  
  124. #define ATOM_PANEL_MISC_DUAL               0x00000001
  125. #define ATOM_PANEL_MISC_888RGB             0x00000002
  126. #define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C
  127. #define ATOM_PANEL_MISC_FPDI               0x00000010
  128. #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
  129. #define ATOM_PANEL_MISC_SPATIAL            0x00000020
  130. #define ATOM_PANEL_MISC_TEMPORAL           0x00000040
  131. #define ATOM_PANEL_MISC_API_ENABLED        0x00000080
  132.  
  133.  
  134. #define MEMTYPE_DDR1              "DDR1"
  135. #define MEMTYPE_DDR2              "DDR2"
  136. #define MEMTYPE_DDR3              "DDR3"
  137. #define MEMTYPE_DDR4              "DDR4"
  138.  
  139. #define ASIC_BUS_TYPE_PCI         "PCI"
  140. #define ASIC_BUS_TYPE_AGP         "AGP"
  141. #define ASIC_BUS_TYPE_PCIE        "PCI_EXPRESS"
  142.  
  143. /* Maximum size of that FireGL flag string */
  144.  
  145. #define ATOM_FIREGL_FLAG_STRING     "FGL"             //Flag used to enable FireGL Support
  146. #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING  3        //sizeof( ATOM_FIREGL_FLAG_STRING )
  147.  
  148. #define ATOM_FAKE_DESKTOP_STRING    "DSK"             //Flag used to enable mobile ASIC on Desktop
  149. #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING  ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
  150.  
  151. #define ATOM_M54T_FLAG_STRING       "M54T"            //Flag used to enable M54T Support
  152. #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING    4        //sizeof( ATOM_M54T_FLAG_STRING )
  153.  
  154. #define HW_ASSISTED_I2C_STATUS_FAILURE          2
  155. #define HW_ASSISTED_I2C_STATUS_SUCCESS          1
  156.  
  157. #pragma pack(1)                                       /* BIOS data must use byte aligment */
  158.  
  159. /*  Define offset to location of ROM header. */
  160.  
  161. #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER            0x00000048L
  162. #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE                               0x00000002L
  163.  
  164. #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE    0x94
  165. #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE   20    /* including the terminator 0x0! */
  166. #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER           0x002f
  167. #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START            0x006e
  168.  
  169. /* Common header for all ROM Data tables.
  170.   Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header.
  171.   And the pointer actually points to this header. */
  172.  
  173. typedef struct _ATOM_COMMON_TABLE_HEADER
  174. {
  175.   USHORT usStructureSize;
  176.   UCHAR  ucTableFormatRevision;   /*Change it when the Parser is not backward compatible */
  177.   UCHAR  ucTableContentRevision;  /*Change it only when the table needs to change but the firmware */
  178.                                   /*Image can't be updated, while Driver needs to carry the new table! */
  179. }ATOM_COMMON_TABLE_HEADER;
  180.  
  181. typedef struct _ATOM_ROM_HEADER
  182. {
  183.   ATOM_COMMON_TABLE_HEADER              sHeader;
  184.   UCHAR  uaFirmWareSignature[4];    /*Signature to distinguish between Atombios and non-atombios,
  185.                                       atombios should init it as "ATOM", don't change the position */
  186.   USHORT usBiosRuntimeSegmentAddress;
  187.   USHORT usProtectedModeInfoOffset;
  188.   USHORT usConfigFilenameOffset;
  189.   USHORT usCRC_BlockOffset;
  190.   USHORT usBIOS_BootupMessageOffset;
  191.   USHORT usInt10Offset;
  192.   USHORT usPciBusDevInitCode;
  193.   USHORT usIoBaseAddress;
  194.   USHORT usSubsystemVendorID;
  195.   USHORT usSubsystemID;
  196.   USHORT usPCI_InfoOffset;
  197.   USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
  198.   USHORT usMasterDataTableOffset;   /*Offset for SW to get all data table offsets, Don't change the position */
  199.   UCHAR  ucExtendedFunctionCode;
  200.   UCHAR  ucReserved;
  201. }ATOM_ROM_HEADER;
  202.  
  203. /*==============================Command Table Portion==================================== */
  204.  
  205. #ifdef  UEFI_BUILD
  206.         #define UTEMP   USHORT
  207.         #define USHORT  void*
  208. #endif
  209.  
  210. /****************************************************************************/ 
  211. // Structures used in Command.mtb
  212. /****************************************************************************/ 
  213. typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
  214.   USHORT ASIC_Init;                              //Function Table, used by various SW components,latest version 1.1
  215.   USHORT GetDisplaySurfaceSize;                  //Atomic Table,  Used by Bios when enabling HW ICON
  216.   USHORT ASIC_RegistersInit;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
  217.   USHORT VRAM_BlockVenderDetection;              //Atomic Table,  used only by Bios
  218.   USHORT DIGxEncoderControl;                                                                             //Only used by Bios
  219.   USHORT MemoryControllerInit;                   //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
  220.   USHORT EnableCRTCMemReq;                       //Function Table,directly used by various SW components,latest version 2.1
  221.   USHORT MemoryParamAdjust;                                                                              //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed
  222.   USHORT DVOEncoderControl;                      //Function Table,directly used by various SW components,latest version 1.2
  223.   USHORT GPIOPinControl;                                                                                                 //Atomic Table,  only used by Bios
  224.   USHORT SetEngineClock;                         //Function Table,directly used by various SW components,latest version 1.1
  225.   USHORT SetMemoryClock;                         //Function Table,directly used by various SW components,latest version 1.1
  226.   USHORT SetPixelClock;                          //Function Table,directly used by various SW components,latest version 1.2  
  227.   USHORT DynamicClockGating;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
  228.   USHORT ResetMemoryDLL;                         //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
  229.   USHORT ResetMemoryDevice;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
  230.   USHORT MemoryPLLInit;
  231.   USHORT AdjustDisplayPll;                                                                                              //only used by Bios
  232.   USHORT AdjustMemoryController;                 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock                
  233.   USHORT EnableASIC_StaticPwrMgt;                //Atomic Table,  only used by Bios
  234.   USHORT ASIC_StaticPwrMgtStatusChange;          //Obsolete ,     only used by Bios  
  235.   USHORT DAC_LoadDetection;                      //Atomic Table,  directly used by various SW components,latest version 1.2  
  236.   USHORT LVTMAEncoderControl;                    //Atomic Table,directly used by various SW components,latest version 1.3
  237.   USHORT LCD1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
  238.   USHORT DAC1EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1  
  239.   USHORT DAC2EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
  240.   USHORT DVOOutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1
  241.   USHORT CV1OutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1
  242.   USHORT GetConditionalGoldenSetting;            //only used by Bios
  243.   USHORT TVEncoderControl;                       //Function Table,directly used by various SW components,latest version 1.1
  244.   USHORT TMDSAEncoderControl;                    //Atomic Table,  directly used by various SW components,latest version 1.3
  245.   USHORT LVDSEncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.3
  246.   USHORT TV1OutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1
  247.   USHORT EnableScaler;                           //Atomic Table,  used only by Bios
  248.   USHORT BlankCRTC;                              //Atomic Table,  directly used by various SW components,latest version 1.1
  249.   USHORT EnableCRTC;                             //Atomic Table,  directly used by various SW components,latest version 1.1
  250.   USHORT GetPixelClock;                          //Atomic Table,  directly used by various SW components,latest version 1.1
  251.   USHORT EnableVGA_Render;                       //Function Table,directly used by various SW components,latest version 1.1
  252.   USHORT EnableVGA_Access;                       //Obsolete ,     only used by Bios
  253.   USHORT SetCRTC_Timing;                         //Atomic Table,  directly used by various SW components,latest version 1.1
  254.   USHORT SetCRTC_OverScan;                       //Atomic Table,  used by various SW components,latest version 1.1
  255.   USHORT SetCRTC_Replication;                    //Atomic Table,  used only by Bios
  256.   USHORT SelectCRTC_Source;                      //Atomic Table,  directly used by various SW components,latest version 1.1
  257.   USHORT EnableGraphSurfaces;                    //Atomic Table,  used only by Bios
  258.   USHORT UpdateCRTC_DoubleBufferRegisters;
  259.   USHORT LUT_AutoFill;                           //Atomic Table,  only used by Bios
  260.   USHORT EnableHW_IconCursor;                    //Atomic Table,  only used by Bios
  261.   USHORT GetMemoryClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
  262.   USHORT GetEngineClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
  263.   USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
  264.   USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
  265.   USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
  266.   USHORT VRAM_BlockDetectionByStrap;             //Atomic Table,  used only by Bios
  267.   USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios    
  268.   USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
  269.   USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components
  270.   USHORT ReadHWAssistedI2CStatus;                //Atomic Table,  indirectly used by various SW components
  271.   USHORT SpeedFanControl;                        //Function Table,indirectly used by various SW components,called from ASIC_Init
  272.   USHORT PowerConnectorDetection;                //Atomic Table,  directly used by various SW components,latest version 1.1
  273.   USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
  274.   USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
  275.   USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
  276.   USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
  277.   USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
  278.   USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
  279.   USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
  280.   USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
  281.   USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
  282.   USHORT DAC1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
  283.   USHORT DAC2OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
  284.   USHORT SetupHWAssistedI2CStatus;               //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
  285.   USHORT ClockSource;                            //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
  286.   USHORT MemoryDeviceInit;                       //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
  287.   USHORT EnableYUV;                              //Atomic Table,  indirectly used by various SW components,called from EnableVGARender
  288.   USHORT DIG1EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
  289.   USHORT DIG2EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
  290.   USHORT DIG1TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
  291.   USHORT DIG2TransmitterControl;                       //Atomic Table,directly used by various SW components,latest version 1.1
  292.   USHORT ProcessAuxChannelTransaction;                                   //Function Table,only used by Bios
  293.   USHORT DPEncoderService;                                                                                       //Function Table,only used by Bios
  294. }ATOM_MASTER_LIST_OF_COMMAND_TABLES;  
  295.  
  296. // For backward compatible
  297. #define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
  298. #define UNIPHYTransmitterControl                                                     DIG1TransmitterControl
  299. #define LVTMATransmitterControl                                                      DIG2TransmitterControl
  300. #define SetCRTC_DPM_State                        GetConditionalGoldenSetting
  301. #define SetUniphyInstance                        ASIC_StaticPwrMgtStatusChange
  302.  
  303. typedef struct _ATOM_MASTER_COMMAND_TABLE
  304. {
  305.   ATOM_COMMON_TABLE_HEADER           sHeader;
  306.   ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
  307. }ATOM_MASTER_COMMAND_TABLE;
  308.  
  309. /****************************************************************************/ 
  310. // Structures used in every command table
  311. /****************************************************************************/ 
  312. typedef struct _ATOM_TABLE_ATTRIBUTE
  313. {
  314.   USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword),
  315.   USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword),
  316.   USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
  317. }ATOM_TABLE_ATTRIBUTE;
  318.  
  319. /****************************************************************************/ 
  320. // Common header for all command tables.
  321. // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
  322. // And the pointer actually points to this header.
  323. /****************************************************************************/ 
  324. typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
  325. {
  326.   ATOM_COMMON_TABLE_HEADER CommonHeader;
  327.   ATOM_TABLE_ATTRIBUTE     TableAttribute;     
  328. }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
  329.  
  330.  
  331. /****************************************************************************/ 
  332. // Structures used by ComputeMemoryEnginePLLTable
  333. /****************************************************************************/ 
  334.  
  335. #define COMPUTE_MEMORY_PLL_PARAM        1
  336. #define COMPUTE_ENGINE_PLL_PARAM        2
  337.  
  338. typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
  339. {
  340.   ULONG   ulClock;        //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
  341.   UCHAR   ucAction;       //0:reserved //1:Memory //2:Engine  
  342.   UCHAR   ucReserved;     //may expand to return larger Fbdiv later
  343.   UCHAR   ucFbDiv;        //return value
  344.   UCHAR   ucPostDiv;      //return value
  345. }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
  346.  
  347. typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
  348. {
  349.   ULONG   ulClock;        //When return, [23:0] return real clock
  350.   UCHAR   ucAction;       //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
  351.   USHORT  usFbDiv;                  //return Feedback value to be written to register
  352.   UCHAR   ucPostDiv;      //return post div to be written to register
  353. }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
  354. #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
  355.  
  356.  
  357. #define SET_CLOCK_FREQ_MASK                     0x00FFFFFF  //Clock change tables only take bit [23:0] as the requested clock value
  358. #define USE_NON_BUS_CLOCK_MASK                  0x01000000  //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
  359. #define USE_MEMORY_SELF_REFRESH_MASK            0x02000000      //Only applicable to memory clock change, when set, using memory self refresh during clock transition
  360. #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04000000  //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
  361. #define FIRST_TIME_CHANGE_CLOCK                                                                 0x08000000      //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
  362. #define SKIP_SW_PROGRAM_PLL                                                                                     0x10000000      //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
  363. #define USE_SS_ENABLED_PIXEL_CLOCK  USE_NON_BUS_CLOCK_MASK
  364.  
  365. #define b3USE_NON_BUS_CLOCK_MASK                  0x01       //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
  366. #define b3USE_MEMORY_SELF_REFRESH                 0x02       //Only applicable to memory clock change, when set, using memory self refresh during clock transition
  367. #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04       //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
  368. #define b3FIRST_TIME_CHANGE_CLOCK                                                                       0x08       //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
  369. #define b3SKIP_SW_PROGRAM_PLL                                                                                   0x10                     //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
  370.  
  371. typedef struct _ATOM_COMPUTE_CLOCK_FREQ
  372. {
  373.   ULONG ulClockFreq:24;                       // in unit of 10kHz
  374.   ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
  375. }ATOM_COMPUTE_CLOCK_FREQ;
  376.  
  377. typedef struct _ATOM_S_MPLL_FB_DIVIDER
  378. {
  379.   USHORT usFbDivFrac;  
  380.   USHORT usFbDiv;  
  381. }ATOM_S_MPLL_FB_DIVIDER;
  382.  
  383. typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
  384. {
  385.   union
  386.   {
  387.     ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
  388.     ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
  389.   };
  390.   UCHAR   ucRefDiv;                           //Output Parameter      
  391.   UCHAR   ucPostDiv;                          //Output Parameter      
  392.   UCHAR   ucCntlFlag;                         //Output Parameter      
  393.   UCHAR   ucReserved;
  394. }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
  395.  
  396. // ucCntlFlag
  397. #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN          1
  398. #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE            2
  399. #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE         4
  400.  
  401. typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
  402. {
  403.   ATOM_COMPUTE_CLOCK_FREQ ulClock;
  404.   ULONG ulReserved[2];
  405. }DYNAMICE_MEMORY_SETTINGS_PARAMETER;
  406.  
  407. typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
  408. {
  409.   ATOM_COMPUTE_CLOCK_FREQ ulClock;
  410.   ULONG ulMemoryClock;
  411.   ULONG ulReserved;
  412. }DYNAMICE_ENGINE_SETTINGS_PARAMETER;
  413.  
  414. /****************************************************************************/ 
  415. // Structures used by SetEngineClockTable
  416. /****************************************************************************/ 
  417. typedef struct _SET_ENGINE_CLOCK_PARAMETERS
  418. {
  419.   ULONG ulTargetEngineClock;          //In 10Khz unit
  420. }SET_ENGINE_CLOCK_PARAMETERS;
  421.  
  422. typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
  423. {
  424.   ULONG ulTargetEngineClock;          //In 10Khz unit
  425.   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
  426. }SET_ENGINE_CLOCK_PS_ALLOCATION;
  427.  
  428. /****************************************************************************/ 
  429. // Structures used by SetMemoryClockTable
  430. /****************************************************************************/ 
  431. typedef struct _SET_MEMORY_CLOCK_PARAMETERS
  432. {
  433.   ULONG ulTargetMemoryClock;          //In 10Khz unit
  434. }SET_MEMORY_CLOCK_PARAMETERS;
  435.  
  436. typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
  437. {
  438.   ULONG ulTargetMemoryClock;          //In 10Khz unit
  439.   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
  440. }SET_MEMORY_CLOCK_PS_ALLOCATION;
  441.  
  442. /****************************************************************************/ 
  443. // Structures used by ASIC_Init.ctb
  444. /****************************************************************************/ 
  445. typedef struct _ASIC_INIT_PARAMETERS
  446. {
  447.   ULONG ulDefaultEngineClock;         //In 10Khz unit
  448.   ULONG ulDefaultMemoryClock;         //In 10Khz unit
  449. }ASIC_INIT_PARAMETERS;
  450.  
  451. typedef struct _ASIC_INIT_PS_ALLOCATION
  452. {
  453.   ASIC_INIT_PARAMETERS sASICInitClocks;
  454.   SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
  455. }ASIC_INIT_PS_ALLOCATION;
  456.  
  457. /****************************************************************************/ 
  458. // Structure used by DynamicClockGatingTable.ctb
  459. /****************************************************************************/ 
  460. typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
  461. {
  462.   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
  463.   UCHAR ucPadding[3];
  464. }DYNAMIC_CLOCK_GATING_PARAMETERS;
  465. #define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS
  466.  
  467. /****************************************************************************/ 
  468. // Structure used by EnableASIC_StaticPwrMgtTable.ctb
  469. /****************************************************************************/ 
  470. typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
  471. {
  472.   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
  473.   UCHAR ucPadding[3];
  474. }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
  475. #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
  476.  
  477. /****************************************************************************/ 
  478. // Structures used by DAC_LoadDetectionTable.ctb
  479. /****************************************************************************/ 
  480. typedef struct _DAC_LOAD_DETECTION_PARAMETERS
  481. {
  482.   USHORT usDeviceID;                  //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
  483.   UCHAR  ucDacType;                   //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
  484.   UCHAR  ucMisc;                                                                                        //Valid only when table revision =1.3 and above
  485. }DAC_LOAD_DETECTION_PARAMETERS;
  486.  
  487. // DAC_LOAD_DETECTION_PARAMETERS.ucMisc
  488. #define DAC_LOAD_MISC_YPrPb                                             0x01
  489.  
  490. typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
  491. {
  492.   DAC_LOAD_DETECTION_PARAMETERS            sDacload;
  493.   ULONG                                    Reserved[2];// Don't set this one, allocation for EXT DAC
  494. }DAC_LOAD_DETECTION_PS_ALLOCATION;
  495.  
  496. /****************************************************************************/ 
  497. // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
  498. /****************************************************************************/ 
  499. typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
  500. {
  501.   USHORT usPixelClock;                // in 10KHz; for bios convenient
  502.   UCHAR  ucDacStandard;               // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
  503.   UCHAR  ucAction;                    // 0: turn off encoder
  504.                                       // 1: setup and turn on encoder
  505.                                       // 7: ATOM_ENCODER_INIT Initialize DAC
  506. }DAC_ENCODER_CONTROL_PARAMETERS;
  507.  
  508. #define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS
  509.  
  510. /****************************************************************************/ 
  511. // Structures used by DIG1EncoderControlTable
  512. //                    DIG2EncoderControlTable
  513. //                    ExternalEncoderControlTable
  514. /****************************************************************************/ 
  515. typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
  516. {
  517.   USHORT usPixelClock;          // in 10KHz; for bios convenient
  518.   UCHAR  ucConfig;               
  519.                             // [2] Link Select:
  520.                             // =0: PHY linkA if bfLane<3
  521.                             // =1: PHY linkB if bfLanes<3
  522.                             // =0: PHY linkA+B if bfLanes=3
  523.                             // [3] Transmitter Sel
  524.                             // =0: UNIPHY or PCIEPHY
  525.                             // =1: LVTMA                                       
  526.   UCHAR ucAction;           // =0: turn off encoder                                    
  527.                             // =1: turn on encoder                     
  528.   UCHAR ucEncoderMode;
  529.                             // =0: DP   encoder      
  530.                             // =1: LVDS encoder          
  531.                             // =2: DVI  encoder  
  532.                             // =3: HDMI encoder
  533.                             // =4: SDVO encoder
  534.   UCHAR ucLaneNum;          // how many lanes to enable
  535.   UCHAR ucReserved[2];
  536. }DIG_ENCODER_CONTROL_PARAMETERS;
  537. #define DIG_ENCODER_CONTROL_PS_ALLOCATION                         DIG_ENCODER_CONTROL_PARAMETERS
  538. #define EXTERNAL_ENCODER_CONTROL_PARAMETER                      DIG_ENCODER_CONTROL_PARAMETERS
  539.  
  540. //ucConfig
  541. #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK                             0x01
  542. #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ          0x00
  543. #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ          0x01
  544. #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK                                 0x04
  545. #define ATOM_ENCODER_CONFIG_LINKA                                                                 0x00
  546. #define ATOM_ENCODER_CONFIG_LINKB                                                                 0x04
  547. #define ATOM_ENCODER_CONFIG_LINKA_B                                                       ATOM_TRANSMITTER_CONFIG_LINKA
  548. #define ATOM_ENCODER_CONFIG_LINKB_A                                                       ATOM_ENCODER_CONFIG_LINKB
  549. #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK        0x08
  550. #define ATOM_ENCODER_CONFIG_UNIPHY                                                        0x00
  551. #define ATOM_ENCODER_CONFIG_LVTMA                                                                 0x08
  552. #define ATOM_ENCODER_CONFIG_TRANSMITTER1                                  0x00
  553. #define ATOM_ENCODER_CONFIG_TRANSMITTER2                                  0x08
  554. #define ATOM_ENCODER_CONFIG_DIGB                                                                  0x80                  // VBIOS Internal use, outside SW should set this bit=0
  555. // ucAction
  556. // ATOM_ENABLE:  Enable Encoder
  557. // ATOM_DISABLE: Disable Encoder
  558.  
  559. //ucEncoderMode
  560. #define ATOM_ENCODER_MODE_DP                                                                                    0
  561. #define ATOM_ENCODER_MODE_LVDS                                                                          1
  562. #define ATOM_ENCODER_MODE_DVI                                                                                   2
  563. #define ATOM_ENCODER_MODE_HDMI                                                                          3
  564. #define ATOM_ENCODER_MODE_SDVO                                                                          4
  565. #define ATOM_ENCODER_MODE_TV                                                                                    13
  566. #define ATOM_ENCODER_MODE_CV                                                                                    14
  567. #define ATOM_ENCODER_MODE_CRT                                                                                   15
  568.  
  569. typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
  570. {
  571.     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
  572.     UCHAR ucReserved:1;
  573.     UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
  574.     UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
  575.     UCHAR ucReserved1:2;
  576. }ATOM_DIG_ENCODER_CONFIG_V2;
  577.  
  578.  
  579. typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
  580. {
  581.   USHORT usPixelClock;      // in 10KHz; for bios convenient
  582.   ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
  583.   UCHAR ucAction;                                      
  584.   UCHAR ucEncoderMode;
  585.                             // =0: DP   encoder      
  586.                             // =1: LVDS encoder          
  587.                             // =2: DVI  encoder  
  588.                             // =3: HDMI encoder
  589.                             // =4: SDVO encoder
  590.   UCHAR ucLaneNum;          // how many lanes to enable
  591.   UCHAR ucReserved[2];
  592. }DIG_ENCODER_CONTROL_PARAMETERS_V2;
  593.  
  594. //ucConfig
  595. #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK                          0x01
  596. #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ                 0x00
  597. #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ                 0x01
  598. #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK                              0x04
  599. #define ATOM_ENCODER_CONFIG_V2_LINKA                                                              0x00
  600. #define ATOM_ENCODER_CONFIG_V2_LINKB                                                              0x04
  601. #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK       0x18
  602. #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1                                 0x00
  603. #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2                                 0x08
  604. #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3                                 0x10
  605.  
  606. /****************************************************************************/ 
  607. // Structures used by UNIPHYTransmitterControlTable
  608. //                    LVTMATransmitterControlTable
  609. //                    DVOOutputControlTable
  610. /****************************************************************************/ 
  611. typedef struct _ATOM_DP_VS_MODE
  612. {
  613.   UCHAR ucLaneSel;
  614.   UCHAR ucLaneSet;
  615. }ATOM_DP_VS_MODE;
  616.  
  617. typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
  618. {
  619.         union
  620.         {
  621.   USHORT usPixelClock;          // in 10KHz; for bios convenient
  622.         USHORT usInitInfo;                      // when init uniphy,lower 8bit is used for connector type defined in objectid.h
  623.   ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
  624.         };
  625.   UCHAR ucConfig;
  626.                                                                                                         // [0]=0: 4 lane Link,      
  627.                                                                                                         //    =1: 8 lane Link ( Dual Links TMDS )
  628.                           // [1]=0: InCoherent mode  
  629.                                                                                                         //    =1: Coherent Mode                                                                        
  630.                                                                                                         // [2] Link Select:
  631.                                                                                                 // =0: PHY linkA   if bfLane<3
  632.                                                                                                         // =1: PHY linkB   if bfLanes<3
  633.                                                                                                 // =0: PHY linkA+B if bfLanes=3        
  634.                           // [5:4]PCIE lane Sel
  635.                           // =0: lane 0~3 or 0~7
  636.                           // =1: lane 4~7
  637.                           // =2: lane 8~11 or 8~15
  638.                           // =3: lane 12~15
  639.         UCHAR ucAction;                           // =0: turn off encoder                                      
  640.                                 // =1: turn on encoder                 
  641.   UCHAR ucReserved[4];
  642. }DIG_TRANSMITTER_CONTROL_PARAMETERS;
  643.  
  644. #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION           DIG_TRANSMITTER_CONTROL_PARAMETERS                                     
  645.  
  646. //ucInitInfo
  647. #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK  0x00ff                 
  648.  
  649. //ucConfig
  650. #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK                      0x01
  651. #define ATOM_TRANSMITTER_CONFIG_COHERENT                                0x02
  652. #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK           0x04
  653. #define ATOM_TRANSMITTER_CONFIG_LINKA                                           0x00
  654. #define ATOM_TRANSMITTER_CONFIG_LINKB                                           0x04
  655. #define ATOM_TRANSMITTER_CONFIG_LINKA_B                                 0x00                   
  656. #define ATOM_TRANSMITTER_CONFIG_LINKB_A                                 0x04
  657.  
  658. #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK        0x08                    // only used when ATOM_TRANSMITTER_ACTION_ENABLE
  659. #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER            0x00                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
  660. #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER            0x08                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
  661.  
  662. #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK                     0x30
  663. #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL                     0x00
  664. #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE                     0x20
  665. #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN           0x30
  666. #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK           0xc0
  667. #define ATOM_TRANSMITTER_CONFIG_LANE_0_3                                0x00
  668. #define ATOM_TRANSMITTER_CONFIG_LANE_0_7                                0x00
  669. #define ATOM_TRANSMITTER_CONFIG_LANE_4_7                                0x40
  670. #define ATOM_TRANSMITTER_CONFIG_LANE_8_11                               0x80
  671. #define ATOM_TRANSMITTER_CONFIG_LANE_8_15                               0x80
  672. #define ATOM_TRANSMITTER_CONFIG_LANE_12_15                      0xc0
  673.  
  674. //ucAction
  675. #define ATOM_TRANSMITTER_ACTION_DISABLE                                        0
  676. #define ATOM_TRANSMITTER_ACTION_ENABLE                                         1
  677. #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF                                      2
  678. #define ATOM_TRANSMITTER_ACTION_LCD_BLON                                       3
  679. #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4
  680. #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START               5
  681. #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP                        6
  682. #define ATOM_TRANSMITTER_ACTION_INIT                                                   7
  683. #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT         8
  684. #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT                  9
  685. #define ATOM_TRANSMITTER_ACTION_SETUP                                                  10
  686. #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11
  687.  
  688.  
  689. // Following are used for DigTransmitterControlTable ver1.2
  690. typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
  691. {
  692.   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
  693.   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
  694.   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
  695.                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
  696.   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
  697.   UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
  698.   UCHAR ucReserved:1;              
  699.   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
  700.                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
  701.                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
  702. }ATOM_DIG_TRANSMITTER_CONFIG_V2;
  703.  
  704. //ucConfig
  705. //Bit0
  706. #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR                  0x01
  707.  
  708. //Bit1
  709. #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT                                       0x02
  710.  
  711. //Bit2
  712. #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK                        0x04
  713. #define ATOM_TRANSMITTER_CONFIG_V2_LINKA                                    0x00                       
  714. #define ATOM_TRANSMITTER_CONFIG_V2_LINKB                                            0x04
  715.  
  716. // Bit3
  717. #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK             0x08
  718. #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER                   0x00                          // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
  719. #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER                   0x08                          // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
  720.  
  721. // Bit4
  722. #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR                          0x10
  723.  
  724. // Bit7:6
  725. #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK     0xC0
  726. #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1                 0x00    //AB
  727. #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2                 0x40    //CD
  728. #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3                 0x80    //EF
  729.  
  730. typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
  731. {
  732.         union
  733.         {
  734.   USHORT usPixelClock;          // in 10KHz; for bios convenient
  735.         USHORT usInitInfo;                      // when init uniphy,lower 8bit is used for connector type defined in objectid.h
  736.   ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
  737.         };
  738.   ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
  739.         UCHAR ucAction;                           // define as ATOM_TRANSMITER_ACTION_XXX                              
  740.   UCHAR ucReserved[4];
  741. }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
  742.  
  743.  
  744. /****************************************************************************/ 
  745. // Structures used by DAC1OuputControlTable
  746. //                    DAC2OuputControlTable
  747. //                    LVTMAOutputControlTable  (Before DEC30)
  748. //                    TMDSAOutputControlTable  (Before DEC30)
  749. /****************************************************************************/ 
  750. typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  751. {
  752.   UCHAR  ucAction;                    // Possible input:ATOM_ENABLE||ATOMDISABLE
  753.                                       // When the display is LCD, in addition to above:
  754.                                       // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
  755.                                       // ATOM_LCD_SELFTEST_STOP
  756.                                      
  757.   UCHAR  aucPadding[3];               // padding to DWORD aligned
  758. }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
  759.  
  760. #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  761.  
  762.  
  763. #define CRT1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  764. #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  765.  
  766. #define CRT2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  767. #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  768.  
  769. #define CV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  770. #define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  771.  
  772. #define TV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  773. #define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  774.  
  775. #define DFP1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  776. #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  777.  
  778. #define DFP2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  779. #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  780.  
  781. #define LCD1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  782. #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  783.  
  784. #define DVO_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  785. #define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
  786. #define DVO_OUTPUT_CONTROL_PARAMETERS_V3         DIG_TRANSMITTER_CONTROL_PARAMETERS
  787.  
  788. /****************************************************************************/ 
  789. // Structures used by BlankCRTCTable
  790. /****************************************************************************/ 
  791. typedef struct _BLANK_CRTC_PARAMETERS
  792. {
  793.   UCHAR  ucCRTC;                        // ATOM_CRTC1 or ATOM_CRTC2
  794.   UCHAR  ucBlanking;                  // ATOM_BLANKING or ATOM_BLANKINGOFF
  795.   USHORT usBlackColorRCr;
  796.   USHORT usBlackColorGY;
  797.   USHORT usBlackColorBCb;
  798. }BLANK_CRTC_PARAMETERS;
  799. #define BLANK_CRTC_PS_ALLOCATION    BLANK_CRTC_PARAMETERS
  800.  
  801. /****************************************************************************/ 
  802. // Structures used by EnableCRTCTable
  803. //                    EnableCRTCMemReqTable
  804. //                    UpdateCRTC_DoubleBufferRegistersTable
  805. /****************************************************************************/ 
  806. typedef struct _ENABLE_CRTC_PARAMETERS
  807. {
  808.   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
  809.   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
  810.   UCHAR ucPadding[2];
  811. }ENABLE_CRTC_PARAMETERS;
  812. #define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS
  813.  
  814. /****************************************************************************/ 
  815. // Structures used by SetCRTC_OverScanTable
  816. /****************************************************************************/ 
  817. typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
  818. {
  819.   USHORT usOverscanRight;             // right
  820.   USHORT usOverscanLeft;              // left
  821.   USHORT usOverscanBottom;            // bottom
  822.   USHORT usOverscanTop;               // top
  823.   UCHAR  ucCRTC;                      // ATOM_CRTC1 or ATOM_CRTC2
  824.   UCHAR  ucPadding[3];
  825. }SET_CRTC_OVERSCAN_PARAMETERS;
  826. #define SET_CRTC_OVERSCAN_PS_ALLOCATION  SET_CRTC_OVERSCAN_PARAMETERS
  827.  
  828. /****************************************************************************/ 
  829. // Structures used by SetCRTC_ReplicationTable
  830. /****************************************************************************/ 
  831. typedef struct _SET_CRTC_REPLICATION_PARAMETERS
  832. {
  833.   UCHAR ucH_Replication;              // horizontal replication
  834.   UCHAR ucV_Replication;              // vertical replication
  835.   UCHAR usCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
  836.   UCHAR ucPadding;
  837. }SET_CRTC_REPLICATION_PARAMETERS;
  838. #define SET_CRTC_REPLICATION_PS_ALLOCATION  SET_CRTC_REPLICATION_PARAMETERS
  839.  
  840. /****************************************************************************/ 
  841. // Structures used by SelectCRTC_SourceTable
  842. /****************************************************************************/ 
  843. typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
  844. {
  845.   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
  846.   UCHAR ucDevice;                     // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
  847.   UCHAR ucPadding[2];
  848. }SELECT_CRTC_SOURCE_PARAMETERS;
  849. #define SELECT_CRTC_SOURCE_PS_ALLOCATION  SELECT_CRTC_SOURCE_PARAMETERS
  850.  
  851. typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
  852. {
  853.   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
  854.   UCHAR ucEncoderID;                  // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
  855.   UCHAR ucEncodeMode;                                                                   // Encoding mode, only valid when using DIG1/DIG2/DVO
  856.   UCHAR ucPadding;
  857. }SELECT_CRTC_SOURCE_PARAMETERS_V2;
  858.  
  859. //ucEncoderID
  860. //#define ASIC_INT_DAC1_ENCODER_ID                                              0x00
  861. //#define ASIC_INT_TV_ENCODER_ID                                                                        0x02
  862. //#define ASIC_INT_DIG1_ENCODER_ID                                                              0x03
  863. //#define ASIC_INT_DAC2_ENCODER_ID                                                              0x04
  864. //#define ASIC_EXT_TV_ENCODER_ID                                                                        0x06
  865. //#define ASIC_INT_DVO_ENCODER_ID                                                                       0x07
  866. //#define ASIC_INT_DIG2_ENCODER_ID                                                              0x09
  867. //#define ASIC_EXT_DIG_ENCODER_ID                                                                       0x05
  868.  
  869. //ucEncodeMode
  870. //#define ATOM_ENCODER_MODE_DP                                                                          0
  871. //#define ATOM_ENCODER_MODE_LVDS                                                                        1
  872. //#define ATOM_ENCODER_MODE_DVI                                                                         2
  873. //#define ATOM_ENCODER_MODE_HDMI                                                                        3
  874. //#define ATOM_ENCODER_MODE_SDVO                                                                        4
  875. //#define ATOM_ENCODER_MODE_TV                                                                          13
  876. //#define ATOM_ENCODER_MODE_CV                                                                          14
  877. //#define ATOM_ENCODER_MODE_CRT                                                                         15
  878.  
  879. /****************************************************************************/ 
  880. // Structures used by SetPixelClockTable
  881. //                    GetPixelClockTable
  882. /****************************************************************************/ 
  883. //Major revision=1., Minor revision=1
  884. typedef struct _PIXEL_CLOCK_PARAMETERS
  885. {
  886.   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
  887.                                       // 0 means disable PPLL
  888.   USHORT usRefDiv;                    // Reference divider
  889.   USHORT usFbDiv;                     // feedback divider
  890.   UCHAR  ucPostDiv;                   // post divider  
  891.   UCHAR  ucFracFbDiv;                 // fractional feedback divider
  892.   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
  893.   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
  894.   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
  895.   UCHAR  ucPadding;
  896. }PIXEL_CLOCK_PARAMETERS;
  897.  
  898. //Major revision=1., Minor revision=2, add ucMiscIfno
  899. //ucMiscInfo:
  900. #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
  901. #define MISC_DEVICE_INDEX_MASK        0xF0
  902. #define MISC_DEVICE_INDEX_SHIFT       4
  903.  
  904. typedef struct _PIXEL_CLOCK_PARAMETERS_V2
  905. {
  906.   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
  907.                                       // 0 means disable PPLL
  908.   USHORT usRefDiv;                    // Reference divider
  909.   USHORT usFbDiv;                     // feedback divider
  910.   UCHAR  ucPostDiv;                   // post divider  
  911.   UCHAR  ucFracFbDiv;                 // fractional feedback divider
  912.   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
  913.   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
  914.   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
  915.   UCHAR  ucMiscInfo;                  // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
  916. }PIXEL_CLOCK_PARAMETERS_V2;
  917.  
  918. //Major revision=1., Minor revision=3, structure/definition change
  919. //ucEncoderMode:
  920. //ATOM_ENCODER_MODE_DP
  921. //ATOM_ENOCDER_MODE_LVDS
  922. //ATOM_ENOCDER_MODE_DVI
  923. //ATOM_ENOCDER_MODE_HDMI
  924. //ATOM_ENOCDER_MODE_SDVO
  925. //ATOM_ENCODER_MODE_TV                                                                          13
  926. //ATOM_ENCODER_MODE_CV                                                                          14
  927. //ATOM_ENCODER_MODE_CRT                                                                         15
  928.  
  929. //ucDVOConfig
  930. //#define DVO_ENCODER_CONFIG_RATE_SEL                                                   0x01
  931. //#define DVO_ENCODER_CONFIG_DDR_SPEED                                          0x00
  932. //#define DVO_ENCODER_CONFIG_SDR_SPEED                                          0x01
  933. //#define DVO_ENCODER_CONFIG_OUTPUT_SEL                                         0x0c
  934. //#define DVO_ENCODER_CONFIG_LOW12BIT                                                   0x00
  935. //#define DVO_ENCODER_CONFIG_UPPER12BIT                                         0x04
  936. //#define DVO_ENCODER_CONFIG_24BIT                                                              0x08
  937.  
  938. //ucMiscInfo: also changed, see below
  939. #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL                                                0x01
  940. #define PIXEL_CLOCK_MISC_VGA_MODE                                                                               0x02
  941. #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK                                                  0x04
  942. #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1                                                 0x00
  943. #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2                                                 0x04
  944. #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK                 0x08
  945.  
  946. typedef struct _PIXEL_CLOCK_PARAMETERS_V3
  947. {
  948.   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
  949.                                       // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
  950.   USHORT usRefDiv;                    // Reference divider
  951.   USHORT usFbDiv;                     // feedback divider
  952.   UCHAR  ucPostDiv;                   // post divider  
  953.   UCHAR  ucFracFbDiv;                 // fractional feedback divider
  954.   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
  955.   UCHAR  ucTransmitterId;             // graphic encoder id defined in objectId.h
  956.         union
  957.         {
  958.   UCHAR  ucEncoderMode;               // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
  959.         UCHAR  ucDVOConfig;                                                                     // when use DVO, need to know SDR/DDR, 12bit or 24bit
  960.         };
  961.   UCHAR  ucMiscInfo;                  // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
  962.                                       // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
  963. }PIXEL_CLOCK_PARAMETERS_V3;
  964.  
  965. #define PIXEL_CLOCK_PARAMETERS_LAST                     PIXEL_CLOCK_PARAMETERS_V2
  966. #define GET_PIXEL_CLOCK_PS_ALLOCATION           PIXEL_CLOCK_PARAMETERS_LAST
  967.  
  968. /****************************************************************************/ 
  969. // Structures used by AdjustDisplayPllTable
  970. /****************************************************************************/ 
  971. typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
  972. {
  973.         USHORT usPixelClock;
  974.         UCHAR ucTransmitterID;
  975.         UCHAR ucEncodeMode;
  976.         union
  977.         {
  978.                 UCHAR ucDVOConfig;                                                                      //if DVO, need passing link rate and output 12bitlow or 24bit
  979.                 UCHAR ucConfig;                                                                                 //if none DVO, not defined yet
  980.         };
  981.         UCHAR ucReserved[3];
  982. }ADJUST_DISPLAY_PLL_PARAMETERS;
  983.  
  984. #define ADJUST_DISPLAY_CONFIG_SS_ENABLE       0x10
  985.  
  986. #define ADJUST_DISPLAY_PLL_PS_ALLOCATION                        ADJUST_DISPLAY_PLL_PARAMETERS
  987.  
  988. /****************************************************************************/ 
  989. // Structures used by EnableYUVTable
  990. /****************************************************************************/ 
  991. typedef struct _ENABLE_YUV_PARAMETERS
  992. {
  993.   UCHAR ucEnable;                     // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
  994.   UCHAR ucCRTC;                       // Which CRTC needs this YUV or RGB format
  995.   UCHAR ucPadding[2];
  996. }ENABLE_YUV_PARAMETERS;
  997. #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
  998.  
  999. /****************************************************************************/ 
  1000. // Structures used by GetMemoryClockTable
  1001. /****************************************************************************/ 
  1002. typedef struct _GET_MEMORY_CLOCK_PARAMETERS
  1003. {
  1004.   ULONG ulReturnMemoryClock;          // current memory speed in 10KHz unit
  1005. } GET_MEMORY_CLOCK_PARAMETERS;
  1006. #define GET_MEMORY_CLOCK_PS_ALLOCATION  GET_MEMORY_CLOCK_PARAMETERS
  1007.  
  1008. /****************************************************************************/ 
  1009. // Structures used by GetEngineClockTable
  1010. /****************************************************************************/ 
  1011. typedef struct _GET_ENGINE_CLOCK_PARAMETERS
  1012. {
  1013.   ULONG ulReturnEngineClock;          // current engine speed in 10KHz unit
  1014. } GET_ENGINE_CLOCK_PARAMETERS;
  1015. #define GET_ENGINE_CLOCK_PS_ALLOCATION  GET_ENGINE_CLOCK_PARAMETERS
  1016.  
  1017. /****************************************************************************/ 
  1018. // Following Structures and constant may be obsolete
  1019. /****************************************************************************/ 
  1020. //Maxium 8 bytes,the data read in will be placed in the parameter space.
  1021. //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
  1022. typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
  1023. {
  1024.   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
  1025.   USHORT    usVRAMAddress;      //Adress in Frame Buffer where to pace raw EDID
  1026.   USHORT    usStatus;           //When use output: lower byte EDID checksum, high byte hardware status
  1027.                                 //WHen use input:  lower byte as 'byte to read':currently limited to 128byte or 1byte
  1028.   UCHAR     ucSlaveAddr;        //Read from which slave
  1029.   UCHAR     ucLineNumber;       //Read from which HW assisted line
  1030. }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
  1031. #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION  READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
  1032.  
  1033.  
  1034. #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE                  0
  1035. #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES              1
  1036. #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK       2
  1037. #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK  3
  1038. #define  ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK       4
  1039.  
  1040. typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
  1041. {
  1042.   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
  1043.   USHORT    usByteOffset;       //Write to which byte
  1044.                                 //Upper portion of usByteOffset is Format of data
  1045.                                 //1bytePS+offsetPS
  1046.                                 //2bytesPS+offsetPS
  1047.                                 //blockID+offsetPS
  1048.                                 //blockID+offsetID
  1049.                                 //blockID+counterID+offsetID
  1050.   UCHAR     ucData;             //PS data1
  1051.   UCHAR     ucStatus;           //Status byte 1=success, 2=failure, Also is used as PS data2
  1052.   UCHAR     ucSlaveAddr;        //Write to which slave
  1053.   UCHAR     ucLineNumber;       //Write from which HW assisted line
  1054. }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
  1055.  
  1056. #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION  WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
  1057.  
  1058. typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
  1059. {
  1060.   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
  1061.   UCHAR     ucSlaveAddr;        //Write to which slave
  1062.   UCHAR     ucLineNumber;       //Write from which HW assisted line
  1063. }SET_UP_HW_I2C_DATA_PARAMETERS;
  1064.  
  1065.  
  1066. /**************************************************************************/
  1067. #define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
  1068.  
  1069. /****************************************************************************/ 
  1070. // Structures used by PowerConnectorDetectionTable
  1071. /****************************************************************************/ 
  1072. typedef struct  _POWER_CONNECTOR_DETECTION_PARAMETERS
  1073. {
  1074.   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
  1075.         UCHAR   ucPwrBehaviorId;                                                       
  1076.         USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
  1077. }POWER_CONNECTOR_DETECTION_PARAMETERS;
  1078.  
  1079. typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
  1080. {                              
  1081.   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
  1082.         UCHAR   ucReserved;
  1083.         USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
  1084.   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved;
  1085. }POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
  1086.  
  1087. /****************************LVDS SS Command Table Definitions**********************/
  1088.  
  1089. /****************************************************************************/ 
  1090. // Structures used by EnableSpreadSpectrumOnPPLLTable
  1091. /****************************************************************************/ 
  1092. typedef struct  _ENABLE_LVDS_SS_PARAMETERS
  1093. {
  1094.   USHORT  usSpreadSpectrumPercentage;      
  1095.   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
  1096.   UCHAR   ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
  1097.   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
  1098.   UCHAR   ucPadding[3];
  1099. }ENABLE_LVDS_SS_PARAMETERS;
  1100.  
  1101. //ucTableFormatRevision=1,ucTableContentRevision=2
  1102. typedef struct  _ENABLE_LVDS_SS_PARAMETERS_V2
  1103. {
  1104.   USHORT  usSpreadSpectrumPercentage;      
  1105.   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
  1106.   UCHAR   ucSpreadSpectrumStep;           //
  1107.   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
  1108.   UCHAR   ucSpreadSpectrumDelay;
  1109.   UCHAR   ucSpreadSpectrumRange;
  1110.   UCHAR   ucPadding;
  1111. }ENABLE_LVDS_SS_PARAMETERS_V2;
  1112.  
  1113. //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
  1114. typedef struct  _ENABLE_SPREAD_SPECTRUM_ON_PPLL
  1115. {
  1116.   USHORT  usSpreadSpectrumPercentage;
  1117.   UCHAR   ucSpreadSpectrumType;           // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
  1118.   UCHAR   ucSpreadSpectrumStep;           //
  1119.   UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
  1120.   UCHAR   ucSpreadSpectrumDelay;
  1121.   UCHAR   ucSpreadSpectrumRange;
  1122.   UCHAR   ucPpll;                                                                                                 // ATOM_PPLL1/ATOM_PPLL2
  1123. }ENABLE_SPREAD_SPECTRUM_ON_PPLL;
  1124.  
  1125. #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION  ENABLE_SPREAD_SPECTRUM_ON_PPLL
  1126.  
  1127. /**************************************************************************/
  1128.  
  1129. typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
  1130. {
  1131.   PIXEL_CLOCK_PARAMETERS sPCLKInput;
  1132.   ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
  1133. }SET_PIXEL_CLOCK_PS_ALLOCATION;
  1134.  
  1135. #define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION
  1136.  
  1137. /****************************************************************************/ 
  1138. // Structures used by ###
  1139. /****************************************************************************/ 
  1140. typedef struct  _MEMORY_TRAINING_PARAMETERS
  1141. {
  1142.   ULONG ulTargetMemoryClock;          //In 10Khz unit
  1143. }MEMORY_TRAINING_PARAMETERS;
  1144. #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
  1145.  
  1146.  
  1147. /****************************LVDS and other encoder command table definitions **********************/
  1148.  
  1149.  
  1150. /****************************************************************************/ 
  1151. // Structures used by LVDSEncoderControlTable   (Before DCE30)
  1152. //                    LVTMAEncoderControlTable  (Before DCE30)
  1153. //                    TMDSAEncoderControlTable  (Before DCE30)
  1154. /****************************************************************************/ 
  1155. typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
  1156. {
  1157.   USHORT usPixelClock;  // in 10KHz; for bios convenient
  1158.   UCHAR  ucMisc;        // bit0=0: Enable single link
  1159.                         //     =1: Enable dual link
  1160.                         // Bit1=0: 666RGB
  1161.                         //     =1: 888RGB
  1162.   UCHAR  ucAction;      // 0: turn off encoder
  1163.                         // 1: setup and turn on encoder
  1164. }LVDS_ENCODER_CONTROL_PARAMETERS;
  1165.  
  1166. #define LVDS_ENCODER_CONTROL_PS_ALLOCATION  LVDS_ENCODER_CONTROL_PARAMETERS
  1167.    
  1168. #define TMDS1_ENCODER_CONTROL_PARAMETERS    LVDS_ENCODER_CONTROL_PARAMETERS
  1169. #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
  1170.  
  1171. #define TMDS2_ENCODER_CONTROL_PARAMETERS    TMDS1_ENCODER_CONTROL_PARAMETERS
  1172. #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
  1173.  
  1174.  
  1175. //ucTableFormatRevision=1,ucTableContentRevision=2
  1176. typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
  1177. {
  1178.   USHORT usPixelClock;  // in 10KHz; for bios convenient
  1179.   UCHAR  ucMisc;        // see PANEL_ENCODER_MISC_xx defintions below
  1180.   UCHAR  ucAction;      // 0: turn off encoder
  1181.                         // 1: setup and turn on encoder
  1182.   UCHAR  ucTruncate;    // bit0=0: Disable truncate
  1183.                         //     =1: Enable truncate
  1184.                         // bit4=0: 666RGB
  1185.                         //     =1: 888RGB
  1186.   UCHAR  ucSpatial;     // bit0=0: Disable spatial dithering
  1187.                         //     =1: Enable spatial dithering
  1188.                         // bit4=0: 666RGB
  1189.                         //     =1: 888RGB
  1190.   UCHAR  ucTemporal;    // bit0=0: Disable temporal dithering
  1191.                         //     =1: Enable temporal dithering
  1192.                         // bit4=0: 666RGB
  1193.                         //     =1: 888RGB
  1194.                         // bit5=0: Gray level 2
  1195.                         //     =1: Gray level 4
  1196.   UCHAR  ucFRC;         // bit4=0: 25FRC_SEL pattern E
  1197.                         //     =1: 25FRC_SEL pattern F
  1198.                         // bit6:5=0: 50FRC_SEL pattern A
  1199.                         //       =1: 50FRC_SEL pattern B
  1200.                         //       =2: 50FRC_SEL pattern C
  1201.                         //       =3: 50FRC_SEL pattern D
  1202.                         // bit7=0: 75FRC_SEL pattern E
  1203.                         //     =1: 75FRC_SEL pattern F
  1204. }LVDS_ENCODER_CONTROL_PARAMETERS_V2;
  1205.  
  1206. #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
  1207.    
  1208. #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2    LVDS_ENCODER_CONTROL_PARAMETERS_V2
  1209. #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
  1210.  
  1211. #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2    TMDS1_ENCODER_CONTROL_PARAMETERS_V2
  1212. #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
  1213.  
  1214. #define LVDS_ENCODER_CONTROL_PARAMETERS_V3     LVDS_ENCODER_CONTROL_PARAMETERS_V2
  1215. #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3  LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1216.  
  1217. #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1218. #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
  1219.  
  1220. #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1221. #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
  1222.  
  1223. /****************************************************************************/ 
  1224. // Structures used by ###
  1225. /****************************************************************************/ 
  1226. typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
  1227. {                              
  1228.   UCHAR    ucEnable;            // Enable or Disable External TMDS encoder
  1229.   UCHAR    ucMisc;              // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
  1230.   UCHAR    ucPadding[2];
  1231. }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
  1232.  
  1233. typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
  1234. {                              
  1235.   ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS    sXTmdsEncoder;
  1236.   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION   sReserved;     //Caller doesn't need to init this portion
  1237. }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
  1238.  
  1239. #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
  1240.  
  1241. typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
  1242. {                              
  1243.   ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2    sXTmdsEncoder;
  1244.   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
  1245. }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
  1246.  
  1247. typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
  1248. {
  1249.   DIG_ENCODER_CONTROL_PARAMETERS            sDigEncoder;
  1250.   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
  1251. }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
  1252.  
  1253. /****************************************************************************/ 
  1254. // Structures used by DVOEncoderControlTable
  1255. /****************************************************************************/ 
  1256. //ucTableFormatRevision=1,ucTableContentRevision=3
  1257. //ucDVOConfig:
  1258. #define DVO_ENCODER_CONFIG_RATE_SEL                                                     0x01
  1259. #define DVO_ENCODER_CONFIG_DDR_SPEED                                            0x00
  1260. #define DVO_ENCODER_CONFIG_SDR_SPEED                                            0x01
  1261. #define DVO_ENCODER_CONFIG_OUTPUT_SEL                                           0x0c
  1262. #define DVO_ENCODER_CONFIG_LOW12BIT                                                     0x00
  1263. #define DVO_ENCODER_CONFIG_UPPER12BIT                                           0x04
  1264. #define DVO_ENCODER_CONFIG_24BIT                                                                0x08
  1265.  
  1266. typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
  1267. {
  1268.   USHORT usPixelClock;
  1269.   UCHAR  ucDVOConfig;
  1270.   UCHAR  ucAction;                                                                                                              //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
  1271.   UCHAR  ucReseved[4];
  1272. }DVO_ENCODER_CONTROL_PARAMETERS_V3;
  1273. #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3    DVO_ENCODER_CONTROL_PARAMETERS_V3
  1274.  
  1275. //ucTableFormatRevision=1
  1276. //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
  1277. // bit1=0: non-coherent mode
  1278. //     =1: coherent mode
  1279.  
  1280. //==========================================================================================
  1281. //Only change is here next time when changing encoder parameter definitions again!
  1282. #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST     LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1283. #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST  LVDS_ENCODER_CONTROL_PARAMETERS_LAST
  1284.  
  1285. #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1286. #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
  1287.  
  1288. #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1289. #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
  1290.  
  1291. #define DVO_ENCODER_CONTROL_PARAMETERS_LAST      DVO_ENCODER_CONTROL_PARAMETERS
  1292. #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION
  1293.  
  1294. //==========================================================================================
  1295. #define PANEL_ENCODER_MISC_DUAL                0x01
  1296. #define PANEL_ENCODER_MISC_COHERENT            0x02
  1297. #define PANEL_ENCODER_MISC_TMDS_LINKB                                    0x04
  1298. #define PANEL_ENCODER_MISC_HDMI_TYPE                                     0x08
  1299.  
  1300. #define PANEL_ENCODER_ACTION_DISABLE           ATOM_DISABLE
  1301. #define PANEL_ENCODER_ACTION_ENABLE            ATOM_ENABLE
  1302. #define PANEL_ENCODER_ACTION_COHERENTSEQ       (ATOM_ENABLE+1)
  1303.  
  1304. #define PANEL_ENCODER_TRUNCATE_EN              0x01
  1305. #define PANEL_ENCODER_TRUNCATE_DEPTH           0x10
  1306. #define PANEL_ENCODER_SPATIAL_DITHER_EN        0x01
  1307. #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH     0x10
  1308. #define PANEL_ENCODER_TEMPORAL_DITHER_EN       0x01
  1309. #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH    0x10
  1310. #define PANEL_ENCODER_TEMPORAL_LEVEL_4         0x20
  1311. #define PANEL_ENCODER_25FRC_MASK               0x10
  1312. #define PANEL_ENCODER_25FRC_E                  0x00
  1313. #define PANEL_ENCODER_25FRC_F                  0x10
  1314. #define PANEL_ENCODER_50FRC_MASK               0x60
  1315. #define PANEL_ENCODER_50FRC_A                  0x00
  1316. #define PANEL_ENCODER_50FRC_B                  0x20
  1317. #define PANEL_ENCODER_50FRC_C                  0x40
  1318. #define PANEL_ENCODER_50FRC_D                  0x60
  1319. #define PANEL_ENCODER_75FRC_MASK               0x80
  1320. #define PANEL_ENCODER_75FRC_E                  0x00
  1321. #define PANEL_ENCODER_75FRC_F                  0x80
  1322.  
  1323. /****************************************************************************/ 
  1324. // Structures used by SetVoltageTable
  1325. /****************************************************************************/ 
  1326. #define SET_VOLTAGE_TYPE_ASIC_VDDC             1
  1327. #define SET_VOLTAGE_TYPE_ASIC_MVDDC            2
  1328. #define SET_VOLTAGE_TYPE_ASIC_MVDDQ            3
  1329. #define SET_VOLTAGE_TYPE_ASIC_VDDCI            4
  1330. #define SET_VOLTAGE_INIT_MODE                  5
  1331. #define SET_VOLTAGE_GET_MAX_VOLTAGE            6                                        //Gets the Max. voltage for the soldered Asic
  1332.  
  1333. #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE       0x1
  1334. #define SET_ASIC_VOLTAGE_MODE_SOURCE_A         0x2
  1335. #define SET_ASIC_VOLTAGE_MODE_SOURCE_B         0x4
  1336.  
  1337. #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE      0x0
  1338. #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL      0x1     
  1339. #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK     0x2
  1340.  
  1341. typedef struct  _SET_VOLTAGE_PARAMETERS
  1342. {
  1343.   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
  1344.   UCHAR    ucVoltageMode;               // To set all, to set source A or source B or ...
  1345.   UCHAR    ucVoltageIndex;              // An index to tell which voltage level
  1346.   UCHAR    ucReserved;          
  1347. }SET_VOLTAGE_PARAMETERS;
  1348.  
  1349. typedef struct  _SET_VOLTAGE_PARAMETERS_V2
  1350. {
  1351.   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
  1352.   UCHAR    ucVoltageMode;               // Not used, maybe use for state machine for differen power mode
  1353.   USHORT   usVoltageLevel;              // real voltage level
  1354. }SET_VOLTAGE_PARAMETERS_V2;
  1355.  
  1356. typedef struct _SET_VOLTAGE_PS_ALLOCATION
  1357. {
  1358.   SET_VOLTAGE_PARAMETERS sASICSetVoltage;
  1359.   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
  1360. }SET_VOLTAGE_PS_ALLOCATION;
  1361.  
  1362. /****************************************************************************/ 
  1363. // Structures used by TVEncoderControlTable
  1364. /****************************************************************************/ 
  1365. typedef struct _TV_ENCODER_CONTROL_PARAMETERS
  1366. {
  1367.   USHORT usPixelClock;                // in 10KHz; for bios convenient
  1368.   UCHAR  ucTvStandard;                // See definition "ATOM_TV_NTSC ..."
  1369.   UCHAR  ucAction;                    // 0: turn off encoder
  1370.                                       // 1: setup and turn on encoder
  1371. }TV_ENCODER_CONTROL_PARAMETERS;
  1372.  
  1373. typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
  1374. {
  1375.   TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;          
  1376.   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved; // Don't set this one
  1377. }TV_ENCODER_CONTROL_PS_ALLOCATION;
  1378.  
  1379. //==============================Data Table Portion====================================
  1380.  
  1381. #ifdef  UEFI_BUILD
  1382.         #define UTEMP   USHORT
  1383.         #define USHORT  void*
  1384. #endif
  1385.  
  1386. /****************************************************************************/ 
  1387. // Structure used in Data.mtb
  1388. /****************************************************************************/ 
  1389. typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
  1390. {
  1391.   USHORT        UtilityPipeLine;                // Offest for the utility to get parser info,Don't change this position!
  1392.   USHORT        MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
  1393.   USHORT        MultimediaConfigInfo;     // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
  1394.   USHORT        StandardVESA_Timing;      // Only used by Bios
  1395.   USHORT        FirmwareInfo;             // Shared by various SW components,latest version 1.4
  1396.   USHORT        DAC_Info;                 // Will be obsolete from R600
  1397.   USHORT        LVDS_Info;                // Shared by various SW components,latest version 1.1
  1398.   USHORT        TMDS_Info;                // Will be obsolete from R600
  1399.   USHORT        AnalogTV_Info;            // Shared by various SW components,latest version 1.1
  1400.   USHORT        SupportedDevicesInfo;     // Will be obsolete from R600
  1401.   USHORT        GPIO_I2C_Info;            // Shared by various SW components,latest version 1.2 will be used from R600          
  1402.   USHORT        VRAM_UsageByFirmware;     // Shared by various SW components,latest version 1.3 will be used from R600
  1403.   USHORT        GPIO_Pin_LUT;             // Shared by various SW components,latest version 1.1
  1404.   USHORT        VESA_ToInternalModeLUT;   // Only used by Bios
  1405.   USHORT        ComponentVideoInfo;       // Shared by various SW components,latest version 2.1 will be used from R600
  1406.   USHORT        PowerPlayInfo;            // Shared by various SW components,latest version 2.1,new design from R600
  1407.   USHORT        CompassionateData;        // Will be obsolete from R600
  1408.   USHORT        SaveRestoreInfo;          // Only used by Bios
  1409.   USHORT        PPLL_SS_Info;             // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
  1410.   USHORT        OemInfo;                  // Defined and used by external SW, should be obsolete soon
  1411.   USHORT        XTMDS_Info;               // Will be obsolete from R600
  1412.   USHORT        MclkSS_Info;              // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
  1413.   USHORT        Object_Header;            // Shared by various SW components,latest version 1.1
  1414.   USHORT        IndirectIOAccess;         // Only used by Bios,this table position can't change at all!!
  1415.   USHORT        MC_InitParameter;         // Only used by command table
  1416.   USHORT        ASIC_VDDC_Info;                                         // Will be obsolete from R600
  1417.   USHORT        ASIC_InternalSS_Info;                   // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
  1418.   USHORT        TV_VideoMode;                                                   // Only used by command table
  1419.   USHORT        VRAM_Info;                                                              // Only used by command table, latest version 1.3
  1420.   USHORT        MemoryTrainingInfo;                             // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
  1421.   USHORT        IntegratedSystemInfo;                   // Shared by various SW components
  1422.   USHORT        ASIC_ProfilingInfo;                             // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
  1423.   USHORT        VoltageObjectInfo;                              // Shared by various SW components, latest version 1.1
  1424.         USHORT                          PowerSourceInfo;                                        // Shared by various SW components, latest versoin 1.1
  1425. }ATOM_MASTER_LIST_OF_DATA_TABLES;
  1426.  
  1427. #ifdef  UEFI_BUILD
  1428.         #define USHORT  UTEMP
  1429. #endif
  1430.  
  1431. typedef struct _ATOM_MASTER_DATA_TABLE
  1432. {
  1433.   ATOM_COMMON_TABLE_HEADER sHeader;  
  1434.   ATOM_MASTER_LIST_OF_DATA_TABLES   ListOfDataTables;
  1435. }ATOM_MASTER_DATA_TABLE;
  1436.  
  1437. /****************************************************************************/ 
  1438. // Structure used in MultimediaCapabilityInfoTable
  1439. /****************************************************************************/ 
  1440. typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
  1441. {
  1442.   ATOM_COMMON_TABLE_HEADER sHeader;  
  1443.   ULONG                    ulSignature;      // HW info table signature string "$ATI"
  1444.   UCHAR                    ucI2C_Type;       // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
  1445.   UCHAR                    ucTV_OutInfo;     // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
  1446.   UCHAR                    ucVideoPortInfo;  // Provides the video port capabilities
  1447.   UCHAR                    ucHostPortInfo;   // Provides host port configuration information
  1448. }ATOM_MULTIMEDIA_CAPABILITY_INFO;
  1449.  
  1450. /****************************************************************************/ 
  1451. // Structure used in MultimediaConfigInfoTable
  1452. /****************************************************************************/ 
  1453. typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
  1454. {
  1455.   ATOM_COMMON_TABLE_HEADER sHeader;
  1456.   ULONG                    ulSignature;      // MM info table signature sting "$MMT"
  1457.   UCHAR                    ucTunerInfo;      // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
  1458.   UCHAR                    ucAudioChipInfo;  // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
  1459.   UCHAR                    ucProductID;      // Defines as OEM ID or ATI board ID dependent on product type setting
  1460.   UCHAR                    ucMiscInfo1;      // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
  1461.   UCHAR                    ucMiscInfo2;      // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
  1462.   UCHAR                    ucMiscInfo3;      // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
  1463.   UCHAR                    ucMiscInfo4;      // Video Decoder Host Config (2:0) reserved (7:3)
  1464.   UCHAR                    ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
  1465.   UCHAR                    ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
  1466.   UCHAR                    ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
  1467.   UCHAR                    ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
  1468.   UCHAR                    ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
  1469. }ATOM_MULTIMEDIA_CONFIG_INFO;
  1470.  
  1471.  
  1472. /****************************************************************************/ 
  1473. // Structures used in FirmwareInfoTable
  1474. /****************************************************************************/ 
  1475.  
  1476. // usBIOSCapability Defintion:
  1477. // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
  1478. // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
  1479. // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
  1480. // Others: Reserved
  1481. #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED         0x0001
  1482. #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT            0x0002
  1483. #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT     0x0004
  1484. #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT      0x0008
  1485. #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT      0x0010
  1486. #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU         0x0020
  1487. #define ATOM_BIOS_INFO_WMI_SUPPORT                  0x0040
  1488. #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080
  1489. #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT          0x0100
  1490. #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK        0x1E00
  1491. #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
  1492. #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE  0x4000
  1493.  
  1494.  
  1495. #ifndef _H2INC
  1496.  
  1497. //Please don't add or expand this bitfield structure below, this one will retire soon.!
  1498. typedef struct _ATOM_FIRMWARE_CAPABILITY
  1499. {
  1500.   USHORT FirmwarePosted:1;
  1501.   USHORT DualCRTC_Support:1;
  1502.   USHORT ExtendedDesktopSupport:1;
  1503.   USHORT MemoryClockSS_Support:1;
  1504.   USHORT EngineClockSS_Support:1;
  1505.   USHORT GPUControlsBL:1;
  1506.   USHORT WMI_SUPPORT:1;
  1507.   USHORT PPMode_Assigned:1;
  1508.   USHORT HyperMemory_Support:1;
  1509.   USHORT HyperMemory_Size:4;
  1510.   USHORT Reserved:3;
  1511. }ATOM_FIRMWARE_CAPABILITY;
  1512.  
  1513. typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
  1514. {
  1515.   ATOM_FIRMWARE_CAPABILITY sbfAccess;
  1516.   USHORT                   susAccess;
  1517. }ATOM_FIRMWARE_CAPABILITY_ACCESS;
  1518.  
  1519. #else
  1520.  
  1521. typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
  1522. {
  1523.   USHORT                   susAccess;
  1524. }ATOM_FIRMWARE_CAPABILITY_ACCESS;
  1525.  
  1526. #endif
  1527.  
  1528. typedef struct _ATOM_FIRMWARE_INFO
  1529. {
  1530.   ATOM_COMMON_TABLE_HEADER        sHeader;
  1531.   ULONG                           ulFirmwareRevision;
  1532.   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
  1533.   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
  1534.   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
  1535.   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
  1536.   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
  1537.   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
  1538.   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
  1539.   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
  1540.   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
  1541.   UCHAR                           ucASICMaxTemperature;
  1542.   UCHAR                           ucPadding[3];               //Don't use them
  1543.   ULONG                           aulReservedForBIOS[3];      //Don't use them
  1544.   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
  1545.   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
  1546.   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
  1547.   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
  1548.   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
  1549.   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
  1550.   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
  1551.   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
  1552.   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
  1553.   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit, the definitions above can't change!!!
  1554.   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
  1555.   USHORT                          usReferenceClock;           //In 10Khz unit  
  1556.   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
  1557.   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
  1558.   UCHAR                           ucDesign_ID;                //Indicate what is the board design
  1559.   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
  1560. }ATOM_FIRMWARE_INFO;
  1561.  
  1562. typedef struct _ATOM_FIRMWARE_INFO_V1_2
  1563. {
  1564.   ATOM_COMMON_TABLE_HEADER        sHeader;
  1565.   ULONG                           ulFirmwareRevision;
  1566.   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
  1567.   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
  1568.   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
  1569.   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
  1570.   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
  1571.   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
  1572.   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
  1573.   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
  1574.   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
  1575.   UCHAR                           ucASICMaxTemperature;
  1576.   UCHAR                           ucMinAllowedBL_Level;
  1577.   UCHAR                           ucPadding[2];               //Don't use them
  1578.   ULONG                           aulReservedForBIOS[2];      //Don't use them
  1579.   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
  1580.   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
  1581.   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
  1582.   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
  1583.   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
  1584.   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
  1585.   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
  1586.   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
  1587.   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
  1588.   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
  1589.   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
  1590.   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
  1591.   USHORT                          usReferenceClock;           //In 10Khz unit  
  1592.   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
  1593.   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
  1594.   UCHAR                           ucDesign_ID;                //Indicate what is the board design
  1595.   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
  1596. }ATOM_FIRMWARE_INFO_V1_2;
  1597.  
  1598. typedef struct _ATOM_FIRMWARE_INFO_V1_3
  1599. {
  1600.   ATOM_COMMON_TABLE_HEADER        sHeader;
  1601.   ULONG                           ulFirmwareRevision;
  1602.   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
  1603.   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
  1604.   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
  1605.   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
  1606.   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
  1607.   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
  1608.   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
  1609.   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
  1610.   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
  1611.   UCHAR                           ucASICMaxTemperature;
  1612.   UCHAR                           ucMinAllowedBL_Level;
  1613.   UCHAR                           ucPadding[2];               //Don't use them
  1614.   ULONG                           aulReservedForBIOS;         //Don't use them
  1615.   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
  1616.   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
  1617.   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
  1618.   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
  1619.   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
  1620.   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
  1621.   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
  1622.   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
  1623.   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
  1624.   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
  1625.   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
  1626.   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
  1627.   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
  1628.   USHORT                          usReferenceClock;           //In 10Khz unit  
  1629.   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
  1630.   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
  1631.   UCHAR                           ucDesign_ID;                //Indicate what is the board design
  1632.   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
  1633. }ATOM_FIRMWARE_INFO_V1_3;
  1634.  
  1635. typedef struct _ATOM_FIRMWARE_INFO_V1_4
  1636. {
  1637.   ATOM_COMMON_TABLE_HEADER        sHeader;
  1638.   ULONG                           ulFirmwareRevision;
  1639.   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
  1640.   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
  1641.   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
  1642.   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
  1643.   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
  1644.   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
  1645.   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
  1646.   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
  1647.   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
  1648.   UCHAR                           ucASICMaxTemperature;
  1649.   UCHAR                           ucMinAllowedBL_Level;
  1650.   USHORT                          usBootUpVDDCVoltage;        //In MV unit
  1651.   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
  1652.   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
  1653.   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
  1654.   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
  1655.   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
  1656.   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
  1657.   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
  1658.   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
  1659.   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
  1660.   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
  1661.   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
  1662.   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
  1663.   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
  1664.   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
  1665.   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
  1666.   USHORT                          usReferenceClock;           //In 10Khz unit  
  1667.   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
  1668.   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
  1669.   UCHAR                           ucDesign_ID;                //Indicate what is the board design
  1670.   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
  1671. }ATOM_FIRMWARE_INFO_V1_4;
  1672.  
  1673. #define ATOM_FIRMWARE_INFO_LAST  ATOM_FIRMWARE_INFO_V1_4
  1674.  
  1675. /****************************************************************************/ 
  1676. // Structures used in IntegratedSystemInfoTable
  1677. /****************************************************************************/ 
  1678. #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN      0x2
  1679. #define IGP_CAP_FLAG_AC_CARD               0x4
  1680. #define IGP_CAP_FLAG_SDVO_CARD             0x8
  1681. #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE     0x10
  1682.  
  1683. typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
  1684. {
  1685.   ATOM_COMMON_TABLE_HEADER        sHeader;
  1686.   ULONG                           ulBootUpEngineClock;              //in 10kHz unit
  1687.   ULONG                           ulBootUpMemoryClock;              //in 10kHz unit
  1688.   ULONG                           ulMaxSystemMemoryClock;           //in 10kHz unit
  1689.   ULONG                           ulMinSystemMemoryClock;           //in 10kHz unit
  1690.   UCHAR                           ucNumberOfCyclesInPeriodHi;
  1691.   UCHAR                           ucLCDTimingSel;             //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
  1692.   USHORT                          usReserved1;
  1693.   USHORT                          usInterNBVoltageLow;        //An intermidiate PMW value to set the voltage
  1694.   USHORT                          usInterNBVoltageHigh;       //Another intermidiate PMW value to set the voltage
  1695.   ULONG                           ulReserved[2];
  1696.  
  1697.   USHORT                                usFSBClock;                                 //In MHz unit
  1698.   USHORT                          usCapabilityFlag;                     //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
  1699.                                                                                                                                                               //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
  1700.                                                               //Bit[4]==1: P/2 mode, ==0: P/1 mode
  1701.   USHORT                                usPCIENBCfgReg7;                                    //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
  1702.   USHORT                                usK8MemoryClock;            //in MHz unit
  1703.   USHORT                                usK8SyncStartDelay;         //in 0.01 us unit
  1704.   USHORT                                usK8DataReturnTime;         //in 0.01 us unit
  1705.   UCHAR                           ucMaxNBVoltage;
  1706.   UCHAR                           ucMinNBVoltage;
  1707.   UCHAR                           ucMemoryType;                                       //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
  1708.   UCHAR                           ucNumberOfCyclesInPeriod;             //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
  1709.   UCHAR                           ucStartingPWM_HighTime;     //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
  1710.   UCHAR                           ucHTLinkWidth;              //16 bit vs. 8 bit
  1711.   UCHAR                           ucMaxNBVoltageHigh;    
  1712.   UCHAR                           ucMinNBVoltageHigh;
  1713. }ATOM_INTEGRATED_SYSTEM_INFO;
  1714.  
  1715. /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
  1716. ulBootUpMemoryClock:    For Intel IGP,it's the UMA system memory clock
  1717.                         For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
  1718. ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
  1719.                         For AMD IGP,for now this can be 0
  1720. ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
  1721.                         For AMD IGP,for now this can be 0
  1722.  
  1723. usFSBClock:             For Intel IGP,it's FSB Freq
  1724.                         For AMD IGP,it's HT Link Speed
  1725.  
  1726. usK8MemoryClock:        For AMD IGP only. For RevF CPU, set it to 200
  1727. usK8SyncStartDelay:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
  1728. usK8DataReturnTime:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
  1729.  
  1730. VC:Voltage Control
  1731. ucMaxNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
  1732. ucMinNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
  1733.  
  1734. ucNumberOfCyclesInPeriod:   Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
  1735. ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
  1736.  
  1737. ucMaxNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of  the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
  1738. ucMinNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
  1739.  
  1740.  
  1741. usInterNBVoltageLow:    Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
  1742. usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
  1743. */
  1744.  
  1745.  
  1746. /*
  1747. The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
  1748. Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
  1749. The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
  1750.  
  1751. SW components can access the IGP system infor structure in the same way as before
  1752. */
  1753.  
  1754.  
  1755. typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
  1756. {
  1757.   ATOM_COMMON_TABLE_HEADER   sHeader;
  1758.   ULONG                      ulBootUpEngineClock;       //in 10kHz unit
  1759.   ULONG                      ulReserved1[2];            //must be 0x0 for the reserved
  1760.   ULONG                      ulBootUpUMAClock;          //in 10kHz unit
  1761.   ULONG                      ulBootUpSidePortClock;     //in 10kHz unit
  1762.   ULONG                      ulMinSidePortClock;        //in 10kHz unit
  1763.   ULONG                      ulReserved2[6];            //must be 0x0 for the reserved
  1764.   ULONG                      ulSystemConfig;            //see explanation below
  1765.   ULONG                      ulBootUpReqDisplayVector;
  1766.   ULONG                      ulOtherDisplayMisc;
  1767.   ULONG                      ulDDISlot1Config;
  1768.   ULONG                      ulDDISlot2Config;
  1769.   UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
  1770.   UCHAR                      ucUMAChannelNumber;
  1771.   UCHAR                      ucDockingPinBit;
  1772.   UCHAR                      ucDockingPinPolarity;
  1773.   ULONG                      ulDockingPinCFGInfo;
  1774.   ULONG                      ulCPUCapInfo;
  1775.   USHORT                     usNumberOfCyclesInPeriod;
  1776.   USHORT                     usMaxNBVoltage;
  1777.   USHORT                     usMinNBVoltage;
  1778.   USHORT                     usBootUpNBVoltage;
  1779.   ULONG                      ulHTLinkFreq;              //in 10Khz
  1780.   USHORT                     usMinHTLinkWidth;
  1781.   USHORT                     usMaxHTLinkWidth;
  1782.   USHORT                     usUMASyncStartDelay;
  1783.   USHORT                     usUMADataReturnTime;
  1784.   USHORT                     usLinkStatusZeroTime;
  1785.   USHORT                     usReserved;
  1786.   ULONG                      ulHighVoltageHTLinkFreq;     // in 10Khz
  1787.   ULONG                      ulLowVoltageHTLinkFreq;      // in 10Khz
  1788.   USHORT                     usMaxUpStreamHTLinkWidth;
  1789.   USHORT                     usMaxDownStreamHTLinkWidth;
  1790.   USHORT                     usMinUpStreamHTLinkWidth;
  1791.   USHORT                     usMinDownStreamHTLinkWidth;
  1792.   ULONG                      ulReserved3[97];          //must be 0x0
  1793. }ATOM_INTEGRATED_SYSTEM_INFO_V2;  
  1794.  
  1795. /*
  1796. ulBootUpEngineClock:   Boot-up Engine Clock in 10Khz;
  1797. ulBootUpUMAClock:      Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
  1798. ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
  1799.  
  1800. ulSystemConfig:  
  1801. Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
  1802. Bit[1]=1: system boots up at AMD overdrived state or user customized  mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
  1803.       =0: system boots up at driver control state. Power state depends on PowerPlay table.
  1804. Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
  1805. Bit[3]=1: Only one power state(Performance) will be supported.
  1806.       =0: Multiple power states supported from PowerPlay table.
  1807. Bit[4]=1: CLMC is supported and enabled on current system.
  1808.       =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.  
  1809. Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.  
  1810.       =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
  1811. Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
  1812.       =0: Voltage settings is determined by powerplay table.
  1813. Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
  1814.       =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
  1815.  
  1816. ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
  1817.  
  1818. ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
  1819.                                       [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
  1820.  
  1821. ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
  1822.       [3:0]  - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
  1823.                         [7:4]  - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)                 
  1824.                         [15:8] - Lane configuration attribute;
  1825.       [23:16]- Connector type, possible value:
  1826.                CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
  1827.                CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
  1828.                CONNECTOR_OBJECT_ID_HDMI_TYPE_A
  1829.                CONNECTOR_OBJECT_ID_DISPLAYPORT
  1830.                         [31:24]- Reserved
  1831.  
  1832. ulDDISlot2Config: Same as Slot1.
  1833. ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
  1834. For IGP, Hypermemory is the only memory type showed in CCC.
  1835.  
  1836. ucUMAChannelNumber:  how many channels for the UMA;
  1837.  
  1838. ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
  1839. ucDockingPinBit:     which bit in this register to read the pin status;
  1840. ucDockingPinPolarity:Polarity of the pin when docked;
  1841.  
  1842. ulCPUCapInfo:        [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0
  1843.  
  1844. usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
  1845. usMaxNBVoltage:Voltage regulator dependent PWM value.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
  1846.  
  1847. usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
  1848. usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
  1849.                     GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
  1850.                     PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
  1851.                     GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
  1852.  
  1853.  
  1854. ulHTLinkFreq:       Bootup HT link Frequency in 10Khz.
  1855. usMinHTLinkWidth:   Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
  1856.                     If CDLW enabled, both upstream and downstream width should be the same during bootup.
  1857. usMaxHTLinkWidth:   Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
  1858.                     If CDLW enabled, both upstream and downstream width should be the same during bootup.  
  1859.  
  1860. usUMASyncStartDelay: Memory access latency, required for watermark calculation
  1861. usUMADataReturnTime: Memory access latency, required for watermark calculation
  1862. usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
  1863. for Griffin or Greyhound. SBIOS needs to convert to actual time by:
  1864.                      if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
  1865.                      if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
  1866.                      if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
  1867.                      if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
  1868.  
  1869. ulHighVoltageHTLinkFreq:     HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
  1870.                              This must be less than or equal to ulHTLinkFreq(bootup frequency).
  1871. ulLowVoltageHTLinkFreq:      HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
  1872.                              This must be less than or equal to ulHighVoltageHTLinkFreq.
  1873.  
  1874. usMaxUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
  1875. usMaxDownStreamHTLinkWidth:  same as above.
  1876. usMinUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
  1877. usMinDownStreamHTLinkWidth:  same as above.
  1878. */
  1879.  
  1880.  
  1881. #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE                 0x00000001
  1882. #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE             0x00000002
  1883. #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE                  0x00000004
  1884. #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY         0x00000008
  1885. #define SYSTEM_CONFIG_CLMC_ENABLED                        0x00000010
  1886. #define SYSTEM_CONFIG_CDLW_ENABLED                        0x00000020
  1887. #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED              0x00000040
  1888. #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED            0x00000080
  1889.  
  1890. #define IGP_DDI_SLOT_LANE_CONFIG_MASK                     0x000000FF
  1891.  
  1892. #define b0IGP_DDI_SLOT_LANE_MAP_MASK                      0x0F
  1893. #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK              0xF0
  1894. #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3                    0x01
  1895. #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7                    0x02
  1896. #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11                   0x04
  1897. #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15                  0x08
  1898.  
  1899. #define IGP_DDI_SLOT_ATTRIBUTE_MASK                       0x0000FF00
  1900. #define IGP_DDI_SLOT_CONFIG_REVERSED                      0x00000100
  1901. #define b1IGP_DDI_SLOT_CONFIG_REVERSED                    0x01
  1902.  
  1903. #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK                  0x00FF0000
  1904.  
  1905. #define ATOM_CRT_INT_ENCODER1_INDEX                       0x00000000
  1906. #define ATOM_LCD_INT_ENCODER1_INDEX                       0x00000001
  1907. #define ATOM_TV_INT_ENCODER1_INDEX                        0x00000002
  1908. #define ATOM_DFP_INT_ENCODER1_INDEX                       0x00000003
  1909. #define ATOM_CRT_INT_ENCODER2_INDEX                       0x00000004
  1910. #define ATOM_LCD_EXT_ENCODER1_INDEX                       0x00000005
  1911. #define ATOM_TV_EXT_ENCODER1_INDEX                        0x00000006
  1912. #define ATOM_DFP_EXT_ENCODER1_INDEX                       0x00000007
  1913. #define ATOM_CV_INT_ENCODER1_INDEX                        0x00000008
  1914. #define ATOM_DFP_INT_ENCODER2_INDEX                       0x00000009
  1915. #define ATOM_CRT_EXT_ENCODER1_INDEX                       0x0000000A
  1916. #define ATOM_CV_EXT_ENCODER1_INDEX                        0x0000000B
  1917. #define ATOM_DFP_INT_ENCODER3_INDEX                       0x0000000C
  1918. #define ATOM_DFP_INT_ENCODER4_INDEX                       0x0000000D
  1919.  
  1920. // define ASIC internal encoder id ( bit vector )
  1921. #define ASIC_INT_DAC1_ENCODER_ID                                                                                        0x00
  1922. #define ASIC_INT_TV_ENCODER_ID                                                                                                          0x02
  1923. #define ASIC_INT_DIG1_ENCODER_ID                                                                                                        0x03
  1924. #define ASIC_INT_DAC2_ENCODER_ID                                                                                                        0x04
  1925. #define ASIC_EXT_TV_ENCODER_ID                                                                                                          0x06
  1926. #define ASIC_INT_DVO_ENCODER_ID                                                                                                         0x07
  1927. #define ASIC_INT_DIG2_ENCODER_ID                                                                                                        0x09
  1928. #define ASIC_EXT_DIG_ENCODER_ID                                                                                                         0x05
  1929.  
  1930. //define Encoder attribute
  1931. #define ATOM_ANALOG_ENCODER                                                                                                                             0
  1932. #define ATOM_DIGITAL_ENCODER                                                                                                                    1              
  1933.  
  1934. #define ATOM_DEVICE_CRT1_INDEX                            0x00000000
  1935. #define ATOM_DEVICE_LCD1_INDEX                            0x00000001
  1936. #define ATOM_DEVICE_TV1_INDEX                             0x00000002
  1937. #define ATOM_DEVICE_DFP1_INDEX                            0x00000003
  1938. #define ATOM_DEVICE_CRT2_INDEX                            0x00000004
  1939. #define ATOM_DEVICE_LCD2_INDEX                            0x00000005
  1940. #define ATOM_DEVICE_TV2_INDEX                             0x00000006
  1941. #define ATOM_DEVICE_DFP2_INDEX                            0x00000007
  1942. #define ATOM_DEVICE_CV_INDEX                              0x00000008
  1943. #define ATOM_DEVICE_DFP3_INDEX                                                                                                          0x00000009
  1944. #define ATOM_DEVICE_DFP4_INDEX                                                                                                          0x0000000A
  1945. #define ATOM_DEVICE_DFP5_INDEX                                                                                                          0x0000000B
  1946. #define ATOM_DEVICE_RESERVEDC_INDEX                       0x0000000C
  1947. #define ATOM_DEVICE_RESERVEDD_INDEX                       0x0000000D
  1948. #define ATOM_DEVICE_RESERVEDE_INDEX                       0x0000000E
  1949. #define ATOM_DEVICE_RESERVEDF_INDEX                       0x0000000F
  1950. #define ATOM_MAX_SUPPORTED_DEVICE_INFO                    (ATOM_DEVICE_DFP3_INDEX+1)
  1951. #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2                  ATOM_MAX_SUPPORTED_DEVICE_INFO
  1952. #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3                  (ATOM_DEVICE_DFP5_INDEX + 1 )
  1953.  
  1954. #define ATOM_MAX_SUPPORTED_DEVICE                         (ATOM_DEVICE_RESERVEDF_INDEX+1)
  1955.  
  1956. #define ATOM_DEVICE_CRT1_SUPPORT                          (0x1L << ATOM_DEVICE_CRT1_INDEX )
  1957. #define ATOM_DEVICE_LCD1_SUPPORT                          (0x1L << ATOM_DEVICE_LCD1_INDEX )
  1958. #define ATOM_DEVICE_TV1_SUPPORT                           (0x1L << ATOM_DEVICE_TV1_INDEX  )
  1959. #define ATOM_DEVICE_DFP1_SUPPORT                          (0x1L << ATOM_DEVICE_DFP1_INDEX)
  1960. #define ATOM_DEVICE_CRT2_SUPPORT                          (0x1L << ATOM_DEVICE_CRT2_INDEX )
  1961. #define ATOM_DEVICE_LCD2_SUPPORT                          (0x1L << ATOM_DEVICE_LCD2_INDEX )
  1962. #define ATOM_DEVICE_TV2_SUPPORT                           (0x1L << ATOM_DEVICE_TV2_INDEX  )
  1963. #define ATOM_DEVICE_DFP2_SUPPORT                          (0x1L << ATOM_DEVICE_DFP2_INDEX)
  1964. #define ATOM_DEVICE_CV_SUPPORT                            (0x1L << ATOM_DEVICE_CV_INDEX   )
  1965. #define ATOM_DEVICE_DFP3_SUPPORT                                                                                                        (0x1L << ATOM_DEVICE_DFP3_INDEX )
  1966. #define ATOM_DEVICE_DFP4_SUPPORT                                                                                                        (0x1L << ATOM_DEVICE_DFP4_INDEX )
  1967. #define ATOM_DEVICE_DFP5_SUPPORT                                                                                                        (0x1L << ATOM_DEVICE_DFP5_INDEX )
  1968.  
  1969. #define ATOM_DEVICE_CRT_SUPPORT                           ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT
  1970. #define ATOM_DEVICE_DFP_SUPPORT                           ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT |  ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT
  1971. #define ATOM_DEVICE_TV_SUPPORT                            ATOM_DEVICE_TV1_SUPPORT  | ATOM_DEVICE_TV2_SUPPORT
  1972. #define ATOM_DEVICE_LCD_SUPPORT                           ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT
  1973.  
  1974. #define ATOM_DEVICE_CONNECTOR_TYPE_MASK                   0x000000F0
  1975. #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT                  0x00000004
  1976. #define ATOM_DEVICE_CONNECTOR_VGA                         0x00000001
  1977. #define ATOM_DEVICE_CONNECTOR_DVI_I                       0x00000002
  1978. #define ATOM_DEVICE_CONNECTOR_DVI_D                       0x00000003
  1979. #define ATOM_DEVICE_CONNECTOR_DVI_A                       0x00000004
  1980. #define ATOM_DEVICE_CONNECTOR_SVIDEO                      0x00000005
  1981. #define ATOM_DEVICE_CONNECTOR_COMPOSITE                   0x00000006
  1982. #define ATOM_DEVICE_CONNECTOR_LVDS                        0x00000007
  1983. #define ATOM_DEVICE_CONNECTOR_DIGI_LINK                   0x00000008
  1984. #define ATOM_DEVICE_CONNECTOR_SCART                       0x00000009
  1985. #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A                 0x0000000A
  1986. #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B                 0x0000000B
  1987. #define ATOM_DEVICE_CONNECTOR_CASE_1                      0x0000000E
  1988. #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT                 0x0000000F
  1989.  
  1990.  
  1991. #define ATOM_DEVICE_DAC_INFO_MASK                         0x0000000F
  1992. #define ATOM_DEVICE_DAC_INFO_SHIFT                        0x00000000
  1993. #define ATOM_DEVICE_DAC_INFO_NODAC                        0x00000000
  1994. #define ATOM_DEVICE_DAC_INFO_DACA                         0x00000001
  1995. #define ATOM_DEVICE_DAC_INFO_DACB                         0x00000002
  1996. #define ATOM_DEVICE_DAC_INFO_EXDAC                        0x00000003
  1997.  
  1998. #define ATOM_DEVICE_I2C_ID_NOI2C                          0x00000000
  1999.  
  2000. #define ATOM_DEVICE_I2C_LINEMUX_MASK                      0x0000000F
  2001. #define ATOM_DEVICE_I2C_LINEMUX_SHIFT                     0x00000000
  2002.  
  2003. #define ATOM_DEVICE_I2C_ID_MASK                           0x00000070
  2004. #define ATOM_DEVICE_I2C_ID_SHIFT                          0x00000004
  2005. #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE              0x00000001
  2006. #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE                  0x00000002
  2007. #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE                0x00000003    //For IGP RS600
  2008. #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL                 0x00000004    //For IGP RS690
  2009.  
  2010. #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK                 0x00000080
  2011. #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT                0x00000007
  2012. #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C            0x00000000
  2013. #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C            0x00000001
  2014.  
  2015. //  usDeviceSupport:
  2016. //  Bits0       = 0 - no CRT1 support= 1- CRT1 is supported
  2017. //  Bit 1       = 0 - no LCD1 support= 1- LCD1 is supported
  2018. //  Bit 2       = 0 - no TV1  support= 1- TV1  is supported
  2019. //  Bit 3       = 0 - no DFP1 support= 1- DFP1 is supported
  2020. //  Bit 4       = 0 - no CRT2 support= 1- CRT2 is supported
  2021. //  Bit 5       = 0 - no LCD2 support= 1- LCD2 is supported
  2022. //  Bit 6       = 0 - no TV2  support= 1- TV2  is supported
  2023. //  Bit 7       = 0 - no DFP2 support= 1- DFP2 is supported
  2024. //  Bit 8       = 0 - no CV   support= 1- CV   is supported
  2025. //  Bit 9       = 0 - no DFP3 support= 1- DFP3 is supported
  2026. //  Byte1 (Supported Device Info)
  2027. //  Bit 0       = = 0 - no CV support= 1- CV is supported
  2028. //  
  2029. //  
  2030.  
  2031. //              ucI2C_ConfigID
  2032. //    [7:0] - I2C LINE Associate ID
  2033. //          = 0   - no I2C
  2034. //    [7]               -       HW_Cap        = 1,  [6:0]=HW assisted I2C ID(HW line selection)
  2035. //                          =   0,  [6:0]=SW assisted I2C ID
  2036. //    [6-4]     - HW_ENGINE_ID  =       1,  HW engine for NON multimedia use
  2037. //                          =   2,      HW engine for Multimedia use
  2038. //                          =   3-7     Reserved for future I2C engines
  2039. //              [3-0] - I2C_LINE_MUX  = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
  2040.  
  2041. typedef struct _ATOM_I2C_ID_CONFIG
  2042. {
  2043.   UCHAR   bfI2C_LineMux:4;
  2044.   UCHAR   bfHW_EngineID:3;
  2045.   UCHAR   bfHW_Capable:1;
  2046. }ATOM_I2C_ID_CONFIG;
  2047.  
  2048. typedef union _ATOM_I2C_ID_CONFIG_ACCESS
  2049. {
  2050.   ATOM_I2C_ID_CONFIG sbfAccess;
  2051.   UCHAR              ucAccess;
  2052. }ATOM_I2C_ID_CONFIG_ACCESS;
  2053.    
  2054. /****************************************************************************/ 
  2055. // Structure used in GPIO_I2C_InfoTable
  2056. /****************************************************************************/ 
  2057. typedef struct _ATOM_GPIO_I2C_ASSIGMENT
  2058. {
  2059.   USHORT                    usClkMaskRegisterIndex;
  2060.   USHORT                    usClkEnRegisterIndex;
  2061.   USHORT                    usClkY_RegisterIndex;
  2062.   USHORT                    usClkA_RegisterIndex;
  2063.   USHORT                    usDataMaskRegisterIndex;
  2064.   USHORT                    usDataEnRegisterIndex;
  2065.   USHORT                    usDataY_RegisterIndex;
  2066.   USHORT                    usDataA_RegisterIndex;
  2067.   ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
  2068.   UCHAR                     ucClkMaskShift;
  2069.   UCHAR                     ucClkEnShift;
  2070.   UCHAR                     ucClkY_Shift;
  2071.   UCHAR                     ucClkA_Shift;
  2072.   UCHAR                     ucDataMaskShift;
  2073.   UCHAR                     ucDataEnShift;
  2074.   UCHAR                     ucDataY_Shift;
  2075.   UCHAR                     ucDataA_Shift;
  2076.   UCHAR                     ucReserved1;
  2077.   UCHAR                     ucReserved2;
  2078. }ATOM_GPIO_I2C_ASSIGMENT;
  2079.  
  2080. typedef struct _ATOM_GPIO_I2C_INFO
  2081. {
  2082.   ATOM_COMMON_TABLE_HEADER      sHeader;
  2083.   ATOM_GPIO_I2C_ASSIGMENT   asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
  2084. }ATOM_GPIO_I2C_INFO;
  2085.  
  2086. /****************************************************************************/ 
  2087. // Common Structure used in other structures
  2088. /****************************************************************************/ 
  2089.  
  2090. #ifndef _H2INC
  2091.  
  2092. //Please don't add or expand this bitfield structure below, this one will retire soon.!
  2093. typedef struct _ATOM_MODE_MISC_INFO
  2094. {
  2095.   USHORT HorizontalCutOff:1;
  2096.   USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
  2097.   USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
  2098.   USHORT VerticalCutOff:1;
  2099.   USHORT H_ReplicationBy2:1;
  2100.   USHORT V_ReplicationBy2:1;
  2101.   USHORT CompositeSync:1;
  2102.   USHORT Interlace:1;
  2103.   USHORT DoubleClock:1;
  2104.   USHORT RGB888:1;
  2105.   USHORT Reserved:6;          
  2106. }ATOM_MODE_MISC_INFO;
  2107.  
  2108. typedef union _ATOM_MODE_MISC_INFO_ACCESS
  2109. {
  2110.   ATOM_MODE_MISC_INFO sbfAccess;
  2111.   USHORT              usAccess;
  2112. }ATOM_MODE_MISC_INFO_ACCESS;
  2113.  
  2114. #else
  2115.  
  2116. typedef union _ATOM_MODE_MISC_INFO_ACCESS
  2117. {
  2118.   USHORT              usAccess;
  2119. }ATOM_MODE_MISC_INFO_ACCESS;
  2120.    
  2121. #endif
  2122.  
  2123. // usModeMiscInfo-
  2124. #define ATOM_H_CUTOFF           0x01
  2125. #define ATOM_HSYNC_POLARITY     0x02             //0=Active High, 1=Active Low
  2126. #define ATOM_VSYNC_POLARITY     0x04             //0=Active High, 1=Active Low
  2127. #define ATOM_V_CUTOFF           0x08
  2128. #define ATOM_H_REPLICATIONBY2   0x10
  2129. #define ATOM_V_REPLICATIONBY2   0x20
  2130. #define ATOM_COMPOSITESYNC      0x40
  2131. #define ATOM_INTERLACE          0x80
  2132. #define ATOM_DOUBLE_CLOCK_MODE  0x100
  2133. #define ATOM_RGB888_MODE        0x200
  2134.  
  2135. //usRefreshRate-
  2136. #define ATOM_REFRESH_43         43
  2137. #define ATOM_REFRESH_47         47
  2138. #define ATOM_REFRESH_56         56     
  2139. #define ATOM_REFRESH_60         60
  2140. #define ATOM_REFRESH_65         65
  2141. #define ATOM_REFRESH_70         70
  2142. #define ATOM_REFRESH_72         72
  2143. #define ATOM_REFRESH_75         75
  2144. #define ATOM_REFRESH_85         85
  2145.  
  2146. // ATOM_MODE_TIMING data are exactly the same as VESA timing data.
  2147. // Translation from EDID to ATOM_MODE_TIMING, use the following formula.
  2148. //
  2149. //      VESA_HTOTAL                     =       VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
  2150. //                                              =       EDID_HA + EDID_HBL
  2151. //      VESA_HDISP                      =       VESA_ACTIVE     =       EDID_HA
  2152. //      VESA_HSYNC_START        =       VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
  2153. //                                              =       EDID_HA + EDID_HSO
  2154. //      VESA_HSYNC_WIDTH        =       VESA_HSYNC_TIME =       EDID_HSPW
  2155. //      VESA_BORDER                     =       EDID_BORDER
  2156.  
  2157. /****************************************************************************/ 
  2158. // Structure used in SetCRTC_UsingDTDTimingTable
  2159. /****************************************************************************/ 
  2160. typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
  2161. {
  2162.   USHORT  usH_Size;
  2163.   USHORT  usH_Blanking_Time;
  2164.   USHORT  usV_Size;
  2165.   USHORT  usV_Blanking_Time;                   
  2166.   USHORT  usH_SyncOffset;
  2167.   USHORT  usH_SyncWidth;
  2168.   USHORT  usV_SyncOffset;
  2169.   USHORT  usV_SyncWidth;
  2170.   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;  
  2171.   UCHAR   ucH_Border;         // From DFP EDID
  2172.   UCHAR   ucV_Border;
  2173.   UCHAR   ucCRTC;             // ATOM_CRTC1 or ATOM_CRTC2  
  2174.   UCHAR   ucPadding[3];
  2175. }SET_CRTC_USING_DTD_TIMING_PARAMETERS;
  2176.  
  2177. /****************************************************************************/ 
  2178. // Structure used in SetCRTC_TimingTable
  2179. /****************************************************************************/ 
  2180. typedef struct _SET_CRTC_TIMING_PARAMETERS
  2181. {
  2182.   USHORT                      usH_Total;        // horizontal total
  2183.   USHORT                      usH_Disp;         // horizontal display
  2184.   USHORT                      usH_SyncStart;    // horozontal Sync start
  2185.   USHORT                      usH_SyncWidth;    // horizontal Sync width
  2186.   USHORT                      usV_Total;        // vertical total
  2187.   USHORT                      usV_Disp;         // vertical display
  2188.   USHORT                      usV_SyncStart;    // vertical Sync start
  2189.   USHORT                      usV_SyncWidth;    // vertical Sync width
  2190.   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
  2191.   UCHAR                       ucCRTC;           // ATOM_CRTC1 or ATOM_CRTC2
  2192.   UCHAR                       ucOverscanRight;  // right
  2193.   UCHAR                       ucOverscanLeft;   // left
  2194.   UCHAR                       ucOverscanBottom; // bottom
  2195.   UCHAR                       ucOverscanTop;    // top
  2196.   UCHAR                       ucReserved;
  2197. }SET_CRTC_TIMING_PARAMETERS;
  2198. #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
  2199.  
  2200. /****************************************************************************/ 
  2201. // Structure used in StandardVESA_TimingTable
  2202. //                   AnalogTV_InfoTable
  2203. //                   ComponentVideoInfoTable
  2204. /****************************************************************************/ 
  2205. typedef struct _ATOM_MODE_TIMING
  2206. {
  2207.   USHORT  usCRTC_H_Total;
  2208.   USHORT  usCRTC_H_Disp;
  2209.   USHORT  usCRTC_H_SyncStart;
  2210.   USHORT  usCRTC_H_SyncWidth;
  2211.   USHORT  usCRTC_V_Total;
  2212.   USHORT  usCRTC_V_Disp;
  2213.   USHORT  usCRTC_V_SyncStart;
  2214.   USHORT  usCRTC_V_SyncWidth;
  2215.   USHORT  usPixelClock;                                                  //in 10Khz unit
  2216.   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
  2217.   USHORT  usCRTC_OverscanRight;
  2218.   USHORT  usCRTC_OverscanLeft;
  2219.   USHORT  usCRTC_OverscanBottom;
  2220.   USHORT  usCRTC_OverscanTop;
  2221.   USHORT  usReserve;
  2222.   UCHAR   ucInternalModeNumber;
  2223.   UCHAR   ucRefreshRate;
  2224. }ATOM_MODE_TIMING;
  2225.  
  2226. typedef struct _ATOM_DTD_FORMAT
  2227. {
  2228.   USHORT  usPixClk;
  2229.   USHORT  usHActive;
  2230.   USHORT  usHBlanking_Time;
  2231.   USHORT  usVActive;
  2232.   USHORT  usVBlanking_Time;                    
  2233.   USHORT  usHSyncOffset;
  2234.   USHORT  usHSyncWidth;
  2235.   USHORT  usVSyncOffset;
  2236.   USHORT  usVSyncWidth;
  2237.   USHORT  usImageHSize;
  2238.   USHORT  usImageVSize;
  2239.   UCHAR   ucHBorder;
  2240.   UCHAR   ucVBorder;
  2241.   ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
  2242.   UCHAR   ucInternalModeNumber;
  2243.   UCHAR   ucRefreshRate;
  2244. }ATOM_DTD_FORMAT;
  2245.  
  2246. /****************************************************************************/ 
  2247. // Structure used in LVDS_InfoTable
  2248. //  * Need a document to describe this table
  2249. /****************************************************************************/ 
  2250. #define SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
  2251. #define SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
  2252. #define SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
  2253. #define SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
  2254.  
  2255. //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
  2256. //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
  2257. #define LCDPANEL_CAP_READ_EDID                                                                  0x1
  2258.  
  2259. //ucTableFormatRevision=1
  2260. //ucTableContentRevision=1
  2261. typedef struct _ATOM_LVDS_INFO
  2262. {
  2263.   ATOM_COMMON_TABLE_HEADER sHeader;  
  2264.   ATOM_DTD_FORMAT     sLCDTiming;
  2265.   USHORT              usModePatchTableOffset;
  2266.   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
  2267.   USHORT              usOffDelayInMs;
  2268.   UCHAR               ucPowerSequenceDigOntoDEin10Ms;
  2269.   UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
  2270.   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
  2271.                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
  2272.                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
  2273.                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
  2274.   UCHAR               ucPanelDefaultRefreshRate;
  2275.   UCHAR               ucPanelIdentification;
  2276.   UCHAR               ucSS_Id;
  2277. }ATOM_LVDS_INFO;
  2278.  
  2279. //ucTableFormatRevision=1
  2280. //ucTableContentRevision=2
  2281. typedef struct _ATOM_LVDS_INFO_V12
  2282. {
  2283.   ATOM_COMMON_TABLE_HEADER sHeader;  
  2284.   ATOM_DTD_FORMAT     sLCDTiming;
  2285.   USHORT              usExtInfoTableOffset;
  2286.   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
  2287.   USHORT              usOffDelayInMs;
  2288.   UCHAR               ucPowerSequenceDigOntoDEin10Ms;
  2289.   UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
  2290.   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
  2291.                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
  2292.                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
  2293.                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
  2294.   UCHAR               ucPanelDefaultRefreshRate;
  2295.   UCHAR               ucPanelIdentification;
  2296.   UCHAR               ucSS_Id;
  2297.   USHORT              usLCDVenderID;
  2298.   USHORT              usLCDProductID;
  2299.   UCHAR               ucLCDPanel_SpecialHandlingCap;
  2300.         UCHAR                                                           ucPanelInfoSize;                                        //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
  2301.   UCHAR               ucReserved[2];
  2302. }ATOM_LVDS_INFO_V12;
  2303.  
  2304. #define ATOM_LVDS_INFO_LAST  ATOM_LVDS_INFO_V12
  2305.  
  2306. typedef struct  _ATOM_PATCH_RECORD_MODE
  2307. {
  2308.   UCHAR     ucRecordType;
  2309.   USHORT    usHDisp;
  2310.   USHORT    usVDisp;
  2311. }ATOM_PATCH_RECORD_MODE;
  2312.  
  2313. typedef struct  _ATOM_LCD_RTS_RECORD
  2314. {
  2315.   UCHAR     ucRecordType;
  2316.   UCHAR     ucRTSValue;
  2317. }ATOM_LCD_RTS_RECORD;
  2318.  
  2319. //!! If the record below exits, it shoud always be the first record for easy use in command table!!!
  2320. typedef struct  _ATOM_LCD_MODE_CONTROL_CAP
  2321. {
  2322.   UCHAR     ucRecordType;
  2323.   USHORT    usLCDCap;
  2324. }ATOM_LCD_MODE_CONTROL_CAP;
  2325.  
  2326. #define LCD_MODE_CAP_BL_OFF                   1
  2327. #define LCD_MODE_CAP_CRTC_OFF                 2
  2328. #define LCD_MODE_CAP_PANEL_OFF                4
  2329.  
  2330. typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
  2331. {
  2332.   UCHAR ucRecordType;
  2333.   UCHAR ucFakeEDIDLength;
  2334.   UCHAR ucFakeEDIDString[1];    // This actually has ucFakeEdidLength elements.
  2335. } ATOM_FAKE_EDID_PATCH_RECORD;
  2336.  
  2337. typedef struct  _ATOM_PANEL_RESOLUTION_PATCH_RECORD
  2338. {
  2339.    UCHAR    ucRecordType;
  2340.    USHORT               usHSize;
  2341.    USHORT               usVSize;
  2342. }ATOM_PANEL_RESOLUTION_PATCH_RECORD;
  2343.  
  2344. #define LCD_MODE_PATCH_RECORD_MODE_TYPE       1
  2345. #define LCD_RTS_RECORD_TYPE                   2
  2346. #define LCD_CAP_RECORD_TYPE                   3
  2347. #define LCD_FAKE_EDID_PATCH_RECORD_TYPE       4
  2348. #define LCD_PANEL_RESOLUTION_RECORD_TYPE      5
  2349. #define ATOM_RECORD_END_TYPE                  0xFF
  2350.  
  2351. /****************************Spread Spectrum Info Table Definitions **********************/
  2352.  
  2353. //ucTableFormatRevision=1
  2354. //ucTableContentRevision=2
  2355. typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
  2356. {
  2357.   USHORT              usSpreadSpectrumPercentage;
  2358.   UCHAR               ucSpreadSpectrumType;         //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
  2359.   UCHAR               ucSS_Step;
  2360.   UCHAR               ucSS_Delay;
  2361.   UCHAR               ucSS_Id;
  2362.   UCHAR               ucRecommandedRef_Div;
  2363.   UCHAR               ucSS_Range;               //it was reserved for V11
  2364. }ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
  2365.  
  2366. #define ATOM_MAX_SS_ENTRY                      16
  2367. #define ATOM_DP_SS_ID1                                                                                           0x0f1                  // SS modulation freq=30k
  2368. #define ATOM_DP_SS_ID2                                                                                           0x0f2                  // SS modulation freq=33k
  2369.  
  2370.  
  2371. #define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
  2372. #define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
  2373. #define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
  2374. #define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
  2375. #define ATOM_INTERNAL_SS_MASK                  0x00000000
  2376. #define ATOM_EXTERNAL_SS_MASK                  0x00000002
  2377. #define EXEC_SS_STEP_SIZE_SHIFT                2
  2378. #define EXEC_SS_DELAY_SHIFT                    4    
  2379. #define ACTIVEDATA_TO_BLON_DELAY_SHIFT         4
  2380.  
  2381. typedef struct _ATOM_SPREAD_SPECTRUM_INFO
  2382. {
  2383.   ATOM_COMMON_TABLE_HEADER      sHeader;
  2384.   ATOM_SPREAD_SPECTRUM_ASSIGNMENT   asSS_Info[ATOM_MAX_SS_ENTRY];
  2385. }ATOM_SPREAD_SPECTRUM_INFO;
  2386.  
  2387. /****************************************************************************/ 
  2388. // Structure used in AnalogTV_InfoTable (Top level)
  2389. /****************************************************************************/ 
  2390. //ucTVBootUpDefaultStd definiton:
  2391.  
  2392. //ATOM_TV_NTSC                1
  2393. //ATOM_TV_NTSCJ               2
  2394. //ATOM_TV_PAL                 3
  2395. //ATOM_TV_PALM                4
  2396. //ATOM_TV_PALCN               5
  2397. //ATOM_TV_PALN                6
  2398. //ATOM_TV_PAL60               7
  2399. //ATOM_TV_SECAM               8
  2400.  
  2401. //ucTVSuppportedStd definition:
  2402. #define NTSC_SUPPORT          0x1
  2403. #define NTSCJ_SUPPORT         0x2
  2404.  
  2405. #define PAL_SUPPORT           0x4
  2406. #define PALM_SUPPORT          0x8
  2407. #define PALCN_SUPPORT         0x10
  2408. #define PALN_SUPPORT          0x20
  2409. #define PAL60_SUPPORT         0x40
  2410. #define SECAM_SUPPORT         0x80
  2411.  
  2412. #define MAX_SUPPORTED_TV_TIMING    2
  2413.  
  2414. typedef struct _ATOM_ANALOG_TV_INFO
  2415. {
  2416.   ATOM_COMMON_TABLE_HEADER sHeader;  
  2417.   UCHAR                    ucTV_SupportedStandard;
  2418.   UCHAR                    ucTV_BootUpDefaultStandard;
  2419.   UCHAR                    ucExt_TV_ASIC_ID;
  2420.   UCHAR                    ucExt_TV_ASIC_SlaveAddr;
  2421. /*   ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING]; */
  2422.   ATOM_MODE_TIMING         aModeTimings[MAX_SUPPORTED_TV_TIMING];
  2423. }ATOM_ANALOG_TV_INFO;
  2424.  
  2425.  
  2426. /**************************************************************************/
  2427. // VRAM usage and their defintions
  2428.  
  2429. // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
  2430. // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
  2431. // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
  2432. // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
  2433. // To Bios:  ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
  2434.  
  2435. #ifndef VESA_MEMORY_IN_64K_BLOCK
  2436. #define VESA_MEMORY_IN_64K_BLOCK        0x100       //256*64K=16Mb (Max. VESA memory is 16Mb!)
  2437. #endif
  2438.  
  2439. #define ATOM_EDID_RAW_DATASIZE          256         //In Bytes
  2440. #define ATOM_HWICON_SURFACE_SIZE        4096        //In Bytes
  2441. #define ATOM_HWICON_INFOTABLE_SIZE      32
  2442. #define MAX_DTD_MODE_IN_VRAM            6
  2443. #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE  (MAX_DTD_MODE_IN_VRAM*28)    //28= (SIZEOF ATOM_DTD_FORMAT)
  2444. #define ATOM_STD_MODE_SUPPORT_TBL_SIZE  32*8                         //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
  2445. #define DFP_ENCODER_TYPE_OFFSET                                 0x80
  2446. #define DP_ENCODER_LANE_NUM_OFFSET                      0x84
  2447. #define DP_ENCODER_LINK_RATE_OFFSET                     0x88
  2448.  
  2449. #define ATOM_HWICON1_SURFACE_ADDR       0
  2450. #define ATOM_HWICON2_SURFACE_ADDR       (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
  2451. #define ATOM_HWICON_INFOTABLE_ADDR      (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
  2452. #define ATOM_CRT1_EDID_ADDR             (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
  2453. #define ATOM_CRT1_DTD_MODE_TBL_ADDR     (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  2454. #define ATOM_CRT1_STD_MODE_TBL_ADDR         (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2455.  
  2456. #define ATOM_LCD1_EDID_ADDR             (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  2457. #define ATOM_LCD1_DTD_MODE_TBL_ADDR     (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  2458. #define ATOM_LCD1_STD_MODE_TBL_ADDR     (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2459.  
  2460. #define ATOM_TV1_DTD_MODE_TBL_ADDR      (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  2461.  
  2462. #define ATOM_DFP1_EDID_ADDR             (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2463. #define ATOM_DFP1_DTD_MODE_TBL_ADDR     (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  2464. #define ATOM_DFP1_STD_MODE_TBL_ADDR         (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2465.  
  2466. #define ATOM_CRT2_EDID_ADDR             (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  2467. #define ATOM_CRT2_DTD_MODE_TBL_ADDR     (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  2468. #define ATOM_CRT2_STD_MODE_TBL_ADDR         (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2469.  
  2470. #define ATOM_LCD2_EDID_ADDR             (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  2471. #define ATOM_LCD2_DTD_MODE_TBL_ADDR     (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  2472. #define ATOM_LCD2_STD_MODE_TBL_ADDR     (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2473.  
  2474. #define ATOM_TV2_EDID_ADDR              (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  2475. #define ATOM_TV2_DTD_MODE_TBL_ADDR      (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  2476. #define ATOM_TV2_STD_MODE_TBL_ADDR        (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2477.  
  2478. #define ATOM_DFP2_EDID_ADDR             (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  2479. #define ATOM_DFP2_DTD_MODE_TBL_ADDR     (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  2480. #define ATOM_DFP2_STD_MODE_TBL_ADDR     (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2481.  
  2482. #define ATOM_CV_EDID_ADDR               (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  2483. #define ATOM_CV_DTD_MODE_TBL_ADDR       (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  2484. #define ATOM_CV_STD_MODE_TBL_ADDR       (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2485.  
  2486. #define ATOM_DFP3_EDID_ADDR             (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  2487. #define ATOM_DFP3_DTD_MODE_TBL_ADDR     (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  2488. #define ATOM_DFP3_STD_MODE_TBL_ADDR     (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2489.  
  2490. #define ATOM_DFP4_EDID_ADDR             (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  2491. #define ATOM_DFP4_DTD_MODE_TBL_ADDR     (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  2492. #define ATOM_DFP4_STD_MODE_TBL_ADDR     (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2493.  
  2494. #define ATOM_DFP5_EDID_ADDR             (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  2495. #define ATOM_DFP5_DTD_MODE_TBL_ADDR     (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  2496. #define ATOM_DFP5_STD_MODE_TBL_ADDR     (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  2497.  
  2498. #define ATOM_DP_TRAINING_TBL_ADDR                               (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE)      
  2499.  
  2500. #define ATOM_STACK_STORAGE_START        (ATOM_DP_TRAINING_TBL_ADDR+256)      
  2501. #define ATOM_STACK_STORAGE_END          ATOM_STACK_STORAGE_START+512        
  2502.  
  2503. //The size below is in Kb!
  2504. #define ATOM_VRAM_RESERVE_SIZE         ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
  2505.    
  2506. #define ATOM_VRAM_OPERATION_FLAGS_MASK         0xC0000000L
  2507. #define ATOM_VRAM_OPERATION_FLAGS_SHIFT        30
  2508. #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION   0x1
  2509. #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION      0x0
  2510.  
  2511. /***********************************************************************************/  
  2512. // Structure used in VRAM_UsageByFirmwareTable
  2513. // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
  2514. //        at running time.  
  2515. // note2: From RV770, the memory is more than 32bit addressable, so we will change
  2516. //        ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
  2517. //        exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
  2518. //        (in offset to start of memory address) is KB aligned instead of byte aligend.
  2519. /***********************************************************************************/  
  2520. #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO                       1
  2521.  
  2522. typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
  2523. {
  2524.   ULONG   ulStartAddrUsedByFirmware;
  2525.   USHORT  usFirmwareUseInKb;
  2526.   USHORT  usReserved;
  2527. }ATOM_FIRMWARE_VRAM_RESERVE_INFO;
  2528.  
  2529. typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
  2530. {
  2531.   ATOM_COMMON_TABLE_HEADER sHeader;  
  2532.   ATOM_FIRMWARE_VRAM_RESERVE_INFO       asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
  2533. }ATOM_VRAM_USAGE_BY_FIRMWARE;
  2534.  
  2535. /****************************************************************************/ 
  2536. // Structure used in GPIO_Pin_LUTTable
  2537. /****************************************************************************/ 
  2538. typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
  2539. {
  2540.   USHORT                   usGpioPin_AIndex;
  2541.   UCHAR                    ucGpioPinBitShift;
  2542.   UCHAR                    ucGPIO_ID;
  2543. }ATOM_GPIO_PIN_ASSIGNMENT;
  2544.  
  2545. typedef struct _ATOM_GPIO_PIN_LUT
  2546. {
  2547.   ATOM_COMMON_TABLE_HEADER  sHeader;
  2548.   ATOM_GPIO_PIN_ASSIGNMENT      asGPIO_Pin[1];
  2549. }ATOM_GPIO_PIN_LUT;
  2550.  
  2551. /****************************************************************************/ 
  2552. // Structure used in ComponentVideoInfoTable   
  2553. /****************************************************************************/ 
  2554. #define GPIO_PIN_ACTIVE_HIGH          0x1
  2555.  
  2556. #define MAX_SUPPORTED_CV_STANDARDS    5
  2557.  
  2558. // definitions for ATOM_D_INFO.ucSettings
  2559. #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK  0x1F    // [4:0]
  2560. #define ATOM_GPIO_SETTINGS_RESERVED_MASK  0x60    // [6:5] = must be zeroed out
  2561. #define ATOM_GPIO_SETTINGS_ACTIVE_MASK    0x80    // [7]
  2562.  
  2563. typedef struct _ATOM_GPIO_INFO
  2564. {
  2565.   USHORT  usAOffset;
  2566.   UCHAR   ucSettings;
  2567.   UCHAR   ucReserved;
  2568. }ATOM_GPIO_INFO;
  2569.  
  2570. // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
  2571. #define ATOM_CV_RESTRICT_FORMAT_SELECTION           0x2
  2572.  
  2573. // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
  2574. #define ATOM_GPIO_DEFAULT_MODE_EN                   0x80 //[7];
  2575. #define ATOM_GPIO_SETTING_PERMODE_MASK              0x7F //[6:0]
  2576.  
  2577. // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
  2578. //Line 3 out put 5V.
  2579. #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A       0x01     //represent gpio 3 state for 16:9
  2580. #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B       0x02     //represent gpio 4 state for 16:9
  2581. #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT   0x0  
  2582.  
  2583. //Line 3 out put 2.2V              
  2584. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04     //represent gpio 3 state for 4:3 Letter box
  2585. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08     //represent gpio 4 state for 4:3 Letter box
  2586. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2    
  2587.  
  2588. //Line 3 out put 0V
  2589. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A        0x10     //represent gpio 3 state for 4:3
  2590. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B        0x20     //represent gpio 4 state for 4:3
  2591. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT    0x4
  2592.  
  2593. #define ATOM_CV_LINE3_ASPECTRATIO_MASK              0x3F     // bit [5:0]
  2594.  
  2595. #define ATOM_CV_LINE3_ASPECTRATIO_EXIST             0x80     //bit 7
  2596.  
  2597. //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
  2598. #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A   3   //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
  2599. #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B   4   //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
  2600.  
  2601.  
  2602. typedef struct _ATOM_COMPONENT_VIDEO_INFO
  2603. {
  2604.   ATOM_COMMON_TABLE_HEADER sHeader;
  2605.   USHORT             usMask_PinRegisterIndex;
  2606.   USHORT             usEN_PinRegisterIndex;
  2607.   USHORT             usY_PinRegisterIndex;
  2608.   USHORT             usA_PinRegisterIndex;
  2609.   UCHAR              ucBitShift;
  2610.   UCHAR              ucPinActiveState;  //ucPinActiveState: Bit0=1 active high, =0 active low
  2611.   ATOM_DTD_FORMAT    sReserved;         // must be zeroed out
  2612.   UCHAR              ucMiscInfo;
  2613.   UCHAR              uc480i;
  2614.   UCHAR              uc480p;
  2615.   UCHAR              uc720p;
  2616.   UCHAR              uc1080i;
  2617.   UCHAR              ucLetterBoxMode;
  2618.   UCHAR              ucReserved[3];
  2619.   UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
  2620.   ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
  2621.   ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
  2622. }ATOM_COMPONENT_VIDEO_INFO;
  2623.  
  2624. //ucTableFormatRevision=2
  2625. //ucTableContentRevision=1
  2626. typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
  2627. {
  2628.   ATOM_COMMON_TABLE_HEADER sHeader;
  2629.   UCHAR              ucMiscInfo;
  2630.   UCHAR              uc480i;
  2631.   UCHAR              uc480p;
  2632.   UCHAR              uc720p;
  2633.   UCHAR              uc1080i;
  2634.   UCHAR              ucReserved;
  2635.   UCHAR              ucLetterBoxMode;
  2636.   UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
  2637.   ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
  2638.   ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
  2639. }ATOM_COMPONENT_VIDEO_INFO_V21;
  2640.  
  2641. #define ATOM_COMPONENT_VIDEO_INFO_LAST  ATOM_COMPONENT_VIDEO_INFO_V21
  2642.  
  2643. /****************************************************************************/ 
  2644. // Structure used in object_InfoTable
  2645. /****************************************************************************/ 
  2646. typedef struct _ATOM_OBJECT_HEADER
  2647. {
  2648.   ATOM_COMMON_TABLE_HEADER      sHeader;
  2649.   USHORT                    usDeviceSupport;
  2650.   USHORT                    usConnectorObjectTableOffset;
  2651.   USHORT                    usRouterObjectTableOffset;
  2652.   USHORT                    usEncoderObjectTableOffset;
  2653.   USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
  2654.   USHORT                    usDisplayPathTableOffset;
  2655. }ATOM_OBJECT_HEADER;
  2656.  
  2657.  
  2658. typedef struct  _ATOM_DISPLAY_OBJECT_PATH
  2659. {
  2660.   USHORT    usDeviceTag;                                   //supported device
  2661.   USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
  2662.   USHORT    usConnObjectId;                                //Connector Object ID
  2663.   USHORT    usGPUObjectId;                                 //GPU ID
  2664.   USHORT    usGraphicObjIds[1];                             //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
  2665. }ATOM_DISPLAY_OBJECT_PATH;
  2666.  
  2667. typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
  2668. {
  2669.   UCHAR                           ucNumOfDispPath;
  2670.   UCHAR                           ucVersion;
  2671.   UCHAR                           ucPadding[2];
  2672.   ATOM_DISPLAY_OBJECT_PATH        asDispPath[1];
  2673. }ATOM_DISPLAY_OBJECT_PATH_TABLE;
  2674.  
  2675.  
  2676. typedef struct _ATOM_OBJECT                                //each object has this structure    
  2677. {
  2678.   USHORT              usObjectID;
  2679.   USHORT              usSrcDstTableOffset;
  2680.   USHORT              usRecordOffset;                     //this pointing to a bunch of records defined below
  2681.   USHORT              usReserved;
  2682. }ATOM_OBJECT;
  2683.  
  2684. typedef struct _ATOM_OBJECT_TABLE                         //Above 4 object table offset pointing to a bunch of objects all have this structure    
  2685. {
  2686.   UCHAR               ucNumberOfObjects;
  2687.   UCHAR               ucPadding[3];
  2688.   ATOM_OBJECT         asObjects[1];
  2689. }ATOM_OBJECT_TABLE;
  2690.  
  2691. typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT         //usSrcDstTableOffset pointing to this structure
  2692. {
  2693.   UCHAR               ucNumberOfSrc;
  2694.   USHORT              usSrcObjectID[1];
  2695.   UCHAR               ucNumberOfDst;
  2696.   USHORT              usDstObjectID[1];
  2697. }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
  2698.  
  2699.  
  2700. //Related definitions, all records are differnt but they have a commond header
  2701. typedef struct _ATOM_COMMON_RECORD_HEADER
  2702. {
  2703.   UCHAR               ucRecordType;                      //An emun to indicate the record type
  2704.   UCHAR               ucRecordSize;                      //The size of the whole record in byte
  2705. }ATOM_COMMON_RECORD_HEADER;
  2706.  
  2707.  
  2708. #define ATOM_I2C_RECORD_TYPE                           1        
  2709. #define ATOM_HPD_INT_RECORD_TYPE                       2
  2710. #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE             3
  2711. #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE          4
  2712. #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE             5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
  2713. #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE          6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
  2714. #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE      7
  2715. #define ATOM_JTAG_RECORD_TYPE                          8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
  2716. #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE              9
  2717. #define ATOM_ENCODER_DVO_CF_RECORD_TYPE               10
  2718. #define ATOM_CONNECTOR_CF_RECORD_TYPE                 11
  2719. #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE       12
  2720. #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE  13
  2721. #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE                         14
  2722. #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE                                  15
  2723.  
  2724. //Must be updated when new record type is added,equal to that record definition!
  2725. #define ATOM_MAX_OBJECT_RECORD_NUMBER             ATOM_CONNECTOR_CF_RECORD_TYPE    
  2726.  
  2727. typedef struct  _ATOM_I2C_RECORD
  2728. {
  2729.   ATOM_COMMON_RECORD_HEADER   sheader;
  2730.   ATOM_I2C_ID_CONFIG          sucI2cId;
  2731.   UCHAR                       ucI2CAddr;              //The slave address, it's 0 when the record is attached to connector for DDC
  2732. }ATOM_I2C_RECORD;
  2733.  
  2734. typedef struct  _ATOM_HPD_INT_RECORD
  2735. {
  2736.   ATOM_COMMON_RECORD_HEADER   sheader;
  2737.   UCHAR                       ucHPDIntGPIOID;         //Corresponding block in GPIO_PIN_INFO table gives the pin info          
  2738.   UCHAR                       ucPluggged_PinState;
  2739. }ATOM_HPD_INT_RECORD;
  2740.  
  2741.  
  2742. typedef struct  _ATOM_OUTPUT_PROTECTION_RECORD
  2743. {
  2744.   ATOM_COMMON_RECORD_HEADER   sheader;
  2745.   UCHAR                       ucProtectionFlag;
  2746.   UCHAR                       ucReserved;
  2747. }ATOM_OUTPUT_PROTECTION_RECORD;
  2748.  
  2749. typedef struct  _ATOM_CONNECTOR_DEVICE_TAG
  2750. {
  2751.   ULONG                       ulACPIDeviceEnum;       //Reserved for now
  2752.   USHORT                      usDeviceID;             //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
  2753.   USHORT                      usPadding;
  2754. }ATOM_CONNECTOR_DEVICE_TAG;
  2755.  
  2756. typedef struct  _ATOM_CONNECTOR_DEVICE_TAG_RECORD
  2757. {
  2758.   ATOM_COMMON_RECORD_HEADER   sheader;
  2759.   UCHAR                       ucNumberOfDevice;
  2760.   UCHAR                       ucReserved;
  2761.   ATOM_CONNECTOR_DEVICE_TAG   asDeviceTag[1];         //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
  2762. }ATOM_CONNECTOR_DEVICE_TAG_RECORD;
  2763.  
  2764.  
  2765. typedef struct  _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
  2766. {
  2767.   ATOM_COMMON_RECORD_HEADER   sheader;
  2768.   UCHAR                                                     ucConfigGPIOID;
  2769.   UCHAR                                                     ucConfigGPIOState;      //Set to 1 when it's active high to enable external flow in
  2770.   UCHAR                       ucFlowinGPIPID;
  2771.   UCHAR                       ucExtInGPIPID;
  2772. }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
  2773.  
  2774. typedef struct  _ATOM_ENCODER_FPGA_CONTROL_RECORD
  2775. {
  2776.   ATOM_COMMON_RECORD_HEADER   sheader;
  2777.   UCHAR                       ucCTL1GPIO_ID;
  2778.   UCHAR                       ucCTL1GPIOState;        //Set to 1 when it's active high
  2779.   UCHAR                       ucCTL2GPIO_ID;
  2780.   UCHAR                       ucCTL2GPIOState;        //Set to 1 when it's active high
  2781.   UCHAR                       ucCTL3GPIO_ID;
  2782.   UCHAR                       ucCTL3GPIOState;        //Set to 1 when it's active high
  2783.   UCHAR                       ucCTLFPGA_IN_ID;
  2784.   UCHAR                       ucPadding[3];
  2785. }ATOM_ENCODER_FPGA_CONTROL_RECORD;
  2786.  
  2787. typedef struct  _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
  2788. {
  2789.   ATOM_COMMON_RECORD_HEADER   sheader;
  2790.   UCHAR                       ucGPIOID;               //Corresponding block in GPIO_PIN_INFO table gives the pin info
  2791.   UCHAR                       ucTVActiveState;        //Indicating when the pin==0 or 1 when TV is connected
  2792. }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
  2793.  
  2794. typedef struct  _ATOM_JTAG_RECORD
  2795. {
  2796.   ATOM_COMMON_RECORD_HEADER   sheader;
  2797.   UCHAR                       ucTMSGPIO_ID;
  2798.   UCHAR                       ucTMSGPIOState;         //Set to 1 when it's active high
  2799.   UCHAR                       ucTCKGPIO_ID;
  2800.   UCHAR                       ucTCKGPIOState;         //Set to 1 when it's active high
  2801.   UCHAR                       ucTDOGPIO_ID;
  2802.   UCHAR                       ucTDOGPIOState;         //Set to 1 when it's active high
  2803.   UCHAR                       ucTDIGPIO_ID;
  2804.   UCHAR                       ucTDIGPIOState;         //Set to 1 when it's active high
  2805.   UCHAR                       ucPadding[2];
  2806. }ATOM_JTAG_RECORD;
  2807.  
  2808.  
  2809. //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
  2810. typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
  2811. {
  2812.   UCHAR                       ucGPIOID;               // GPIO_ID, find the corresponding ID in GPIO_LUT table
  2813.   UCHAR                       ucGPIO_PinState;        // Pin state showing how to set-up the pin
  2814. }ATOM_GPIO_PIN_CONTROL_PAIR;
  2815.  
  2816. typedef struct  _ATOM_OBJECT_GPIO_CNTL_RECORD
  2817. {
  2818.   ATOM_COMMON_RECORD_HEADER   sheader;
  2819.   UCHAR                       ucFlags;                // Future expnadibility
  2820.   UCHAR                       ucNumberOfPins;         // Number of GPIO pins used to control the object
  2821.   ATOM_GPIO_PIN_CONTROL_PAIR  asGpio[1];              // the real gpio pin pair determined by number of pins ucNumberOfPins
  2822. }ATOM_OBJECT_GPIO_CNTL_RECORD;
  2823.  
  2824. //Definitions for GPIO pin state
  2825. #define GPIO_PIN_TYPE_INPUT             0x00
  2826. #define GPIO_PIN_TYPE_OUTPUT            0x10
  2827. #define GPIO_PIN_TYPE_HW_CONTROL        0x20
  2828.  
  2829. //For GPIO_PIN_TYPE_OUTPUT the following is defined
  2830. #define GPIO_PIN_OUTPUT_STATE_MASK      0x01
  2831. #define GPIO_PIN_OUTPUT_STATE_SHIFT     0
  2832. #define GPIO_PIN_STATE_ACTIVE_LOW       0x0
  2833. #define GPIO_PIN_STATE_ACTIVE_HIGH      0x1
  2834.  
  2835. typedef struct  _ATOM_ENCODER_DVO_CF_RECORD
  2836. {
  2837.   ATOM_COMMON_RECORD_HEADER   sheader;
  2838.   ULONG                       ulStrengthControl;      // DVOA strength control for CF
  2839.   UCHAR                       ucPadding[2];
  2840. }ATOM_ENCODER_DVO_CF_RECORD;
  2841.  
  2842. // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
  2843. #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA   1
  2844. #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB   2
  2845.  
  2846. typedef struct  _ATOM_CONNECTOR_CF_RECORD
  2847. {
  2848.   ATOM_COMMON_RECORD_HEADER   sheader;
  2849.   USHORT                      usMaxPixClk;
  2850.   UCHAR                       ucFlowCntlGpioId;
  2851.   UCHAR                       ucSwapCntlGpioId;
  2852.   UCHAR                       ucConnectedDvoBundle;
  2853.   UCHAR                       ucPadding;
  2854. }ATOM_CONNECTOR_CF_RECORD;
  2855.  
  2856. typedef struct  _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
  2857. {
  2858.   ATOM_COMMON_RECORD_HEADER   sheader;
  2859.         ATOM_DTD_FORMAT                                                 asTiming;
  2860. }ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
  2861.  
  2862. typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
  2863. {
  2864.   ATOM_COMMON_RECORD_HEADER   sheader;                //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
  2865.   UCHAR                       ucSubConnectorType;     //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
  2866.   UCHAR                       ucReserved;
  2867. }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
  2868.  
  2869.  
  2870. typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
  2871. {
  2872.         ATOM_COMMON_RECORD_HEADER   sheader;                
  2873.         UCHAR                                                                                           ucMuxType;                                                      //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
  2874.         UCHAR                                                                                           ucMuxControlPin;
  2875.         UCHAR                                                                                           ucMuxState[2];                                  //for alligment purpose
  2876. }ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
  2877.  
  2878. typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
  2879. {
  2880.         ATOM_COMMON_RECORD_HEADER   sheader;                
  2881.         UCHAR                                                                                           ucMuxType;
  2882.         UCHAR                                                                                           ucMuxControlPin;
  2883.         UCHAR                                                                                           ucMuxState[2];                                  //for alligment purpose
  2884. }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
  2885.  
  2886. // define ucMuxType
  2887. #define ATOM_ROUTER_MUX_PIN_STATE_MASK                                                          0x0f
  2888. #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT             0x01
  2889.  
  2890. /****************************************************************************/ 
  2891. // ASIC voltage data table
  2892. /****************************************************************************/ 
  2893. typedef struct  _ATOM_VOLTAGE_INFO_HEADER
  2894. {
  2895.    USHORT   usVDDCBaseLevel;                //In number of 50mv unit
  2896.    USHORT   usReserved;                     //For possible extension table offset
  2897.    UCHAR    ucNumOfVoltageEntries;
  2898.    UCHAR    ucBytesPerVoltageEntry;
  2899.    UCHAR    ucVoltageStep;                  //Indicating in how many mv increament is one step, 0.5mv unit
  2900.    UCHAR    ucDefaultVoltageEntry;
  2901.    UCHAR    ucVoltageControlI2cLine;
  2902.    UCHAR    ucVoltageControlAddress;
  2903.    UCHAR    ucVoltageControlOffset;
  2904. }ATOM_VOLTAGE_INFO_HEADER;
  2905.  
  2906. typedef struct  _ATOM_VOLTAGE_INFO
  2907. {
  2908.    ATOM_COMMON_TABLE_HEADER     sHeader;
  2909.    ATOM_VOLTAGE_INFO_HEADER viHeader;
  2910.    UCHAR    ucVoltageEntries[64];            //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
  2911. }ATOM_VOLTAGE_INFO;
  2912.  
  2913.  
  2914. typedef struct  _ATOM_VOLTAGE_FORMULA
  2915. {
  2916.    USHORT   usVoltageBaseLevel;             // In number of 1mv unit
  2917.    USHORT   usVoltageStep;                  // Indicating in how many mv increament is one step, 1mv unit
  2918.          UCHAR          ucNumOfVoltageEntries;                                  // Number of Voltage Entry, which indicate max Voltage
  2919.          UCHAR          ucFlag;                                                                                                 // bit0=0 :step is 1mv =1 0.5mv
  2920.          UCHAR          ucBaseVID;                                                                                      // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
  2921.          UCHAR          ucReserved;
  2922.          UCHAR          ucVIDAdjustEntries[32];                                 // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
  2923. }ATOM_VOLTAGE_FORMULA;
  2924.  
  2925. typedef struct _ATOM_VOLTAGE_CONTROL
  2926. {
  2927.         UCHAR            ucVoltageControlId;                                                    //Indicate it is controlled by I2C or GPIO or HW state machine         
  2928.   UCHAR    ucVoltageControlI2cLine;
  2929.   UCHAR    ucVoltageControlAddress;
  2930.   UCHAR    ucVoltageControlOffset;             
  2931.   USHORT   usGpioPin_AIndex;                                                            //GPIO_PAD register index
  2932.   UCHAR    ucGpioPinBitShift[9];                                                //at most 8 pin support 255 VIDs, termintate with 0xff
  2933.         UCHAR            ucReserved;
  2934. }ATOM_VOLTAGE_CONTROL;
  2935.  
  2936. // Define ucVoltageControlId
  2937. #define VOLTAGE_CONTROLLED_BY_HW                                                        0x00
  2938. #define VOLTAGE_CONTROLLED_BY_I2C_MASK                          0x7F
  2939. #define VOLTAGE_CONTROLLED_BY_GPIO                                              0x80
  2940. #define VOLTAGE_CONTROL_ID_LM64                                                         0x01                                                                    //I2C control, used for R5xx Core Voltage
  2941. #define VOLTAGE_CONTROL_ID_DAC                                                          0x02                                                                    //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
  2942. #define VOLTAGE_CONTROL_ID_VT116xM                                              0x03                                                                    //I2C control, used for R6xx Core Voltage
  2943. #define VOLTAGE_CONTROL_ID_DS4402                                                       0x04                                                                   
  2944.  
  2945. typedef struct  _ATOM_VOLTAGE_OBJECT
  2946. {
  2947.          UCHAR          ucVoltageType;                                                                  //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI  
  2948.          UCHAR          ucSize;                                                                                                 //Size of Object       
  2949.          ATOM_VOLTAGE_CONTROL                   asControl;                      //describ how to control        
  2950.          ATOM_VOLTAGE_FORMULA                   asFormula;                      //Indicate How to convert real Voltage to VID
  2951. }ATOM_VOLTAGE_OBJECT;
  2952.  
  2953. typedef struct  _ATOM_VOLTAGE_OBJECT_INFO
  2954. {
  2955.    ATOM_COMMON_TABLE_HEADER     sHeader;
  2956.          ATOM_VOLTAGE_OBJECT                    asVoltageObj[3];        //Info for Voltage control               
  2957. }ATOM_VOLTAGE_OBJECT_INFO;
  2958.  
  2959. typedef struct  _ATOM_LEAKID_VOLTAGE
  2960. {
  2961.         UCHAR           ucLeakageId;
  2962.         UCHAR           ucReserved;
  2963.         USHORT  usVoltage;
  2964. }ATOM_LEAKID_VOLTAGE;
  2965.  
  2966. typedef struct  _ATOM_ASIC_PROFILE_VOLTAGE
  2967. {
  2968.         UCHAR           ucProfileId;
  2969.         UCHAR           ucReserved;
  2970.         USHORT  usSize;
  2971.         USHORT  usEfuseSpareStartAddr;
  2972.         USHORT  usFuseIndex[8];                                                                                         //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
  2973.         ATOM_LEAKID_VOLTAGE                                     asLeakVol[2];                   //Leakid and relatd voltage
  2974. }ATOM_ASIC_PROFILE_VOLTAGE;
  2975.  
  2976. //ucProfileId
  2977. #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE                      1              
  2978. #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE                  1
  2979. #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE                                      2
  2980.  
  2981. typedef struct  _ATOM_ASIC_PROFILING_INFO
  2982. {
  2983.   ATOM_COMMON_TABLE_HEADER                      asHeader;
  2984.         ATOM_ASIC_PROFILE_VOLTAGE                       asVoltage;
  2985. }ATOM_ASIC_PROFILING_INFO;
  2986.  
  2987. typedef struct _ATOM_POWER_SOURCE_OBJECT
  2988. {
  2989.         UCHAR   ucPwrSrcId;                                                                                                     // Power source
  2990.         UCHAR   ucPwrSensorType;                                                                                // GPIO, I2C or none
  2991.         UCHAR   ucPwrSensId;                                                                                      // if GPIO detect, it is GPIO id,  if I2C detect, it is I2C id
  2992.         UCHAR   ucPwrSensSlaveAddr;                                                                     // Slave address if I2C detect
  2993.         UCHAR ucPwrSensRegIndex;                                                                        // I2C register Index if I2C detect
  2994.         UCHAR ucPwrSensRegBitMask;                                                              // detect which bit is used if I2C detect
  2995.         UCHAR   ucPwrSensActiveState;                                                           // high active or low active
  2996.         UCHAR   ucReserve[3];                                                                                           // reserve             
  2997.         USHORT usSensPwr;                                                                                                       // in unit of watt
  2998. }ATOM_POWER_SOURCE_OBJECT;
  2999.  
  3000. typedef struct _ATOM_POWER_SOURCE_INFO
  3001. {
  3002.                 ATOM_COMMON_TABLE_HEADER                asHeader;
  3003.                 UCHAR                                                                                           asPwrbehave[16];
  3004.                 ATOM_POWER_SOURCE_OBJECT                asPwrObj[1];
  3005. }ATOM_POWER_SOURCE_INFO;
  3006.  
  3007.  
  3008. //Define ucPwrSrcId
  3009. #define POWERSOURCE_PCIE_ID1                                            0x00
  3010. #define POWERSOURCE_6PIN_CONNECTOR_ID1  0x01
  3011. #define POWERSOURCE_8PIN_CONNECTOR_ID1  0x02
  3012. #define POWERSOURCE_6PIN_CONNECTOR_ID2  0x04
  3013. #define POWERSOURCE_8PIN_CONNECTOR_ID2  0x08
  3014.  
  3015. //define ucPwrSensorId
  3016. #define POWER_SENSOR_ALWAYS                                                     0x00
  3017. #define POWER_SENSOR_GPIO                                                               0x01
  3018. #define POWER_SENSOR_I2C                                                                0x02
  3019.  
  3020. /**************************************************************************/
  3021. // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
  3022. //Memory SS Info Table
  3023. //Define Memory Clock SS chip ID
  3024. #define ICS91719  1
  3025. #define ICS91720  2
  3026.  
  3027. //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
  3028. typedef struct _ATOM_I2C_DATA_RECORD
  3029. {
  3030.   UCHAR         ucNunberOfBytes;                                              //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
  3031.   UCHAR         ucI2CData[1];                                                 //I2C data in bytes, should be less than 16 bytes usually
  3032. }ATOM_I2C_DATA_RECORD;
  3033.  
  3034.  
  3035. //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
  3036. typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
  3037. {
  3038.   ATOM_I2C_ID_CONFIG_ACCESS       sucI2cId;               //I2C line and HW/SW assisted cap.
  3039.   UCHAR                                 ucSSChipID;             //SS chip being used
  3040.   UCHAR                                 ucSSChipSlaveAddr;      //Slave Address to set up this SS chip
  3041.   UCHAR                           ucNumOfI2CDataRecords;  //number of data block
  3042.   ATOM_I2C_DATA_RECORD            asI2CData[1];  
  3043. }ATOM_I2C_DEVICE_SETUP_INFO;
  3044.  
  3045. //==========================================================================================
  3046. typedef struct  _ATOM_ASIC_MVDD_INFO
  3047. {
  3048.   ATOM_COMMON_TABLE_HEADER            sHeader;
  3049.   ATOM_I2C_DEVICE_SETUP_INFO      asI2CSetup[1];
  3050. }ATOM_ASIC_MVDD_INFO;
  3051.  
  3052. //==========================================================================================
  3053. #define ATOM_MCLK_SS_INFO         ATOM_ASIC_MVDD_INFO
  3054.  
  3055. //==========================================================================================
  3056. /**************************************************************************/
  3057.  
  3058. typedef struct _ATOM_ASIC_SS_ASSIGNMENT
  3059. {
  3060.         ULONG                                                           ulTargetClockRange;                                             //Clock Out frequence (VCO ), in unit of 10Khz
  3061.   USHORT              usSpreadSpectrumPercentage;               //in unit of 0.01%
  3062.         USHORT                                                  usSpreadRateInKhz;                                              //in unit of kHz, modulation freq
  3063.   UCHAR               ucClockIndication;                                          //Indicate which clock source needs SS
  3064.         UCHAR                                                           ucSpreadSpectrumMode;                                   //Bit1=0 Down Spread,=1 Center Spread.
  3065.         UCHAR                                                           ucReserved[2];
  3066. }ATOM_ASIC_SS_ASSIGNMENT;
  3067.  
  3068. //Define ucSpreadSpectrumType
  3069. #define ASIC_INTERNAL_MEMORY_SS                 1
  3070. #define ASIC_INTERNAL_ENGINE_SS                 2
  3071. #define ASIC_INTERNAL_UVD_SS                            3
  3072.  
  3073. typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
  3074.   ATOM_COMMON_TABLE_HEADER            sHeader;
  3075.   ATOM_ASIC_SS_ASSIGNMENT                     asSpreadSpectrum[4];
  3076. }ATOM_ASIC_INTERNAL_SS_INFO;
  3077.  
  3078. //==============================Scratch Pad Definition Portion===============================
  3079. #define ATOM_DEVICE_CONNECT_INFO_DEF  0
  3080. #define ATOM_ROM_LOCATION_DEF         1
  3081. #define ATOM_TV_STANDARD_DEF          2
  3082. #define ATOM_ACTIVE_INFO_DEF          3
  3083. #define ATOM_LCD_INFO_DEF             4
  3084. #define ATOM_DOS_REQ_INFO_DEF         5
  3085. #define ATOM_ACC_CHANGE_INFO_DEF      6
  3086. #define ATOM_DOS_MODE_INFO_DEF        7
  3087. #define ATOM_I2C_CHANNEL_STATUS_DEF   8
  3088. #define ATOM_I2C_CHANNEL_STATUS1_DEF  9
  3089.  
  3090.  
  3091. // BIOS_0_SCRATCH Definition
  3092. #define ATOM_S0_CRT1_MONO               0x00000001L
  3093. #define ATOM_S0_CRT1_COLOR              0x00000002L
  3094. #define ATOM_S0_CRT1_MASK               (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
  3095.  
  3096. #define ATOM_S0_TV1_COMPOSITE_A         0x00000004L
  3097. #define ATOM_S0_TV1_SVIDEO_A            0x00000008L
  3098. #define ATOM_S0_TV1_MASK_A              (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
  3099.  
  3100. #define ATOM_S0_CV_A                    0x00000010L
  3101. #define ATOM_S0_CV_DIN_A                0x00000020L
  3102. #define ATOM_S0_CV_MASK_A               (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
  3103.  
  3104.  
  3105. #define ATOM_S0_CRT2_MONO               0x00000100L
  3106. #define ATOM_S0_CRT2_COLOR              0x00000200L
  3107. #define ATOM_S0_CRT2_MASK               (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
  3108.  
  3109. #define ATOM_S0_TV1_COMPOSITE           0x00000400L
  3110. #define ATOM_S0_TV1_SVIDEO              0x00000800L
  3111. #define ATOM_S0_TV1_SCART               0x00004000L
  3112. #define ATOM_S0_TV1_MASK                (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
  3113.  
  3114. #define ATOM_S0_CV                      0x00001000L
  3115. #define ATOM_S0_CV_DIN                  0x00002000L
  3116. #define ATOM_S0_CV_MASK                 (ATOM_S0_CV+ATOM_S0_CV_DIN)
  3117.  
  3118. #define ATOM_S0_DFP1                    0x00010000L
  3119. #define ATOM_S0_DFP2                    0x00020000L
  3120. #define ATOM_S0_LCD1                    0x00040000L
  3121. #define ATOM_S0_LCD2                    0x00080000L
  3122. #define ATOM_S0_TV2                     0x00100000L
  3123. #define ATOM_S0_DFP3                                                                            0x00200000L
  3124. #define ATOM_S0_DFP4                                                                            0x00400000L
  3125. #define ATOM_S0_DFP5                                                                            0x00800000L
  3126.  
  3127. #define ATOM_S0_DFP_MASK                ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5
  3128.  
  3129. #define ATOM_S0_FAD_REGISTER_BUG        0x02000000L // If set, indicates we are running a PCIE asic with
  3130.                                                     // the FAD/HDP reg access bug.  Bit is read by DAL
  3131.  
  3132. #define ATOM_S0_THERMAL_STATE_MASK      0x1C000000L
  3133. #define ATOM_S0_THERMAL_STATE_SHIFT     26
  3134.  
  3135. #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
  3136. #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
  3137.  
  3138. #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC     1
  3139. #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC     2
  3140. #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
  3141.  
  3142. //Byte aligned defintion for BIOS usage
  3143. #define ATOM_S0_CRT1_MONOb0             0x01
  3144. #define ATOM_S0_CRT1_COLORb0            0x02
  3145. #define ATOM_S0_CRT1_MASKb0             (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
  3146.  
  3147. #define ATOM_S0_TV1_COMPOSITEb0         0x04
  3148. #define ATOM_S0_TV1_SVIDEOb0            0x08
  3149. #define ATOM_S0_TV1_MASKb0              (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
  3150.  
  3151. #define ATOM_S0_CVb0                    0x10
  3152. #define ATOM_S0_CV_DINb0                0x20
  3153. #define ATOM_S0_CV_MASKb0               (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
  3154.  
  3155. #define ATOM_S0_CRT2_MONOb1             0x01
  3156. #define ATOM_S0_CRT2_COLORb1            0x02
  3157. #define ATOM_S0_CRT2_MASKb1             (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
  3158.  
  3159. #define ATOM_S0_TV1_COMPOSITEb1         0x04
  3160. #define ATOM_S0_TV1_SVIDEOb1            0x08
  3161. #define ATOM_S0_TV1_SCARTb1             0x40
  3162. #define ATOM_S0_TV1_MASKb1              (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
  3163.  
  3164. #define ATOM_S0_CVb1                    0x10
  3165. #define ATOM_S0_CV_DINb1                0x20
  3166. #define ATOM_S0_CV_MASKb1               (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
  3167.  
  3168. #define ATOM_S0_DFP1b2                  0x01
  3169. #define ATOM_S0_DFP2b2                  0x02
  3170. #define ATOM_S0_LCD1b2                  0x04
  3171. #define ATOM_S0_LCD2b2                  0x08
  3172. #define ATOM_S0_TV2b2                   0x10
  3173. #define ATOM_S0_DFP3b2                                                                  0x20
  3174. #define ATOM_S0_DFP4b2                                                                  0x40
  3175. #define ATOM_S0_DFP5b2                                                                  0x80
  3176.  
  3177. #define ATOM_S0_THERMAL_STATE_MASKb3    0x1C
  3178. #define ATOM_S0_THERMAL_STATE_SHIFTb3   2
  3179.  
  3180. #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
  3181. #define ATOM_S0_LCD1_SHIFT              18
  3182.  
  3183. // BIOS_1_SCRATCH Definition
  3184. #define ATOM_S1_ROM_LOCATION_MASK       0x0000FFFFL
  3185. #define ATOM_S1_PCI_BUS_DEV_MASK        0xFFFF0000L
  3186.  
  3187. //      BIOS_2_SCRATCH Definition
  3188. #define ATOM_S2_TV1_STANDARD_MASK       0x0000000FL
  3189. #define ATOM_S2_CURRENT_BL_LEVEL_MASK   0x0000FF00L
  3190. #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT  8
  3191.  
  3192. #define ATOM_S2_CRT1_DPMS_STATE         0x00010000L
  3193. #define ATOM_S2_LCD1_DPMS_STATE         0x00020000L
  3194. #define ATOM_S2_TV1_DPMS_STATE          0x00040000L
  3195. #define ATOM_S2_DFP1_DPMS_STATE         0x00080000L
  3196. #define ATOM_S2_CRT2_DPMS_STATE         0x00100000L
  3197. #define ATOM_S2_LCD2_DPMS_STATE         0x00200000L
  3198. #define ATOM_S2_TV2_DPMS_STATE          0x00400000L
  3199. #define ATOM_S2_DFP2_DPMS_STATE         0x00800000L
  3200. #define ATOM_S2_CV_DPMS_STATE           0x01000000L
  3201. #define ATOM_S2_DFP3_DPMS_STATE                                 0x02000000L
  3202. #define ATOM_S2_DFP4_DPMS_STATE                                 0x04000000L
  3203. #define ATOM_S2_DFP5_DPMS_STATE                                 0x08000000L
  3204.  
  3205. #define ATOM_S2_DFP_DPM_STATE           ATOM_S2_DFP1_DPMS_STATE | ATOM_S2_DFP2_DPMS_STATE | ATOM_S2_DFP3_DPMS_STATE | ATOM_S2_DFP4_DPMS_STATE | ATOM_S2_DFP5_DPMS_STATE
  3206.  
  3207. #define ATOM_S2_DEVICE_DPMS_STATE       (ATOM_S2_CRT1_DPMS_STATE+ATOM_S2_LCD1_DPMS_STATE+ATOM_S2_TV1_DPMS_STATE+\
  3208.                                         ATOM_S2_DFP_DPMS_STATE+ATOM_S2_CRT2_DPMS_STATE+ATOM_S2_LCD2_DPMS_STATE+\
  3209.                                         ATOM_S2_TV2_DPMS_STATE+ATOM_S2_CV_DPMS_STATE
  3210.  
  3211. #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK       0x0C000000L
  3212. #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
  3213. #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE     0x10000000L
  3214.  
  3215. #define ATOM_S2_VRI_BRIGHT_ENABLE       0x20000000L
  3216.  
  3217. #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE     0x0
  3218. #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE    0x1
  3219. #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE   0x2
  3220. #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE   0x3
  3221. #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
  3222. #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK   0xC0000000L
  3223.  
  3224.  
  3225. //Byte aligned defintion for BIOS usage
  3226. #define ATOM_S2_TV1_STANDARD_MASKb0     0x0F
  3227. #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
  3228. #define ATOM_S2_CRT1_DPMS_STATEb2       0x01
  3229. #define ATOM_S2_LCD1_DPMS_STATEb2       0x02
  3230. #define ATOM_S2_TV1_DPMS_STATEb2        0x04
  3231. #define ATOM_S2_DFP1_DPMS_STATEb2       0x08
  3232. #define ATOM_S2_CRT2_DPMS_STATEb2       0x10
  3233. #define ATOM_S2_LCD2_DPMS_STATEb2       0x20
  3234. #define ATOM_S2_TV2_DPMS_STATEb2        0x40
  3235. #define ATOM_S2_DFP2_DPMS_STATEb2       0x80
  3236. #define ATOM_S2_CV_DPMS_STATEb3         0x01
  3237. #define ATOM_S2_DFP3_DPMS_STATEb3                               0x02
  3238. #define ATOM_S2_DFP4_DPMS_STATEb3                               0x04
  3239. #define ATOM_S2_DFP5_DPMS_STATEb3                               0x08
  3240.  
  3241. #define ATOM_S2_DEVICE_DPMS_MASKw1      0x3FF
  3242. #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3     0x0C
  3243. #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3   0x10
  3244. #define ATOM_S2_VRI_BRIGHT_ENABLEb3     0x20
  3245. #define ATOM_S2_ROTATION_STATE_MASKb3   0xC0
  3246.  
  3247.  
  3248. // BIOS_3_SCRATCH Definition
  3249. #define ATOM_S3_CRT1_ACTIVE             0x00000001L
  3250. #define ATOM_S3_LCD1_ACTIVE             0x00000002L
  3251. #define ATOM_S3_TV1_ACTIVE              0x00000004L
  3252. #define ATOM_S3_DFP1_ACTIVE             0x00000008L
  3253. #define ATOM_S3_CRT2_ACTIVE             0x00000010L
  3254. #define ATOM_S3_LCD2_ACTIVE             0x00000020L
  3255. #define ATOM_S3_TV2_ACTIVE              0x00000040L
  3256. #define ATOM_S3_DFP2_ACTIVE             0x00000080L
  3257. #define ATOM_S3_CV_ACTIVE               0x00000100L
  3258. #define ATOM_S3_DFP3_ACTIVE                                                     0x00000200L
  3259. #define ATOM_S3_DFP4_ACTIVE                                                     0x00000400L
  3260. #define ATOM_S3_DFP5_ACTIVE                                                     0x00000800L
  3261.  
  3262. #define ATOM_S3_DEVICE_ACTIVE_MASK      0x00000FFFL
  3263.  
  3264. #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE         0x00001000L
  3265. #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
  3266.  
  3267. #define ATOM_S3_CRT1_CRTC_ACTIVE        0x00010000L
  3268. #define ATOM_S3_LCD1_CRTC_ACTIVE        0x00020000L
  3269. #define ATOM_S3_TV1_CRTC_ACTIVE         0x00040000L
  3270. #define ATOM_S3_DFP1_CRTC_ACTIVE        0x00080000L
  3271. #define ATOM_S3_CRT2_CRTC_ACTIVE        0x00100000L
  3272. #define ATOM_S3_LCD2_CRTC_ACTIVE        0x00200000L
  3273. #define ATOM_S3_TV2_CRTC_ACTIVE         0x00400000L
  3274. #define ATOM_S3_DFP2_CRTC_ACTIVE        0x00800000L
  3275. #define ATOM_S3_CV_CRTC_ACTIVE          0x01000000L
  3276. #define ATOM_S3_DFP3_CRTC_ACTIVE                                0x02000000L
  3277. #define ATOM_S3_DFP4_CRTC_ACTIVE                                0x04000000L
  3278. #define ATOM_S3_DFP5_CRTC_ACTIVE                                0x08000000L
  3279.  
  3280. #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
  3281. #define ATOM_S3_ASIC_GUI_ENGINE_HUNG    0x20000000L
  3282. #define ATOM_S3_ALLOW_FAST_PWR_SWITCH   0x40000000L
  3283. #define ATOM_S3_RQST_GPU_USE_MIN_PWR    0x80000000L
  3284.  
  3285. //Byte aligned defintion for BIOS usage
  3286. #define ATOM_S3_CRT1_ACTIVEb0           0x01
  3287. #define ATOM_S3_LCD1_ACTIVEb0           0x02
  3288. #define ATOM_S3_TV1_ACTIVEb0            0x04
  3289. #define ATOM_S3_DFP1_ACTIVEb0           0x08
  3290. #define ATOM_S3_CRT2_ACTIVEb0           0x10
  3291. #define ATOM_S3_LCD2_ACTIVEb0           0x20
  3292. #define ATOM_S3_TV2_ACTIVEb0            0x40
  3293. #define ATOM_S3_DFP2_ACTIVEb0           0x80
  3294. #define ATOM_S3_CV_ACTIVEb1             0x01
  3295. #define ATOM_S3_DFP3_ACTIVEb1                                           0x02
  3296. #define ATOM_S3_DFP4_ACTIVEb1                                           0x04
  3297. #define ATOM_S3_DFP5_ACTIVEb1                                           0x08
  3298.  
  3299. #define ATOM_S3_ACTIVE_CRTC1w0          0xFFF
  3300.  
  3301. #define ATOM_S3_CRT1_CRTC_ACTIVEb2      0x01
  3302. #define ATOM_S3_LCD1_CRTC_ACTIVEb2      0x02
  3303. #define ATOM_S3_TV1_CRTC_ACTIVEb2       0x04
  3304. #define ATOM_S3_DFP1_CRTC_ACTIVEb2      0x08
  3305. #define ATOM_S3_CRT2_CRTC_ACTIVEb2      0x10
  3306. #define ATOM_S3_LCD2_CRTC_ACTIVEb2      0x20
  3307. #define ATOM_S3_TV2_CRTC_ACTIVEb2       0x40
  3308. #define ATOM_S3_DFP2_CRTC_ACTIVEb2      0x80
  3309. #define ATOM_S3_CV_CRTC_ACTIVEb3        0x01
  3310. #define ATOM_S3_DFP3_CRTC_ACTIVEb3                      0x02
  3311. #define ATOM_S3_DFP4_CRTC_ACTIVEb3                      0x04
  3312. #define ATOM_S3_DFP5_CRTC_ACTIVEb3                      0x08
  3313.  
  3314. #define ATOM_S3_ACTIVE_CRTC2w1          0xFFF
  3315.  
  3316. #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3  0x20
  3317. #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
  3318. #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3  0x80
  3319.  
  3320. // BIOS_4_SCRATCH Definition
  3321. #define ATOM_S4_LCD1_PANEL_ID_MASK      0x000000FFL
  3322. #define ATOM_S4_LCD1_REFRESH_MASK       0x0000FF00L
  3323. #define ATOM_S4_LCD1_REFRESH_SHIFT      8
  3324.  
  3325. //Byte aligned defintion for BIOS usage
  3326. #define ATOM_S4_LCD1_PANEL_ID_MASKb0      0x0FF
  3327. #define ATOM_S4_LCD1_REFRESH_MASKb1               ATOM_S4_LCD1_PANEL_ID_MASKb0
  3328. #define ATOM_S4_VRAM_INFO_MASKb2        ATOM_S4_LCD1_PANEL_ID_MASKb0
  3329.  
  3330. // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
  3331. #define ATOM_S5_DOS_REQ_CRT1b0          0x01
  3332. #define ATOM_S5_DOS_REQ_LCD1b0          0x02
  3333. #define ATOM_S5_DOS_REQ_TV1b0           0x04
  3334. #define ATOM_S5_DOS_REQ_DFP1b0          0x08
  3335. #define ATOM_S5_DOS_REQ_CRT2b0          0x10
  3336. #define ATOM_S5_DOS_REQ_LCD2b0          0x20
  3337. #define ATOM_S5_DOS_REQ_TV2b0           0x40
  3338. #define ATOM_S5_DOS_REQ_DFP2b0          0x80
  3339. #define ATOM_S5_DOS_REQ_CVb1            0x01
  3340. #define ATOM_S5_DOS_REQ_DFP3b1                                  0x02
  3341. #define ATOM_S5_DOS_REQ_DFP4b1                                  0x04
  3342. #define ATOM_S5_DOS_REQ_DFP5b1                                  0x08
  3343.  
  3344. #define ATOM_S5_DOS_REQ_DEVICEw0        0x03FF
  3345.  
  3346. #define ATOM_S5_DOS_REQ_CRT1            0x0001
  3347. #define ATOM_S5_DOS_REQ_LCD1            0x0002
  3348. #define ATOM_S5_DOS_REQ_TV1             0x0004
  3349. #define ATOM_S5_DOS_REQ_DFP1            0x0008
  3350. #define ATOM_S5_DOS_REQ_CRT2            0x0010
  3351. #define ATOM_S5_DOS_REQ_LCD2            0x0020
  3352. #define ATOM_S5_DOS_REQ_TV2             0x0040
  3353. #define ATOM_S5_DOS_REQ_DFP2            0x0080
  3354. #define ATOM_S5_DOS_REQ_CV              0x0100
  3355. #define ATOM_S5_DOS_REQ_DFP3                                            0x0200
  3356. #define ATOM_S5_DOS_REQ_DFP4                                            0x0400
  3357. #define ATOM_S5_DOS_REQ_DFP5                                            0x0800
  3358.  
  3359. #define ATOM_S5_DOS_FORCE_CRT1b2        ATOM_S5_DOS_REQ_CRT1b0
  3360. #define ATOM_S5_DOS_FORCE_TV1b2         ATOM_S5_DOS_REQ_TV1b0
  3361. #define ATOM_S5_DOS_FORCE_CRT2b2        ATOM_S5_DOS_REQ_CRT2b0
  3362. #define ATOM_S5_DOS_FORCE_CVb3          ATOM_S5_DOS_REQ_CVb1
  3363. #define ATOM_S5_DOS_FORCE_DEVICEw1      (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
  3364.                                         (ATOM_S5_DOS_FORCE_CVb3<<8))
  3365.  
  3366. // BIOS_6_SCRATCH Definition
  3367. #define ATOM_S6_DEVICE_CHANGE           0x00000001L
  3368. #define ATOM_S6_SCALER_CHANGE           0x00000002L
  3369. #define ATOM_S6_LID_CHANGE              0x00000004L
  3370. #define ATOM_S6_DOCKING_CHANGE          0x00000008L
  3371. #define ATOM_S6_ACC_MODE                0x00000010L
  3372. #define ATOM_S6_EXT_DESKTOP_MODE        0x00000020L
  3373. #define ATOM_S6_LID_STATE               0x00000040L
  3374. #define ATOM_S6_DOCK_STATE              0x00000080L
  3375. #define ATOM_S6_CRITICAL_STATE          0x00000100L
  3376. #define ATOM_S6_HW_I2C_BUSY_STATE       0x00000200L
  3377. #define ATOM_S6_THERMAL_STATE_CHANGE    0x00000400L
  3378. #define ATOM_S6_INTERRUPT_SET_BY_BIOS   0x00000800L
  3379. #define ATOM_S6_REQ_LCD_EXPANSION_FULL         0x00001000L //Normal expansion Request bit for LCD
  3380. #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO  0x00002000L //Aspect ratio expansion Request bit for LCD
  3381.  
  3382. #define ATOM_S6_DISPLAY_STATE_CHANGE    0x00004000L        //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
  3383. #define ATOM_S6_I2C_STATE_CHANGE        0x00008000L        //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
  3384.  
  3385. #define ATOM_S6_ACC_REQ_CRT1            0x00010000L
  3386. #define ATOM_S6_ACC_REQ_LCD1            0x00020000L
  3387. #define ATOM_S6_ACC_REQ_TV1             0x00040000L
  3388. #define ATOM_S6_ACC_REQ_DFP1            0x00080000L
  3389. #define ATOM_S6_ACC_REQ_CRT2            0x00100000L
  3390. #define ATOM_S6_ACC_REQ_LCD2            0x00200000L
  3391. #define ATOM_S6_ACC_REQ_TV2             0x00400000L
  3392. #define ATOM_S6_ACC_REQ_DFP2            0x00800000L
  3393. #define ATOM_S6_ACC_REQ_CV              0x01000000L
  3394. #define ATOM_S6_ACC_REQ_DFP3                                            0x02000000L
  3395. #define ATOM_S6_ACC_REQ_DFP4                                            0x04000000L
  3396. #define ATOM_S6_ACC_REQ_DFP5                                            0x08000000L
  3397.  
  3398. #define ATOM_S6_ACC_REQ_MASK                0x0FFF0000L
  3399. #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE    0x10000000L
  3400. #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH    0x20000000L
  3401. #define ATOM_S6_VRI_BRIGHTNESS_CHANGE       0x40000000L
  3402. #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK  0x80000000L
  3403.  
  3404. //Byte aligned defintion for BIOS usage
  3405. #define ATOM_S6_DEVICE_CHANGEb0         0x01
  3406. #define ATOM_S6_SCALER_CHANGEb0         0x02
  3407. #define ATOM_S6_LID_CHANGEb0            0x04
  3408. #define ATOM_S6_DOCKING_CHANGEb0        0x08
  3409. #define ATOM_S6_ACC_MODEb0              0x10
  3410. #define ATOM_S6_EXT_DESKTOP_MODEb0      0x20
  3411. #define ATOM_S6_LID_STATEb0             0x40
  3412. #define ATOM_S6_DOCK_STATEb0            0x80
  3413. #define ATOM_S6_CRITICAL_STATEb1        0x01
  3414. #define ATOM_S6_HW_I2C_BUSY_STATEb1     0x02  
  3415. #define ATOM_S6_THERMAL_STATE_CHANGEb1  0x04
  3416. #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
  3417. #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1        0x10    
  3418. #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
  3419.  
  3420. #define ATOM_S6_ACC_REQ_CRT1b2          0x01
  3421. #define ATOM_S6_ACC_REQ_LCD1b2          0x02
  3422. #define ATOM_S6_ACC_REQ_TV1b2           0x04
  3423. #define ATOM_S6_ACC_REQ_DFP1b2          0x08
  3424. #define ATOM_S6_ACC_REQ_CRT2b2          0x10
  3425. #define ATOM_S6_ACC_REQ_LCD2b2          0x20
  3426. #define ATOM_S6_ACC_REQ_TV2b2           0x40
  3427. #define ATOM_S6_ACC_REQ_DFP2b2          0x80
  3428. #define ATOM_S6_ACC_REQ_CVb3            0x01
  3429. #define ATOM_S6_ACC_REQ_DFP3b3                                  0x02
  3430. #define ATOM_S6_ACC_REQ_DFP4b3                                  0x04
  3431. #define ATOM_S6_ACC_REQ_DFP5b3                                  0x08
  3432.  
  3433. #define ATOM_S6_ACC_REQ_DEVICEw1        ATOM_S5_DOS_REQ_DEVICEw0
  3434. #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
  3435. #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
  3436. #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3    0x40
  3437. #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3    0x80
  3438.  
  3439. #define ATOM_S6_DEVICE_CHANGE_SHIFT             0
  3440. #define ATOM_S6_SCALER_CHANGE_SHIFT             1
  3441. #define ATOM_S6_LID_CHANGE_SHIFT                2
  3442. #define ATOM_S6_DOCKING_CHANGE_SHIFT            3
  3443. #define ATOM_S6_ACC_MODE_SHIFT                  4
  3444. #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT          5
  3445. #define ATOM_S6_LID_STATE_SHIFT                 6
  3446. #define ATOM_S6_DOCK_STATE_SHIFT                7
  3447. #define ATOM_S6_CRITICAL_STATE_SHIFT            8
  3448. #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT         9
  3449. #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT      10
  3450. #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT     11
  3451. #define ATOM_S6_REQ_SCALER_SHIFT                12
  3452. #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT         13
  3453. #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT      14
  3454. #define ATOM_S6_I2C_STATE_CHANGE_SHIFT          15
  3455. #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT  28
  3456. #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT  29
  3457. #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT     30
  3458. #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT     31
  3459.  
  3460. // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
  3461. #define ATOM_S7_DOS_MODE_TYPEb0             0x03
  3462. #define ATOM_S7_DOS_MODE_VGAb0              0x00
  3463. #define ATOM_S7_DOS_MODE_VESAb0             0x01
  3464. #define ATOM_S7_DOS_MODE_EXTb0              0x02
  3465. #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0      0x0C
  3466. #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0     0xF0
  3467. #define ATOM_S7_DOS_8BIT_DAC_ENb1           0x01
  3468. #define ATOM_S7_DOS_MODE_NUMBERw1           0x0FFFF
  3469.  
  3470. #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT       8
  3471.  
  3472. // BIOS_8_SCRATCH Definition
  3473. #define ATOM_S8_I2C_CHANNEL_BUSY_MASK       0x00000FFFF
  3474. #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK     0x0FFFF0000  
  3475.  
  3476. #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT      0
  3477. #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT       16
  3478.  
  3479. // BIOS_9_SCRATCH Definition
  3480. #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
  3481. #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK  0x0000FFFF
  3482. #endif
  3483. #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK  
  3484. #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK    0xFFFF0000
  3485. #endif
  3486. #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
  3487. #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
  3488. #endif
  3489. #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT  
  3490. #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT   16
  3491. #endif
  3492.  
  3493.  
  3494. #define ATOM_FLAG_SET                         0x20
  3495. #define ATOM_FLAG_CLEAR                       0
  3496. #define CLEAR_ATOM_S6_ACC_MODE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
  3497. #define SET_ATOM_S6_DEVICE_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
  3498. #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
  3499. #define SET_ATOM_S6_SCALER_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
  3500. #define SET_ATOM_S6_LID_CHANGE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
  3501.  
  3502. #define SET_ATOM_S6_LID_STATE                 ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
  3503. #define CLEAR_ATOM_S6_LID_STATE               ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
  3504.  
  3505. #define SET_ATOM_S6_DOCK_CHANGE                           ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
  3506. #define SET_ATOM_S6_DOCK_STATE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
  3507. #define CLEAR_ATOM_S6_DOCK_STATE              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
  3508.  
  3509. #define SET_ATOM_S6_THERMAL_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
  3510. #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE  ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
  3511. #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
  3512.  
  3513. #define SET_ATOM_S6_CRITICAL_STATE            ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
  3514. #define CLEAR_ATOM_S6_CRITICAL_STATE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
  3515.  
  3516. #define SET_ATOM_S6_REQ_SCALER                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)  
  3517. #define CLEAR_ATOM_S6_REQ_SCALER              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
  3518.  
  3519. #define SET_ATOM_S6_REQ_SCALER_ARATIO         ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
  3520. #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO       ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
  3521.  
  3522. #define SET_ATOM_S6_I2C_STATE_CHANGE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
  3523.  
  3524. #define SET_ATOM_S6_DISPLAY_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
  3525.  
  3526. #define SET_ATOM_S6_DEVICE_RECONFIG           ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
  3527. #define CLEAR_ATOM_S0_LCD1                    ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )|  ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
  3528. #define SET_ATOM_S7_DOS_8BIT_DAC_EN           ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
  3529. #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN         ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
  3530.  
  3531. /****************************************************************************/ 
  3532. //Portion II: Definitinos only used in Driver
  3533. /****************************************************************************/
  3534.  
  3535. // Macros used by driver
  3536.  
  3537. #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
  3538.  
  3539. #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
  3540. #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
  3541.  
  3542. #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
  3543. #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
  3544.  
  3545. /****************************************************************************/ 
  3546. //Portion III: Definitinos only used in VBIOS
  3547. /****************************************************************************/
  3548. #define ATOM_DAC_SRC                                    0x80
  3549. #define ATOM_SRC_DAC1                                   0
  3550. #define ATOM_SRC_DAC2                                   0x80
  3551.  
  3552.  
  3553. #ifdef  UEFI_BUILD
  3554.         #define USHORT  UTEMP
  3555. #endif
  3556.  
  3557. typedef struct _MEMORY_PLLINIT_PARAMETERS
  3558. {
  3559.   ULONG ulTargetMemoryClock; //In 10Khz unit
  3560.   UCHAR   ucAction;                                      //not define yet
  3561.   UCHAR   ucFbDiv_Hi;                            //Fbdiv Hi byte
  3562.   UCHAR   ucFbDiv;                                       //FB value
  3563.   UCHAR   ucPostDiv;                             //Post div
  3564. }MEMORY_PLLINIT_PARAMETERS;
  3565.  
  3566. #define MEMORY_PLLINIT_PS_ALLOCATION  MEMORY_PLLINIT_PARAMETERS
  3567.  
  3568.  
  3569. #define GPIO_PIN_WRITE                                                                                                  0x01                   
  3570. #define GPIO_PIN_READ                                                                                                           0x00
  3571.  
  3572. typedef struct  _GPIO_PIN_CONTROL_PARAMETERS
  3573. {
  3574.   UCHAR ucGPIO_ID;           //return value, read from GPIO pins
  3575.   UCHAR ucGPIOBitShift;      //define which bit in uGPIOBitVal need to be update
  3576.         UCHAR ucGPIOBitVal;                  //Set/Reset corresponding bit defined in ucGPIOBitMask
  3577.   UCHAR ucAction;                                    //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
  3578. }GPIO_PIN_CONTROL_PARAMETERS;
  3579.  
  3580. typedef struct _ENABLE_SCALER_PARAMETERS
  3581. {
  3582.   UCHAR ucScaler;            // ATOM_SCALER1, ATOM_SCALER2
  3583.   UCHAR ucEnable;            // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
  3584.   UCHAR ucTVStandard;        //
  3585.   UCHAR ucPadding[1];
  3586. }ENABLE_SCALER_PARAMETERS;
  3587. #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
  3588.  
  3589. //ucEnable:
  3590. #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION    0
  3591. #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION  1
  3592. #define SCALER_ENABLE_2TAP_ALPHA_MODE               2
  3593. #define SCALER_ENABLE_MULTITAP_MODE                 3
  3594.  
  3595. typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
  3596. {
  3597.   ULONG  usHWIconHorzVertPosn;        // Hardware Icon Vertical position
  3598.   UCHAR  ucHWIconVertOffset;          // Hardware Icon Vertical offset
  3599.   UCHAR  ucHWIconHorzOffset;          // Hardware Icon Horizontal offset
  3600.   UCHAR  ucSelection;                 // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
  3601.   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
  3602. }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
  3603.  
  3604. typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
  3605. {
  3606.   ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS  sEnableIcon;
  3607.   ENABLE_CRTC_PARAMETERS                  sReserved;  
  3608. }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
  3609.  
  3610. typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
  3611. {
  3612.   USHORT usHight;                     // Image Hight
  3613.   USHORT usWidth;                     // Image Width
  3614.   UCHAR  ucSurface;                   // Surface 1 or 2
  3615.   UCHAR  ucPadding[3];
  3616. }ENABLE_GRAPH_SURFACE_PARAMETERS;
  3617.  
  3618. typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
  3619. {
  3620.   USHORT usHight;                     // Image Hight
  3621.   USHORT usWidth;                     // Image Width
  3622.   UCHAR  ucSurface;                   // Surface 1 or 2
  3623.   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
  3624.   UCHAR  ucPadding[2];
  3625. }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
  3626.  
  3627. typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
  3628. {
  3629.   ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;          
  3630.   ENABLE_YUV_PS_ALLOCATION        sReserved; // Don't set this one
  3631. }ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
  3632.  
  3633. typedef struct _MEMORY_CLEAN_UP_PARAMETERS
  3634. {
  3635.   USHORT  usMemoryStart;                //in 8Kb boundry, offset from memory base address
  3636.   USHORT  usMemorySize;                 //8Kb blocks aligned
  3637. }MEMORY_CLEAN_UP_PARAMETERS;
  3638. #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
  3639.  
  3640. typedef struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
  3641. {
  3642.   USHORT  usX_Size;                     //When use as input parameter, usX_Size indicates which CRTC                
  3643.   USHORT  usY_Size;
  3644. }GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
  3645.  
  3646. typedef struct _INDIRECT_IO_ACCESS
  3647. {
  3648.   ATOM_COMMON_TABLE_HEADER sHeader;  
  3649.   UCHAR                    IOAccessSequence[256];
  3650. } INDIRECT_IO_ACCESS;
  3651.  
  3652. #define INDIRECT_READ              0x00
  3653. #define INDIRECT_WRITE             0x80
  3654.  
  3655. #define INDIRECT_IO_MM             0
  3656. #define INDIRECT_IO_PLL            1
  3657. #define INDIRECT_IO_MC             2
  3658. #define INDIRECT_IO_PCIE           3
  3659. #define INDIRECT_IO_PCIEP          4
  3660. #define INDIRECT_IO_NBMISC         5
  3661.  
  3662. #define INDIRECT_IO_PLL_READ       INDIRECT_IO_PLL   | INDIRECT_READ
  3663. #define INDIRECT_IO_PLL_WRITE      INDIRECT_IO_PLL   | INDIRECT_WRITE
  3664. #define INDIRECT_IO_MC_READ        INDIRECT_IO_MC    | INDIRECT_READ
  3665. #define INDIRECT_IO_MC_WRITE       INDIRECT_IO_MC    | INDIRECT_WRITE
  3666. #define INDIRECT_IO_PCIE_READ      INDIRECT_IO_PCIE  | INDIRECT_READ
  3667. #define INDIRECT_IO_PCIE_WRITE     INDIRECT_IO_PCIE  | INDIRECT_WRITE
  3668. #define INDIRECT_IO_PCIEP_READ     INDIRECT_IO_PCIEP | INDIRECT_READ
  3669. #define INDIRECT_IO_PCIEP_WRITE    INDIRECT_IO_PCIEP | INDIRECT_WRITE
  3670. #define INDIRECT_IO_NBMISC_READ    INDIRECT_IO_NBMISC | INDIRECT_READ
  3671. #define INDIRECT_IO_NBMISC_WRITE   INDIRECT_IO_NBMISC | INDIRECT_WRITE
  3672.  
  3673. typedef struct _ATOM_OEM_INFO
  3674. {
  3675.   ATOM_COMMON_TABLE_HEADER      sHeader;
  3676.   ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
  3677. }ATOM_OEM_INFO;
  3678.  
  3679. typedef struct _ATOM_TV_MODE
  3680. {
  3681.    UCHAR        ucVMode_Num;                      //Video mode number
  3682.    UCHAR        ucTV_Mode_Num;                  //Internal TV mode number
  3683. }ATOM_TV_MODE;
  3684.  
  3685. typedef struct _ATOM_BIOS_INT_TVSTD_MODE
  3686. {
  3687.   ATOM_COMMON_TABLE_HEADER sHeader;  
  3688.    USHORT       usTV_Mode_LUT_Offset;   // Pointer to standard to internal number conversion table
  3689.    USHORT       usTV_FIFO_Offset;                 // Pointer to FIFO entry table
  3690.    USHORT       usNTSC_Tbl_Offset;              // Pointer to SDTV_Mode_NTSC table
  3691.    USHORT       usPAL_Tbl_Offset;                 // Pointer to SDTV_Mode_PAL table
  3692.    USHORT       usCV_Tbl_Offset;                  // Pointer to SDTV_Mode_PAL table
  3693. }ATOM_BIOS_INT_TVSTD_MODE;
  3694.  
  3695.  
  3696. typedef struct _ATOM_TV_MODE_SCALER_PTR
  3697. {
  3698.    USHORT       ucFilter0_Offset;               //Pointer to filter format 0 coefficients
  3699.    USHORT       usFilter1_Offset;               //Pointer to filter format 0 coefficients
  3700.    UCHAR        ucTV_Mode_Num;
  3701. }ATOM_TV_MODE_SCALER_PTR;
  3702.  
  3703. typedef struct _ATOM_STANDARD_VESA_TIMING
  3704. {
  3705.   ATOM_COMMON_TABLE_HEADER sHeader;  
  3706.   ATOM_DTD_FORMAT                                aModeTimings[16];      // 16 is not the real array number, just for initial allocation
  3707. }ATOM_STANDARD_VESA_TIMING;
  3708.  
  3709.  
  3710. typedef struct _ATOM_STD_FORMAT
  3711. {
  3712.   USHORT    usSTD_HDisp;
  3713.   USHORT    usSTD_VDisp;
  3714.   USHORT    usSTD_RefreshRate;
  3715.   USHORT    usReserved;
  3716. }ATOM_STD_FORMAT;
  3717.  
  3718. typedef struct _ATOM_VESA_TO_EXTENDED_MODE
  3719. {
  3720.   USHORT  usVESA_ModeNumber;
  3721.   USHORT  usExtendedModeNumber;
  3722. }ATOM_VESA_TO_EXTENDED_MODE;
  3723.  
  3724. typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
  3725. {
  3726.   ATOM_COMMON_TABLE_HEADER   sHeader;  
  3727.   ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
  3728. }ATOM_VESA_TO_INTENAL_MODE_LUT;
  3729.  
  3730. /*************** ATOM Memory Related Data Structure ***********************/
  3731. typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
  3732.         UCHAR                                                                                           ucMemoryType;
  3733.         UCHAR                                                                                           ucMemoryVendor;
  3734.         UCHAR                                                                                           ucAdjMCId;
  3735.         UCHAR                                                                                           ucDynClkId;
  3736.         ULONG                                                                                           ulDllResetClkRange;
  3737. }ATOM_MEMORY_VENDOR_BLOCK;
  3738.  
  3739.  
  3740. typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
  3741.         ULONG                                                                                           ulMemClockRange:24;
  3742.         ULONG                                                                                           ucMemBlkId:8;
  3743. }ATOM_MEMORY_SETTING_ID_CONFIG;
  3744.  
  3745. typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
  3746. {
  3747.   ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
  3748.   ULONG                         ulAccess;
  3749. }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
  3750.  
  3751.  
  3752. typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
  3753.         ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS                    ulMemoryID;
  3754.         ULONG                                                                                                                           aulMemData[1];
  3755. }ATOM_MEMORY_SETTING_DATA_BLOCK;
  3756.  
  3757.  
  3758. typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
  3759.          USHORT                                                                                 usRegIndex;                                     // MC register index
  3760.          UCHAR                                                                                  ucPreRegDataLength;                             // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
  3761. }ATOM_INIT_REG_INDEX_FORMAT;
  3762.  
  3763.  
  3764. typedef struct _ATOM_INIT_REG_BLOCK{
  3765.         USHORT                                                                                                  usRegIndexTblSize;                                                                                                      //size of asRegIndexBuf
  3766.         USHORT                                                                                                  usRegDataBlkSize;                                                                                                               //size of ATOM_MEMORY_SETTING_DATA_BLOCK
  3767.         ATOM_INIT_REG_INDEX_FORMAT                      asRegIndexBuf[1];
  3768.         ATOM_MEMORY_SETTING_DATA_BLOCK  asRegDataBuf[1];
  3769. }ATOM_INIT_REG_BLOCK;
  3770.  
  3771. #define END_OF_REG_INDEX_BLOCK  0x0ffff
  3772. #define END_OF_REG_DATA_BLOCK   0x00000000
  3773. #define ATOM_INIT_REG_MASK_FLAG 0x80
  3774. #define CLOCK_RANGE_HIGHEST                     0x00ffffff
  3775.  
  3776. #define VALUE_DWORD             SIZEOF ULONG
  3777. #define VALUE_SAME_AS_ABOVE     0
  3778. #define VALUE_MASK_DWORD        0x84
  3779.  
  3780. #define INDEX_ACCESS_RANGE_BEGIN            (VALUE_DWORD + 1)
  3781. #define INDEX_ACCESS_RANGE_END              (INDEX_ACCESS_RANGE_BEGIN + 1)
  3782. #define VALUE_INDEX_ACCESS_SINGLE           (INDEX_ACCESS_RANGE_END + 1)
  3783.  
  3784.  
  3785. typedef struct _ATOM_MC_INIT_PARAM_TABLE
  3786. {
  3787.   ATOM_COMMON_TABLE_HEADER              sHeader;
  3788.   USHORT                                                                                        usAdjustARB_SEQDataOffset;
  3789.   USHORT                                                                                        usMCInitMemTypeTblOffset;
  3790.   USHORT                                                                                        usMCInitCommonTblOffset;
  3791.   USHORT                                                                                        usMCInitPowerDownTblOffset;
  3792.         ULONG                                                                                           ulARB_SEQDataBuf[32];
  3793.         ATOM_INIT_REG_BLOCK                                     asMCInitMemType;
  3794.         ATOM_INIT_REG_BLOCK                                     asMCInitCommon;
  3795. }ATOM_MC_INIT_PARAM_TABLE;
  3796.  
  3797.  
  3798. #define _4Mx16              0x2
  3799. #define _4Mx32              0x3
  3800. #define _8Mx16              0x12
  3801. #define _8Mx32              0x13
  3802. #define _16Mx16             0x22
  3803. #define _16Mx32             0x23
  3804. #define _32Mx16             0x32
  3805. #define _32Mx32             0x33
  3806. #define _64Mx8              0x41
  3807. #define _64Mx16             0x42
  3808.  
  3809. #define SAMSUNG             0x1
  3810. #define INFINEON            0x2
  3811. #define ELPIDA              0x3
  3812. #define ETRON               0x4
  3813. #define NANYA               0x5
  3814. #define HYNIX               0x6
  3815. #define MOSEL               0x7
  3816. #define WINBOND             0x8
  3817. #define ESMT                0x9
  3818. #define MICRON              0xF
  3819.  
  3820. #define QIMONDA             INFINEON
  3821. #define PROMOS              MOSEL
  3822.  
  3823. /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
  3824.  
  3825. #define UCODE_ROM_START_ADDRESS         0x1c000
  3826. #define UCODE_SIGNATURE                 0x4375434d // 'MCuC' - MC uCode
  3827.  
  3828. //uCode block header for reference
  3829.  
  3830. typedef struct _MCuCodeHeader
  3831. {
  3832.   ULONG  ulSignature;
  3833.   UCHAR  ucRevision;
  3834.   UCHAR  ucChecksum;
  3835.   UCHAR  ucReserved1;
  3836.   UCHAR  ucReserved2;
  3837.   USHORT usParametersLength;
  3838.   USHORT usUCodeLength;
  3839.   USHORT usReserved1;
  3840.   USHORT usReserved2;
  3841. } MCuCodeHeader;
  3842.  
  3843. //////////////////////////////////////////////////////////////////////////////////
  3844.  
  3845. #define ATOM_MAX_NUMBER_OF_VRAM_MODULE  16
  3846.  
  3847. #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK  0xF
  3848. typedef struct _ATOM_VRAM_MODULE_V1
  3849. {
  3850.   ULONG                      ulReserved;
  3851.   USHORT                     usEMRSValue;  
  3852.   USHORT                     usMRSValue;
  3853.   USHORT                     usReserved;
  3854.   UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  3855.   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
  3856.   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender
  3857.   UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
  3858.   UCHAR                      ucRow;             // Number of Row,in power of 2;
  3859.   UCHAR                      ucColumn;          // Number of Column,in power of 2;
  3860.   UCHAR                      ucBank;            // Nunber of Bank;
  3861.   UCHAR                      ucRank;            // Number of Rank, in power of 2
  3862.   UCHAR                      ucChannelNum;      // Number of channel;
  3863.   UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
  3864.   UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
  3865.   UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
  3866.   UCHAR                      ucReserved[2];
  3867. }ATOM_VRAM_MODULE_V1;
  3868.  
  3869.  
  3870. typedef struct _ATOM_VRAM_MODULE_V2
  3871. {
  3872.   ULONG                      ulReserved;
  3873.   ULONG                      ulFlags;                           // To enable/disable functionalities based on memory type
  3874.   ULONG                      ulEngineClock;     // Override of default engine clock for particular memory type
  3875.   ULONG                      ulMemoryClock;     // Override of default memory clock for particular memory type
  3876.   USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  3877.   USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  3878.   USHORT                     usEMRSValue;  
  3879.   USHORT                     usMRSValue;
  3880.   USHORT                     usReserved;
  3881.   UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  3882.   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
  3883.   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
  3884.   UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
  3885.   UCHAR                      ucRow;             // Number of Row,in power of 2;
  3886.   UCHAR                      ucColumn;          // Number of Column,in power of 2;
  3887.   UCHAR                      ucBank;            // Nunber of Bank;
  3888.   UCHAR                      ucRank;            // Number of Rank, in power of 2
  3889.   UCHAR                      ucChannelNum;      // Number of channel;
  3890.   UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
  3891.   UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
  3892.   UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
  3893.   UCHAR                      ucRefreshRateFactor;
  3894.   UCHAR                      ucReserved[3];
  3895. }ATOM_VRAM_MODULE_V2;
  3896.  
  3897.  
  3898. typedef struct _ATOM_MEMORY_TIMING_FORMAT
  3899. {
  3900.         ULONG                                                                                    ulClkRange;                            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing    
  3901.   union{
  3902.           USHORT                                                                                 usMRS;                                                 // mode register                                               
  3903.     USHORT                     usDDR3_MR0;
  3904.   };
  3905.   union{
  3906.           USHORT                                                                                 usEMRS;                                                // extended mode register
  3907.     USHORT                     usDDR3_MR1;
  3908.   };
  3909.         UCHAR                                                                                    ucCL;                                                  // CAS latency
  3910.         UCHAR                                                                                    ucWL;                                                  // WRITE Latency                               
  3911.         UCHAR                                                                                    uctRAS;                                                // tRAS
  3912.         UCHAR                                                                                    uctRC;                                                 // tRC 
  3913.         UCHAR                                                                                    uctRFC;                                                // tRFC
  3914.         UCHAR                                                                                    uctRCDR;                                               // tRCDR       
  3915.         UCHAR                                                                                    uctRCDW;                                               // tRCDW
  3916.         UCHAR                                                                                    uctRP;                                                 // tRP
  3917.         UCHAR                                                                                    uctRRD;                                                // tRRD
  3918.         UCHAR                                                                                    uctWR;                                                 // tWR
  3919.         UCHAR                                                                                    uctWTR;                                                // tWTR
  3920.         UCHAR                                                                                    uctPDIX;                                               // tPDIX
  3921.         UCHAR                                                                                    uctFAW;                                                // tFAW
  3922.         UCHAR                                                                                    uctAOND;                                               // tAOND
  3923.   union
  3924.   {
  3925.     struct {
  3926.             UCHAR                                                                                        ucflag;                                                // flag to control memory timing calculation. bit0= control EMRS2 Infineon
  3927.             UCHAR                                                                                        ucReserved;                                           
  3928.     };
  3929.     USHORT                   usDDR3_MR2;
  3930.   };
  3931. }ATOM_MEMORY_TIMING_FORMAT;
  3932.  
  3933.  
  3934. typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1
  3935. {
  3936.         ULONG                                                                                    ulClkRange;                            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing    
  3937.         USHORT                                                                           usMRS;                                                 // mode register                                               
  3938.         USHORT                                                                           usEMRS;                                                // extended mode register
  3939.         UCHAR                                                                                    ucCL;                                                  // CAS latency
  3940.         UCHAR                                                                                    ucWL;                                                  // WRITE Latency                               
  3941.         UCHAR                                                                                    uctRAS;                                                // tRAS
  3942.         UCHAR                                                                                    uctRC;                                                 // tRC 
  3943.         UCHAR                                                                                    uctRFC;                                                // tRFC
  3944.         UCHAR                                                                                    uctRCDR;                                               // tRCDR       
  3945.         UCHAR                                                                                    uctRCDW;                                               // tRCDW
  3946.         UCHAR                                                                                    uctRP;                                                 // tRP
  3947.         UCHAR                                                                                    uctRRD;                                                // tRRD
  3948.         UCHAR                                                                                    uctWR;                                                 // tWR
  3949.         UCHAR                                                                                    uctWTR;                                                // tWTR
  3950.         UCHAR                                                                                    uctPDIX;                                               // tPDIX
  3951.         UCHAR                                                                                    uctFAW;                                                // tFAW
  3952.         UCHAR                                                                                    uctAOND;                                               // tAOND
  3953.         UCHAR                                                                                    ucflag;                                                // flag to control memory timing calculation. bit0= control EMRS2 Infineon
  3954. ////////////////////////////////////GDDR parameters///////////////////////////////////
  3955.         UCHAR                                                                                    uctCCDL;                                               //
  3956.         UCHAR                                                                                    uctCRCRL;                                              //
  3957.         UCHAR                                                                                    uctCRCWL;                                              //
  3958.         UCHAR                                                                                    uctCKE;                                                //
  3959.         UCHAR                                                                                    uctCKRSE;                                              //
  3960.         UCHAR                                                                                    uctCKRSX;                                              //
  3961.         UCHAR                                                                                    uctFAW32;                                              //
  3962.         UCHAR                                                                                    ucReserved1;                                   //
  3963.         UCHAR                                                                                    ucReserved2;                                   //
  3964.         UCHAR                                                                                    ucTerminator;
  3965. }ATOM_MEMORY_TIMING_FORMAT_V1;
  3966.  
  3967.  
  3968. typedef struct _ATOM_MEMORY_FORMAT
  3969. {
  3970.         ULONG                                                                                    ulDllDisClock;                 // memory DLL will be disable when target memory clock is below this clock
  3971.   union{
  3972.     USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  3973.     USHORT                     usDDR3_Reserved;   // Not used for DDR3 memory
  3974.   };
  3975.   union{
  3976.     USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  3977.     USHORT                     usDDR3_MR3;        // Used for DDR3 memory
  3978.   };
  3979.   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
  3980.   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
  3981.   UCHAR                      ucRow;             // Number of Row,in power of 2;
  3982.   UCHAR                      ucColumn;          // Number of Column,in power of 2;
  3983.   UCHAR                      ucBank;            // Nunber of Bank;
  3984.   UCHAR                      ucRank;            // Number of Rank, in power of 2
  3985.         UCHAR                                                                                    ucBurstSize;                           // burst size, 0= burst size=4  1= burst size=8
  3986.   UCHAR                      ucDllDisBit;                               // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
  3987.   UCHAR                      ucRefreshRateFactor;       // memory refresh rate in unit of ms   
  3988.         UCHAR                                                                                    ucDensity;                                     // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  3989.         UCHAR                                                                                    ucPreamble;                            //[7:4] Write Preamble, [3:0] Read Preamble
  3990.   UCHAR                                                                                  ucMemAttrib;                           // Memory Device Addribute, like RDBI/WDBI etc
  3991.         ATOM_MEMORY_TIMING_FORMAT        asMemTiming[5];                //Memory Timing block sort from lower clock to higher clock
  3992. }ATOM_MEMORY_FORMAT;
  3993.  
  3994.  
  3995. typedef struct _ATOM_VRAM_MODULE_V3
  3996. {
  3997.         ULONG                                                                                    ulChannelMapCfg;               // board dependent paramenter:Channel combination
  3998.         USHORT                                                                           usSize;                                                // size of ATOM_VRAM_MODULE_V3
  3999.   USHORT                     usDefaultMVDDQ;            // board dependent parameter:Default Memory Core Voltage
  4000.   USHORT                     usDefaultMVDDC;            // board dependent parameter:Default Memory IO Voltage
  4001.         UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  4002.   UCHAR                      ucChannelNum;      // board dependent parameter:Number of channel;
  4003.         UCHAR                                                                                    ucChannelSize;                 // board dependent parameter:32bit or 64bit    
  4004.         UCHAR                                                                                    ucVREFI;                                               // board dependnt parameter: EXT or INT +160mv to -140mv
  4005.         UCHAR                                                                                    ucNPL_RT;                                      // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
  4006.         UCHAR                                                                                    ucFlag;                                                // To enable/disable functionalities based on memory type
  4007.         ATOM_MEMORY_FORMAT                               asMemory;                                      // describ all of video memory parameters from memory spec
  4008. }ATOM_VRAM_MODULE_V3;
  4009.  
  4010.  
  4011. //ATOM_VRAM_MODULE_V3.ucNPL_RT
  4012. #define NPL_RT_MASK                                                                                                                     0x0f
  4013. #define BATTERY_ODT_MASK                                                                                                0xc0
  4014.  
  4015. #define ATOM_VRAM_MODULE                 ATOM_VRAM_MODULE_V3
  4016.  
  4017. typedef struct _ATOM_VRAM_MODULE_V4
  4018. {
  4019.   ULONG   ulChannelMapCfg;                      // board dependent parameter: Channel combination
  4020.   USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
  4021.   USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  4022.                                             // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
  4023.   USHORT  usReserved;
  4024.   UCHAR   ucExtMemoryID;                            // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  4025.   UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
  4026.   UCHAR   ucChannelNum;                     // Number of channels present in this module config
  4027.   UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
  4028.         UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  4029.         UCHAR     ucFlag;                                                               // To enable/disable functionalities based on memory type
  4030.         UCHAR     ucMisc;                                                               // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
  4031.   UCHAR         ucVREFI;                          // board dependent parameter
  4032.   UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
  4033.   UCHAR         ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
  4034.   UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  4035.                                             // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
  4036.   UCHAR   ucReserved[3];
  4037.  
  4038. //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
  4039.   union{
  4040.     USHORT      usEMRS2Value;                   // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  4041.     USHORT  usDDR3_Reserved;
  4042.   };
  4043.   union{
  4044.     USHORT      usEMRS3Value;                   // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  4045.     USHORT  usDDR3_MR3;                     // Used for DDR3 memory
  4046.   };  
  4047.   UCHAR   ucMemoryVenderID;                         // Predefined, If not predefined, vendor detection table gets executed
  4048.   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
  4049.   UCHAR   ucReserved2[2];
  4050.   ATOM_MEMORY_TIMING_FORMAT  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
  4051. }ATOM_VRAM_MODULE_V4;
  4052.  
  4053. #define VRAM_MODULE_V4_MISC_RANK_MASK       0x3
  4054. #define VRAM_MODULE_V4_MISC_DUAL_RANK       0x1
  4055. #define VRAM_MODULE_V4_MISC_BL_MASK         0x4
  4056. #define VRAM_MODULE_V4_MISC_BL8             0x4
  4057. #define VRAM_MODULE_V4_MISC_DUAL_CS         0x10
  4058.  
  4059. typedef struct _ATOM_VRAM_MODULE_V5
  4060. {
  4061.   ULONG   ulChannelMapCfg;                      // board dependent parameter: Channel combination
  4062.   USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
  4063.   USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  4064.                                             // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
  4065.   USHORT  usReserved;
  4066.   UCHAR   ucExtMemoryID;                            // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  4067.   UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
  4068.   UCHAR   ucChannelNum;                     // Number of channels present in this module config
  4069.   UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
  4070.         UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  4071.         UCHAR     ucFlag;                                                               // To enable/disable functionalities based on memory type
  4072.         UCHAR     ucMisc;                                                               // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
  4073.   UCHAR         ucVREFI;                          // board dependent parameter
  4074.   UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
  4075.   UCHAR         ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
  4076.   UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  4077.                                             // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
  4078.   UCHAR   ucReserved[3];
  4079.  
  4080. //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
  4081.   USHORT        usEMRS2Value;                               // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  4082.   USHORT        usEMRS3Value;                               // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  4083.   UCHAR   ucMemoryVenderID;                         // Predefined, If not predefined, vendor detection table gets executed
  4084.   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
  4085.   UCHAR   ucFIFODepth;                                  // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
  4086.   UCHAR   ucCDR_Bandwidth;                 // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
  4087.   ATOM_MEMORY_TIMING_FORMAT_V1  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
  4088. }ATOM_VRAM_MODULE_V5;
  4089.  
  4090. typedef struct _ATOM_VRAM_INFO_V2
  4091. {
  4092.   ATOM_COMMON_TABLE_HEADER   sHeader;
  4093.   UCHAR                      ucNumOfVRAMModule;
  4094.   ATOM_VRAM_MODULE           aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
  4095. }ATOM_VRAM_INFO_V2;
  4096.  
  4097. typedef struct _ATOM_VRAM_INFO_V3
  4098. {
  4099.   ATOM_COMMON_TABLE_HEADER   sHeader;
  4100.         USHORT                                                                           usMemAdjustTblOffset;                                                                                                   // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
  4101.         USHORT                                                                           usMemClkPatchTblOffset;                                                                                                 //     offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
  4102.         USHORT                                                                           usRerseved;
  4103.         UCHAR                            aVID_PinsShift[9];                                                                                                                      // 8 bit strap maximum+terminator
  4104.   UCHAR                      ucNumOfVRAMModule;
  4105.   ATOM_VRAM_MODULE                     aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
  4106.         ATOM_INIT_REG_BLOCK                              asMemPatch;                                                                                                                                             // for allocation
  4107.                                                                                                                                                                                                                                                                                                                  //     ATOM_INIT_REG_BLOCK                              aMemAdjust;
  4108. }ATOM_VRAM_INFO_V3;
  4109.  
  4110. #define ATOM_VRAM_INFO_LAST          ATOM_VRAM_INFO_V3
  4111.  
  4112. typedef struct _ATOM_VRAM_INFO_V4
  4113. {
  4114.   ATOM_COMMON_TABLE_HEADER   sHeader;
  4115.         USHORT                                                                           usMemAdjustTblOffset;                                                                                                   // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
  4116.         USHORT                                                                           usMemClkPatchTblOffset;                                                                                                 //     offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
  4117.         USHORT                                                                           usRerseved;
  4118.         UCHAR                            ucMemDQ7_0ByteRemap;                                                                                                      // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
  4119.   ULONG                      ulMemDQ7_0BitRemap;                             // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
  4120.   UCHAR                      ucReservde[4];
  4121.   UCHAR                      ucNumOfVRAMModule;
  4122.   ATOM_VRAM_MODULE_V4                aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
  4123.         ATOM_INIT_REG_BLOCK                              asMemPatch;                                                                                                                                             // for allocation
  4124.                                                                                                                                                                                                                                                                                                                  //     ATOM_INIT_REG_BLOCK                              aMemAdjust;
  4125. }ATOM_VRAM_INFO_V4;
  4126.  
  4127. typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
  4128. {
  4129.   ATOM_COMMON_TABLE_HEADER   sHeader;
  4130.   UCHAR                          aVID_PinsShift[9];   //8 bit strap maximum+terminator
  4131. }ATOM_VRAM_GPIO_DETECTION_INFO;
  4132.  
  4133.  
  4134. typedef struct _ATOM_MEMORY_TRAINING_INFO
  4135. {
  4136.         ATOM_COMMON_TABLE_HEADER   sHeader;
  4137.         UCHAR                                                                                    ucTrainingLoop;
  4138.         UCHAR                                                                                    ucReserved[3];
  4139.         ATOM_INIT_REG_BLOCK                              asMemTrainingSetting;
  4140. }ATOM_MEMORY_TRAINING_INFO;
  4141.  
  4142.  
  4143. typedef struct SW_I2C_CNTL_DATA_PARAMETERS
  4144. {
  4145.   UCHAR    ucControl;
  4146.   UCHAR    ucData;
  4147.   UCHAR    ucSatus;
  4148.   UCHAR    ucTemp;
  4149. } SW_I2C_CNTL_DATA_PARAMETERS;
  4150.  
  4151. #define SW_I2C_CNTL_DATA_PS_ALLOCATION  SW_I2C_CNTL_DATA_PARAMETERS
  4152.  
  4153. typedef struct _SW_I2C_IO_DATA_PARAMETERS
  4154. {                              
  4155.   USHORT   GPIO_Info;
  4156.   UCHAR    ucAct;
  4157.   UCHAR    ucData;
  4158.  } SW_I2C_IO_DATA_PARAMETERS;
  4159.  
  4160. #define SW_I2C_IO_DATA_PS_ALLOCATION  SW_I2C_IO_DATA_PARAMETERS
  4161.  
  4162. /****************************SW I2C CNTL DEFINITIONS**********************/
  4163. #define SW_I2C_IO_RESET       0
  4164. #define SW_I2C_IO_GET         1
  4165. #define SW_I2C_IO_DRIVE       2
  4166. #define SW_I2C_IO_SET         3
  4167. #define SW_I2C_IO_START       4
  4168.  
  4169. #define SW_I2C_IO_CLOCK       0
  4170. #define SW_I2C_IO_DATA        0x80
  4171.  
  4172. #define SW_I2C_IO_ZERO        0
  4173. #define SW_I2C_IO_ONE         0x100
  4174.  
  4175. #define SW_I2C_CNTL_READ      0
  4176. #define SW_I2C_CNTL_WRITE     1
  4177. #define SW_I2C_CNTL_START     2
  4178. #define SW_I2C_CNTL_STOP      3
  4179. #define SW_I2C_CNTL_OPEN      4
  4180. #define SW_I2C_CNTL_CLOSE     5
  4181. #define SW_I2C_CNTL_WRITE1BIT 6
  4182.  
  4183. //==============================VESA definition Portion===============================
  4184. #define VESA_OEM_PRODUCT_REV                                '01.00'
  4185. #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT             0xBB       //refer to VBE spec p.32, no TTY support
  4186. #define VESA_MODE_WIN_ATTRIBUTE                                              7
  4187. #define VESA_WIN_SIZE                                                                                        64
  4188.  
  4189. typedef struct _PTR_32_BIT_STRUCTURE
  4190. {
  4191.         USHORT  Offset16;                      
  4192.         USHORT  Segment16;                             
  4193. } PTR_32_BIT_STRUCTURE;
  4194.  
  4195. typedef union _PTR_32_BIT_UNION
  4196. {
  4197.         PTR_32_BIT_STRUCTURE    SegmentOffset;
  4198.         ULONG                                           Ptr32_Bit;
  4199. } PTR_32_BIT_UNION;
  4200.  
  4201. typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
  4202. {
  4203.         UCHAR                                 VbeSignature[4];
  4204.         USHORT                              VbeVersion;
  4205.         PTR_32_BIT_UNION        OemStringPtr;
  4206.         UCHAR                                 Capabilities[4];
  4207.         PTR_32_BIT_UNION        VideoModePtr;
  4208.         USHORT                              TotalMemory;
  4209. } VBE_1_2_INFO_BLOCK_UPDATABLE;
  4210.  
  4211.  
  4212. typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
  4213. {
  4214.         VBE_1_2_INFO_BLOCK_UPDATABLE    CommonBlock;
  4215.         USHORT                                                      OemSoftRev;
  4216.         PTR_32_BIT_UNION                                OemVendorNamePtr;
  4217.         PTR_32_BIT_UNION                                OemProductNamePtr;
  4218.         PTR_32_BIT_UNION                                OemProductRevPtr;
  4219. } VBE_2_0_INFO_BLOCK_UPDATABLE;
  4220.  
  4221. typedef union _VBE_VERSION_UNION
  4222. {
  4223.         VBE_2_0_INFO_BLOCK_UPDATABLE    VBE_2_0_InfoBlock;
  4224.         VBE_1_2_INFO_BLOCK_UPDATABLE    VBE_1_2_InfoBlock;
  4225. } VBE_VERSION_UNION;
  4226.  
  4227. typedef struct _VBE_INFO_BLOCK
  4228. {
  4229.         VBE_VERSION_UNION                       UpdatableVBE_Info;
  4230.         UCHAR                                                 Reserved[222];
  4231.         UCHAR                                                 OemData[256];
  4232. } VBE_INFO_BLOCK;
  4233.  
  4234. typedef struct _VBE_FP_INFO
  4235. {
  4236.   USHORT        HSize;
  4237.         USHORT  VSize;
  4238.         USHORT  FPType;
  4239.         UCHAR           RedBPP;
  4240.         UCHAR           GreenBPP;
  4241.         UCHAR           BlueBPP;
  4242.         UCHAR           ReservedBPP;
  4243.         ULONG           RsvdOffScrnMemSize;
  4244.         ULONG           RsvdOffScrnMEmPtr;
  4245.         UCHAR           Reserved[14];
  4246. } VBE_FP_INFO;
  4247.  
  4248. typedef struct _VESA_MODE_INFO_BLOCK
  4249. {
  4250. // Mandatory information for all VBE revisions
  4251.   USHORT    ModeAttributes;  //                 dw      ?       ; mode attributes
  4252.         UCHAR     WinAAttributes;  //                   db      ?       ; window A attributes
  4253.         UCHAR     WinBAttributes;  //                   db      ?       ; window B attributes
  4254.         USHORT    WinGranularity;  //                   dw      ?       ; window granularity
  4255.         USHORT    WinSize;         //                   dw      ?       ; window size
  4256.         USHORT    WinASegment;     //                   dw      ?       ; window A start segment
  4257.         USHORT    WinBSegment;     //                   dw      ?       ; window B start segment
  4258.         ULONG     WinFuncPtr;      //                   dd      ?       ; real mode pointer to window function
  4259.         USHORT    BytesPerScanLine;//                   dw      ?       ; bytes per scan line
  4260.  
  4261. //; Mandatory information for VBE 1.2 and above
  4262.   USHORT    XResolution;      //                        dw      ?       ; horizontal resolution in pixels or characters
  4263.         USHORT    YResolution;      //                  dw      ?       ; vertical resolution in pixels or characters
  4264.         UCHAR     XCharSize;        //                  db      ?       ; character cell width in pixels
  4265.         UCHAR     YCharSize;        //                  db      ?       ; character cell height in pixels
  4266.         UCHAR     NumberOfPlanes;   //                  db      ?       ; number of memory planes
  4267.         UCHAR     BitsPerPixel;     //                  db      ?       ; bits per pixel
  4268.         UCHAR     NumberOfBanks;    //                  db      ?       ; number of banks
  4269.         UCHAR     MemoryModel;      //                  db      ?       ; memory model type
  4270.         UCHAR     BankSize;         //                  db      ?       ; bank size in KB
  4271.         UCHAR     NumberOfImagePages;//           db    ?       ; number of images
  4272.         UCHAR     ReservedForPageFunction;//db  1       ; reserved for page function
  4273.  
  4274. //; Direct Color fields(required for direct/6 and YUV/7 memory models)
  4275.         UCHAR                   RedMaskSize;        //          db      ?       ; size of direct color red mask in bits
  4276.         UCHAR                   RedFieldPosition;   //          db      ?       ; bit position of lsb of red mask
  4277.         UCHAR                   GreenMaskSize;      //          db      ?       ; size of direct color green mask in bits
  4278.         UCHAR                   GreenFieldPosition; //          db      ?       ; bit position of lsb of green mask
  4279.         UCHAR                   BlueMaskSize;       //          db      ?       ; size of direct color blue mask in bits
  4280.         UCHAR                   BlueFieldPosition;  //          db      ?       ; bit position of lsb of blue mask
  4281.         UCHAR                   RsvdMaskSize;       //          db      ?       ; size of direct color reserved mask in bits
  4282.         UCHAR                   RsvdFieldPosition;  //          db      ?       ; bit position of lsb of reserved mask
  4283.         UCHAR                   DirectColorModeInfo;//          db      ?       ; direct color mode attributes
  4284.  
  4285. //; Mandatory information for VBE 2.0 and above
  4286.         ULONG                   PhysBasePtr;        //          dd      ?       ; physical address for flat memory frame buffer
  4287.         ULONG                   Reserved_1;         //          dd      0       ; reserved - always set to 0
  4288.         USHORT          Reserved_2;         //    dw    0       ; reserved - always set to 0
  4289.  
  4290. //; Mandatory information for VBE 3.0 and above
  4291.         USHORT          LinBytesPerScanLine;  //        dw      ?       ; bytes per scan line for linear modes
  4292.         UCHAR                   BnkNumberOfImagePages;//        db      ?       ; number of images for banked modes
  4293.         UCHAR                   LinNumberOfImagPages; //        db      ?       ; number of images for linear modes
  4294.         UCHAR                   LinRedMaskSize;       //        db      ?       ; size of direct color red mask(linear modes)
  4295.         UCHAR                   LinRedFieldPosition;  //        db      ?       ; bit position of lsb of red mask(linear modes)
  4296.         UCHAR                   LinGreenMaskSize;     //        db      ?       ; size of direct color green mask(linear modes)
  4297.         UCHAR                   LinGreenFieldPosition;//        db      ?       ; bit position of lsb of green mask(linear modes)
  4298.         UCHAR                   LinBlueMaskSize;      //        db      ?       ; size of direct color blue mask(linear modes)
  4299.         UCHAR                   LinBlueFieldPosition; //        db      ?       ; bit position of lsb of blue mask(linear modes)
  4300.         UCHAR                   LinRsvdMaskSize;      //        db      ?       ; size of direct color reserved mask(linear modes)
  4301.         UCHAR                   LinRsvdFieldPosition; //        db      ?       ; bit position of lsb of reserved mask(linear modes)
  4302.         ULONG                   MaxPixelClock;        //        dd      ?       ; maximum pixel clock(in Hz) for graphics mode
  4303.         UCHAR                   Reserved;             //        db      190 dup (0)
  4304. } VESA_MODE_INFO_BLOCK;
  4305.  
  4306. // BIOS function CALLS
  4307. #define ATOM_BIOS_EXTENDED_FUNCTION_CODE        0xA0            // ATI Extended Function code
  4308. #define ATOM_BIOS_FUNCTION_COP_MODE             0x00
  4309. #define ATOM_BIOS_FUNCTION_SHORT_QUERY1         0x04
  4310. #define ATOM_BIOS_FUNCTION_SHORT_QUERY2         0x05
  4311. #define ATOM_BIOS_FUNCTION_SHORT_QUERY3         0x06
  4312. #define ATOM_BIOS_FUNCTION_GET_DDC              0x0B  
  4313. #define ATOM_BIOS_FUNCTION_ASIC_DSTATE          0x0E
  4314. #define ATOM_BIOS_FUNCTION_DEBUG_PLAY           0x0F
  4315. #define ATOM_BIOS_FUNCTION_STV_STD              0x16
  4316. #define ATOM_BIOS_FUNCTION_DEVICE_DET           0x17
  4317. #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH        0x18
  4318.  
  4319. #define ATOM_BIOS_FUNCTION_PANEL_CONTROL        0x82
  4320. #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET       0x83
  4321. #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH    0x84
  4322. #define ATOM_BIOS_FUNCTION_HW_ICON              0x8A
  4323. #define ATOM_BIOS_FUNCTION_SET_CMOS             0x8B
  4324. #define SUB_FUNCTION_UPDATE_DISPLAY_INFO        0x8000          // Sub function 80
  4325. #define SUB_FUNCTION_UPDATE_EXPANSION_INFO      0x8100          // Sub function 80
  4326.  
  4327. #define ATOM_BIOS_FUNCTION_DISPLAY_INFO         0x8D
  4328. #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF        0x8E
  4329. #define ATOM_BIOS_FUNCTION_VIDEO_STATE          0x8F
  4330. #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE    0x0300          // Sub function 03  
  4331. #define ATOM_SUB_FUNCTION_GET_LIDSTATE          0x0700          // Sub function 7
  4332. #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE  0x1400          // Notify caller the current thermal state
  4333. #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300          // Notify caller the current critical state
  4334. #define ATOM_SUB_FUNCTION_SET_LIDSTATE          0x8500          // Sub function 85
  4335. #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
  4336. #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT    0x9400          // Notify caller that ADC is supported
  4337.      
  4338.  
  4339. #define ATOM_BIOS_FUNCTION_VESA_DPMS            0x4F10          // Set DPMS
  4340. #define ATOM_SUB_FUNCTION_SET_DPMS              0x0001          // BL: Sub function 01
  4341. #define ATOM_SUB_FUNCTION_GET_DPMS              0x0002          // BL: Sub function 02
  4342. #define ATOM_PARAMETER_VESA_DPMS_ON             0x0000          // BH Parameter for DPMS ON.  
  4343. #define ATOM_PARAMETER_VESA_DPMS_STANDBY        0x0100          // BH Parameter for DPMS STANDBY  
  4344. #define ATOM_PARAMETER_VESA_DPMS_SUSPEND        0x0200          // BH Parameter for DPMS SUSPEND
  4345. #define ATOM_PARAMETER_VESA_DPMS_OFF            0x0400          // BH Parameter for DPMS OFF
  4346. #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON      0x0800          // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
  4347.  
  4348. #define ATOM_BIOS_RETURN_CODE_MASK              0x0000FF00L
  4349. #define ATOM_BIOS_REG_HIGH_MASK                 0x0000FF00L
  4350. #define ATOM_BIOS_REG_LOW_MASK                  0x000000FFL
  4351.  
  4352. // structure used for VBIOS only
  4353.  
  4354. //DispOutInfoTable
  4355. typedef struct _ASIC_TRANSMITTER_INFO
  4356. {
  4357.         USHORT usTransmitterObjId;
  4358.         USHORT usSupportDevice;
  4359.   UCHAR  ucTransmitterCmdTblId;
  4360.         UCHAR  ucConfig;
  4361.         UCHAR  ucEncoderID;                                      //available 1st encoder ( default )
  4362.         UCHAR  ucOptionEncoderID;    //available 2nd encoder ( optional )
  4363.         UCHAR  uc2ndEncoderID;
  4364.         UCHAR  ucReserved;
  4365. }ASIC_TRANSMITTER_INFO;
  4366.  
  4367. typedef struct _ASIC_ENCODER_INFO
  4368. {
  4369.         UCHAR ucEncoderID;
  4370.         UCHAR ucEncoderConfig;
  4371.   USHORT usEncoderCmdTblId;
  4372. }ASIC_ENCODER_INFO;
  4373.  
  4374. typedef struct _ATOM_DISP_OUT_INFO
  4375. {
  4376.   ATOM_COMMON_TABLE_HEADER sHeader;  
  4377.         USHORT ptrTransmitterInfo;
  4378.         USHORT ptrEncoderInfo;
  4379.         ASIC_TRANSMITTER_INFO  asTransmitterInfo[1];
  4380.         ASIC_ENCODER_INFO      asEncoderInfo[1];
  4381. }ATOM_DISP_OUT_INFO;
  4382.  
  4383. // DispDevicePriorityInfo
  4384. typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
  4385. {
  4386.   ATOM_COMMON_TABLE_HEADER sHeader;  
  4387.         USHORT asDevicePriority[16];
  4388. }ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
  4389.  
  4390. //ProcessAuxChannelTransactionTable
  4391. typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
  4392. {
  4393.         USHORT  lpAuxRequest;
  4394.         USHORT  lpDataOut;
  4395.         UCHAR           ucChannelID;
  4396.         union
  4397.         {
  4398.   UCHAR   ucReplyStatus;
  4399.         UCHAR   ucDelay;
  4400.         };
  4401.   UCHAR   ucDataOutLen;
  4402.         UCHAR   ucReserved;
  4403. }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
  4404.  
  4405. #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION                   PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
  4406.  
  4407. //GetSinkType
  4408.  
  4409. typedef struct _DP_ENCODER_SERVICE_PARAMETERS
  4410. {
  4411.         USHORT ucLinkClock;
  4412.         union
  4413.         {
  4414.         UCHAR ucConfig;                         // for DP training command
  4415.         UCHAR ucI2cId;                          // use for GET_SINK_TYPE command
  4416.         };
  4417.         UCHAR ucAction;
  4418.         UCHAR ucStatus;
  4419.         UCHAR ucLaneNum;
  4420.         UCHAR ucReserved[2];
  4421. }DP_ENCODER_SERVICE_PARAMETERS;
  4422.  
  4423. // ucAction
  4424. #define ATOM_DP_ACTION_GET_SINK_TYPE                                                    0x01
  4425. #define ATOM_DP_ACTION_TRAINING_START                                                   0x02
  4426. #define ATOM_DP_ACTION_TRAINING_COMPLETE                                        0x03
  4427. #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL                             0x04
  4428. #define ATOM_DP_ACTION_SET_VSWING_PREEMP                                        0x05
  4429. #define ATOM_DP_ACTION_GET_VSWING_PREEMP                                        0x06
  4430. #define ATOM_DP_ACTION_BLANKING                   0x07
  4431.  
  4432. // ucConfig
  4433. #define ATOM_DP_CONFIG_ENCODER_SEL_MASK                                         0x03
  4434. #define ATOM_DP_CONFIG_DIG1_ENCODER                                                             0x00
  4435. #define ATOM_DP_CONFIG_DIG2_ENCODER                                                             0x01
  4436. #define ATOM_DP_CONFIG_EXTERNAL_ENCODER                                         0x02
  4437. #define ATOM_DP_CONFIG_LINK_SEL_MASK                                                    0x04
  4438. #define ATOM_DP_CONFIG_LINK_A                                                                                   0x00
  4439. #define ATOM_DP_CONFIG_LINK_B                                                                                   0x04
  4440.  
  4441. #define DP_ENCODER_SERVICE_PS_ALLOCATION                                WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
  4442.  
  4443. // DP_TRAINING_TABLE
  4444. #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR                             ATOM_DP_TRAINING_TBL_ADDR              
  4445. #define DPCD_SET_SS_CNTL_TBL_ADDR                                                                                                       (ATOM_DP_TRAINING_TBL_ADDR + 8 )
  4446. #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR                                                    (ATOM_DP_TRAINING_TBL_ADDR + 16 )
  4447. #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 24 )
  4448. #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 32)
  4449. #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR                                                   (ATOM_DP_TRAINING_TBL_ADDR + 40)
  4450. #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR                                                    (ATOM_DP_TRAINING_TBL_ADDR + 48)
  4451. #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 60)
  4452. #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR                                                                                   (ATOM_DP_TRAINING_TBL_ADDR + 64)
  4453. #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR                                                              (ATOM_DP_TRAINING_TBL_ADDR + 72)
  4454. #define DP_I2C_AUX_DDC_READ_TBL_ADDR                                                                                    (ATOM_DP_TRAINING_TBL_ADDR + 76)
  4455. #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR                                                                        (ATOM_DP_TRAINING_TBL_ADDR + 80)
  4456.  
  4457.  
  4458. typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
  4459. {
  4460.         UCHAR   ucI2CSpeed;
  4461.         union
  4462.         {
  4463.    UCHAR ucRegIndex;
  4464.    UCHAR ucStatus;
  4465.         };
  4466.         USHORT  lpI2CDataOut;
  4467.   UCHAR   ucFlag;              
  4468.   UCHAR   ucTransBytes;
  4469.   UCHAR   ucSlaveAddr;
  4470.   UCHAR   ucLineNumber;
  4471. }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
  4472.  
  4473. #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION       PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
  4474.  
  4475. //ucFlag
  4476. #define HW_I2C_WRITE        1
  4477. #define HW_I2C_READ         0
  4478.  
  4479.  
  4480. /****************************************************************************/ 
  4481. //Portion VI: Definitinos being oboselete
  4482. /****************************************************************************/
  4483.  
  4484. //==========================================================================================
  4485. //Remove the definitions below when driver is ready!
  4486. typedef struct _ATOM_DAC_INFO
  4487. {
  4488.   ATOM_COMMON_TABLE_HEADER sHeader;  
  4489.   USHORT                   usMaxFrequency;      // in 10kHz unit
  4490.   USHORT                   usReserved;
  4491. }ATOM_DAC_INFO;
  4492.  
  4493.  
  4494. typedef struct  _COMPASSIONATE_DATA          
  4495. {
  4496.   ATOM_COMMON_TABLE_HEADER sHeader;
  4497.  
  4498.   //==============================  DAC1 portion
  4499.   UCHAR   ucDAC1_BG_Adjustment;
  4500.   UCHAR   ucDAC1_DAC_Adjustment;
  4501.   USHORT  usDAC1_FORCE_Data;
  4502.   //==============================  DAC2 portion
  4503.   UCHAR   ucDAC2_CRT2_BG_Adjustment;
  4504.   UCHAR   ucDAC2_CRT2_DAC_Adjustment;
  4505.   USHORT  usDAC2_CRT2_FORCE_Data;
  4506.   USHORT  usDAC2_CRT2_MUX_RegisterIndex;
  4507.   UCHAR   ucDAC2_CRT2_MUX_RegisterInfo;     //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
  4508.   UCHAR   ucDAC2_NTSC_BG_Adjustment;
  4509.   UCHAR   ucDAC2_NTSC_DAC_Adjustment;
  4510.   USHORT  usDAC2_TV1_FORCE_Data;
  4511.   USHORT  usDAC2_TV1_MUX_RegisterIndex;
  4512.   UCHAR   ucDAC2_TV1_MUX_RegisterInfo;      //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
  4513.   UCHAR   ucDAC2_CV_BG_Adjustment;
  4514.   UCHAR   ucDAC2_CV_DAC_Adjustment;
  4515.   USHORT  usDAC2_CV_FORCE_Data;
  4516.   USHORT  usDAC2_CV_MUX_RegisterIndex;
  4517.   UCHAR   ucDAC2_CV_MUX_RegisterInfo;       //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
  4518.   UCHAR   ucDAC2_PAL_BG_Adjustment;
  4519.   UCHAR   ucDAC2_PAL_DAC_Adjustment;
  4520.   USHORT  usDAC2_TV2_FORCE_Data;
  4521. }COMPASSIONATE_DATA;
  4522.  
  4523. /****************************Supported Device Info Table Definitions**********************/
  4524. //  ucConnectInfo:
  4525. //    [7:4] - connector type
  4526. //      = 1   - VGA connector  
  4527. //      = 2   - DVI-I
  4528. //      = 3   - DVI-D
  4529. //      = 4   - DVI-A
  4530. //      = 5   - SVIDEO
  4531. //      = 6   - COMPOSITE
  4532. //      = 7   - LVDS
  4533. //      = 8   - DIGITAL LINK
  4534. //      = 9   - SCART
  4535. //      = 0xA - HDMI_type A
  4536. //      = 0xB - HDMI_type B
  4537. //      = 0xE - Special case1 (DVI+DIN)
  4538. //      Others=TBD
  4539. //    [3:0] - DAC Associated
  4540. //      = 0   - no DAC
  4541. //      = 1   - DACA
  4542. //      = 2   - DACB
  4543. //      = 3   - External DAC
  4544. //      Others=TBD
  4545. //    
  4546.  
  4547. typedef struct _ATOM_CONNECTOR_INFO
  4548. {
  4549.   UCHAR   bfAssociatedDAC:4;
  4550.   UCHAR   bfConnectorType:4;
  4551. }ATOM_CONNECTOR_INFO;
  4552.  
  4553. typedef union _ATOM_CONNECTOR_INFO_ACCESS
  4554. {
  4555.   ATOM_CONNECTOR_INFO sbfAccess;
  4556.   UCHAR               ucAccess;
  4557. }ATOM_CONNECTOR_INFO_ACCESS;
  4558.  
  4559. typedef struct _ATOM_CONNECTOR_INFO_I2C
  4560. {
  4561.   ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
  4562.   ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;
  4563. }ATOM_CONNECTOR_INFO_I2C;
  4564.  
  4565.  
  4566. typedef struct _ATOM_SUPPORTED_DEVICES_INFO
  4567. {
  4568.   ATOM_COMMON_TABLE_HEADER      sHeader;
  4569.   USHORT                    usDeviceSupport;
  4570.   ATOM_CONNECTOR_INFO_I2C   asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
  4571. }ATOM_SUPPORTED_DEVICES_INFO;
  4572.  
  4573. #define NO_INT_SRC_MAPPED       0xFF
  4574.  
  4575. typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
  4576. {
  4577.   UCHAR   ucIntSrcBitmap;
  4578. }ATOM_CONNECTOR_INC_SRC_BITMAP;
  4579.  
  4580. typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
  4581. {
  4582.   ATOM_COMMON_TABLE_HEADER      sHeader;
  4583.   USHORT                        usDeviceSupport;
  4584.   ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
  4585.   ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
  4586. }ATOM_SUPPORTED_DEVICES_INFO_2;
  4587.  
  4588. typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
  4589. {
  4590.   ATOM_COMMON_TABLE_HEADER      sHeader;
  4591.   USHORT                        usDeviceSupport;
  4592.   ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
  4593.   ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
  4594. }ATOM_SUPPORTED_DEVICES_INFO_2d1;
  4595.  
  4596. #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
  4597.  
  4598.  
  4599.  
  4600. typedef struct _ATOM_MISC_CONTROL_INFO
  4601. {
  4602.    USHORT usFrequency;
  4603.    UCHAR  ucPLL_ChargePump;                                             // PLL charge-pump gain control
  4604.    UCHAR  ucPLL_DutyCycle;                                              // PLL duty cycle control
  4605.    UCHAR  ucPLL_VCO_Gain;                                                 // PLL VCO gain control
  4606.    UCHAR  ucPLL_VoltageSwing;                                   // PLL driver voltage swing control
  4607. }ATOM_MISC_CONTROL_INFO;  
  4608.  
  4609.  
  4610. #define ATOM_MAX_MISC_INFO       4
  4611.  
  4612. typedef struct _ATOM_TMDS_INFO
  4613. {
  4614.   ATOM_COMMON_TABLE_HEADER sHeader;  
  4615.   USHORT                                                        usMaxFrequency;             // in 10Khz
  4616.   ATOM_MISC_CONTROL_INFO                                asMiscInfo[ATOM_MAX_MISC_INFO];
  4617. }ATOM_TMDS_INFO;
  4618.  
  4619.  
  4620. typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
  4621. {
  4622.   UCHAR ucTVStandard;     //Same as TV standards defined above,
  4623.   UCHAR ucPadding[1];
  4624. }ATOM_ENCODER_ANALOG_ATTRIBUTE;
  4625.  
  4626. typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
  4627. {
  4628.   UCHAR ucAttribute;      //Same as other digital encoder attributes defined above
  4629.   UCHAR ucPadding[1];          
  4630. }ATOM_ENCODER_DIGITAL_ATTRIBUTE;
  4631.  
  4632. typedef union _ATOM_ENCODER_ATTRIBUTE
  4633. {
  4634.   ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
  4635.   ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
  4636. }ATOM_ENCODER_ATTRIBUTE;
  4637.  
  4638.  
  4639. typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
  4640. {
  4641.   USHORT usPixelClock;
  4642.   USHORT usEncoderID;
  4643.   UCHAR  ucDeviceType;                                                                                          //Use ATOM_DEVICE_xxx1_Index to indicate device type only.     
  4644.   UCHAR  ucAction;                                                                                                              //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
  4645.   ATOM_ENCODER_ATTRIBUTE usDevAttr;                    
  4646. }DVO_ENCODER_CONTROL_PARAMETERS;
  4647.  
  4648. typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
  4649. {                              
  4650.   DVO_ENCODER_CONTROL_PARAMETERS    sDVOEncoder;
  4651.   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
  4652. }DVO_ENCODER_CONTROL_PS_ALLOCATION;
  4653.  
  4654.  
  4655. #define ATOM_XTMDS_ASIC_SI164_ID        1
  4656. #define ATOM_XTMDS_ASIC_SI178_ID        2
  4657. #define ATOM_XTMDS_ASIC_TFP513_ID       3
  4658. #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
  4659. #define ATOM_XTMDS_SUPPORTED_DUALLINK   0x00000002
  4660. #define ATOM_XTMDS_MVPU_FPGA            0x00000004
  4661.  
  4662.                            
  4663. typedef struct _ATOM_XTMDS_INFO
  4664. {
  4665.   ATOM_COMMON_TABLE_HEADER   sHeader;  
  4666.   USHORT                     usSingleLinkMaxFrequency;
  4667.   ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;           //Point the ID on which I2C is used to control external chip
  4668.   UCHAR                      ucXtransimitterID;          
  4669.   UCHAR                      ucSupportedLink;    // Bit field, bit0=1, single link supported;bit1=1,dual link supported
  4670.   UCHAR                      ucSequnceAlterID;   // Even with the same external TMDS asic, it's possible that the program seqence alters
  4671.                                                  // due to design. This ID is used to alert driver that the sequence is not "standard"!              
  4672.   UCHAR                      ucMasterAddress;    // Address to control Master xTMDS Chip
  4673.   UCHAR                      ucSlaveAddress;     // Address to control Slave xTMDS Chip
  4674. }ATOM_XTMDS_INFO;
  4675.  
  4676. typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
  4677. {  
  4678.   UCHAR ucEnable;                     // ATOM_ENABLE=On or ATOM_DISABLE=Off
  4679.   UCHAR ucDevice;                     // ATOM_DEVICE_DFP1_INDEX....
  4680.   UCHAR ucPadding[2];            
  4681. }DFP_DPMS_STATUS_CHANGE_PARAMETERS;
  4682.  
  4683. /****************************Legacy Power Play Table Definitions **********************/
  4684.  
  4685. //Definitions for ulPowerPlayMiscInfo
  4686. #define ATOM_PM_MISCINFO_SPLIT_CLOCK                     0x00000000L
  4687. #define ATOM_PM_MISCINFO_USING_MCLK_SRC                  0x00000001L
  4688. #define ATOM_PM_MISCINFO_USING_SCLK_SRC                  0x00000002L
  4689.  
  4690. #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT            0x00000004L
  4691. #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH        0x00000008L
  4692.  
  4693. #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN             0x00000010L
  4694.  
  4695. #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN          0x00000020L
  4696. #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN          0x00000040L
  4697. #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE                 0x00000080L  //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program  
  4698.  
  4699. #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN      0x00000100L
  4700. #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN         0x00000200L
  4701. #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN              0x00000400L
  4702. #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN                 0x00000800L
  4703. #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE     0x00001000L
  4704. #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
  4705. #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE            0x00004000L
  4706.  
  4707. #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE             0x00008000L
  4708. #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE                 0x00010000L
  4709. #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE                 0x00020000L
  4710. #define ATOM_PM_MISCINFO_POWER_SAVING_MODE               0x00040000L
  4711. #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE              0x00080000L
  4712.  
  4713. #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK           0x00300000L  //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
  4714. #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT          20
  4715.  
  4716. #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE                 0x00400000L
  4717. #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2      0x00800000L
  4718. #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4      0x01000000L
  4719. #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN            0x02000000L  //When set, Dynamic
  4720. #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN        0x04000000L  //When set, Dynamic
  4721. #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN              0x08000000L  //When set, This mode is for acceleated 3D mode
  4722.  
  4723. #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK   0x70000000L  //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
  4724. #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT  28
  4725. #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS                0x80000000L
  4726.  
  4727. #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE            0x00000001L
  4728. #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT          0x00000002L
  4729. #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN           0x00000004L
  4730. #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO            0x00000008L
  4731. #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE              0x00000010L
  4732. #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN       0x00000020L
  4733. #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE         0x00000040L  //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
  4734.                                                                       //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
  4735. #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC                0x00000080L
  4736. #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN                0x00000100L
  4737. #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE               0x00000200L
  4738.  
  4739. //ucTableFormatRevision=1
  4740. //ucTableContentRevision=1
  4741. typedef struct  _ATOM_POWERMODE_INFO
  4742. {
  4743.   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
  4744.   ULONG     ulReserved1;                // must set to 0
  4745.   ULONG     ulReserved2;                // must set to 0
  4746.   USHORT    usEngineClock;
  4747.   USHORT    usMemoryClock;
  4748.   UCHAR     ucVoltageDropIndex;         // index to GPIO table
  4749.   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
  4750.   UCHAR     ucMinTemperature;
  4751.   UCHAR     ucMaxTemperature;
  4752.   UCHAR     ucNumPciELanes;             // number of PCIE lanes
  4753. }ATOM_POWERMODE_INFO;
  4754.  
  4755. //ucTableFormatRevision=2
  4756. //ucTableContentRevision=1
  4757. typedef struct  _ATOM_POWERMODE_INFO_V2
  4758. {
  4759.   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
  4760.   ULONG     ulMiscInfo2;                
  4761.   ULONG     ulEngineClock;                
  4762.   ULONG     ulMemoryClock;
  4763.   UCHAR     ucVoltageDropIndex;         // index to GPIO table
  4764.   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
  4765.   UCHAR     ucMinTemperature;
  4766.   UCHAR     ucMaxTemperature;
  4767.   UCHAR     ucNumPciELanes;             // number of PCIE lanes
  4768. }ATOM_POWERMODE_INFO_V2;
  4769.  
  4770. //ucTableFormatRevision=2
  4771. //ucTableContentRevision=2
  4772. typedef struct  _ATOM_POWERMODE_INFO_V3
  4773. {
  4774.   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
  4775.   ULONG     ulMiscInfo2;                
  4776.   ULONG     ulEngineClock;                
  4777.   ULONG     ulMemoryClock;
  4778.   UCHAR     ucVoltageDropIndex;         // index to Core (VDDC) votage table
  4779.   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
  4780.   UCHAR     ucMinTemperature;
  4781.   UCHAR     ucMaxTemperature;
  4782.   UCHAR     ucNumPciELanes;             // number of PCIE lanes
  4783.   UCHAR     ucVDDCI_VoltageDropIndex;   // index to VDDCI votage table
  4784. }ATOM_POWERMODE_INFO_V3;
  4785.  
  4786.  
  4787. #define ATOM_MAX_NUMBEROF_POWER_BLOCK  8
  4788.  
  4789. #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN            0x01
  4790. #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE         0x02
  4791.  
  4792. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63      0x01
  4793. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032   0x02
  4794. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030   0x03
  4795. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649   0x04
  4796. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64      0x05
  4797. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375    0x06
  4798. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512   0x07      // Andigilog
  4799.  
  4800.  
  4801. typedef struct  _ATOM_POWERPLAY_INFO
  4802. {
  4803.   ATOM_COMMON_TABLE_HEADER      sHeader;
  4804.   UCHAR    ucOverdriveThermalController;
  4805.   UCHAR    ucOverdriveI2cLine;
  4806.   UCHAR    ucOverdriveIntBitmap;
  4807.   UCHAR    ucOverdriveControllerAddress;
  4808.   UCHAR    ucSizeOfPowerModeEntry;
  4809.   UCHAR    ucNumOfPowerModeEntries;
  4810.   ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
  4811. }ATOM_POWERPLAY_INFO;
  4812.  
  4813. typedef struct  _ATOM_POWERPLAY_INFO_V2
  4814. {
  4815.   ATOM_COMMON_TABLE_HEADER      sHeader;
  4816.   UCHAR    ucOverdriveThermalController;
  4817.   UCHAR    ucOverdriveI2cLine;
  4818.   UCHAR    ucOverdriveIntBitmap;
  4819.   UCHAR    ucOverdriveControllerAddress;
  4820.   UCHAR    ucSizeOfPowerModeEntry;
  4821.   UCHAR    ucNumOfPowerModeEntries;
  4822.   ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
  4823. }ATOM_POWERPLAY_INFO_V2;
  4824.  
  4825. typedef struct  _ATOM_POWERPLAY_INFO_V3
  4826. {
  4827.   ATOM_COMMON_TABLE_HEADER      sHeader;
  4828.   UCHAR    ucOverdriveThermalController;
  4829.   UCHAR    ucOverdriveI2cLine;
  4830.   UCHAR    ucOverdriveIntBitmap;
  4831.   UCHAR    ucOverdriveControllerAddress;
  4832.   UCHAR    ucSizeOfPowerModeEntry;
  4833.   UCHAR    ucNumOfPowerModeEntries;
  4834.   ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
  4835. }ATOM_POWERPLAY_INFO_V3;
  4836.  
  4837.  
  4838.  
  4839. /**************************************************************************/
  4840.  
  4841.  
  4842. // Following definitions are for compatiblity issue in different SW components.
  4843. #define ATOM_MASTER_DATA_TABLE_REVISION   0x01
  4844. #define Object_Info                                                                                             Object_Header                  
  4845. #define AdjustARB_SEQ                                                                                   MC_InitParameter
  4846. #define VRAM_GPIO_DetectionInfo                                         VoltageObjectInfo
  4847. #define ASIC_VDDCI_Info                   ASIC_ProfilingInfo                                                                                                           
  4848. #define ASIC_MVDDQ_Info                                                                         MemoryTrainingInfo
  4849. #define SS_Info                           PPLL_SS_Info                      
  4850. #define ASIC_MVDDC_Info                   ASIC_InternalSS_Info
  4851. #define DispDevicePriorityInfo                                          SaveRestoreInfo
  4852. #define DispOutInfo                                                                                             TV_VideoMode
  4853.  
  4854.  
  4855. #define ATOM_ENCODER_OBJECT_TABLE         ATOM_OBJECT_TABLE
  4856. #define ATOM_CONNECTOR_OBJECT_TABLE       ATOM_OBJECT_TABLE
  4857.  
  4858. //New device naming, remove them when both DAL/VBIOS is ready
  4859. #define DFP2I_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
  4860. #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
  4861.  
  4862. #define DFP1X_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
  4863. #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
  4864.  
  4865. #define DFP1I_OUTPUT_CONTROL_PARAMETERS    DFP1_OUTPUT_CONTROL_PARAMETERS
  4866. #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
  4867.  
  4868. #define ATOM_DEVICE_DFP1I_SUPPORT          ATOM_DEVICE_DFP1_SUPPORT
  4869. #define ATOM_DEVICE_DFP1X_SUPPORT          ATOM_DEVICE_DFP2_SUPPORT
  4870.  
  4871. #define ATOM_DEVICE_DFP1I_INDEX            ATOM_DEVICE_DFP1_INDEX
  4872. #define ATOM_DEVICE_DFP1X_INDEX            ATOM_DEVICE_DFP2_INDEX
  4873.  
  4874. #define ATOM_DEVICE_DFP2I_INDEX            0x00000009
  4875. #define ATOM_DEVICE_DFP2I_SUPPORT          (0x1L << ATOM_DEVICE_DFP2I_INDEX)
  4876.  
  4877. #define ATOM_S0_DFP1I                      ATOM_S0_DFP1
  4878. #define ATOM_S0_DFP1X                      ATOM_S0_DFP2
  4879.  
  4880. #define ATOM_S0_DFP2I                      0x00200000L
  4881. #define ATOM_S0_DFP2Ib2                    0x20
  4882.  
  4883. #define ATOM_S2_DFP1I_DPMS_STATE           ATOM_S2_DFP1_DPMS_STATE
  4884. #define ATOM_S2_DFP1X_DPMS_STATE           ATOM_S2_DFP2_DPMS_STATE
  4885.  
  4886. #define ATOM_S2_DFP2I_DPMS_STATE           0x02000000L
  4887. #define ATOM_S2_DFP2I_DPMS_STATEb3         0x02
  4888.  
  4889. #define ATOM_S3_DFP2I_ACTIVEb1             0x02
  4890.  
  4891. #define ATOM_S3_DFP1I_ACTIVE               ATOM_S3_DFP1_ACTIVE
  4892. #define ATOM_S3_DFP1X_ACTIVE               ATOM_S3_DFP2_ACTIVE
  4893.  
  4894. #define ATOM_S3_DFP2I_ACTIVE               0x00000200L
  4895.  
  4896. #define ATOM_S3_DFP1I_CRTC_ACTIVE          ATOM_S3_DFP1_CRTC_ACTIVE
  4897. #define ATOM_S3_DFP1X_CRTC_ACTIVE          ATOM_S3_DFP2_CRTC_ACTIVE
  4898. #define ATOM_S3_DFP2I_CRTC_ACTIVE          0x02000000L
  4899.  
  4900. #define ATOM_S3_DFP2I_CRTC_ACTIVEb3        0x02
  4901. #define ATOM_S5_DOS_REQ_DFP2Ib1            0x02
  4902.  
  4903. #define ATOM_S5_DOS_REQ_DFP2I              0x0200
  4904. #define ATOM_S6_ACC_REQ_DFP1I              ATOM_S6_ACC_REQ_DFP1
  4905. #define ATOM_S6_ACC_REQ_DFP1X              ATOM_S6_ACC_REQ_DFP2
  4906.  
  4907. #define ATOM_S6_ACC_REQ_DFP2Ib3            0x02
  4908. #define ATOM_S6_ACC_REQ_DFP2I              0x02000000L
  4909.  
  4910. #define TMDS1XEncoderControl               DVOEncoderControl          
  4911. #define DFP1XOutputControl                 DVOOutputControl
  4912.  
  4913. #define ExternalDFPOutputControl           DFP1XOutputControl
  4914. #define EnableExternalTMDS_Encoder         TMDS1XEncoderControl
  4915.  
  4916. #define DFP1IOutputControl                 TMDSAOutputControl
  4917. #define DFP2IOutputControl                 LVTMAOutputControl      
  4918.  
  4919. #define DAC1_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
  4920. #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
  4921.  
  4922. #define DAC2_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
  4923. #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
  4924.  
  4925. #define ucDac1Standard  ucDacStandard
  4926. #define ucDac2Standard  ucDacStandard  
  4927.  
  4928. #define TMDS1EncoderControl TMDSAEncoderControl
  4929. #define TMDS2EncoderControl LVTMAEncoderControl
  4930.  
  4931. #define DFP1OutputControl   TMDSAOutputControl
  4932. #define DFP2OutputControl   LVTMAOutputControl
  4933. #define CRT1OutputControl   DAC1OutputControl
  4934. #define CRT2OutputControl   DAC2OutputControl
  4935.  
  4936. //These two lines will be removed for sure in a few days, will follow up with Michael V.
  4937. #define EnableLVDS_SS   EnableSpreadSpectrumOnPPLL
  4938. #define ENABLE_LVDS_SS_PARAMETERS_V3  ENABLE_SPREAD_SPECTRUM_ON_PPLL  
  4939.  
  4940. /*********************************************************************************/
  4941.  
  4942. #pragma pack() // BIOS data must use byte aligment
  4943.  
  4944. #endif /* _ATOMBIOS_H */
  4945.