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  1. /**************************************************************************
  2.  *
  3.  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4.  * All Rights Reserved.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the
  8.  * "Software"), to deal in the Software without restriction, including
  9.  * without limitation the rights to use, copy, modify, merge, publish,
  10.  * distribute, sub license, and/or sell copies of the Software, and to
  11.  * permit persons to whom the Software is furnished to do so, subject to
  12.  * the following conditions:
  13.  *
  14.  * The above copyright notice and this permission notice (including the
  15.  * next paragraph) shall be included in all copies or substantial portions
  16.  * of the Software.
  17.  *
  18.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20.  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21.  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22.  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23.  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24.  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25.  *
  26.  **************************************************************************/
  27. #define mb()    asm volatile("mfence" : : : "memory")
  28. #define rmb()   asm volatile("lfence" : : : "memory")
  29. #define wmb()   asm volatile("sfence" : : : "memory")
  30.  
  31. #include "vmwgfx_drv.h"
  32. #include <drm/drmP.h>
  33. #include <drm/ttm/ttm_placement.h>
  34.  
  35. #define TASK_INTERRUPTIBLE      1
  36. #define TASK_UNINTERRUPTIBLE    2
  37.  
  38. bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
  39. {
  40.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  41.         uint32_t fifo_min, hwversion;
  42.         const struct vmw_fifo_state *fifo = &dev_priv->fifo;
  43.  
  44.         if (!(dev_priv->capabilities & SVGA_CAP_3D))
  45.                 return false;
  46.  
  47.         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
  48.                 uint32_t result;
  49.  
  50.                 if (!dev_priv->has_mob)
  51.                         return false;
  52.  
  53.                 mutex_lock(&dev_priv->hw_mutex);
  54.                 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
  55.                 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
  56.                 mutex_unlock(&dev_priv->hw_mutex);
  57.  
  58.                 return (result != 0);
  59.         }
  60.  
  61.         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  62.                 return false;
  63.  
  64.         fifo_min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
  65.         if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
  66.                 return false;
  67.  
  68.         hwversion = ioread32(fifo_mem +
  69.                              ((fifo->capabilities &
  70.                                SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
  71.                               SVGA_FIFO_3D_HWVERSION_REVISED :
  72.                               SVGA_FIFO_3D_HWVERSION));
  73.  
  74.         if (hwversion == 0)
  75.                 return false;
  76.  
  77.         if (hwversion < SVGA3D_HWVERSION_WS8_B1)
  78.                 return false;
  79.  
  80.         /* Non-Screen Object path does not support surfaces */
  81.         if (!dev_priv->sou_priv)
  82.                 return false;
  83.  
  84.         return true;
  85. }
  86.  
  87. bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
  88. {
  89.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  90.         uint32_t caps;
  91.  
  92.         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  93.                 return false;
  94.  
  95.         caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
  96.         if (caps & SVGA_FIFO_CAP_PITCHLOCK)
  97.                 return true;
  98.  
  99.         return false;
  100. }
  101.  
  102. int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
  103. {
  104.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  105.         uint32_t max;
  106.         uint32_t min;
  107.         uint32_t dummy;
  108.  
  109.         fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
  110.     fifo->static_buffer = KernelAlloc(fifo->static_buffer_size);
  111.         if (unlikely(fifo->static_buffer == NULL))
  112.                 return -ENOMEM;
  113.  
  114.         fifo->dynamic_buffer = NULL;
  115.         fifo->reserved_size = 0;
  116.         fifo->using_bounce_buffer = false;
  117.  
  118.         mutex_init(&fifo->fifo_mutex);
  119. //   init_rwsem(&fifo->rwsem);
  120.  
  121.         /*
  122.          * Allow mapping the first page read-only to user-space.
  123.          */
  124.  
  125.         DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
  126.         DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
  127.         DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
  128.  
  129.         mutex_lock(&dev_priv->hw_mutex);
  130.         dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
  131.         dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
  132.         dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
  133.         vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
  134.  
  135.         min = 4;
  136.         if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
  137.                 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
  138.         min <<= 2;
  139.  
  140.         if (min < PAGE_SIZE)
  141.                 min = PAGE_SIZE;
  142.  
  143.         iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
  144.         iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
  145.     wmb();
  146.         iowrite32(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
  147.         iowrite32(min,  fifo_mem + SVGA_FIFO_STOP);
  148.         iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
  149.     mb();
  150.  
  151.     vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
  152.         mutex_unlock(&dev_priv->hw_mutex);
  153.  
  154.         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
  155.         min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
  156.         fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
  157.  
  158.         DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
  159.                  (unsigned int) max,
  160.                  (unsigned int) min,
  161.                  (unsigned int) fifo->capabilities);
  162.  
  163.         atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
  164.         iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
  165.     vmw_marker_queue_init(&fifo->marker_queue);
  166.  
  167.     int ret = 0; //vmw_fifo_send_fence(dev_priv, &dummy);
  168.     return ret;
  169. }
  170.  
  171. void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
  172. {
  173.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  174.  
  175.         mutex_lock(&dev_priv->hw_mutex);
  176.  
  177.         if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
  178.                 iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
  179.                 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
  180.         }
  181.  
  182.         mutex_unlock(&dev_priv->hw_mutex);
  183. }
  184.  
  185. void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
  186. {
  187.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  188.  
  189.         mutex_lock(&dev_priv->hw_mutex);
  190.  
  191.         while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
  192.                 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
  193.  
  194.         dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
  195.  
  196.         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
  197.                   dev_priv->config_done_state);
  198.         vmw_write(dev_priv, SVGA_REG_ENABLE,
  199.                   dev_priv->enable_state);
  200.         vmw_write(dev_priv, SVGA_REG_TRACES,
  201.                   dev_priv->traces_state);
  202.  
  203.         mutex_unlock(&dev_priv->hw_mutex);
  204.         vmw_marker_queue_takedown(&fifo->marker_queue);
  205.  
  206.         if (likely(fifo->static_buffer != NULL)) {
  207.                 vfree(fifo->static_buffer);
  208.                 fifo->static_buffer = NULL;
  209.         }
  210.  
  211.         if (likely(fifo->dynamic_buffer != NULL)) {
  212.                 vfree(fifo->dynamic_buffer);
  213.                 fifo->dynamic_buffer = NULL;
  214.         }
  215. }
  216.  
  217. static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
  218. {
  219.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  220.         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
  221.         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
  222.         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
  223.         uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
  224.  
  225.         return ((max - next_cmd) + (stop - min) <= bytes);
  226. }
  227.  
  228. static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
  229.                                uint32_t bytes, bool interruptible,
  230.                                unsigned long timeout)
  231. {
  232.         int ret = 0;
  233.         unsigned long end_jiffies = jiffies + timeout;
  234. //      DEFINE_WAIT(__wait);
  235.  
  236.         DRM_INFO("Fifo wait noirq.\n");
  237.  
  238.         for (;;) {
  239. //       prepare_to_wait(&dev_priv->fifo_queue, &__wait,
  240. //               (interruptible) ?
  241. //               TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
  242.                 if (!vmw_fifo_is_full(dev_priv, bytes))
  243.                         break;
  244.                 if (time_after_eq(jiffies, end_jiffies)) {
  245.                         ret = -EBUSY;
  246.                         DRM_ERROR("SVGA device lockup.\n");
  247.                         break;
  248.                 }
  249.         delay(1);
  250.         }
  251. //   finish_wait(&dev_priv->fifo_queue, &__wait);
  252.         wake_up_all(&dev_priv->fifo_queue);
  253.         DRM_INFO("Fifo noirq exit.\n");
  254.         return ret;
  255. }
  256.  
  257. static int vmw_fifo_wait(struct vmw_private *dev_priv,
  258.                          uint32_t bytes, bool interruptible,
  259.                          unsigned long timeout)
  260. {
  261.         long ret = 1L;
  262.         unsigned long irq_flags;
  263.  
  264.         if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
  265.                 return 0;
  266.  
  267.         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
  268.         if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
  269.                 return vmw_fifo_wait_noirq(dev_priv, bytes,
  270.                                            interruptible, timeout);
  271.  
  272.         mutex_lock(&dev_priv->hw_mutex);
  273.         if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
  274.                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  275.                 outl(SVGA_IRQFLAG_FIFO_PROGRESS,
  276.                      dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  277.                 dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS;
  278.                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  279.                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  280.         }
  281.         mutex_unlock(&dev_priv->hw_mutex);
  282.  
  283.         if (interruptible)
  284.                 ret = wait_event_interruptible_timeout
  285.                     (dev_priv->fifo_queue,
  286.                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
  287.         else
  288.                 ret = wait_event_timeout
  289.                     (dev_priv->fifo_queue,
  290.                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
  291.  
  292.         if (unlikely(ret == 0))
  293.                 ret = -EBUSY;
  294.         else if (likely(ret > 0))
  295.                 ret = 0;
  296.  
  297.         mutex_lock(&dev_priv->hw_mutex);
  298.         if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
  299.                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  300.                 dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
  301.                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  302.                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  303.         }
  304.         mutex_unlock(&dev_priv->hw_mutex);
  305.  
  306.         return ret;
  307. }
  308.  
  309. /**
  310.  * Reserve @bytes number of bytes in the fifo.
  311.  *
  312.  * This function will return NULL (error) on two conditions:
  313.  *  If it timeouts waiting for fifo space, or if @bytes is larger than the
  314.  *   available fifo space.
  315.  *
  316.  * Returns:
  317.  *   Pointer to the fifo, or null on error (possible hardware hang).
  318.  */
  319. void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
  320. {
  321.         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
  322.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  323.         uint32_t max;
  324.         uint32_t min;
  325.         uint32_t next_cmd;
  326.         uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
  327.         int ret;
  328.  
  329.         mutex_lock(&fifo_state->fifo_mutex);
  330.         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
  331.         min = ioread32(fifo_mem + SVGA_FIFO_MIN);
  332.         next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
  333.  
  334.         if (unlikely(bytes >= (max - min)))
  335.                 goto out_err;
  336.  
  337.         BUG_ON(fifo_state->reserved_size != 0);
  338.         BUG_ON(fifo_state->dynamic_buffer != NULL);
  339.  
  340.         fifo_state->reserved_size = bytes;
  341.  
  342.         while (1) {
  343.                 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
  344.                 bool need_bounce = false;
  345.                 bool reserve_in_place = false;
  346.  
  347.                 if (next_cmd >= stop) {
  348.                         if (likely((next_cmd + bytes < max ||
  349.                                     (next_cmd + bytes == max && stop > min))))
  350.                                 reserve_in_place = true;
  351.  
  352.                         else if (vmw_fifo_is_full(dev_priv, bytes)) {
  353.                                 ret = vmw_fifo_wait(dev_priv, bytes,
  354.                                                     false, 3 * HZ);
  355.                                 if (unlikely(ret != 0))
  356.                                         goto out_err;
  357.                         } else
  358.                                 need_bounce = true;
  359.  
  360.                 } else {
  361.  
  362.                         if (likely((next_cmd + bytes < stop)))
  363.                                 reserve_in_place = true;
  364.                         else {
  365.                                 ret = vmw_fifo_wait(dev_priv, bytes,
  366.                                                     false, 3 * HZ);
  367.                                 if (unlikely(ret != 0))
  368.                                         goto out_err;
  369.                         }
  370.                 }
  371.  
  372.                 if (reserve_in_place) {
  373.                         if (reserveable || bytes <= sizeof(uint32_t)) {
  374.                                 fifo_state->using_bounce_buffer = false;
  375.  
  376.                                 if (reserveable)
  377.                                         iowrite32(bytes, fifo_mem +
  378.                                                   SVGA_FIFO_RESERVED);
  379.                                 return fifo_mem + (next_cmd >> 2);
  380.                         } else {
  381.                                 need_bounce = true;
  382.                         }
  383.                 }
  384.  
  385.                 if (need_bounce) {
  386.                         fifo_state->using_bounce_buffer = true;
  387.                         if (bytes < fifo_state->static_buffer_size)
  388.                                 return fifo_state->static_buffer;
  389.                         else {
  390.                 fifo_state->dynamic_buffer = kmalloc(bytes,0);
  391.                                 return fifo_state->dynamic_buffer;
  392.                         }
  393.                 }
  394.         }
  395. out_err:
  396.         fifo_state->reserved_size = 0;
  397.         mutex_unlock(&fifo_state->fifo_mutex);
  398.         return NULL;
  399. }
  400.  
  401. static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
  402.                               __le32 __iomem *fifo_mem,
  403.                               uint32_t next_cmd,
  404.                               uint32_t max, uint32_t min, uint32_t bytes)
  405. {
  406.         uint32_t chunk_size = max - next_cmd;
  407.         uint32_t rest;
  408.         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
  409.             fifo_state->dynamic_buffer : fifo_state->static_buffer;
  410.  
  411.         if (bytes < chunk_size)
  412.                 chunk_size = bytes;
  413.  
  414.         iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
  415.     mb();
  416.     memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
  417.         rest = bytes - chunk_size;
  418.         if (rest)
  419.         memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
  420.                             rest);
  421. }
  422.  
  423. static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
  424.                                __le32 __iomem *fifo_mem,
  425.                                uint32_t next_cmd,
  426.                                uint32_t max, uint32_t min, uint32_t bytes)
  427. {
  428.         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
  429.             fifo_state->dynamic_buffer : fifo_state->static_buffer;
  430.  
  431.         while (bytes > 0) {
  432.                 iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
  433.                 next_cmd += sizeof(uint32_t);
  434.                 if (unlikely(next_cmd == max))
  435.                         next_cmd = min;
  436.                 mb();
  437.                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
  438.                 mb();
  439.                 bytes -= sizeof(uint32_t);
  440.         }
  441. }
  442.  
  443. void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
  444. {
  445.         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
  446.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  447.         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
  448.         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
  449.         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
  450.         bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
  451.  
  452.         BUG_ON((bytes & 3) != 0);
  453.         BUG_ON(bytes > fifo_state->reserved_size);
  454.  
  455.         fifo_state->reserved_size = 0;
  456.  
  457.         if (fifo_state->using_bounce_buffer) {
  458.                 if (reserveable)
  459.                         vmw_fifo_res_copy(fifo_state, fifo_mem,
  460.                                           next_cmd, max, min, bytes);
  461.                 else
  462.                         vmw_fifo_slow_copy(fifo_state, fifo_mem,
  463.                                            next_cmd, max, min, bytes);
  464.  
  465.                 if (fifo_state->dynamic_buffer) {
  466.                         vfree(fifo_state->dynamic_buffer);
  467.                         fifo_state->dynamic_buffer = NULL;
  468.                 }
  469.  
  470.         }
  471.  
  472. //   down_write(&fifo_state->rwsem);
  473.         if (fifo_state->using_bounce_buffer || reserveable) {
  474.                 next_cmd += bytes;
  475.                 if (next_cmd >= max)
  476.                         next_cmd -= max - min;
  477.                 mb();
  478.                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
  479.         }
  480.  
  481.         if (reserveable)
  482.                 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
  483.     mb();
  484. //   up_write(&fifo_state->rwsem);
  485.         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
  486.         mutex_unlock(&fifo_state->fifo_mutex);
  487. }
  488.  
  489. int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
  490. {
  491.         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
  492.         struct svga_fifo_cmd_fence *cmd_fence;
  493.         void *fm;
  494.         int ret = 0;
  495.         uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
  496.  
  497.         fm = vmw_fifo_reserve(dev_priv, bytes);
  498.         if (unlikely(fm == NULL)) {
  499.                 *seqno = atomic_read(&dev_priv->marker_seq);
  500.                 ret = -ENOMEM;
  501.                 (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
  502.                                         false, 3*HZ);
  503.                 goto out_err;
  504.         }
  505.  
  506.         do {
  507.                 *seqno = atomic_add_return(1, &dev_priv->marker_seq);
  508.         } while (*seqno == 0);
  509.  
  510.         if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
  511.  
  512.                 /*
  513.                  * Don't request hardware to send a fence. The
  514.                  * waiting code in vmwgfx_irq.c will emulate this.
  515.                  */
  516.  
  517.                 vmw_fifo_commit(dev_priv, 0);
  518.                 return 0;
  519.         }
  520.  
  521.         *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
  522.         cmd_fence = (struct svga_fifo_cmd_fence *)
  523.             ((unsigned long)fm + sizeof(__le32));
  524.  
  525.         iowrite32(*seqno, &cmd_fence->fence);
  526.         vmw_fifo_commit(dev_priv, bytes);
  527.         (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
  528.         vmw_update_seqno(dev_priv, fifo_state);
  529.  
  530. out_err:
  531.         return ret;
  532. }
  533.  
  534. /**
  535.  * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
  536.  * legacy query commands.
  537.  *
  538.  * @dev_priv: The device private structure.
  539.  * @cid: The hardware context id used for the query.
  540.  *
  541.  * See the vmw_fifo_emit_dummy_query documentation.
  542.  */
  543. static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
  544.                               uint32_t cid)
  545. {
  546.         /*
  547.          * A query wait without a preceding query end will
  548.          * actually finish all queries for this cid
  549.          * without writing to the query result structure.
  550.          */
  551.  
  552.         struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
  553.         struct {
  554.                 SVGA3dCmdHeader header;
  555.                 SVGA3dCmdWaitForQuery body;
  556.         } *cmd;
  557.  
  558.         cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
  559.  
  560.         if (unlikely(cmd == NULL)) {
  561.                 DRM_ERROR("Out of fifo space for dummy query.\n");
  562.                 return -ENOMEM;
  563.         }
  564.  
  565.         cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
  566.         cmd->header.size = sizeof(cmd->body);
  567.         cmd->body.cid = cid;
  568.         cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
  569.  
  570.         if (bo->mem.mem_type == TTM_PL_VRAM) {
  571.                 cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
  572.                 cmd->body.guestResult.offset = bo->offset;
  573.         } else {
  574.                 cmd->body.guestResult.gmrId = bo->mem.start;
  575.                 cmd->body.guestResult.offset = 0;
  576.         }
  577.  
  578.         vmw_fifo_commit(dev_priv, sizeof(*cmd));
  579.  
  580.         return 0;
  581. }
  582.  
  583. /**
  584.  * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
  585.  * guest-backed resource query commands.
  586.  *
  587.  * @dev_priv: The device private structure.
  588.  * @cid: The hardware context id used for the query.
  589.  *
  590.  * See the vmw_fifo_emit_dummy_query documentation.
  591.  */
  592. static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
  593.                                         uint32_t cid)
  594. {
  595.         /*
  596.          * A query wait without a preceding query end will
  597.          * actually finish all queries for this cid
  598.          * without writing to the query result structure.
  599.          */
  600.  
  601.         struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
  602.         struct {
  603.                 SVGA3dCmdHeader header;
  604.                 SVGA3dCmdWaitForGBQuery body;
  605.         } *cmd;
  606.  
  607.         cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
  608.  
  609.         if (unlikely(cmd == NULL)) {
  610.                 DRM_ERROR("Out of fifo space for dummy query.\n");
  611.                 return -ENOMEM;
  612.         }
  613.  
  614.         cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
  615.         cmd->header.size = sizeof(cmd->body);
  616.         cmd->body.cid = cid;
  617.         cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
  618.         BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
  619.         cmd->body.mobid = bo->mem.start;
  620.         cmd->body.offset = 0;
  621.  
  622.         vmw_fifo_commit(dev_priv, sizeof(*cmd));
  623.  
  624.         return 0;
  625. }
  626.  
  627.  
  628. /**
  629.  * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
  630.  * appropriate resource query commands.
  631.  *
  632.  * @dev_priv: The device private structure.
  633.  * @cid: The hardware context id used for the query.
  634.  *
  635.  * This function is used to emit a dummy occlusion query with
  636.  * no primitives rendered between query begin and query end.
  637.  * It's used to provide a query barrier, in order to know that when
  638.  * this query is finished, all preceding queries are also finished.
  639.  *
  640.  * A Query results structure should have been initialized at the start
  641.  * of the dev_priv->dummy_query_bo buffer object. And that buffer object
  642.  * must also be either reserved or pinned when this function is called.
  643.  *
  644.  * Returns -ENOMEM on failure to reserve fifo space.
  645.  */
  646. int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
  647.                               uint32_t cid)
  648. {
  649.         if (dev_priv->has_mob)
  650.                 return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);
  651.  
  652.         return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);
  653. }
  654.