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  1. /**************************************************************************
  2.  *
  3.  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4.  * All Rights Reserved.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the
  8.  * "Software"), to deal in the Software without restriction, including
  9.  * without limitation the rights to use, copy, modify, merge, publish,
  10.  * distribute, sub license, and/or sell copies of the Software, and to
  11.  * permit persons to whom the Software is furnished to do so, subject to
  12.  * the following conditions:
  13.  *
  14.  * The above copyright notice and this permission notice (including the
  15.  * next paragraph) shall be included in all copies or substantial portions
  16.  * of the Software.
  17.  *
  18.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20.  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21.  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22.  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23.  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24.  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25.  *
  26.  **************************************************************************/
  27. #define mb()    asm volatile("mfence" : : : "memory")
  28. #define rmb()   asm volatile("lfence" : : : "memory")
  29. #define wmb()   asm volatile("sfence" : : : "memory")
  30.  
  31. #include "vmwgfx_drv.h"
  32. #include <drm/drmP.h>
  33. #include <drm/ttm/ttm_placement.h>
  34.  
  35. #define TASK_INTERRUPTIBLE      1
  36. #define TASK_UNINTERRUPTIBLE    2
  37.  
  38. bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
  39. {
  40.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  41.         uint32_t fifo_min, hwversion;
  42.         const struct vmw_fifo_state *fifo = &dev_priv->fifo;
  43.  
  44.         if (!(dev_priv->capabilities & SVGA_CAP_3D))
  45.                 return false;
  46.  
  47.         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
  48.                 uint32_t result;
  49.  
  50.                 if (!dev_priv->has_mob)
  51.                         return false;
  52.  
  53.                 mutex_lock(&dev_priv->hw_mutex);
  54.                 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
  55.                 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
  56.                 mutex_unlock(&dev_priv->hw_mutex);
  57.  
  58.                 return (result != 0);
  59.         }
  60.  
  61.         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  62.                 return false;
  63.  
  64.         fifo_min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
  65.         if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
  66.                 return false;
  67.  
  68.         hwversion = ioread32(fifo_mem +
  69.                              ((fifo->capabilities &
  70.                                SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
  71.                               SVGA_FIFO_3D_HWVERSION_REVISED :
  72.                               SVGA_FIFO_3D_HWVERSION));
  73.  
  74.         if (hwversion == 0)
  75.                 return false;
  76.  
  77.         if (hwversion < SVGA3D_HWVERSION_WS8_B1)
  78.                 return false;
  79.  
  80.         /* Non-Screen Object path does not support surfaces */
  81.         if (!dev_priv->sou_priv)
  82.                 return false;
  83.  
  84.         return true;
  85. }
  86.  
  87. bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
  88. {
  89.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  90.         uint32_t caps;
  91.  
  92.         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  93.                 return false;
  94.  
  95.         caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
  96.         if (caps & SVGA_FIFO_CAP_PITCHLOCK)
  97.                 return true;
  98.  
  99.         return false;
  100. }
  101.  
  102. int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
  103. {
  104.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  105.         uint32_t max;
  106.         uint32_t min;
  107.         uint32_t dummy;
  108.  
  109.     ENTER();
  110.  
  111.         fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
  112.     fifo->static_buffer = KernelAlloc(fifo->static_buffer_size);
  113.         if (unlikely(fifo->static_buffer == NULL))
  114.                 return -ENOMEM;
  115.  
  116.         fifo->dynamic_buffer = NULL;
  117.         fifo->reserved_size = 0;
  118.         fifo->using_bounce_buffer = false;
  119.  
  120.         mutex_init(&fifo->fifo_mutex);
  121. //   init_rwsem(&fifo->rwsem);
  122.  
  123.         /*
  124.          * Allow mapping the first page read-only to user-space.
  125.          */
  126.  
  127.         DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
  128.         DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
  129.         DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
  130.  
  131.         mutex_lock(&dev_priv->hw_mutex);
  132.         dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
  133.         dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
  134.         dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
  135.         vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
  136.  
  137.         min = 4;
  138.         if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
  139.                 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
  140.         min <<= 2;
  141.  
  142.         if (min < PAGE_SIZE)
  143.                 min = PAGE_SIZE;
  144.  
  145.         iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
  146.         iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
  147.     wmb();
  148.         iowrite32(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
  149.         iowrite32(min,  fifo_mem + SVGA_FIFO_STOP);
  150.         iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
  151.     mb();
  152.  
  153.     vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
  154.         mutex_unlock(&dev_priv->hw_mutex);
  155.  
  156.         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
  157.         min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
  158.         fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
  159.  
  160.         DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
  161.                  (unsigned int) max,
  162.                  (unsigned int) min,
  163.                  (unsigned int) fifo->capabilities);
  164.  
  165.         atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
  166.         iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
  167.     vmw_marker_queue_init(&fifo->marker_queue);
  168.  
  169.     int ret = 0; //vmw_fifo_send_fence(dev_priv, &dummy);
  170.     LEAVE();
  171.     return ret;
  172. }
  173.  
  174. void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
  175. {
  176.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  177.  
  178.         mutex_lock(&dev_priv->hw_mutex);
  179.  
  180.         if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
  181.                 iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
  182.                 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
  183.         }
  184.  
  185.         mutex_unlock(&dev_priv->hw_mutex);
  186. }
  187.  
  188. void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
  189. {
  190.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  191.  
  192.         mutex_lock(&dev_priv->hw_mutex);
  193.  
  194.         while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
  195.                 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
  196.  
  197.         dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
  198.  
  199.         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
  200.                   dev_priv->config_done_state);
  201.         vmw_write(dev_priv, SVGA_REG_ENABLE,
  202.                   dev_priv->enable_state);
  203.         vmw_write(dev_priv, SVGA_REG_TRACES,
  204.                   dev_priv->traces_state);
  205.  
  206.         mutex_unlock(&dev_priv->hw_mutex);
  207.         vmw_marker_queue_takedown(&fifo->marker_queue);
  208.  
  209.         if (likely(fifo->static_buffer != NULL)) {
  210.                 vfree(fifo->static_buffer);
  211.                 fifo->static_buffer = NULL;
  212.         }
  213.  
  214.         if (likely(fifo->dynamic_buffer != NULL)) {
  215.                 vfree(fifo->dynamic_buffer);
  216.                 fifo->dynamic_buffer = NULL;
  217.         }
  218. }
  219.  
  220. static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
  221. {
  222.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  223.         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
  224.         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
  225.         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
  226.         uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
  227.  
  228.         return ((max - next_cmd) + (stop - min) <= bytes);
  229. }
  230.  
  231. static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
  232.                                uint32_t bytes, bool interruptible,
  233.                                unsigned long timeout)
  234. {
  235.         int ret = 0;
  236.     unsigned long end_jiffies = GetTimerTicks() + timeout;
  237.         DEFINE_WAIT(__wait);
  238.  
  239.         DRM_INFO("Fifo wait noirq.\n");
  240.  
  241.         for (;;) {
  242. //       prepare_to_wait(&dev_priv->fifo_queue, &__wait,
  243. //               (interruptible) ?
  244. //               TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
  245.                 if (!vmw_fifo_is_full(dev_priv, bytes))
  246.                         break;
  247.         if (time_after_eq(GetTimerTicks(), end_jiffies)) {
  248.                         ret = -EBUSY;
  249.                         DRM_ERROR("SVGA device lockup.\n");
  250.                         break;
  251.                 }
  252.         delay(1);
  253.         }
  254. //   finish_wait(&dev_priv->fifo_queue, &__wait);
  255.         wake_up_all(&dev_priv->fifo_queue);
  256.         DRM_INFO("Fifo noirq exit.\n");
  257.         return ret;
  258. }
  259.  
  260. static int vmw_fifo_wait(struct vmw_private *dev_priv,
  261.                          uint32_t bytes, bool interruptible,
  262.                          unsigned long timeout)
  263. {
  264.         long ret = 1L;
  265.         unsigned long irq_flags;
  266.  
  267.         if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
  268.                 return 0;
  269.  
  270.         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
  271.         if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
  272.                 return vmw_fifo_wait_noirq(dev_priv, bytes,
  273.                                            interruptible, timeout);
  274.  
  275.         mutex_lock(&dev_priv->hw_mutex);
  276.         if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
  277.                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  278.                 outl(SVGA_IRQFLAG_FIFO_PROGRESS,
  279.                      dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  280.                 dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS;
  281.                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  282.                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  283.         }
  284.         mutex_unlock(&dev_priv->hw_mutex);
  285.  
  286.         if (interruptible)
  287.                 ret = wait_event_interruptible_timeout
  288.                     (dev_priv->fifo_queue,
  289.                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
  290.         else
  291.                 ret = wait_event_timeout
  292.                     (dev_priv->fifo_queue,
  293.                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
  294.  
  295.         if (unlikely(ret == 0))
  296.                 ret = -EBUSY;
  297.         else if (likely(ret > 0))
  298.                 ret = 0;
  299.  
  300.         mutex_lock(&dev_priv->hw_mutex);
  301.         if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
  302.                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  303.                 dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
  304.                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  305.                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  306.         }
  307.         mutex_unlock(&dev_priv->hw_mutex);
  308.  
  309.         return ret;
  310. }
  311.  
  312. /**
  313.  * Reserve @bytes number of bytes in the fifo.
  314.  *
  315.  * This function will return NULL (error) on two conditions:
  316.  *  If it timeouts waiting for fifo space, or if @bytes is larger than the
  317.  *   available fifo space.
  318.  *
  319.  * Returns:
  320.  *   Pointer to the fifo, or null on error (possible hardware hang).
  321.  */
  322. void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
  323. {
  324.         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
  325.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  326.         uint32_t max;
  327.         uint32_t min;
  328.         uint32_t next_cmd;
  329.         uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
  330.         int ret;
  331.  
  332.         mutex_lock(&fifo_state->fifo_mutex);
  333.         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
  334.         min = ioread32(fifo_mem + SVGA_FIFO_MIN);
  335.         next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
  336.  
  337.         if (unlikely(bytes >= (max - min)))
  338.                 goto out_err;
  339.  
  340.         BUG_ON(fifo_state->reserved_size != 0);
  341.         BUG_ON(fifo_state->dynamic_buffer != NULL);
  342.  
  343.         fifo_state->reserved_size = bytes;
  344.  
  345.         while (1) {
  346.                 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
  347.                 bool need_bounce = false;
  348.                 bool reserve_in_place = false;
  349.  
  350.                 if (next_cmd >= stop) {
  351.                         if (likely((next_cmd + bytes < max ||
  352.                                     (next_cmd + bytes == max && stop > min))))
  353.                                 reserve_in_place = true;
  354.  
  355.                         else if (vmw_fifo_is_full(dev_priv, bytes)) {
  356.                                 ret = vmw_fifo_wait(dev_priv, bytes,
  357.                                                     false, 3 * HZ);
  358.                                 if (unlikely(ret != 0))
  359.                                         goto out_err;
  360.                         } else
  361.                                 need_bounce = true;
  362.  
  363.                 } else {
  364.  
  365.                         if (likely((next_cmd + bytes < stop)))
  366.                                 reserve_in_place = true;
  367.                         else {
  368.                                 ret = vmw_fifo_wait(dev_priv, bytes,
  369.                                                     false, 3 * HZ);
  370.                                 if (unlikely(ret != 0))
  371.                                         goto out_err;
  372.                         }
  373.                 }
  374.  
  375.                 if (reserve_in_place) {
  376.                         if (reserveable || bytes <= sizeof(uint32_t)) {
  377.                                 fifo_state->using_bounce_buffer = false;
  378.  
  379.                                 if (reserveable)
  380.                                         iowrite32(bytes, fifo_mem +
  381.                                                   SVGA_FIFO_RESERVED);
  382.                                 return fifo_mem + (next_cmd >> 2);
  383.                         } else {
  384.                                 need_bounce = true;
  385.                         }
  386.                 }
  387.  
  388.                 if (need_bounce) {
  389.                         fifo_state->using_bounce_buffer = true;
  390.                         if (bytes < fifo_state->static_buffer_size)
  391.                                 return fifo_state->static_buffer;
  392.                         else {
  393.                 fifo_state->dynamic_buffer = kmalloc(bytes,0);
  394.                                 return fifo_state->dynamic_buffer;
  395.                         }
  396.                 }
  397.         }
  398. out_err:
  399.         fifo_state->reserved_size = 0;
  400.         mutex_unlock(&fifo_state->fifo_mutex);
  401.         return NULL;
  402. }
  403.  
  404. static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
  405.                               __le32 __iomem *fifo_mem,
  406.                               uint32_t next_cmd,
  407.                               uint32_t max, uint32_t min, uint32_t bytes)
  408. {
  409.         uint32_t chunk_size = max - next_cmd;
  410.         uint32_t rest;
  411.         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
  412.             fifo_state->dynamic_buffer : fifo_state->static_buffer;
  413.  
  414.         if (bytes < chunk_size)
  415.                 chunk_size = bytes;
  416.  
  417.         iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
  418.     mb();
  419.     memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
  420.         rest = bytes - chunk_size;
  421.         if (rest)
  422.         memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
  423.                             rest);
  424. }
  425.  
  426. static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
  427.                                __le32 __iomem *fifo_mem,
  428.                                uint32_t next_cmd,
  429.                                uint32_t max, uint32_t min, uint32_t bytes)
  430. {
  431.         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
  432.             fifo_state->dynamic_buffer : fifo_state->static_buffer;
  433.  
  434.         while (bytes > 0) {
  435.                 iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
  436.                 next_cmd += sizeof(uint32_t);
  437.                 if (unlikely(next_cmd == max))
  438.                         next_cmd = min;
  439.                 mb();
  440.                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
  441.                 mb();
  442.                 bytes -= sizeof(uint32_t);
  443.         }
  444. }
  445.  
  446. void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
  447. {
  448.         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
  449.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  450.         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
  451.         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
  452.         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
  453.         bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
  454.  
  455.         BUG_ON((bytes & 3) != 0);
  456.         BUG_ON(bytes > fifo_state->reserved_size);
  457.  
  458.         fifo_state->reserved_size = 0;
  459.  
  460.         if (fifo_state->using_bounce_buffer) {
  461.                 if (reserveable)
  462.                         vmw_fifo_res_copy(fifo_state, fifo_mem,
  463.                                           next_cmd, max, min, bytes);
  464.                 else
  465.                         vmw_fifo_slow_copy(fifo_state, fifo_mem,
  466.                                            next_cmd, max, min, bytes);
  467.  
  468.                 if (fifo_state->dynamic_buffer) {
  469.                         vfree(fifo_state->dynamic_buffer);
  470.                         fifo_state->dynamic_buffer = NULL;
  471.                 }
  472.  
  473.         }
  474.  
  475. //   down_write(&fifo_state->rwsem);
  476.         if (fifo_state->using_bounce_buffer || reserveable) {
  477.                 next_cmd += bytes;
  478.                 if (next_cmd >= max)
  479.                         next_cmd -= max - min;
  480.                 mb();
  481.                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
  482.         }
  483.  
  484.         if (reserveable)
  485.                 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
  486.     mb();
  487. //   up_write(&fifo_state->rwsem);
  488.         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
  489.         mutex_unlock(&fifo_state->fifo_mutex);
  490. }
  491.  
  492. int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
  493. {
  494.         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
  495.         struct svga_fifo_cmd_fence *cmd_fence;
  496.         void *fm;
  497.         int ret = 0;
  498.         uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
  499.  
  500.         fm = vmw_fifo_reserve(dev_priv, bytes);
  501.         if (unlikely(fm == NULL)) {
  502.                 *seqno = atomic_read(&dev_priv->marker_seq);
  503.                 ret = -ENOMEM;
  504.                 (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
  505.                                         false, 3*HZ);
  506.                 goto out_err;
  507.         }
  508.  
  509.         do {
  510.                 *seqno = atomic_add_return(1, &dev_priv->marker_seq);
  511.         } while (*seqno == 0);
  512.  
  513.         if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
  514.  
  515.                 /*
  516.                  * Don't request hardware to send a fence. The
  517.                  * waiting code in vmwgfx_irq.c will emulate this.
  518.                  */
  519.  
  520.                 vmw_fifo_commit(dev_priv, 0);
  521.                 return 0;
  522.         }
  523.  
  524.         *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
  525.         cmd_fence = (struct svga_fifo_cmd_fence *)
  526.             ((unsigned long)fm + sizeof(__le32));
  527.  
  528.         iowrite32(*seqno, &cmd_fence->fence);
  529.         vmw_fifo_commit(dev_priv, bytes);
  530.         (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
  531.         vmw_update_seqno(dev_priv, fifo_state);
  532.  
  533. out_err:
  534.         return ret;
  535. }
  536.  
  537. /**
  538.  * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
  539.  * legacy query commands.
  540.  *
  541.  * @dev_priv: The device private structure.
  542.  * @cid: The hardware context id used for the query.
  543.  *
  544.  * See the vmw_fifo_emit_dummy_query documentation.
  545.  */
  546. static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
  547.                               uint32_t cid)
  548. {
  549.         /*
  550.          * A query wait without a preceding query end will
  551.          * actually finish all queries for this cid
  552.          * without writing to the query result structure.
  553.          */
  554.  
  555.         struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
  556.         struct {
  557.                 SVGA3dCmdHeader header;
  558.                 SVGA3dCmdWaitForQuery body;
  559.         } *cmd;
  560.  
  561.         cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
  562.  
  563.         if (unlikely(cmd == NULL)) {
  564.                 DRM_ERROR("Out of fifo space for dummy query.\n");
  565.                 return -ENOMEM;
  566.         }
  567.  
  568.         cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
  569.         cmd->header.size = sizeof(cmd->body);
  570.         cmd->body.cid = cid;
  571.         cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
  572.  
  573.         if (bo->mem.mem_type == TTM_PL_VRAM) {
  574.                 cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
  575.                 cmd->body.guestResult.offset = bo->offset;
  576.         } else {
  577.                 cmd->body.guestResult.gmrId = bo->mem.start;
  578.                 cmd->body.guestResult.offset = 0;
  579.         }
  580.  
  581.         vmw_fifo_commit(dev_priv, sizeof(*cmd));
  582.  
  583.         return 0;
  584. }
  585.  
  586. /**
  587.  * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
  588.  * guest-backed resource query commands.
  589.  *
  590.  * @dev_priv: The device private structure.
  591.  * @cid: The hardware context id used for the query.
  592.  *
  593.  * See the vmw_fifo_emit_dummy_query documentation.
  594.  */
  595. static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
  596.                                         uint32_t cid)
  597. {
  598.         /*
  599.          * A query wait without a preceding query end will
  600.          * actually finish all queries for this cid
  601.          * without writing to the query result structure.
  602.          */
  603.  
  604.         struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
  605.         struct {
  606.                 SVGA3dCmdHeader header;
  607.                 SVGA3dCmdWaitForGBQuery body;
  608.         } *cmd;
  609.  
  610.         cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
  611.  
  612.         if (unlikely(cmd == NULL)) {
  613.                 DRM_ERROR("Out of fifo space for dummy query.\n");
  614.                 return -ENOMEM;
  615.         }
  616.  
  617.         cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
  618.         cmd->header.size = sizeof(cmd->body);
  619.         cmd->body.cid = cid;
  620.         cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
  621.         BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
  622.         cmd->body.mobid = bo->mem.start;
  623.         cmd->body.offset = 0;
  624.  
  625.         vmw_fifo_commit(dev_priv, sizeof(*cmd));
  626.  
  627.         return 0;
  628. }
  629.  
  630.  
  631. /**
  632.  * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
  633.  * appropriate resource query commands.
  634.  *
  635.  * @dev_priv: The device private structure.
  636.  * @cid: The hardware context id used for the query.
  637.  *
  638.  * This function is used to emit a dummy occlusion query with
  639.  * no primitives rendered between query begin and query end.
  640.  * It's used to provide a query barrier, in order to know that when
  641.  * this query is finished, all preceding queries are also finished.
  642.  *
  643.  * A Query results structure should have been initialized at the start
  644.  * of the dev_priv->dummy_query_bo buffer object. And that buffer object
  645.  * must also be either reserved or pinned when this function is called.
  646.  *
  647.  * Returns -ENOMEM on failure to reserve fifo space.
  648.  */
  649. int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
  650.                               uint32_t cid)
  651. {
  652.         if (dev_priv->has_mob)
  653.                 return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);
  654.  
  655.         return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);
  656. }
  657.