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  1. /*
  2.  * Copyright 2011 Advanced Micro Devices, Inc.
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice shall be included in
  12.  * all copies or substantial portions of the Software.
  13.  *
  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20.  * OTHER DEALINGS IN THE SOFTWARE.
  21.  *
  22.  */
  23. #ifndef __RV770_DPM_H__
  24. #define __RV770_DPM_H__
  25.  
  26. #include "rv770_smc.h"
  27.  
  28. struct rv770_clock_registers {
  29.         u32 cg_spll_func_cntl;
  30.         u32 cg_spll_func_cntl_2;
  31.         u32 cg_spll_func_cntl_3;
  32.         u32 cg_spll_spread_spectrum;
  33.         u32 cg_spll_spread_spectrum_2;
  34.         u32 mpll_ad_func_cntl;
  35.         u32 mpll_ad_func_cntl_2;
  36.         u32 mpll_dq_func_cntl;
  37.         u32 mpll_dq_func_cntl_2;
  38.         u32 mclk_pwrmgt_cntl;
  39.         u32 dll_cntl;
  40.         u32 mpll_ss1;
  41.         u32 mpll_ss2;
  42. };
  43.  
  44. struct rv730_clock_registers {
  45.         u32 cg_spll_func_cntl;
  46.         u32 cg_spll_func_cntl_2;
  47.         u32 cg_spll_func_cntl_3;
  48.         u32 cg_spll_spread_spectrum;
  49.         u32 cg_spll_spread_spectrum_2;
  50.         u32 mclk_pwrmgt_cntl;
  51.         u32 dll_cntl;
  52.         u32 mpll_func_cntl;
  53.         u32 mpll_func_cntl2;
  54.         u32 mpll_func_cntl3;
  55.         u32 mpll_ss;
  56.         u32 mpll_ss2;
  57. };
  58.  
  59. union r7xx_clock_registers {
  60.         struct rv770_clock_registers rv770;
  61.         struct rv730_clock_registers rv730;
  62. };
  63.  
  64. struct vddc_table_entry {
  65.         u16 vddc;
  66.         u8 vddc_index;
  67.         u8 high_smio;
  68.         u32 low_smio;
  69. };
  70.  
  71. #define MAX_NO_OF_MVDD_VALUES 2
  72. #define MAX_NO_VREG_STEPS 32
  73.  
  74. struct rv7xx_power_info {
  75.         /* flags */
  76.         bool mem_gddr5;
  77.         bool pcie_gen2;
  78.         bool dynamic_pcie_gen2;
  79.         bool acpi_pcie_gen2;
  80.         bool boot_in_gen2;
  81.         bool voltage_control; /* vddc */
  82.         bool mvdd_control;
  83.         bool sclk_ss;
  84.         bool mclk_ss;
  85.         bool dynamic_ss;
  86.         bool gfx_clock_gating;
  87.         bool mg_clock_gating;
  88.         bool mgcgtssm;
  89.         bool power_gating;
  90.         bool thermal_protection;
  91.         bool display_gap;
  92.         bool dcodt;
  93.         bool ulps;
  94.         /* registers */
  95.         union r7xx_clock_registers clk_regs;
  96.         u32 s0_vid_lower_smio_cntl;
  97.         /* voltage */
  98.         u32 vddc_mask_low;
  99.         u32 mvdd_mask_low;
  100.         u32 mvdd_split_frequency;
  101.         u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
  102.         u16 max_vddc;
  103.         u16 max_vddc_in_table;
  104.         u16 min_vddc_in_table;
  105.         struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
  106.         u8 valid_vddc_entries;
  107.         /* dc odt */
  108.         u32 mclk_odt_threshold;
  109.         u8 odt_value_0[2];
  110.         u8 odt_value_1[2];
  111.         /* stored values */
  112.         u32 boot_sclk;
  113.         u16 acpi_vddc;
  114.         u32 ref_div;
  115.         u32 active_auto_throttle_sources;
  116.         u32 mclk_stutter_mode_threshold;
  117.         u32 mclk_strobe_mode_threshold;
  118.         u32 mclk_edc_enable_threshold;
  119.         u32 bsp;
  120.         u32 bsu;
  121.         u32 pbsp;
  122.         u32 pbsu;
  123.         u32 dsp;
  124.         u32 psp;
  125.         u32 asi;
  126.         u32 pasi;
  127.         u32 vrc;
  128.         u32 restricted_levels;
  129.         u32 rlp;
  130.         u32 rmp;
  131.         u32 lhp;
  132.         u32 lmp;
  133.         /* smc offsets */
  134.         u16 state_table_start;
  135.         u16 soft_regs_start;
  136.         u16 sram_end;
  137.         /* scratch structs */
  138.         RV770_SMC_STATETABLE smc_statetable;
  139. };
  140.  
  141. struct rv7xx_pl {
  142.         u32 sclk;
  143.         u32 mclk;
  144.         u16 vddc;
  145.         u16 vddci; /* eg+ only */
  146.         u32 flags;
  147.         enum radeon_pcie_gen pcie_gen; /* si+ only */
  148. };
  149.  
  150. struct rv7xx_ps {
  151.         struct rv7xx_pl high;
  152.         struct rv7xx_pl medium;
  153.         struct rv7xx_pl low;
  154.         bool dc_compatible;
  155. };
  156.  
  157. #define RV770_RLP_DFLT                                10
  158. #define RV770_RMP_DFLT                                25
  159. #define RV770_LHP_DFLT                                25
  160. #define RV770_LMP_DFLT                                10
  161. #define RV770_VRC_DFLT                                0x003f
  162. #define RV770_ASI_DFLT                                1000
  163. #define RV770_HASI_DFLT                               200000
  164. #define RV770_MGCGTTLOCAL0_DFLT                       0x00100000
  165. #define RV7XX_MGCGTTLOCAL0_DFLT                       0
  166. #define RV770_MGCGTTLOCAL1_DFLT                       0xFFFF0000
  167. #define RV770_MGCGCGTSSMCTRL_DFLT                     0x55940000
  168.  
  169. #define MVDD_LOW_INDEX  0
  170. #define MVDD_HIGH_INDEX 1
  171.  
  172. #define MVDD_LOW_VALUE  0
  173. #define MVDD_HIGH_VALUE 0xffff
  174.  
  175. #define RV770_DEFAULT_VCLK_FREQ  53300 /* 10 khz */
  176. #define RV770_DEFAULT_DCLK_FREQ  40000 /* 10 khz */
  177.  
  178. /* rv730/rv710 */
  179. int rv730_populate_sclk_value(struct radeon_device *rdev,
  180.                               u32 engine_clock,
  181.                               RV770_SMC_SCLK_VALUE *sclk);
  182. int rv730_populate_mclk_value(struct radeon_device *rdev,
  183.                               u32 engine_clock, u32 memory_clock,
  184.                               LPRV7XX_SMC_MCLK_VALUE mclk);
  185. void rv730_read_clock_registers(struct radeon_device *rdev);
  186. int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
  187.                                   RV770_SMC_STATETABLE *table);
  188. int rv730_populate_smc_initial_state(struct radeon_device *rdev,
  189.                                      struct radeon_ps *radeon_initial_state,
  190.                                      RV770_SMC_STATETABLE *table);
  191. void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
  192.                                             struct radeon_ps *radeon_state);
  193. void rv730_power_gating_enable(struct radeon_device *rdev,
  194.                                bool enable);
  195. void rv730_start_dpm(struct radeon_device *rdev);
  196. void rv730_stop_dpm(struct radeon_device *rdev);
  197. void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt);
  198. void rv730_get_odt_values(struct radeon_device *rdev);
  199.  
  200. /* rv740 */
  201. int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
  202.                               RV770_SMC_SCLK_VALUE *sclk);
  203. int rv740_populate_mclk_value(struct radeon_device *rdev,
  204.                               u32 engine_clock, u32 memory_clock,
  205.                               RV7XX_SMC_MCLK_VALUE *mclk);
  206. void rv740_read_clock_registers(struct radeon_device *rdev);
  207. int rv740_populate_smc_acpi_state(struct radeon_device *rdev,
  208.                                   RV770_SMC_STATETABLE *table);
  209. void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev,
  210.                                        bool enable);
  211. u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
  212. u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
  213. u32 rv740_get_decoded_reference_divider(u32 encoded_ref);
  214.  
  215. /* rv770 */
  216. u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);
  217. int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
  218.                               RV770_SMC_VOLTAGE_VALUE *voltage);
  219. int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
  220.                               RV770_SMC_VOLTAGE_VALUE *voltage);
  221. u8 rv770_get_seq_value(struct radeon_device *rdev,
  222.                        struct rv7xx_pl *pl);
  223. int rv770_populate_initial_mvdd_value(struct radeon_device *rdev,
  224.                                       RV770_SMC_VOLTAGE_VALUE *voltage);
  225. u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
  226.                                         u32 engine_clock);
  227. void rv770_program_response_times(struct radeon_device *rdev);
  228. int rv770_populate_smc_sp(struct radeon_device *rdev,
  229.                           struct radeon_ps *radeon_state,
  230.                           RV770_SMC_SWSTATE *smc_state);
  231. int rv770_populate_smc_t(struct radeon_device *rdev,
  232.                          struct radeon_ps *radeon_state,
  233.                          RV770_SMC_SWSTATE *smc_state);
  234. void rv770_read_voltage_smio_registers(struct radeon_device *rdev);
  235. void rv770_get_memory_type(struct radeon_device *rdev);
  236. void r7xx_start_smc(struct radeon_device *rdev);
  237. u8 rv770_get_memory_module_index(struct radeon_device *rdev);
  238. void rv770_get_max_vddc(struct radeon_device *rdev);
  239. void rv770_get_pcie_gen2_status(struct radeon_device *rdev);
  240. void rv770_enable_acpi_pm(struct radeon_device *rdev);
  241. void rv770_restore_cgcg(struct radeon_device *rdev);
  242. bool rv770_dpm_enabled(struct radeon_device *rdev);
  243. void rv770_enable_voltage_control(struct radeon_device *rdev,
  244.                                   bool enable);
  245. void rv770_enable_backbias(struct radeon_device *rdev,
  246.                            bool enable);
  247. void rv770_enable_thermal_protection(struct radeon_device *rdev,
  248.                                      bool enable);
  249. void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
  250.                                        enum radeon_dpm_auto_throttle_src source,
  251.                                        bool enable);
  252. void rv770_setup_bsp(struct radeon_device *rdev);
  253. void rv770_program_git(struct radeon_device *rdev);
  254. void rv770_program_tp(struct radeon_device *rdev);
  255. void rv770_program_tpp(struct radeon_device *rdev);
  256. void rv770_program_sstp(struct radeon_device *rdev);
  257. void rv770_program_engine_speed_parameters(struct radeon_device *rdev);
  258. void rv770_program_vc(struct radeon_device *rdev);
  259. void rv770_clear_vc(struct radeon_device *rdev);
  260. int rv770_upload_firmware(struct radeon_device *rdev);
  261. void rv770_stop_dpm(struct radeon_device *rdev);
  262. void r7xx_stop_smc(struct radeon_device *rdev);
  263. void rv770_reset_smio_status(struct radeon_device *rdev);
  264. int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev);
  265. int rv770_dpm_force_performance_level(struct radeon_device *rdev,
  266.                                       enum radeon_dpm_forced_level level);
  267. int rv770_halt_smc(struct radeon_device *rdev);
  268. int rv770_resume_smc(struct radeon_device *rdev);
  269. int rv770_set_sw_state(struct radeon_device *rdev);
  270. int rv770_set_boot_state(struct radeon_device *rdev);
  271. int rv7xx_parse_power_table(struct radeon_device *rdev);
  272. void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
  273.                                               struct radeon_ps *new_ps,
  274.                                               struct radeon_ps *old_ps);
  275. void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
  276.                                              struct radeon_ps *new_ps,
  277.                                              struct radeon_ps *old_ps);
  278. void rv770_get_engine_memory_ss(struct radeon_device *rdev);
  279.  
  280. /* smc */
  281. int rv770_write_smc_soft_register(struct radeon_device *rdev,
  282.                                   u16 reg_offset, u32 value);
  283.  
  284. #endif
  285.