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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. /* RS600 / Radeon X1250/X1270 integrated GPU
  29.  *
  30.  * This file gather function specific to RS600 which is the IGP of
  31.  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32.  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33.  * the avivo one, bios is an atombios, 3D block are the one of the
  34.  * R4XX family. The GART is different from the RS400 one and is very
  35.  * close to the one of the R600 family (R600 likely being an evolution
  36.  * of the RS600 GART block).
  37.  */
  38. #include "drmP.h"
  39. #include "radeon.h"
  40. #include "atom.h"
  41. #include "rs600d.h"
  42.  
  43. #include "rs600_reg_safe.h"
  44.  
  45. void rs600_gpu_init(struct radeon_device *rdev);
  46. int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  47.  
  48. int rs600_mc_init(struct radeon_device *rdev)
  49. {
  50.         /* read back the MC value from the hw */
  51.         int r;
  52.         u32 tmp;
  53.  
  54.         /* Setup GPU memory space */
  55.         tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
  56.         rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
  57.         rdev->mc.gtt_location = 0xffffffffUL;
  58.         r = radeon_mc_setup(rdev);
  59.         if (r)
  60.                 return r;
  61.         return 0;
  62. }
  63.  
  64. /* hpd for digital panel detect/disconnect */
  65. bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  66. {
  67.         u32 tmp;
  68.         bool connected = false;
  69.  
  70.         switch (hpd) {
  71.         case RADEON_HPD_1:
  72.                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
  73.                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
  74.                         connected = true;
  75.                 break;
  76.         case RADEON_HPD_2:
  77.                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
  78.                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
  79.                         connected = true;
  80.                 break;
  81.         default:
  82.                 break;
  83.         }
  84.         return connected;
  85. }
  86.  
  87. void rs600_hpd_set_polarity(struct radeon_device *rdev,
  88.                             enum radeon_hpd_id hpd)
  89. {
  90.         u32 tmp;
  91.         bool connected = rs600_hpd_sense(rdev, hpd);
  92.  
  93.         switch (hpd) {
  94.         case RADEON_HPD_1:
  95.                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
  96.                 if (connected)
  97.                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
  98.                 else
  99.                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
  100.                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  101.                 break;
  102.         case RADEON_HPD_2:
  103.                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
  104.                 if (connected)
  105.                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
  106.                 else
  107.                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
  108.                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  109.                 break;
  110.         default:
  111.                 break;
  112.         }
  113. }
  114.  
  115. void rs600_hpd_init(struct radeon_device *rdev)
  116. {
  117.         struct drm_device *dev = rdev->ddev;
  118.         struct drm_connector *connector;
  119.  
  120.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  121.                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  122.                 switch (radeon_connector->hpd.hpd) {
  123.                 case RADEON_HPD_1:
  124.                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
  125.                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
  126.                         rdev->irq.hpd[0] = true;
  127.                         break;
  128.                 case RADEON_HPD_2:
  129.                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
  130.                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
  131.                         rdev->irq.hpd[1] = true;
  132.                         break;
  133.                 default:
  134.                         break;
  135.                 }
  136.         }
  137.         rs600_irq_set(rdev);
  138. }
  139.  
  140. void rs600_hpd_fini(struct radeon_device *rdev)
  141. {
  142.         struct drm_device *dev = rdev->ddev;
  143.         struct drm_connector *connector;
  144.  
  145.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  146.                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  147.                 switch (radeon_connector->hpd.hpd) {
  148.                 case RADEON_HPD_1:
  149.                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
  150.                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
  151.                         rdev->irq.hpd[0] = false;
  152.                         break;
  153.                 case RADEON_HPD_2:
  154.                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
  155.                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
  156.                         rdev->irq.hpd[1] = false;
  157.                         break;
  158.                 default:
  159.                         break;
  160.                 }
  161.         }
  162. }
  163.  
  164. /*
  165.  * GART.
  166.  */
  167. void rs600_gart_tlb_flush(struct radeon_device *rdev)
  168. {
  169.         uint32_t tmp;
  170.  
  171.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  172.         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  173.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  174.  
  175.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  176.         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
  177.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  178.  
  179.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  180.         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  181.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  182.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  183. }
  184.  
  185. int rs600_gart_init(struct radeon_device *rdev)
  186. {
  187.         int r;
  188.  
  189.         if (rdev->gart.table.vram.robj) {
  190.                 WARN(1, "RS600 GART already initialized.\n");
  191.                 return 0;
  192.         }
  193.         /* Initialize common gart structure */
  194.         r = radeon_gart_init(rdev);
  195.         if (r) {
  196.                 return r;
  197.         }
  198.         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
  199.         return radeon_gart_table_vram_alloc(rdev);
  200. }
  201.  
  202. int rs600_gart_enable(struct radeon_device *rdev)
  203. {
  204.         u32 tmp;
  205.         int r, i;
  206.  
  207.         if (rdev->gart.table.vram.robj == NULL) {
  208.                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  209.                 return -EINVAL;
  210.         }
  211.         r = radeon_gart_table_vram_pin(rdev);
  212.         if (r)
  213.                 return r;
  214.         /* Enable bus master */
  215.         tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
  216.         WREG32(R_00004C_BUS_CNTL, tmp);
  217.         /* FIXME: setup default page */
  218.         WREG32_MC(R_000100_MC_PT0_CNTL,
  219.                  (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
  220.                   S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
  221.  
  222.         for (i = 0; i < 19; i++) {
  223.                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
  224.                         S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
  225.                         S_00016C_SYSTEM_ACCESS_MODE_MASK(
  226.                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
  227.                         S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
  228.                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
  229.                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
  230.                         S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
  231.                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
  232.         }
  233.         /* enable first context */
  234.         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
  235.                         S_000102_ENABLE_PAGE_TABLE(1) |
  236.                         S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
  237.  
  238.         /* disable all other contexts */
  239.         for (i = 1; i < 8; i++)
  240.                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
  241.  
  242.         /* setup the page table */
  243.         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
  244.                  rdev->gart.table_addr);
  245.         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
  246.         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
  247.         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
  248.  
  249.         /* System context maps to VRAM space */
  250.         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
  251.         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
  252.  
  253.         /* enable page tables */
  254.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  255.         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
  256.         tmp = RREG32_MC(R_000009_MC_CNTL1);
  257.         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
  258.         rs600_gart_tlb_flush(rdev);
  259.         rdev->gart.ready = true;
  260.         return 0;
  261. }
  262.  
  263. void rs600_gart_disable(struct radeon_device *rdev)
  264. {
  265.         u32 tmp;
  266.         int r;
  267.  
  268.         /* FIXME: disable out of gart access */
  269.         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
  270.         tmp = RREG32_MC(R_000009_MC_CNTL1);
  271.         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
  272.         if (rdev->gart.table.vram.robj) {
  273. //   radeon_object_kunmap(rdev->gart.table.vram.robj);
  274. //   radeon_object_unpin(rdev->gart.table.vram.robj);
  275.         }
  276. }
  277.  
  278. void rs600_gart_fini(struct radeon_device *rdev)
  279. {
  280.         rs600_gart_disable(rdev);
  281.         radeon_gart_table_vram_free(rdev);
  282.         radeon_gart_fini(rdev);
  283. }
  284.  
  285. #define R600_PTE_VALID     (1 << 0)
  286. #define R600_PTE_SYSTEM    (1 << 1)
  287. #define R600_PTE_SNOOPED   (1 << 2)
  288. #define R600_PTE_READABLE  (1 << 5)
  289. #define R600_PTE_WRITEABLE (1 << 6)
  290.  
  291. int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  292. {
  293.         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  294.  
  295.         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  296.                 return -EINVAL;
  297.         }
  298.         addr = addr & 0xFFFFFFFFFFFFF000ULL;
  299.         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
  300.         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
  301.         writeq(addr, ((void __iomem *)ptr) + (i * 8));
  302.         return 0;
  303. }
  304.  
  305. int rs600_irq_set(struct radeon_device *rdev)
  306. {
  307.         uint32_t tmp = 0;
  308.         uint32_t mode_int = 0;
  309.         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
  310.                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
  311.         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
  312.                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
  313.  
  314.         if (rdev->irq.sw_int) {
  315.                 tmp |= S_000040_SW_INT_EN(1);
  316.         }
  317.         if (rdev->irq.crtc_vblank_int[0]) {
  318.                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
  319.         }
  320.         if (rdev->irq.crtc_vblank_int[1]) {
  321.                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
  322.         }
  323.         if (rdev->irq.hpd[0]) {
  324.                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
  325.         }
  326.         if (rdev->irq.hpd[1]) {
  327.                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
  328.         }
  329.         WREG32(R_000040_GEN_INT_CNTL, tmp);
  330.         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
  331.         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
  332.         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
  333.         return 0;
  334. }
  335.  
  336. static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
  337. {
  338.         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
  339.         uint32_t irq_mask = ~C_000044_SW_INT;
  340.         u32 tmp;
  341.  
  342.         if (G_000044_DISPLAY_INT_STAT(irqs)) {
  343.                 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
  344.                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
  345.                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
  346.                                 S_006534_D1MODE_VBLANK_ACK(1));
  347.                 }
  348.                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
  349.                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
  350.                                 S_006D34_D2MODE_VBLANK_ACK(1));
  351.                 }
  352.                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
  353.                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
  354.                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
  355.                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  356.                 }
  357.                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
  358.                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
  359.                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
  360.                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  361.                 }
  362.         } else {
  363.                 *r500_disp_int = 0;
  364.         }
  365.  
  366.         if (irqs) {
  367.                 WREG32(R_000044_GEN_INT_STATUS, irqs);
  368.         }
  369.         return irqs & irq_mask;
  370. }
  371.  
  372. void rs600_irq_disable(struct radeon_device *rdev)
  373. {
  374.         u32 tmp;
  375.  
  376.         WREG32(R_000040_GEN_INT_CNTL, 0);
  377.         WREG32(R_006540_DxMODE_INT_MASK, 0);
  378.         /* Wait and acknowledge irq */
  379.         mdelay(1);
  380.         rs600_irq_ack(rdev, &tmp);
  381. }
  382.  
  383.  
  384. u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
  385. {
  386.         if (crtc == 0)
  387.                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
  388.         else
  389.                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
  390. }
  391.  
  392. int rs600_mc_wait_for_idle(struct radeon_device *rdev)
  393. {
  394.         unsigned i;
  395.  
  396.         for (i = 0; i < rdev->usec_timeout; i++) {
  397.                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
  398.                         return 0;
  399.                 udelay(1);
  400.         }
  401.         return -1;
  402. }
  403.  
  404. void rs600_gpu_init(struct radeon_device *rdev)
  405. {
  406.         r100_hdp_reset(rdev);
  407.         r420_pipes_init(rdev);
  408.         /* Wait for mc idle */
  409.         if (rs600_mc_wait_for_idle(rdev))
  410.                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  411. }
  412.  
  413. void rs600_vram_info(struct radeon_device *rdev)
  414. {
  415.         rdev->mc.vram_is_ddr = true;
  416.         rdev->mc.vram_width = 128;
  417.  
  418.         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
  419.         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  420.  
  421.         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
  422.         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
  423.  
  424.         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
  425.                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
  426.  
  427.         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
  428.                 rdev->mc.real_vram_size = rdev->mc.aper_size;
  429. }
  430.  
  431. void rs600_bandwidth_update(struct radeon_device *rdev)
  432. {
  433.         /* FIXME: implement, should this be like rs690 ? */
  434. }
  435.  
  436. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  437. {
  438.         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  439.                 S_000070_MC_IND_CITF_ARB0(1));
  440.         return RREG32(R_000074_MC_IND_DATA);
  441. }
  442.  
  443. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  444. {
  445.         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  446.                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
  447.         WREG32(R_000074_MC_IND_DATA, v);
  448. }
  449.  
  450. void rs600_debugfs(struct radeon_device *rdev)
  451. {
  452.         if (r100_debugfs_rbbm_init(rdev))
  453.                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  454. }
  455.  
  456. void rs600_set_safe_registers(struct radeon_device *rdev)
  457. {
  458.         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
  459.         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
  460. }
  461.  
  462. static void rs600_mc_program(struct radeon_device *rdev)
  463. {
  464.         struct rv515_mc_save save;
  465.  
  466.         /* Stops all mc clients */
  467.         rv515_mc_stop(rdev, &save);
  468.  
  469.         /* Wait for mc idle */
  470.         if (rs600_mc_wait_for_idle(rdev))
  471.                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  472.  
  473.         /* FIXME: What does AGP means for such chipset ? */
  474.         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
  475.         WREG32_MC(R_000006_AGP_BASE, 0);
  476.         WREG32_MC(R_000007_AGP_BASE_2, 0);
  477.         /* Program MC */
  478.         WREG32_MC(R_000004_MC_FB_LOCATION,
  479.                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
  480.                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
  481.         WREG32(R_000134_HDP_FB_LOCATION,
  482.                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
  483.  
  484.         rv515_mc_resume(rdev, &save);
  485. }
  486.  
  487. static int rs600_startup(struct radeon_device *rdev)
  488. {
  489.         int r;
  490.  
  491.         rs600_mc_program(rdev);
  492.         /* Resume clock */
  493.         rv515_clock_startup(rdev);
  494.         /* Initialize GPU configuration (# pipes, ...) */
  495.         rs600_gpu_init(rdev);
  496.         /* Initialize GART (initialize after TTM so we can allocate
  497.          * memory through TTM but finalize after TTM) */
  498.         r = rs600_gart_enable(rdev);
  499.         if (r)
  500.         return r;
  501.         /* Enable IRQ */
  502. //      rs600_irq_set(rdev);
  503.         /* 1M ring buffer */
  504. //      r = r100_cp_init(rdev, 1024 * 1024);
  505. //      if (r) {
  506. //              dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
  507. //              return r;
  508. //      }
  509. //      r = r100_wb_init(rdev);
  510. //      if (r)
  511. //              dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
  512. //      r = r100_ib_init(rdev);
  513. //      if (r) {
  514. //              dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
  515. //              return r;
  516. //      }
  517.         return 0;
  518. }
  519.  
  520.  
  521.  
  522. int rs600_init(struct radeon_device *rdev)
  523. {
  524.         int r;
  525.  
  526.         /* Disable VGA */
  527.         rv515_vga_render_disable(rdev);
  528.         /* Initialize scratch registers */
  529.         radeon_scratch_init(rdev);
  530.         /* Initialize surface registers */
  531.         radeon_surface_init(rdev);
  532.         /* BIOS */
  533.         if (!radeon_get_bios(rdev)) {
  534.                 if (ASIC_IS_AVIVO(rdev))
  535.                         return -EINVAL;
  536.         }
  537.         if (rdev->is_atom_bios) {
  538.                 r = radeon_atombios_init(rdev);
  539.                 if (r)
  540.                         return r;
  541.         } else {
  542.                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
  543.                 return -EINVAL;
  544.         }
  545.         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  546.         if (radeon_gpu_reset(rdev)) {
  547.                 dev_warn(rdev->dev,
  548.                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  549.                         RREG32(R_000E40_RBBM_STATUS),
  550.                         RREG32(R_0007C0_CP_STAT));
  551.         }
  552.         /* check if cards are posted or not */
  553.         if (radeon_boot_test_post_card(rdev) == false)
  554.                 return -EINVAL;
  555.  
  556.         /* Initialize clocks */
  557.         radeon_get_clock_info(rdev->ddev);
  558.         /* Initialize power management */
  559.         radeon_pm_init(rdev);
  560.         /* Get vram informations */
  561.         rs600_vram_info(rdev);
  562.         /* Initialize memory controller (also test AGP) */
  563.         r = rs600_mc_init(rdev);
  564.         if (r)
  565.                 return r;
  566.         rs600_debugfs(rdev);
  567.         /* Fence driver */
  568. //      r = radeon_fence_driver_init(rdev);
  569. //      if (r)
  570. //              return r;
  571. //      r = radeon_irq_kms_init(rdev);
  572. //      if (r)
  573. //              return r;
  574.         /* Memory manager */
  575.         r = radeon_bo_init(rdev);
  576.         if (r)
  577.                 return r;
  578.         r = rs600_gart_init(rdev);
  579.         if (r)
  580.                 return r;
  581.         rs600_set_safe_registers(rdev);
  582.         rdev->accel_working = true;
  583.         r = rs600_startup(rdev);
  584.         if (r) {
  585.                 /* Somethings want wront with the accel init stop accel */
  586.                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
  587. //              rs600_suspend(rdev);
  588. //              r100_cp_fini(rdev);
  589. //              r100_wb_fini(rdev);
  590. //              r100_ib_fini(rdev);
  591.                 rs600_gart_fini(rdev);
  592. //              radeon_irq_kms_fini(rdev);
  593.                 rdev->accel_working = false;
  594.         }
  595.         return 0;
  596. }
  597.