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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. /* RS600 / Radeon X1250/X1270 integrated GPU
  29.  *
  30.  * This file gather function specific to RS600 which is the IGP of
  31.  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32.  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33.  * the avivo one, bios is an atombios, 3D block are the one of the
  34.  * R4XX family. The GART is different from the RS400 one and is very
  35.  * close to the one of the R600 family (R600 likely being an evolution
  36.  * of the RS600 GART block).
  37.  */
  38. #include "drmP.h"
  39. #include "radeon.h"
  40. #include "atom.h"
  41. #include "rs600d.h"
  42.  
  43. #include "rs600_reg_safe.h"
  44.  
  45. void rs600_gpu_init(struct radeon_device *rdev);
  46. int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  47.  
  48. int rs600_mc_init(struct radeon_device *rdev)
  49. {
  50.         /* read back the MC value from the hw */
  51.         int r;
  52.         u32 tmp;
  53.  
  54.         /* Setup GPU memory space */
  55.         tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
  56.         rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
  57.         rdev->mc.gtt_location = 0xffffffffUL;
  58.         r = radeon_mc_setup(rdev);
  59.         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
  60.         if (r)
  61.                 return r;
  62.         return 0;
  63. }
  64.  
  65. /* hpd for digital panel detect/disconnect */
  66. bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  67. {
  68.         u32 tmp;
  69.         bool connected = false;
  70.  
  71.         switch (hpd) {
  72.         case RADEON_HPD_1:
  73.                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
  74.                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
  75.                         connected = true;
  76.                 break;
  77.         case RADEON_HPD_2:
  78.                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
  79.                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
  80.                         connected = true;
  81.                 break;
  82.         default:
  83.                 break;
  84.         }
  85.         return connected;
  86. }
  87.  
  88. void rs600_hpd_set_polarity(struct radeon_device *rdev,
  89.                             enum radeon_hpd_id hpd)
  90. {
  91.         u32 tmp;
  92.         bool connected = rs600_hpd_sense(rdev, hpd);
  93.  
  94.         switch (hpd) {
  95.         case RADEON_HPD_1:
  96.                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
  97.                 if (connected)
  98.                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
  99.                 else
  100.                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
  101.                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  102.                 break;
  103.         case RADEON_HPD_2:
  104.                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
  105.                 if (connected)
  106.                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
  107.                 else
  108.                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
  109.                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  110.                 break;
  111.         default:
  112.                 break;
  113.         }
  114. }
  115.  
  116. void rs600_hpd_init(struct radeon_device *rdev)
  117. {
  118.         struct drm_device *dev = rdev->ddev;
  119.         struct drm_connector *connector;
  120.  
  121.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  122.                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  123.                 switch (radeon_connector->hpd.hpd) {
  124.                 case RADEON_HPD_1:
  125.                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
  126.                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
  127. //           rdev->irq.hpd[0] = true;
  128.                         break;
  129.                 case RADEON_HPD_2:
  130.                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
  131.                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
  132. //           rdev->irq.hpd[1] = true;
  133.                         break;
  134.                 default:
  135.                         break;
  136.                 }
  137.         }
  138. //   if (rdev->irq.installed)
  139. //   rs600_irq_set(rdev);
  140. }
  141.  
  142. void rs600_hpd_fini(struct radeon_device *rdev)
  143. {
  144.         struct drm_device *dev = rdev->ddev;
  145.         struct drm_connector *connector;
  146.  
  147.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  148.                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  149.                 switch (radeon_connector->hpd.hpd) {
  150.                 case RADEON_HPD_1:
  151.                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
  152.                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
  153. //           rdev->irq.hpd[0] = false;
  154.                         break;
  155.                 case RADEON_HPD_2:
  156.                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
  157.                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
  158. //           rdev->irq.hpd[1] = false;
  159.                         break;
  160.                 default:
  161.                         break;
  162.                 }
  163.         }
  164. }
  165.  
  166. /*
  167.  * GART.
  168.  */
  169. void rs600_gart_tlb_flush(struct radeon_device *rdev)
  170. {
  171.         uint32_t tmp;
  172.  
  173.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  174.         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  175.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  176.  
  177.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  178.         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
  179.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  180.  
  181.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  182.         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  183.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  184.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  185. }
  186.  
  187. int rs600_gart_init(struct radeon_device *rdev)
  188. {
  189.         int r;
  190.  
  191.         if (rdev->gart.table.vram.robj) {
  192.                 WARN(1, "RS600 GART already initialized.\n");
  193.                 return 0;
  194.         }
  195.         /* Initialize common gart structure */
  196.         r = radeon_gart_init(rdev);
  197.         if (r) {
  198.                 return r;
  199.         }
  200.         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
  201.         return radeon_gart_table_vram_alloc(rdev);
  202. }
  203.  
  204. int rs600_gart_enable(struct radeon_device *rdev)
  205. {
  206.         u32 tmp;
  207.         int r, i;
  208.  
  209.         if (rdev->gart.table.vram.robj == NULL) {
  210.                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  211.                 return -EINVAL;
  212.         }
  213.         r = radeon_gart_table_vram_pin(rdev);
  214.         if (r)
  215.                 return r;
  216.         /* Enable bus master */
  217.         tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
  218.         WREG32(R_00004C_BUS_CNTL, tmp);
  219.         /* FIXME: setup default page */
  220.         WREG32_MC(R_000100_MC_PT0_CNTL,
  221.                  (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
  222.                   S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
  223.  
  224.         for (i = 0; i < 19; i++) {
  225.                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
  226.                         S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
  227.                         S_00016C_SYSTEM_ACCESS_MODE_MASK(
  228.                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
  229.                         S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
  230.                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
  231.                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
  232.                         S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
  233.                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
  234.         }
  235.         /* enable first context */
  236.         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
  237.                         S_000102_ENABLE_PAGE_TABLE(1) |
  238.                         S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
  239.  
  240.         /* disable all other contexts */
  241.         for (i = 1; i < 8; i++)
  242.                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
  243.  
  244.         /* setup the page table */
  245.         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
  246.                  rdev->gart.table_addr);
  247.         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
  248.         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
  249.         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
  250.  
  251.         /* System context maps to VRAM space */
  252.         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
  253.         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
  254.  
  255.         /* enable page tables */
  256.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  257.         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
  258.         tmp = RREG32_MC(R_000009_MC_CNTL1);
  259.         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
  260.         rs600_gart_tlb_flush(rdev);
  261.         rdev->gart.ready = true;
  262.         return 0;
  263. }
  264.  
  265. void rs600_gart_disable(struct radeon_device *rdev)
  266. {
  267.         u32 tmp;
  268.         int r;
  269.  
  270.         /* FIXME: disable out of gart access */
  271.         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
  272.         tmp = RREG32_MC(R_000009_MC_CNTL1);
  273.         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
  274.         if (rdev->gart.table.vram.robj) {
  275.                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
  276.                 if (r == 0) {
  277.                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
  278.                         radeon_bo_unpin(rdev->gart.table.vram.robj);
  279.                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
  280.                 }
  281.         }
  282. }
  283.  
  284. void rs600_gart_fini(struct radeon_device *rdev)
  285. {
  286.         rs600_gart_disable(rdev);
  287.         radeon_gart_table_vram_free(rdev);
  288.         radeon_gart_fini(rdev);
  289. }
  290.  
  291. #define R600_PTE_VALID     (1 << 0)
  292. #define R600_PTE_SYSTEM    (1 << 1)
  293. #define R600_PTE_SNOOPED   (1 << 2)
  294. #define R600_PTE_READABLE  (1 << 5)
  295. #define R600_PTE_WRITEABLE (1 << 6)
  296.  
  297. int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  298. {
  299.         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  300.  
  301.         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  302.                 return -EINVAL;
  303.         }
  304.         addr = addr & 0xFFFFFFFFFFFFF000ULL;
  305.         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
  306.         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
  307.         writeq(addr, ((void __iomem *)ptr) + (i * 8));
  308.         return 0;
  309. }
  310.  
  311. /*
  312. int rs600_irq_set(struct radeon_device *rdev)
  313. {
  314.         uint32_t tmp = 0;
  315.         uint32_t mode_int = 0;
  316.         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
  317.                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
  318.         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
  319.                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
  320.  
  321.    if (!rdev->irq.installed) {
  322.                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
  323.                 WREG32(R_000040_GEN_INT_CNTL, 0);
  324.                 return -EINVAL;
  325.         }
  326.         if (rdev->irq.sw_int) {
  327.                 tmp |= S_000040_SW_INT_EN(1);
  328.         }
  329.         if (rdev->irq.crtc_vblank_int[0]) {
  330.                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
  331.         }
  332.         if (rdev->irq.crtc_vblank_int[1]) {
  333.                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
  334.         }
  335.         if (rdev->irq.hpd[0]) {
  336.                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
  337.         }
  338.         if (rdev->irq.hpd[1]) {
  339.                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
  340.         }
  341.         WREG32(R_000040_GEN_INT_CNTL, tmp);
  342.         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
  343.         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
  344.         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
  345.         return 0;
  346. }
  347. */
  348.  
  349. static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
  350. {
  351.         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
  352.         uint32_t irq_mask = ~C_000044_SW_INT;
  353.         u32 tmp;
  354.  
  355.         if (G_000044_DISPLAY_INT_STAT(irqs)) {
  356.                 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
  357.                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
  358.                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
  359.                                 S_006534_D1MODE_VBLANK_ACK(1));
  360.                 }
  361.                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
  362.                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
  363.                                 S_006D34_D2MODE_VBLANK_ACK(1));
  364.                 }
  365.                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
  366.                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
  367.                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
  368.                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  369.                 }
  370.                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
  371.                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
  372.                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
  373.                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  374.                 }
  375.         } else {
  376.                 *r500_disp_int = 0;
  377.         }
  378.  
  379.         if (irqs) {
  380.                 WREG32(R_000044_GEN_INT_STATUS, irqs);
  381.         }
  382.         return irqs & irq_mask;
  383. }
  384.  
  385. void rs600_irq_disable(struct radeon_device *rdev)
  386. {
  387.         u32 tmp;
  388.  
  389.         WREG32(R_000040_GEN_INT_CNTL, 0);
  390.         WREG32(R_006540_DxMODE_INT_MASK, 0);
  391.         /* Wait and acknowledge irq */
  392.         mdelay(1);
  393.         rs600_irq_ack(rdev, &tmp);
  394. }
  395.  
  396.  
  397. u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
  398. {
  399.         if (crtc == 0)
  400.                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
  401.         else
  402.                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
  403. }
  404.  
  405. int rs600_mc_wait_for_idle(struct radeon_device *rdev)
  406. {
  407.         unsigned i;
  408.  
  409.         for (i = 0; i < rdev->usec_timeout; i++) {
  410.                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
  411.                         return 0;
  412.                 udelay(1);
  413.         }
  414.         return -1;
  415. }
  416.  
  417. void rs600_gpu_init(struct radeon_device *rdev)
  418. {
  419.         r100_hdp_reset(rdev);
  420.         r420_pipes_init(rdev);
  421.         /* Wait for mc idle */
  422.         if (rs600_mc_wait_for_idle(rdev))
  423.                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  424. }
  425.  
  426. void rs600_vram_info(struct radeon_device *rdev)
  427. {
  428.         rdev->mc.vram_is_ddr = true;
  429.         rdev->mc.vram_width = 128;
  430.  
  431.         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
  432.         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  433.  
  434.         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
  435.         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
  436.  
  437.         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
  438.                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
  439.  
  440.         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
  441.                 rdev->mc.real_vram_size = rdev->mc.aper_size;
  442. }
  443.  
  444. void rs600_bandwidth_update(struct radeon_device *rdev)
  445. {
  446.         /* FIXME: implement, should this be like rs690 ? */
  447. }
  448.  
  449. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  450. {
  451.         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  452.                 S_000070_MC_IND_CITF_ARB0(1));
  453.         return RREG32(R_000074_MC_IND_DATA);
  454. }
  455.  
  456. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  457. {
  458.         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  459.                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
  460.         WREG32(R_000074_MC_IND_DATA, v);
  461. }
  462.  
  463. void rs600_debugfs(struct radeon_device *rdev)
  464. {
  465.         if (r100_debugfs_rbbm_init(rdev))
  466.                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  467. }
  468.  
  469. void rs600_set_safe_registers(struct radeon_device *rdev)
  470. {
  471.         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
  472.         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
  473. }
  474.  
  475. static void rs600_mc_program(struct radeon_device *rdev)
  476. {
  477.         struct rv515_mc_save save;
  478.  
  479.         /* Stops all mc clients */
  480.         rv515_mc_stop(rdev, &save);
  481.  
  482.         /* Wait for mc idle */
  483.         if (rs600_mc_wait_for_idle(rdev))
  484.                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  485.  
  486.         /* FIXME: What does AGP means for such chipset ? */
  487.         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
  488.         WREG32_MC(R_000006_AGP_BASE, 0);
  489.         WREG32_MC(R_000007_AGP_BASE_2, 0);
  490.         /* Program MC */
  491.         WREG32_MC(R_000004_MC_FB_LOCATION,
  492.                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
  493.                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
  494.         WREG32(R_000134_HDP_FB_LOCATION,
  495.                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
  496.  
  497.         rv515_mc_resume(rdev, &save);
  498. }
  499.  
  500. static int rs600_startup(struct radeon_device *rdev)
  501. {
  502.         int r;
  503.  
  504.         rs600_mc_program(rdev);
  505.         /* Resume clock */
  506.         rv515_clock_startup(rdev);
  507.         /* Initialize GPU configuration (# pipes, ...) */
  508.         rs600_gpu_init(rdev);
  509.         /* Initialize GART (initialize after TTM so we can allocate
  510.          * memory through TTM but finalize after TTM) */
  511.         r = rs600_gart_enable(rdev);
  512.         if (r)
  513.         return r;
  514.         /* Enable IRQ */
  515. //      rs600_irq_set(rdev);
  516.         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  517.         /* 1M ring buffer */
  518.         r = r100_cp_init(rdev, 1024 * 1024);
  519.         if (r) {
  520.                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
  521.                 return r;
  522.         }
  523. //      r = r100_wb_init(rdev);
  524. //      if (r)
  525. //              dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
  526. //      r = r100_ib_init(rdev);
  527. //      if (r) {
  528. //              dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
  529. //              return r;
  530. //      }
  531.         return 0;
  532. }
  533.  
  534.  
  535.  
  536. int rs600_init(struct radeon_device *rdev)
  537. {
  538.         int r;
  539.  
  540.         /* Disable VGA */
  541.         rv515_vga_render_disable(rdev);
  542.         /* Initialize scratch registers */
  543.         radeon_scratch_init(rdev);
  544.         /* Initialize surface registers */
  545.         radeon_surface_init(rdev);
  546.         /* BIOS */
  547.         if (!radeon_get_bios(rdev)) {
  548.                 if (ASIC_IS_AVIVO(rdev))
  549.                         return -EINVAL;
  550.         }
  551.         if (rdev->is_atom_bios) {
  552.                 r = radeon_atombios_init(rdev);
  553.                 if (r)
  554.                         return r;
  555.         } else {
  556.                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
  557.                 return -EINVAL;
  558.         }
  559.         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  560.         if (radeon_gpu_reset(rdev)) {
  561.                 dev_warn(rdev->dev,
  562.                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  563.                         RREG32(R_000E40_RBBM_STATUS),
  564.                         RREG32(R_0007C0_CP_STAT));
  565.         }
  566.         /* check if cards are posted or not */
  567.         if (radeon_boot_test_post_card(rdev) == false)
  568.                 return -EINVAL;
  569.  
  570.         /* Initialize clocks */
  571.         radeon_get_clock_info(rdev->ddev);
  572.         /* Initialize power management */
  573.         radeon_pm_init(rdev);
  574.         /* Get vram informations */
  575.         rs600_vram_info(rdev);
  576.         /* Initialize memory controller (also test AGP) */
  577.         r = rs600_mc_init(rdev);
  578.         if (r)
  579.                 return r;
  580.         rs600_debugfs(rdev);
  581.         /* Fence driver */
  582. //      r = radeon_fence_driver_init(rdev);
  583. //      if (r)
  584. //              return r;
  585. //      r = radeon_irq_kms_init(rdev);
  586. //      if (r)
  587. //              return r;
  588.         /* Memory manager */
  589.         r = radeon_bo_init(rdev);
  590.         if (r)
  591.                 return r;
  592.         r = rs600_gart_init(rdev);
  593.         if (r)
  594.                 return r;
  595.         rs600_set_safe_registers(rdev);
  596.         rdev->accel_working = true;
  597.         r = rs600_startup(rdev);
  598.         if (r) {
  599.                 /* Somethings want wront with the accel init stop accel */
  600.                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
  601. //              r100_cp_fini(rdev);
  602. //              r100_wb_fini(rdev);
  603. //              r100_ib_fini(rdev);
  604.                 rs600_gart_fini(rdev);
  605. //              radeon_irq_kms_fini(rdev);
  606.                 rdev->accel_working = false;
  607.         }
  608.         return 0;
  609. }
  610.