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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include <linux/seq_file.h>
  29. #include <drm/drmP.h>
  30. #include "radeon.h"
  31. #include "rs400d.h"
  32.  
  33. /* This files gather functions specifics to : rs400,rs480 */
  34. static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  35.  
  36. void rs400_gart_adjust_size(struct radeon_device *rdev)
  37. {
  38.         /* Check gart size */
  39.         switch (rdev->mc.gtt_size/(1024*1024)) {
  40.         case 32:
  41.         case 64:
  42.         case 128:
  43.         case 256:
  44.         case 512:
  45.         case 1024:
  46.         case 2048:
  47.                 break;
  48.         default:
  49.                 DRM_ERROR("Unable to use IGP GART size %uM\n",
  50.                           (unsigned)(rdev->mc.gtt_size >> 20));
  51.                 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
  52.                 DRM_ERROR("Forcing to 32M GART size\n");
  53.                 rdev->mc.gtt_size = 32 * 1024 * 1024;
  54.                 return;
  55.         }
  56.         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  57.                 /* FIXME: RS400 & RS480 seems to have issue with GART size
  58.                  * if 4G of system memory (needs more testing) */
  59.                 rdev->mc.gtt_size = 32 * 1024 * 1024;
  60.                 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
  61.         }
  62. }
  63.  
  64. void rs400_gart_tlb_flush(struct radeon_device *rdev)
  65. {
  66.         uint32_t tmp;
  67.         unsigned int timeout = rdev->usec_timeout;
  68.  
  69.         WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
  70.         do {
  71.                 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
  72.                 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
  73.                         break;
  74.                 DRM_UDELAY(1);
  75.                 timeout--;
  76.         } while (timeout > 0);
  77.         WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
  78. }
  79.  
  80. int rs400_gart_init(struct radeon_device *rdev)
  81. {
  82.         int r;
  83.  
  84.         if (rdev->gart.table.ram.ptr) {
  85.                 WARN(1, "RS400 GART already initialized.\n");
  86.                 return 0;
  87.         }
  88.         /* Check gart size */
  89.         switch(rdev->mc.gtt_size / (1024 * 1024)) {
  90.         case 32:
  91.         case 64:
  92.         case 128:
  93.         case 256:
  94.         case 512:
  95.         case 1024:
  96.         case 2048:
  97.                 break;
  98.         default:
  99.                 return -EINVAL;
  100.         }
  101.         /* Initialize common gart structure */
  102.         r = radeon_gart_init(rdev);
  103.         if (r)
  104.                 return r;
  105.         if (rs400_debugfs_pcie_gart_info_init(rdev))
  106.                 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
  107.         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
  108.         return radeon_gart_table_ram_alloc(rdev);
  109. }
  110.  
  111. int rs400_gart_enable(struct radeon_device *rdev)
  112. {
  113.         uint32_t size_reg;
  114.         uint32_t tmp;
  115.  
  116.         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
  117.         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
  118.         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
  119.         /* Check gart size */
  120.         switch(rdev->mc.gtt_size / (1024 * 1024)) {
  121.         case 32:
  122.                 size_reg = RS480_VA_SIZE_32MB;
  123.                 break;
  124.         case 64:
  125.                 size_reg = RS480_VA_SIZE_64MB;
  126.                 break;
  127.         case 128:
  128.                 size_reg = RS480_VA_SIZE_128MB;
  129.                 break;
  130.         case 256:
  131.                 size_reg = RS480_VA_SIZE_256MB;
  132.                 break;
  133.         case 512:
  134.                 size_reg = RS480_VA_SIZE_512MB;
  135.                 break;
  136.         case 1024:
  137.                 size_reg = RS480_VA_SIZE_1GB;
  138.                 break;
  139.         case 2048:
  140.                 size_reg = RS480_VA_SIZE_2GB;
  141.                 break;
  142.         default:
  143.                 return -EINVAL;
  144.         }
  145.         /* It should be fine to program it to max value */
  146.         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
  147.                 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
  148.                 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
  149.         } else {
  150.                 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
  151.                 WREG32(RS480_AGP_BASE_2, 0);
  152.         }
  153.         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  154.         tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16);
  155.         tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16);
  156.         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
  157.                 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
  158.                 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
  159.                 WREG32(RADEON_BUS_CNTL, tmp);
  160.         } else {
  161.                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
  162.                 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
  163.                 WREG32(RADEON_BUS_CNTL, tmp);
  164.         }
  165.         /* Table should be in 32bits address space so ignore bits above. */
  166.         tmp = (u32)rdev->gart.table_addr & 0xfffff000;
  167.         tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
  168.  
  169.         WREG32_MC(RS480_GART_BASE, tmp);
  170.         /* TODO: more tweaking here */
  171.         WREG32_MC(RS480_GART_FEATURE_ID,
  172.                   (RS480_TLB_ENABLE |
  173.                    RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
  174.         /* Disable snooping */
  175.         WREG32_MC(RS480_AGP_MODE_CNTL,
  176.                   (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
  177.         /* Disable AGP mode */
  178.         /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
  179.          * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
  180.         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
  181.                 WREG32_MC(RS480_MC_MISC_CNTL,
  182.                           (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
  183.         } else {
  184.                 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
  185.         }
  186.         /* Enable gart */
  187.         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
  188.         rs400_gart_tlb_flush(rdev);
  189.         rdev->gart.ready = true;
  190.         return 0;
  191. }
  192.  
  193. void rs400_gart_disable(struct radeon_device *rdev)
  194. {
  195.         uint32_t tmp;
  196.  
  197.         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
  198.         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
  199.         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
  200.         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
  201. }
  202.  
  203. void rs400_gart_fini(struct radeon_device *rdev)
  204. {
  205.         rs400_gart_disable(rdev);
  206.         radeon_gart_table_ram_free(rdev);
  207.         radeon_gart_fini(rdev);
  208. }
  209.  
  210. int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  211. {
  212.         uint32_t entry;
  213.  
  214.         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  215.                 return -EINVAL;
  216.         }
  217.  
  218.         entry = (lower_32_bits(addr) & PAGE_MASK) |
  219.                 ((upper_32_bits(addr) & 0xff) << 4) |
  220.                 0xc;
  221.         entry = cpu_to_le32(entry);
  222.         rdev->gart.table.ram.ptr[i] = entry;
  223.         return 0;
  224. }
  225.  
  226. int rs400_mc_wait_for_idle(struct radeon_device *rdev)
  227. {
  228.         unsigned i;
  229.         uint32_t tmp;
  230.  
  231.         for (i = 0; i < rdev->usec_timeout; i++) {
  232.                 /* read MC_STATUS */
  233.                 tmp = RREG32(0x0150);
  234.                 if (tmp & (1 << 2)) {
  235.                         return 0;
  236.                 }
  237.                 DRM_UDELAY(1);
  238.         }
  239.         return -1;
  240. }
  241.  
  242. void rs400_gpu_init(struct radeon_device *rdev)
  243. {
  244.         /* FIXME: HDP same place on rs400 ? */
  245.         r100_hdp_reset(rdev);
  246.         /* FIXME: is this correct ? */
  247.         r420_pipes_init(rdev);
  248.         if (rs400_mc_wait_for_idle(rdev)) {
  249.                 printk(KERN_WARNING "rs400: Failed to wait MC idle while "
  250.                        "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
  251.         }
  252. }
  253.  
  254. void rs400_vram_info(struct radeon_device *rdev)
  255. {
  256.         rs400_gart_adjust_size(rdev);
  257.         /* DDR for all card after R300 & IGP */
  258.         rdev->mc.vram_is_ddr = true;
  259.         rdev->mc.vram_width = 128;
  260.  
  261.         r100_vram_init_sizes(rdev);
  262. }
  263.  
  264. uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  265. {
  266.         uint32_t r;
  267.  
  268.         WREG32(RS480_NB_MC_INDEX, reg & 0xff);
  269.         r = RREG32(RS480_NB_MC_DATA);
  270.         WREG32(RS480_NB_MC_INDEX, 0xff);
  271.         return r;
  272. }
  273.  
  274. void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  275. {
  276.         WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
  277.         WREG32(RS480_NB_MC_DATA, (v));
  278.         WREG32(RS480_NB_MC_INDEX, 0xff);
  279. }
  280.  
  281. #if defined(CONFIG_DEBUG_FS)
  282. static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
  283. {
  284.         struct drm_info_node *node = (struct drm_info_node *) m->private;
  285.         struct drm_device *dev = node->minor->dev;
  286.         struct radeon_device *rdev = dev->dev_private;
  287.         uint32_t tmp;
  288.  
  289.         tmp = RREG32(RADEON_HOST_PATH_CNTL);
  290.         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
  291.         tmp = RREG32(RADEON_BUS_CNTL);
  292.         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
  293.         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
  294.         seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
  295.         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
  296.                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
  297.                 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
  298.                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
  299.                 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
  300.                 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
  301.                 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
  302.                 tmp = RREG32_MC(0x100);
  303.                 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
  304.                 tmp = RREG32(0x134);
  305.                 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
  306.         } else {
  307.                 tmp = RREG32(RADEON_AGP_BASE);
  308.                 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
  309.                 tmp = RREG32(RS480_AGP_BASE_2);
  310.                 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
  311.                 tmp = RREG32(RADEON_MC_AGP_LOCATION);
  312.                 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
  313.         }
  314.         tmp = RREG32_MC(RS480_GART_BASE);
  315.         seq_printf(m, "GART_BASE 0x%08x\n", tmp);
  316.         tmp = RREG32_MC(RS480_GART_FEATURE_ID);
  317.         seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
  318.         tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
  319.         seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
  320.         tmp = RREG32_MC(RS480_MC_MISC_CNTL);
  321.         seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
  322.         tmp = RREG32_MC(0x5F);
  323.         seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
  324.         tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
  325.         seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
  326.         tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
  327.         seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
  328.         tmp = RREG32_MC(0x3B);
  329.         seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
  330.         tmp = RREG32_MC(0x3C);
  331.         seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
  332.         tmp = RREG32_MC(0x30);
  333.         seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
  334.         tmp = RREG32_MC(0x31);
  335.         seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
  336.         tmp = RREG32_MC(0x32);
  337.         seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
  338.         tmp = RREG32_MC(0x33);
  339.         seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
  340.         tmp = RREG32_MC(0x34);
  341.         seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
  342.         tmp = RREG32_MC(0x35);
  343.         seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
  344.         tmp = RREG32_MC(0x36);
  345.         seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
  346.         tmp = RREG32_MC(0x37);
  347.         seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
  348.         return 0;
  349. }
  350.  
  351. static struct drm_info_list rs400_gart_info_list[] = {
  352.         {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
  353. };
  354. #endif
  355.  
  356. static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
  357. {
  358. #if defined(CONFIG_DEBUG_FS)
  359.         return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
  360. #else
  361.         return 0;
  362. #endif
  363. }
  364.  
  365. static int rs400_mc_init(struct radeon_device *rdev)
  366. {
  367.         int r;
  368.         u32 tmp;
  369.  
  370.         /* Setup GPU memory space */
  371.         tmp = RREG32(R_00015C_NB_TOM);
  372.         rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
  373.         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  374.         r = radeon_mc_setup(rdev);
  375.         rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
  376.         if (r)
  377.                 return r;
  378.         return 0;
  379. }
  380.  
  381. void rs400_mc_program(struct radeon_device *rdev)
  382. {
  383.         struct r100_mc_save save;
  384.  
  385.         /* Stops all mc clients */
  386.         r100_mc_stop(rdev, &save);
  387.  
  388.         /* Wait for mc idle */
  389.         if (rs400_mc_wait_for_idle(rdev))
  390.                 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
  391.         WREG32(R_000148_MC_FB_LOCATION,
  392.                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
  393.                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
  394.  
  395.         r100_mc_resume(rdev, &save);
  396. }
  397.  
  398. static int rs400_startup(struct radeon_device *rdev)
  399. {
  400.         int r;
  401.  
  402.         rs400_mc_program(rdev);
  403.         /* Resume clock */
  404.         r300_clock_startup(rdev);
  405.         /* Initialize GPU configuration (# pipes, ...) */
  406.         rs400_gpu_init(rdev);
  407.         r100_enable_bm(rdev);
  408.         /* Initialize GART (initialize after TTM so we can allocate
  409.          * memory through TTM but finalize after TTM) */
  410.         r = rs400_gart_enable(rdev);
  411.         if (r)
  412.                 return r;
  413.         /* Enable IRQ */
  414. //      r100_irq_set(rdev);
  415.         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  416.         /* 1M ring buffer */
  417.    r = r100_cp_init(rdev, 1024 * 1024);
  418.    if (r) {
  419.        dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
  420.        return r;
  421.    }
  422. //      r = r100_wb_init(rdev);
  423. //      if (r)
  424. //              dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
  425. //      r = r100_ib_init(rdev);
  426. //      if (r) {
  427. //              dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
  428. //              return r;
  429. //      }
  430.         return 0;
  431. }
  432.  
  433.  
  434.  
  435.  
  436. int rs400_init(struct radeon_device *rdev)
  437. {
  438.         int r;
  439.  
  440.         /* Disable VGA */
  441.         r100_vga_render_disable(rdev);
  442.         /* Initialize scratch registers */
  443.         radeon_scratch_init(rdev);
  444.         /* Initialize surface registers */
  445.         radeon_surface_init(rdev);
  446.         /* TODO: disable VGA need to use VGA request */
  447.         /* BIOS*/
  448.         if (!radeon_get_bios(rdev)) {
  449.                 if (ASIC_IS_AVIVO(rdev))
  450.                         return -EINVAL;
  451.         }
  452.         if (rdev->is_atom_bios) {
  453.                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
  454.                 return -EINVAL;
  455.         } else {
  456.                 r = radeon_combios_init(rdev);
  457.                 if (r)
  458.                         return r;
  459.         }
  460.         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  461.         if (radeon_gpu_reset(rdev)) {
  462.                 dev_warn(rdev->dev,
  463.                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  464.                         RREG32(R_000E40_RBBM_STATUS),
  465.                         RREG32(R_0007C0_CP_STAT));
  466.         }
  467.         /* check if cards are posted or not */
  468.         if (radeon_boot_test_post_card(rdev) == false)
  469.                 return -EINVAL;
  470.  
  471.         /* Initialize clocks */
  472.         radeon_get_clock_info(rdev->ddev);
  473.         /* Initialize power management */
  474.         radeon_pm_init(rdev);
  475.         /* Get vram informations */
  476.         rs400_vram_info(rdev);
  477.         /* Initialize memory controller (also test AGP) */
  478.         r = rs400_mc_init(rdev);
  479.         if (r)
  480.                 return r;
  481.         /* Fence driver */
  482. //      r = radeon_fence_driver_init(rdev);
  483. //      if (r)
  484. //              return r;
  485. //      r = radeon_irq_kms_init(rdev);
  486. //      if (r)
  487. //              return r;
  488.         /* Memory manager */
  489.         r = radeon_bo_init(rdev);
  490.         if (r)
  491.                 return r;
  492.         r = rs400_gart_init(rdev);
  493.         if (r)
  494.                 return r;
  495.         r300_set_reg_safe(rdev);
  496.         rdev->accel_working = true;
  497.         r = rs400_startup(rdev);
  498.         if (r) {
  499.                 /* Somethings want wront with the accel init stop accel */
  500.                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
  501. //              r100_cp_fini(rdev);
  502. //              r100_wb_fini(rdev);
  503. //              r100_ib_fini(rdev);
  504.                 rs400_gart_fini(rdev);
  505. //              radeon_irq_kms_fini(rdev);
  506.                 rdev->accel_working = false;
  507.         }
  508.         return 0;
  509. }
  510.