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  1. /*
  2.  * Copyright 2009 Jerome Glisse.
  3.  * All Rights Reserved.
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the
  7.  * "Software"), to deal in the Software without restriction, including
  8.  * without limitation the rights to use, copy, modify, merge, publish,
  9.  * distribute, sub license, and/or sell copies of the Software, and to
  10.  * permit persons to whom the Software is furnished to do so, subject to
  11.  * the following conditions:
  12.  *
  13.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15.  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16.  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17.  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18.  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19.  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20.  *
  21.  * The above copyright notice and this permission notice (including the
  22.  * next paragraph) shall be included in all copies or substantial portions
  23.  * of the Software.
  24.  *
  25.  */
  26. /*
  27.  * Authors:
  28.  *    Jerome Glisse <glisse@freedesktop.org>
  29.  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30.  *    Dave Airlie
  31.  */
  32. #include <ttm/ttm_bo_api.h>
  33. #include <ttm/ttm_bo_driver.h>
  34. #include <ttm/ttm_placement.h>
  35. #include <ttm/ttm_module.h>
  36. #include <ttm/ttm_page_alloc.h>
  37. #include <drm/drmP.h>
  38. #include <drm/radeon_drm.h>
  39. #include <linux/seq_file.h>
  40. #include <linux/slab.h>
  41. #include "radeon_reg.h"
  42. #include "radeon.h"
  43.  
  44. #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  45.  
  46. static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
  47. static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
  48.  
  49. static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  50. {
  51.         struct radeon_mman *mman;
  52.         struct radeon_device *rdev;
  53.  
  54.         mman = container_of(bdev, struct radeon_mman, bdev);
  55.         rdev = container_of(mman, struct radeon_device, mman);
  56.         return rdev;
  57. }
  58.  
  59.  
  60. /*
  61.  * Global memory.
  62.  */
  63. static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
  64. {
  65.         return ttm_mem_global_init(ref->object);
  66. }
  67.  
  68. static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
  69. {
  70.         ttm_mem_global_release(ref->object);
  71. }
  72.  
  73. static int radeon_ttm_global_init(struct radeon_device *rdev)
  74. {
  75.         struct drm_global_reference *global_ref;
  76.         int r;
  77.  
  78.         rdev->mman.mem_global_referenced = false;
  79.         global_ref = &rdev->mman.mem_global_ref;
  80.         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  81.         global_ref->size = sizeof(struct ttm_mem_global);
  82.         global_ref->init = &radeon_ttm_mem_global_init;
  83.         global_ref->release = &radeon_ttm_mem_global_release;
  84.         r = drm_global_item_ref(global_ref);
  85.         if (r != 0) {
  86.                 DRM_ERROR("Failed setting up TTM memory accounting "
  87.                           "subsystem.\n");
  88.                 return r;
  89.         }
  90.  
  91.         rdev->mman.bo_global_ref.mem_glob =
  92.                 rdev->mman.mem_global_ref.object;
  93.         global_ref = &rdev->mman.bo_global_ref.ref;
  94.         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  95.         global_ref->size = sizeof(struct ttm_bo_global);
  96.         global_ref->init = &ttm_bo_global_init;
  97.         global_ref->release = &ttm_bo_global_release;
  98.         r = drm_global_item_ref(global_ref);
  99.         if (r != 0) {
  100.                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
  101.                 drm_global_item_unref(&rdev->mman.mem_global_ref);
  102.                 return r;
  103.         }
  104.  
  105.         rdev->mman.mem_global_referenced = true;
  106.         return 0;
  107. }
  108.  
  109.  
  110. static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  111. {
  112.         return 0;
  113. }
  114.  
  115. static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  116.                                 struct ttm_mem_type_manager *man)
  117. {
  118.         struct radeon_device *rdev;
  119.  
  120.         rdev = radeon_get_rdev(bdev);
  121.  
  122.         switch (type) {
  123.         case TTM_PL_SYSTEM:
  124.                 /* System memory */
  125.                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  126.                 man->available_caching = TTM_PL_MASK_CACHING;
  127.                 man->default_caching = TTM_PL_FLAG_CACHED;
  128.                 break;
  129.         case TTM_PL_TT:
  130.                 man->func = &ttm_bo_manager_func;
  131.                 man->gpu_offset = rdev->mc.gtt_start;
  132.                 man->available_caching = TTM_PL_MASK_CACHING;
  133.                 man->default_caching = TTM_PL_FLAG_CACHED;
  134.                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
  135. #if __OS_HAS_AGP
  136.                 if (rdev->flags & RADEON_IS_AGP) {
  137.                         if (!rdev->ddev->agp) {
  138.                                 DRM_ERROR("AGP is not enabled for memory type %u\n",
  139.                                           (unsigned)type);
  140.                                 return -EINVAL;
  141.                         }
  142.                         if (!rdev->ddev->agp->cant_use_aperture)
  143.                                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  144.                         man->available_caching = TTM_PL_FLAG_UNCACHED |
  145.                                                  TTM_PL_FLAG_WC;
  146.                         man->default_caching = TTM_PL_FLAG_WC;
  147.                 }
  148. #endif
  149.                 break;
  150.         case TTM_PL_VRAM:
  151.                 /* "On-card" video ram */
  152.                 man->func = &ttm_bo_manager_func;
  153.                 man->gpu_offset = rdev->mc.vram_start;
  154.                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
  155.                              TTM_MEMTYPE_FLAG_MAPPABLE;
  156.                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
  157.                 man->default_caching = TTM_PL_FLAG_WC;
  158.                 break;
  159.         default:
  160.                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
  161.                 return -EINVAL;
  162.         }
  163.         return 0;
  164. }
  165.  
  166. static void radeon_evict_flags(struct ttm_buffer_object *bo,
  167.                                 struct ttm_placement *placement)
  168. {
  169.         struct radeon_bo *rbo;
  170.         static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  171.  
  172.         if (!radeon_ttm_bo_is_radeon_bo(bo)) {
  173.                 placement->fpfn = 0;
  174.                 placement->lpfn = 0;
  175.                 placement->placement = &placements;
  176.                 placement->busy_placement = &placements;
  177.                 placement->num_placement = 1;
  178.                 placement->num_busy_placement = 1;
  179.                 return;
  180.         }
  181.         rbo = container_of(bo, struct radeon_bo, tbo);
  182.         switch (bo->mem.mem_type) {
  183.         case TTM_PL_VRAM:
  184.                 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
  185.                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
  186.                 else
  187.                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
  188.                 break;
  189.         case TTM_PL_TT:
  190.         default:
  191.                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
  192.         }
  193.         *placement = rbo->placement;
  194. }
  195.  
  196. static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
  197. {
  198.         return 0;
  199. }
  200.  
  201. static void radeon_move_null(struct ttm_buffer_object *bo,
  202.                              struct ttm_mem_reg *new_mem)
  203. {
  204.         struct ttm_mem_reg *old_mem = &bo->mem;
  205.  
  206.         BUG_ON(old_mem->mm_node != NULL);
  207.         *old_mem = *new_mem;
  208.         new_mem->mm_node = NULL;
  209. }
  210.  
  211. static int radeon_move_blit(struct ttm_buffer_object *bo,
  212.                         bool evict, bool no_wait_gpu,
  213.                         struct ttm_mem_reg *new_mem,
  214.                         struct ttm_mem_reg *old_mem)
  215. {
  216.         struct radeon_device *rdev;
  217.         uint64_t old_start, new_start;
  218.         struct radeon_fence *fence;
  219.         int r, ridx;
  220.  
  221.         rdev = radeon_get_rdev(bo->bdev);
  222.         ridx = radeon_copy_ring_index(rdev);
  223.         old_start = old_mem->start << PAGE_SHIFT;
  224.         new_start = new_mem->start << PAGE_SHIFT;
  225.  
  226.         switch (old_mem->mem_type) {
  227.         case TTM_PL_VRAM:
  228.                 old_start += rdev->mc.vram_start;
  229.                 break;
  230.         case TTM_PL_TT:
  231.                 old_start += rdev->mc.gtt_start;
  232.                 break;
  233.         default:
  234.                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  235.                 return -EINVAL;
  236.         }
  237.         switch (new_mem->mem_type) {
  238.         case TTM_PL_VRAM:
  239.                 new_start += rdev->mc.vram_start;
  240.                 break;
  241.         case TTM_PL_TT:
  242.                 new_start += rdev->mc.gtt_start;
  243.                 break;
  244.         default:
  245.                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  246.                 return -EINVAL;
  247.         }
  248.         if (!rdev->ring[ridx].ready) {
  249.                 DRM_ERROR("Trying to move memory with ring turned off.\n");
  250.                 return -EINVAL;
  251.         }
  252.  
  253.         BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
  254.  
  255.         /* sync other rings */
  256.         fence = bo->sync_obj;
  257.         r = radeon_copy(rdev, old_start, new_start,
  258.                         new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */
  259.                         &fence);
  260.         /* FIXME: handle copy error */
  261.         r = ttm_bo_move_accel_cleanup(bo, (void *)fence,
  262.                                       evict, no_wait_gpu, new_mem);
  263.         radeon_fence_unref(&fence);
  264.         return r;
  265. }
  266.  
  267. static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
  268.                                 bool evict, bool interruptible,
  269.                                 bool no_wait_gpu,
  270.                                 struct ttm_mem_reg *new_mem)
  271. {
  272.         struct radeon_device *rdev;
  273.         struct ttm_mem_reg *old_mem = &bo->mem;
  274.         struct ttm_mem_reg tmp_mem;
  275.         u32 placements;
  276.         struct ttm_placement placement;
  277.         int r;
  278.  
  279.         rdev = radeon_get_rdev(bo->bdev);
  280.         tmp_mem = *new_mem;
  281.         tmp_mem.mm_node = NULL;
  282.         placement.fpfn = 0;
  283.         placement.lpfn = 0;
  284.         placement.num_placement = 1;
  285.         placement.placement = &placements;
  286.         placement.num_busy_placement = 1;
  287.         placement.busy_placement = &placements;
  288.         placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  289.         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
  290.                              interruptible, no_wait_gpu);
  291.         if (unlikely(r)) {
  292.                 return r;
  293.         }
  294.  
  295.         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
  296.         if (unlikely(r)) {
  297.                 goto out_cleanup;
  298.         }
  299.  
  300.         r = ttm_tt_bind(bo->ttm, &tmp_mem);
  301.         if (unlikely(r)) {
  302.                 goto out_cleanup;
  303.         }
  304.         r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
  305.         if (unlikely(r)) {
  306.                 goto out_cleanup;
  307.         }
  308.         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
  309. out_cleanup:
  310.         ttm_bo_mem_put(bo, &tmp_mem);
  311.         return r;
  312. }
  313.  
  314. static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
  315.                                 bool evict, bool interruptible,
  316.                                 bool no_wait_gpu,
  317.                                 struct ttm_mem_reg *new_mem)
  318. {
  319.         struct radeon_device *rdev;
  320.         struct ttm_mem_reg *old_mem = &bo->mem;
  321.         struct ttm_mem_reg tmp_mem;
  322.         struct ttm_placement placement;
  323.         u32 placements;
  324.         int r;
  325.  
  326.         rdev = radeon_get_rdev(bo->bdev);
  327.         tmp_mem = *new_mem;
  328.         tmp_mem.mm_node = NULL;
  329.         placement.fpfn = 0;
  330.         placement.lpfn = 0;
  331.         placement.num_placement = 1;
  332.         placement.placement = &placements;
  333.         placement.num_busy_placement = 1;
  334.         placement.busy_placement = &placements;
  335.         placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  336.         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
  337.                              interruptible, no_wait_gpu);
  338.         if (unlikely(r)) {
  339.                 return r;
  340.         }
  341.         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
  342.         if (unlikely(r)) {
  343.                 goto out_cleanup;
  344.         }
  345.         r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
  346.         if (unlikely(r)) {
  347.                 goto out_cleanup;
  348.         }
  349. out_cleanup:
  350.         ttm_bo_mem_put(bo, &tmp_mem);
  351.         return r;
  352. }
  353.  
  354. static int radeon_bo_move(struct ttm_buffer_object *bo,
  355.                         bool evict, bool interruptible,
  356.                         bool no_wait_gpu,
  357.                         struct ttm_mem_reg *new_mem)
  358. {
  359.         struct radeon_device *rdev;
  360.         struct ttm_mem_reg *old_mem = &bo->mem;
  361.         int r;
  362.  
  363.         rdev = radeon_get_rdev(bo->bdev);
  364.         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
  365.                 radeon_move_null(bo, new_mem);
  366.                 return 0;
  367.         }
  368.         if ((old_mem->mem_type == TTM_PL_TT &&
  369.              new_mem->mem_type == TTM_PL_SYSTEM) ||
  370.             (old_mem->mem_type == TTM_PL_SYSTEM &&
  371.              new_mem->mem_type == TTM_PL_TT)) {
  372.                 /* bind is enough */
  373.                 radeon_move_null(bo, new_mem);
  374.                 return 0;
  375.         }
  376.         if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
  377.             rdev->asic->copy.copy == NULL) {
  378.                 /* use memcpy */
  379.                 goto memcpy;
  380.         }
  381.  
  382.         if (old_mem->mem_type == TTM_PL_VRAM &&
  383.             new_mem->mem_type == TTM_PL_SYSTEM) {
  384.                 r = radeon_move_vram_ram(bo, evict, interruptible,
  385.                                         no_wait_gpu, new_mem);
  386.         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
  387.                    new_mem->mem_type == TTM_PL_VRAM) {
  388.                 r = radeon_move_ram_vram(bo, evict, interruptible,
  389.                                             no_wait_gpu, new_mem);
  390.         } else {
  391.                 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
  392.         }
  393.  
  394.         if (r) {
  395. memcpy:
  396.                 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
  397.                 if (r) {
  398.                         return r;
  399.                 }
  400.         }
  401.  
  402.         /* update statistics */
  403. //      atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
  404.         return 0;
  405. }
  406.  
  407. static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  408. {
  409.         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
  410.         struct radeon_device *rdev = radeon_get_rdev(bdev);
  411.  
  412.         mem->bus.addr = NULL;
  413.         mem->bus.offset = 0;
  414.         mem->bus.size = mem->num_pages << PAGE_SHIFT;
  415.         mem->bus.base = 0;
  416.         mem->bus.is_iomem = false;
  417.         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
  418.                 return -EINVAL;
  419.         switch (mem->mem_type) {
  420.         case TTM_PL_SYSTEM:
  421.                 /* system memory */
  422.                 return 0;
  423.         case TTM_PL_TT:
  424. #if __OS_HAS_AGP
  425.                 if (rdev->flags & RADEON_IS_AGP) {
  426.                         /* RADEON_IS_AGP is set only if AGP is active */
  427.                         mem->bus.offset = mem->start << PAGE_SHIFT;
  428.                         mem->bus.base = rdev->mc.agp_base;
  429.                         mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
  430.                 }
  431. #endif
  432.                 break;
  433.         case TTM_PL_VRAM:
  434.                 mem->bus.offset = mem->start << PAGE_SHIFT;
  435.                 /* check if it's visible */
  436.                 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
  437.                         return -EINVAL;
  438.                 mem->bus.base = rdev->mc.aper_base;
  439.                 mem->bus.is_iomem = true;
  440. #ifdef __alpha__
  441.                 /*
  442.                  * Alpha: use bus.addr to hold the ioremap() return,
  443.                  * so we can modify bus.base below.
  444.                  */
  445.                 if (mem->placement & TTM_PL_FLAG_WC)
  446.                         mem->bus.addr =
  447.                                 ioremap_wc(mem->bus.base + mem->bus.offset,
  448.                                            mem->bus.size);
  449.                 else
  450.                         mem->bus.addr =
  451.                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
  452.                                                 mem->bus.size);
  453.  
  454.                 /*
  455.                  * Alpha: Use just the bus offset plus
  456.                  * the hose/domain memory base for bus.base.
  457.                  * It then can be used to build PTEs for VRAM
  458.                  * access, as done in ttm_bo_vm_fault().
  459.                  */
  460.                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
  461.                         rdev->ddev->hose->dense_mem_base;
  462. #endif
  463.                 break;
  464.         default:
  465.                 return -EINVAL;
  466.         }
  467.         return 0;
  468. }
  469.  
  470. static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  471. {
  472. }
  473.  
  474. static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible)
  475. {
  476.         return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
  477. }
  478.  
  479. static int radeon_sync_obj_flush(void *sync_obj)
  480. {
  481.         return 0;
  482. }
  483.  
  484. static void radeon_sync_obj_unref(void **sync_obj)
  485. {
  486.         radeon_fence_unref((struct radeon_fence **)sync_obj);
  487. }
  488.  
  489. static void *radeon_sync_obj_ref(void *sync_obj)
  490. {
  491.         return radeon_fence_ref((struct radeon_fence *)sync_obj);
  492. }
  493.  
  494. static bool radeon_sync_obj_signaled(void *sync_obj)
  495. {
  496.         return radeon_fence_signaled((struct radeon_fence *)sync_obj);
  497. }
  498.  
  499. /*
  500.  * TTM backend functions.
  501.  */
  502. struct radeon_ttm_tt {
  503.         struct ttm_dma_tt               ttm;
  504.         struct radeon_device            *rdev;
  505.         u64                             offset;
  506. };
  507.  
  508. static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
  509.                                    struct ttm_mem_reg *bo_mem)
  510. {
  511.         struct radeon_ttm_tt *gtt = (void*)ttm;
  512.         uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
  513.                 RADEON_GART_PAGE_WRITE;
  514.         int r;
  515.  
  516.         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
  517.         if (!ttm->num_pages) {
  518.                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
  519.                      ttm->num_pages, bo_mem, ttm);
  520.         }
  521.         if (ttm->caching_state == tt_cached)
  522.                 flags |= RADEON_GART_PAGE_SNOOP;
  523.         r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
  524.                              ttm->pages, gtt->ttm.dma_address, flags);
  525.         if (r) {
  526.                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
  527.                           ttm->num_pages, (unsigned)gtt->offset);
  528.                 return r;
  529.         }
  530.         return 0;
  531. }
  532.  
  533. static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
  534. {
  535.         struct radeon_ttm_tt *gtt = (void *)ttm;
  536.  
  537.         radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
  538.         return 0;
  539. }
  540.  
  541. static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
  542. {
  543.         struct radeon_ttm_tt *gtt = (void *)ttm;
  544.  
  545. //   ttm_dma_tt_fini(&gtt->ttm);
  546.         kfree(gtt);
  547. }
  548.  
  549. static struct ttm_backend_func radeon_backend_func = {
  550.         .bind = &radeon_ttm_backend_bind,
  551.         .unbind = &radeon_ttm_backend_unbind,
  552.         .destroy = &radeon_ttm_backend_destroy,
  553. };
  554.  
  555. static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
  556.                                     unsigned long size, uint32_t page_flags,
  557.                                     struct page *dummy_read_page)
  558. {
  559.         struct radeon_device *rdev;
  560.         struct radeon_ttm_tt *gtt;
  561.  
  562.         rdev = radeon_get_rdev(bdev);
  563. #if __OS_HAS_AGP
  564.         if (rdev->flags & RADEON_IS_AGP) {
  565.                 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
  566.                                          size, page_flags, dummy_read_page);
  567.         }
  568. #endif
  569.  
  570.         gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
  571.         if (gtt == NULL) {
  572.                 return NULL;
  573.         }
  574.         gtt->ttm.ttm.func = &radeon_backend_func;
  575.         gtt->rdev = rdev;
  576.         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
  577.                 kfree(gtt);
  578.                 return NULL;
  579.         }
  580.         return &gtt->ttm.ttm;
  581. }
  582.  
  583. static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
  584. {
  585.         struct radeon_device *rdev;
  586.         struct radeon_ttm_tt *gtt = (void *)ttm;
  587.         unsigned i;
  588.         int r;
  589.         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
  590.  
  591.         if (ttm->state != tt_unpopulated)
  592.                 return 0;
  593.  
  594.         if (slave && ttm->sg) {
  595.                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
  596.                                                  gtt->ttm.dma_address, ttm->num_pages);
  597.                 ttm->state = tt_unbound;
  598.                 return 0;
  599.         }
  600.  
  601.         rdev = radeon_get_rdev(ttm->bdev);
  602. #if __OS_HAS_AGP
  603.         if (rdev->flags & RADEON_IS_AGP) {
  604.                 return ttm_agp_tt_populate(ttm);
  605.         }
  606. #endif
  607.  
  608. #ifdef CONFIG_SWIOTLB
  609.         if (swiotlb_nr_tbl()) {
  610.                 return ttm_dma_populate(&gtt->ttm, rdev->dev);
  611.         }
  612. #endif
  613.  
  614.         r = ttm_pool_populate(ttm);
  615.         if (r) {
  616.                 return r;
  617.         }
  618.  
  619.         for (i = 0; i < ttm->num_pages; i++) {
  620.                 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
  621.                                                        0, PAGE_SIZE,
  622.                                                        PCI_DMA_BIDIRECTIONAL);
  623.  
  624.         }
  625.         return 0;
  626. }
  627.  
  628. static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
  629. {
  630.         struct radeon_device *rdev;
  631.         struct radeon_ttm_tt *gtt = (void *)ttm;
  632.         unsigned i;
  633.         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
  634.  
  635.         if (slave)
  636.                 return;
  637.  
  638.         rdev = radeon_get_rdev(ttm->bdev);
  639. #if __OS_HAS_AGP
  640.         if (rdev->flags & RADEON_IS_AGP) {
  641.                 ttm_agp_tt_unpopulate(ttm);
  642.                 return;
  643.         }
  644. #endif
  645.  
  646. #ifdef CONFIG_SWIOTLB
  647.         if (swiotlb_nr_tbl()) {
  648.                 ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
  649.                 return;
  650.         }
  651. #endif
  652.  
  653.  
  654.         ttm_pool_unpopulate(ttm);
  655. }
  656.  
  657. static struct ttm_bo_driver radeon_bo_driver = {
  658.         .ttm_tt_create = &radeon_ttm_tt_create,
  659.         .ttm_tt_populate = &radeon_ttm_tt_populate,
  660.         .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
  661.         .invalidate_caches = &radeon_invalidate_caches,
  662.         .init_mem_type = &radeon_init_mem_type,
  663.         .evict_flags = &radeon_evict_flags,
  664.         .move = &radeon_bo_move,
  665.         .verify_access = &radeon_verify_access,
  666.         .sync_obj_signaled = &radeon_sync_obj_signaled,
  667.         .sync_obj_wait = &radeon_sync_obj_wait,
  668.         .sync_obj_flush = &radeon_sync_obj_flush,
  669.         .sync_obj_unref = &radeon_sync_obj_unref,
  670.         .sync_obj_ref = &radeon_sync_obj_ref,
  671.         .move_notify = &radeon_bo_move_notify,
  672. //      .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
  673.         .io_mem_reserve = &radeon_ttm_io_mem_reserve,
  674.         .io_mem_free = &radeon_ttm_io_mem_free,
  675. };
  676.  
  677. int radeon_ttm_init(struct radeon_device *rdev)
  678. {
  679.         int r;
  680.  
  681.         r = radeon_ttm_global_init(rdev);
  682.         if (r) {
  683.                 return r;
  684.         }
  685.         /* No others user of address space so set it to 0 */
  686.         r = ttm_bo_device_init(&rdev->mman.bdev,
  687.                                rdev->mman.bo_global_ref.ref.object,
  688.                                &radeon_bo_driver,
  689.                                NULL,
  690.                                DRM_FILE_PAGE_OFFSET,
  691.                                rdev->need_dma32);
  692.         if (r) {
  693.                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
  694.                 return r;
  695.         }
  696.         rdev->mman.initialized = true;
  697.         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
  698.                                 rdev->mc.real_vram_size >> PAGE_SHIFT);
  699.         if (r) {
  700.                 DRM_ERROR("Failed initializing VRAM heap.\n");
  701.                 return r;
  702.         }
  703.         /* Change the size here instead of the init above so only lpfn is affected */
  704.         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
  705.  
  706.     r = radeon_bo_create(rdev, 16*1024*1024, PAGE_SIZE, true,
  707.                              RADEON_GEM_DOMAIN_VRAM, 0,
  708.                              NULL, &rdev->stollen_vga_memory);
  709.         if (r) {
  710.                 return r;
  711.         }
  712.         r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
  713.         if (r)
  714.                 return r;
  715.         r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
  716.         radeon_bo_unreserve(rdev->stollen_vga_memory);
  717.         if (r) {
  718.                 radeon_bo_unref(&rdev->stollen_vga_memory);
  719.                 return r;
  720.         }
  721.         DRM_INFO("radeon: %uM of VRAM memory ready\n",
  722.                  (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
  723.         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
  724.                                 rdev->mc.gtt_size >> PAGE_SHIFT);
  725.         if (r) {
  726.                 DRM_ERROR("Failed initializing GTT heap.\n");
  727.                 return r;
  728.         }
  729.         DRM_INFO("radeon: %uM of GTT memory ready.\n",
  730.                  (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
  731.  
  732.     return 0;
  733. }
  734.  
  735.  
  736. /* this should only be called at bootup or when userspace
  737.  * isn't running */
  738. void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
  739. {
  740.         struct ttm_mem_type_manager *man;
  741.  
  742.         if (!rdev->mman.initialized)
  743.                 return;
  744.  
  745.         man = &rdev->mman.bdev.man[TTM_PL_VRAM];
  746.         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
  747.         man->size = size >> PAGE_SHIFT;
  748. }
  749.  
  750. static struct vm_operations_struct radeon_ttm_vm_ops;
  751. static const struct vm_operations_struct *ttm_vm_ops = NULL;
  752.  
  753. #if 0
  754.  
  755. radeon_bo_init
  756. {
  757.     <6>[drm] Detected VRAM RAM=1024M, BAR=256M
  758.     <6>[drm] RAM width 128bits DDR
  759.  
  760.     radeon_ttm_init
  761.     {
  762.         radeon_ttm_global_init
  763.         {
  764.             radeon_ttm_mem_global_init
  765.  
  766.             ttm_bo_global_init
  767.         }
  768.  
  769.         ttm_bo_device_init
  770.         {
  771.             ttm_bo_init_mm
  772.             {
  773.                 radeon_init_mem_type
  774.             };
  775.         }
  776.  
  777.         ttm_bo_init_mm
  778.         {
  779.             radeon_init_mem_type
  780.  
  781.             ttm_bo_man_init
  782.         }
  783.  
  784.         <6>[drm] radeon: 1024M of VRAM memory ready
  785.  
  786.         ttm_bo_init_mm
  787.         {
  788.             radeon_init_mem_type
  789.  
  790.             ttm_bo_man_init
  791.         }
  792.  
  793.         <6>[drm] radeon: 512M of GTT memory ready.
  794.     }
  795. };
  796.  
  797. #endif
  798.  
  799.  
  800.  
  801.  
  802. int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page **pages,
  803.                                      dma_addr_t *addrs, int max_pages)
  804. {
  805.     unsigned count;
  806.     struct scatterlist *sg;
  807.     struct page *page;
  808.     u32 len;
  809.     int pg_index;
  810.     dma_addr_t addr;
  811.  
  812.     pg_index = 0;
  813.     for_each_sg(sgt->sgl, sg, sgt->nents, count) {
  814.         len = sg->length;
  815.         page = sg_page(sg);
  816.         addr = sg_dma_address(sg);
  817.  
  818.         while (len > 0) {
  819.             if (WARN_ON(pg_index >= max_pages))
  820.                     return -1;
  821.             pages[pg_index] = page;
  822.             if (addrs)
  823.                     addrs[pg_index] = addr;
  824.  
  825.             page++;
  826.             addr += PAGE_SIZE;
  827.             len -= PAGE_SIZE;
  828.             pg_index++;
  829.         }
  830.     }
  831.     return 0;
  832. }
  833.