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  1.  
  2. #include <linux/list.h>
  3. #include <drm/drmP.h>
  4. #include "radeon_drm.h"
  5. #include "radeon.h"
  6.  
  7.  
  8. static struct drm_mm   mm_gtt;
  9. static struct drm_mm   mm_vram;
  10.  
  11.  
  12. /**
  13.  * Initialize an already allocate GEM object of the specified size with
  14.  * shmfs backing store.
  15.  */
  16. int drm_gem_object_init(struct drm_device *dev,
  17.             struct drm_gem_object *obj, size_t size)
  18. {
  19.     BUG_ON((size & (PAGE_SIZE - 1)) != 0);
  20.  
  21.     obj->dev = dev;
  22.     obj->filp = NULL;
  23.  
  24.     atomic_set(&obj->handle_count, 0);
  25.     obj->size = size;
  26.  
  27.     return 0;
  28. }
  29.  
  30.  
  31. int drm_mm_alloc(struct drm_mm *mm, size_t num_pages,
  32.                  struct drm_mm_node **node)
  33. {
  34.     struct drm_mm_node *vm_node;
  35.     int    r;
  36.  
  37. retry_pre_get:
  38.  
  39.     r = drm_mm_pre_get(mm);
  40.  
  41.     if (unlikely(r != 0))
  42.        return r;
  43.  
  44.     vm_node = drm_mm_search_free(mm, num_pages, 0, 0);
  45.  
  46.     if (unlikely(vm_node == NULL)) {
  47.         r = -ENOMEM;
  48.         return r;
  49.     }
  50.  
  51.     *node =  drm_mm_get_block_atomic(vm_node, num_pages, 0);
  52.  
  53.     if (unlikely(*node == NULL)) {
  54.             goto retry_pre_get;
  55.     }
  56.  
  57.     return 0;
  58. };
  59.  
  60.  
  61.  
  62. void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  63. {
  64.     u32 c = 0;
  65.  
  66.     rbo->placement.fpfn = 0;
  67.     rbo->placement.lpfn = 0;
  68.     rbo->placement.placement = rbo->placements;
  69.     rbo->placement.busy_placement = rbo->placements;
  70.     if (domain & RADEON_GEM_DOMAIN_VRAM)
  71.         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  72.                     TTM_PL_FLAG_VRAM;
  73.     if (domain & RADEON_GEM_DOMAIN_GTT)
  74.         rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  75.     if (domain & RADEON_GEM_DOMAIN_CPU)
  76.         rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  77.     if (!c)
  78.         rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  79.     rbo->placement.num_placement = c;
  80.     rbo->placement.num_busy_placement = c;
  81. }
  82.  
  83.  
  84. int radeon_bo_init(struct radeon_device *rdev)
  85. {
  86.     int r;
  87.  
  88.     DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
  89.         rdev->mc.mc_vram_size >> 20,
  90.         (unsigned long long)rdev->mc.aper_size >> 20);
  91.     DRM_INFO("RAM width %dbits %cDR\n",
  92.             rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
  93.  
  94.     r = drm_mm_init(&mm_vram, 0xC00000 >> PAGE_SHIFT,
  95.                ((rdev->mc.real_vram_size - 0xC00000) >> PAGE_SHIFT));
  96.     if (r) {
  97.         DRM_ERROR("Failed initializing VRAM heap.\n");
  98.         return r;
  99.     };
  100.  
  101.     r = drm_mm_init(&mm_gtt, 0, rdev->mc.gtt_size >> PAGE_SHIFT);
  102.     if (r) {
  103.         DRM_ERROR("Failed initializing GTT heap.\n");
  104.         return r;
  105.     }
  106.  
  107.     return 0;
  108. }
  109.  
  110.  
  111. int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
  112. {
  113.     int r;
  114.  
  115.     bo->tbo.reserved.counter = 1;
  116.  
  117.     return 0;
  118. }
  119.  
  120. void ttm_bo_unreserve(struct ttm_buffer_object *bo)
  121. {
  122.     bo->reserved.counter = 1;
  123. }
  124.  
  125. int radeon_bo_create(struct radeon_device *rdev,
  126.                      unsigned long size, int byte_align, bool kernel, u32 domain,
  127.                 struct radeon_bo **bo_ptr)
  128. {
  129.         struct radeon_bo *bo;
  130.     enum ttm_bo_type type;
  131.  
  132.     size_t num_pages;
  133.     struct drm_mm      *mman;
  134.     u32                 bo_domain;
  135.     int r;
  136.  
  137.     num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
  138.  
  139.     size = num_pages << PAGE_SHIFT;
  140.  
  141.     if (num_pages == 0) {
  142.         dbgprintf("Illegal buffer object size.\n");
  143.         return -EINVAL;
  144.     }
  145.  
  146.     if(domain & RADEON_GEM_DOMAIN_VRAM)
  147.     {
  148.         mman = &mm_vram;
  149.         bo_domain = RADEON_GEM_DOMAIN_VRAM;
  150.     }
  151.     else if(domain & RADEON_GEM_DOMAIN_GTT)
  152.     {
  153.         mman = &mm_gtt;
  154.         bo_domain = RADEON_GEM_DOMAIN_GTT;
  155.     }
  156.     else return -EINVAL;
  157.  
  158.     if (kernel) {
  159.         type = ttm_bo_type_kernel;
  160.     } else {
  161.         type = ttm_bo_type_device;
  162.     }
  163.     *bo_ptr = NULL;
  164.     bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
  165.     if (bo == NULL)
  166.         return -ENOMEM;
  167.  
  168.         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
  169.     if (unlikely(r)) {
  170.                 kfree(bo);
  171.                 return r;
  172.         }
  173.     bo->rdev = rdev;
  174.         bo->gem_base.driver_private = NULL;
  175.     bo->surface_reg = -1;
  176.     bo->tbo.num_pages = num_pages;
  177.     bo->domain = domain;
  178.  
  179.     INIT_LIST_HEAD(&bo->list);
  180.  
  181. //    radeon_ttm_placement_from_domain(bo, domain);
  182.     /* Kernel allocation are uninterruptible */
  183.  
  184.     r = drm_mm_alloc(mman, num_pages, &bo->tbo.vm_node);
  185.     if (unlikely(r != 0))
  186.         return r;
  187.  
  188.     *bo_ptr = bo;
  189.  
  190.     return 0;
  191. }
  192.  
  193. #define page_tabs  0xFDC00000      /* just another hack */
  194.  
  195. int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
  196. {
  197.     int r=0, i;
  198.  
  199.     if (bo->pin_count) {
  200.         bo->pin_count++;
  201.         if (gpu_addr)
  202.             *gpu_addr = radeon_bo_gpu_offset(bo);
  203.         return 0;
  204.     }
  205.  
  206.     bo->tbo.offset = bo->tbo.vm_node->start << PAGE_SHIFT;
  207.  
  208.     if(bo->domain & RADEON_GEM_DOMAIN_VRAM)
  209.     {
  210.         bo->tbo.offset += (u64)bo->rdev->mc.vram_start;
  211.     }
  212.     else if (bo->domain & RADEON_GEM_DOMAIN_GTT)
  213.     {
  214.         u32_t *pagelist;
  215.         bo->kptr  = KernelAlloc( bo->tbo.num_pages << PAGE_SHIFT );
  216.         dbgprintf("kernel alloc %x\n", bo->kptr );
  217.  
  218.         pagelist =  &((u32_t*)page_tabs)[(u32_t)bo->kptr >> 12];
  219.         dbgprintf("pagelist %x\n", pagelist);
  220.         radeon_gart_bind(bo->rdev, bo->tbo.offset,
  221.                          bo->tbo.vm_node->size,  pagelist);
  222.         bo->tbo.offset += (u64)bo->rdev->mc.gtt_start;
  223.     }
  224.     else
  225.     {
  226.         DRM_ERROR("Unknown placement %x\n", bo->domain);
  227.         bo->tbo.offset = -1;
  228.         r = -1;
  229.     };
  230.  
  231.     if (unlikely(r != 0)) {
  232.         DRM_ERROR("radeon: failed to pin object.\n");
  233.     }
  234.  
  235.     if (likely(r == 0)) {
  236.         bo->pin_count = 1;
  237.         if (gpu_addr != NULL)
  238.             *gpu_addr = radeon_bo_gpu_offset(bo);
  239.     }
  240.  
  241.     if (unlikely(r != 0))
  242.         dev_err(bo->rdev->dev, "%p pin failed\n", bo);
  243.     return r;
  244. };
  245.  
  246. int radeon_bo_unpin(struct radeon_bo *bo)
  247. {
  248.     int r = 0;
  249.  
  250.     if (!bo->pin_count) {
  251.         dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
  252.         return 0;
  253.     }
  254.     bo->pin_count--;
  255.     if (bo->pin_count)
  256.         return 0;
  257.  
  258.     if( bo->tbo.vm_node )
  259.     {
  260.         drm_mm_put_block(bo->tbo.vm_node);
  261.         bo->tbo.vm_node = NULL;
  262.     };
  263.  
  264.     return r;
  265. }
  266.  
  267. int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
  268. {
  269.     bool is_iomem;
  270.  
  271.     if (bo->kptr) {
  272.         if (ptr) {
  273.             *ptr = bo->kptr;
  274.         }
  275.         return 0;
  276.     }
  277.  
  278.     if(bo->domain & RADEON_GEM_DOMAIN_VRAM)
  279.     {
  280.         bo->cpu_addr = bo->rdev->mc.aper_base +
  281.                        (bo->tbo.vm_node->start << PAGE_SHIFT);
  282.         bo->kptr = (void*)MapIoMem(bo->cpu_addr,
  283.                         bo->tbo.vm_node->size << 12, PG_SW);
  284.     }
  285.     else
  286.     {
  287.         return -1;
  288.     }
  289.  
  290.     if (ptr) {
  291.         *ptr = bo->kptr;
  292.     }
  293.  
  294.     return 0;
  295. }
  296.  
  297. void radeon_bo_kunmap(struct radeon_bo *bo)
  298. {
  299.     if (bo->kptr == NULL)
  300.         return;
  301.  
  302.     if (bo->domain & RADEON_GEM_DOMAIN_VRAM)
  303.     {
  304.         FreeKernelSpace(bo->kptr);
  305.     }
  306.  
  307.     bo->kptr = NULL;
  308.  
  309. }
  310.  
  311. void radeon_bo_unref(struct radeon_bo **bo)
  312. {
  313.     struct ttm_buffer_object *tbo;
  314.  
  315.     if ((*bo) == NULL)
  316.         return;
  317.  
  318.     *bo = NULL;
  319. }
  320.  
  321.  
  322. void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
  323.                 uint32_t *tiling_flags,
  324.                 uint32_t *pitch)
  325. {
  326. //    BUG_ON(!atomic_read(&bo->tbo.reserved));
  327.     if (tiling_flags)
  328.         *tiling_flags = bo->tiling_flags;
  329.     if (pitch)
  330.         *pitch = bo->pitch;
  331. }
  332.  
  333.  
  334. /**
  335.  * Allocate a GEM object of the specified size with shmfs backing store
  336.  */
  337. struct drm_gem_object *
  338. drm_gem_object_alloc(struct drm_device *dev, size_t size)
  339. {
  340.     struct drm_gem_object *obj;
  341.  
  342.     BUG_ON((size & (PAGE_SIZE - 1)) != 0);
  343.  
  344.     obj = kzalloc(sizeof(*obj), GFP_KERNEL);
  345.  
  346.     obj->dev = dev;
  347.     obj->size = size;
  348.     return obj;
  349. }
  350.  
  351.  
  352. int radeon_fb_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
  353.             unsigned long size, bool kernel, u32 domain,
  354.             struct radeon_bo **bo_ptr)
  355. {
  356.     enum ttm_bo_type    type;
  357.  
  358.     struct radeon_bo    *bo;
  359.     struct drm_mm       *mman;
  360.     struct drm_mm_node  *vm_node;
  361.  
  362.     size_t  num_pages;
  363.     u32     bo_domain;
  364.     int     r;
  365.  
  366.     num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
  367.  
  368.     if (num_pages == 0) {
  369.         dbgprintf("Illegal buffer object size.\n");
  370.         return -EINVAL;
  371.     }
  372.  
  373.     if( (domain & RADEON_GEM_DOMAIN_VRAM) !=
  374.         RADEON_GEM_DOMAIN_VRAM )
  375.     {
  376.         return -EINVAL;
  377.     };
  378.  
  379.     if (kernel) {
  380.         type = ttm_bo_type_kernel;
  381.     } else {
  382.         type = ttm_bo_type_device;
  383.     }
  384.     *bo_ptr = NULL;
  385.     bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
  386.     if (bo == NULL)
  387.         return -ENOMEM;
  388.  
  389.     bo->rdev = rdev;
  390. //    bo->gobj = gobj;
  391.     bo->surface_reg = -1;
  392.     bo->tbo.num_pages = num_pages;
  393.     bo->domain = domain;
  394.  
  395.     INIT_LIST_HEAD(&bo->list);
  396.  
  397. //    radeon_ttm_placement_from_domain(bo, domain);
  398.     /* Kernel allocation are uninterruptible */
  399.  
  400.     vm_node = kzalloc(sizeof(*vm_node),0);
  401.  
  402.     vm_node->size = 0xC00000 >> 12;
  403.     vm_node->start = 0;
  404.     vm_node->mm = NULL;
  405.  
  406.     bo->tbo.vm_node = vm_node;
  407.     bo->tbo.offset  = bo->tbo.vm_node->start << PAGE_SHIFT;
  408.     bo->tbo.offset += (u64)bo->rdev->mc.vram_start;
  409.     bo->kptr        = (void*)0xFE000000;
  410.     bo->pin_count   = 1;
  411.  
  412.     *bo_ptr = bo;
  413.  
  414.     return 0;
  415. }
  416.