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  1. /*
  2.  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  3.  *                VA Linux Systems Inc., Fremont, California.
  4.  * Copyright 2008 Red Hat Inc.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Original Authors:
  25.  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
  26.  *
  27.  * Kernel port Author: Dave Airlie
  28.  */
  29.  
  30. #ifndef RADEON_MODE_H
  31. #define RADEON_MODE_H
  32.  
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include <drm/drm_dp_helper.h>
  36. #include <drm/drm_fixed.h>
  37. #include <drm/drm_crtc_helper.h>
  38. #include <linux/i2c.h>
  39. #include <linux/i2c-algo-bit.h>
  40.  
  41. struct radeon_bo;
  42. struct radeon_device;
  43.  
  44. #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
  45. #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
  46. #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
  47. #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
  48.  
  49. #define RADEON_MAX_HPD_PINS 7
  50. #define RADEON_MAX_CRTCS 6
  51. #define RADEON_MAX_AFMT_BLOCKS 7
  52.  
  53. enum radeon_rmx_type {
  54.         RMX_OFF,
  55.         RMX_FULL,
  56.         RMX_CENTER,
  57.         RMX_ASPECT
  58. };
  59.  
  60. enum radeon_tv_std {
  61.         TV_STD_NTSC,
  62.         TV_STD_PAL,
  63.         TV_STD_PAL_M,
  64.         TV_STD_PAL_60,
  65.         TV_STD_NTSC_J,
  66.         TV_STD_SCART_PAL,
  67.         TV_STD_SECAM,
  68.         TV_STD_PAL_CN,
  69.         TV_STD_PAL_N,
  70. };
  71.  
  72. enum radeon_underscan_type {
  73.         UNDERSCAN_OFF,
  74.         UNDERSCAN_ON,
  75.         UNDERSCAN_AUTO,
  76. };
  77.  
  78. enum radeon_hpd_id {
  79.         RADEON_HPD_1 = 0,
  80.         RADEON_HPD_2,
  81.         RADEON_HPD_3,
  82.         RADEON_HPD_4,
  83.         RADEON_HPD_5,
  84.         RADEON_HPD_6,
  85.         RADEON_HPD_NONE = 0xff,
  86. };
  87.  
  88. #define RADEON_MAX_I2C_BUS 16
  89.  
  90. /* radeon gpio-based i2c
  91.  * 1. "mask" reg and bits
  92.  *    grabs the gpio pins for software use
  93.  *    0=not held  1=held
  94.  * 2. "a" reg and bits
  95.  *    output pin value
  96.  *    0=low 1=high
  97.  * 3. "en" reg and bits
  98.  *    sets the pin direction
  99.  *    0=input 1=output
  100.  * 4. "y" reg and bits
  101.  *    input pin value
  102.  *    0=low 1=high
  103.  */
  104. struct radeon_i2c_bus_rec {
  105.         bool valid;
  106.         /* id used by atom */
  107.         uint8_t i2c_id;
  108.         /* id used by atom */
  109.         enum radeon_hpd_id hpd;
  110.         /* can be used with hw i2c engine */
  111.         bool hw_capable;
  112.         /* uses multi-media i2c engine */
  113.         bool mm_i2c;
  114.         /* regs and bits */
  115.         uint32_t mask_clk_reg;
  116.         uint32_t mask_data_reg;
  117.         uint32_t a_clk_reg;
  118.         uint32_t a_data_reg;
  119.         uint32_t en_clk_reg;
  120.         uint32_t en_data_reg;
  121.         uint32_t y_clk_reg;
  122.         uint32_t y_data_reg;
  123.         uint32_t mask_clk_mask;
  124.         uint32_t mask_data_mask;
  125.         uint32_t a_clk_mask;
  126.         uint32_t a_data_mask;
  127.         uint32_t en_clk_mask;
  128.         uint32_t en_data_mask;
  129.         uint32_t y_clk_mask;
  130.         uint32_t y_data_mask;
  131. };
  132.  
  133. struct radeon_tmds_pll {
  134.     uint32_t freq;
  135.     uint32_t value;
  136. };
  137.  
  138. #define RADEON_MAX_BIOS_CONNECTOR 16
  139.  
  140. /* pll flags */
  141. #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
  142. #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
  143. #define RADEON_PLL_USE_REF_DIV          (1 << 2)
  144. #define RADEON_PLL_LEGACY               (1 << 3)
  145. #define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
  146. #define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
  147. #define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
  148. #define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
  149. #define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
  150. #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
  151. #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
  152. #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
  153. #define RADEON_PLL_USE_POST_DIV         (1 << 12)
  154. #define RADEON_PLL_IS_LCD               (1 << 13)
  155. #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
  156.  
  157. struct radeon_pll {
  158.         /* reference frequency */
  159.         uint32_t reference_freq;
  160.  
  161.         /* fixed dividers */
  162.         uint32_t reference_div;
  163.         uint32_t post_div;
  164.  
  165.         /* pll in/out limits */
  166.         uint32_t pll_in_min;
  167.         uint32_t pll_in_max;
  168.         uint32_t pll_out_min;
  169.         uint32_t pll_out_max;
  170.         uint32_t lcd_pll_out_min;
  171.         uint32_t lcd_pll_out_max;
  172.         uint32_t best_vco;
  173.  
  174.         /* divider limits */
  175.         uint32_t min_ref_div;
  176.         uint32_t max_ref_div;
  177.         uint32_t min_post_div;
  178.         uint32_t max_post_div;
  179.         uint32_t min_feedback_div;
  180.         uint32_t max_feedback_div;
  181.         uint32_t min_frac_feedback_div;
  182.         uint32_t max_frac_feedback_div;
  183.  
  184.         /* flags for the current clock */
  185.         uint32_t flags;
  186.  
  187.         /* pll id */
  188.         uint32_t id;
  189. };
  190.  
  191. struct radeon_i2c_chan {
  192.         struct i2c_adapter adapter;
  193.         struct drm_device *dev;
  194.                 struct i2c_algo_bit_data bit;
  195.         struct radeon_i2c_bus_rec rec;
  196.         struct drm_dp_aux aux;
  197.         bool has_aux;
  198.         struct mutex mutex;
  199. };
  200.  
  201. /* mostly for macs, but really any system without connector tables */
  202. enum radeon_connector_table {
  203.         CT_NONE = 0,
  204.         CT_GENERIC,
  205.         CT_IBOOK,
  206.         CT_POWERBOOK_EXTERNAL,
  207.         CT_POWERBOOK_INTERNAL,
  208.         CT_POWERBOOK_VGA,
  209.         CT_MINI_EXTERNAL,
  210.         CT_MINI_INTERNAL,
  211.         CT_IMAC_G5_ISIGHT,
  212.         CT_EMAC,
  213.         CT_RN50_POWER,
  214.         CT_MAC_X800,
  215.         CT_MAC_G5_9600,
  216.         CT_SAM440EP,
  217.         CT_MAC_G4_SILVER
  218. };
  219.  
  220. enum radeon_dvo_chip {
  221.         DVO_SIL164,
  222.         DVO_SIL1178,
  223. };
  224.  
  225. struct radeon_fbdev;
  226.  
  227. struct radeon_afmt {
  228.         bool enabled;
  229.         int offset;
  230.         bool last_buffer_filled_status;
  231.         int id;
  232.         struct r600_audio_pin *pin;
  233. };
  234.  
  235. struct radeon_mode_info {
  236.         struct atom_context *atom_context;
  237.         struct card_info *atom_card_info;
  238.         enum radeon_connector_table connector_table;
  239.         bool mode_config_initialized;
  240.         struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
  241.         struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
  242.         /* DVI-I properties */
  243.         struct drm_property *coherent_mode_property;
  244.         /* DAC enable load detect */
  245.         struct drm_property *load_detect_property;
  246.         /* TV standard */
  247.         struct drm_property *tv_std_property;
  248.         /* legacy TMDS PLL detect */
  249.         struct drm_property *tmds_pll_property;
  250.         /* underscan */
  251.         struct drm_property *underscan_property;
  252.         struct drm_property *underscan_hborder_property;
  253.         struct drm_property *underscan_vborder_property;
  254.         /* audio */
  255.         struct drm_property *audio_property;
  256.         /* FMT dithering */
  257.         struct drm_property *dither_property;
  258.         /* hardcoded DFP edid from BIOS */
  259.         struct edid *bios_hardcoded_edid;
  260.         int bios_hardcoded_edid_size;
  261.  
  262.         /* pointer to fbdev info structure */
  263.         struct radeon_fbdev *rfbdev;
  264.         /* firmware flags */
  265.         u16 firmware_flags;
  266.         /* pointer to backlight encoder */
  267.         struct radeon_encoder *bl_encoder;
  268. };
  269.  
  270. #define RADEON_MAX_BL_LEVEL 0xFF
  271.  
  272. #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
  273.  
  274. struct radeon_backlight_privdata {
  275.         struct radeon_encoder *encoder;
  276.         uint8_t negative;
  277. };
  278.  
  279. #endif
  280.  
  281. #define MAX_H_CODE_TIMING_LEN 32
  282. #define MAX_V_CODE_TIMING_LEN 32
  283.  
  284. /* need to store these as reading
  285.    back code tables is excessive */
  286. struct radeon_tv_regs {
  287.         uint32_t tv_uv_adr;
  288.         uint32_t timing_cntl;
  289.         uint32_t hrestart;
  290.         uint32_t vrestart;
  291.         uint32_t frestart;
  292.         uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
  293.         uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
  294. };
  295.  
  296. struct radeon_atom_ss {
  297.         uint16_t percentage;
  298.         uint16_t percentage_divider;
  299.         uint8_t type;
  300.         uint16_t step;
  301.         uint8_t delay;
  302.         uint8_t range;
  303.         uint8_t refdiv;
  304.         /* asic_ss */
  305.         uint16_t rate;
  306.         uint16_t amount;
  307. };
  308.  
  309. enum radeon_flip_status {
  310.         RADEON_FLIP_NONE,
  311.         RADEON_FLIP_PENDING,
  312.         RADEON_FLIP_SUBMITTED
  313. };
  314.  
  315. struct radeon_crtc {
  316.         struct drm_crtc base;
  317.         int crtc_id;
  318.         u16 lut_r[256], lut_g[256], lut_b[256];
  319.         bool enabled;
  320.         bool can_tile;
  321.         uint32_t crtc_offset;
  322.         struct drm_gem_object *cursor_bo;
  323.         uint64_t cursor_addr;
  324.         int cursor_x;
  325.         int cursor_y;
  326.         int cursor_hot_x;
  327.         int cursor_hot_y;
  328.         int cursor_width;
  329.         int cursor_height;
  330.         int max_cursor_width;
  331.         int max_cursor_height;
  332.         uint32_t legacy_display_base_addr;
  333.         uint32_t legacy_cursor_offset;
  334.         enum radeon_rmx_type rmx_type;
  335.         u8 h_border;
  336.         u8 v_border;
  337.         fixed20_12 vsc;
  338.         fixed20_12 hsc;
  339.         struct drm_display_mode native_mode;
  340.         int pll_id;
  341.         /* page flipping */
  342.         struct workqueue_struct *flip_queue;
  343.         struct radeon_flip_work *flip_work;
  344.         enum radeon_flip_status flip_status;
  345.         /* pll sharing */
  346.         struct radeon_atom_ss ss;
  347.         bool ss_enabled;
  348.         u32 adjusted_clock;
  349.         int bpc;
  350.         u32 pll_reference_div;
  351.         u32 pll_post_div;
  352.         u32 pll_flags;
  353.         struct drm_encoder *encoder;
  354.         struct drm_connector *connector;
  355.         /* for dpm */
  356.         u32 line_time;
  357.         u32 wm_low;
  358.         u32 wm_high;
  359.         struct drm_display_mode hw_mode;
  360. };
  361.  
  362. struct radeon_encoder_primary_dac {
  363.         /* legacy primary dac */
  364.         uint32_t ps2_pdac_adj;
  365. };
  366.  
  367. struct radeon_encoder_lvds {
  368.         /* legacy lvds */
  369.         uint16_t panel_vcc_delay;
  370.         uint8_t  panel_pwr_delay;
  371.         uint8_t  panel_digon_delay;
  372.         uint8_t  panel_blon_delay;
  373.         uint16_t panel_ref_divider;
  374.         uint8_t  panel_post_divider;
  375.         uint16_t panel_fb_divider;
  376.         bool     use_bios_dividers;
  377.         uint32_t lvds_gen_cntl;
  378.         /* panel mode */
  379.         struct drm_display_mode native_mode;
  380.         struct backlight_device *bl_dev;
  381.         int      dpms_mode;
  382.         uint8_t  backlight_level;
  383. };
  384.  
  385. struct radeon_encoder_tv_dac {
  386.         /* legacy tv dac */
  387.         uint32_t ps2_tvdac_adj;
  388.         uint32_t ntsc_tvdac_adj;
  389.         uint32_t pal_tvdac_adj;
  390.  
  391.         int               h_pos;
  392.         int               v_pos;
  393.         int               h_size;
  394.         int               supported_tv_stds;
  395.         bool              tv_on;
  396.         enum radeon_tv_std tv_std;
  397.         struct radeon_tv_regs tv;
  398. };
  399.  
  400. struct radeon_encoder_int_tmds {
  401.         /* legacy int tmds */
  402.         struct radeon_tmds_pll tmds_pll[4];
  403. };
  404.  
  405. struct radeon_encoder_ext_tmds {
  406.         /* tmds over dvo */
  407.         struct radeon_i2c_chan *i2c_bus;
  408.         uint8_t slave_addr;
  409.         enum radeon_dvo_chip dvo_chip;
  410. };
  411.  
  412. /* spread spectrum */
  413. struct radeon_encoder_atom_dig {
  414.         bool linkb;
  415.         /* atom dig */
  416.         bool coherent_mode;
  417.         int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
  418.         /* atom lvds/edp */
  419.         uint32_t lcd_misc;
  420.         uint16_t panel_pwr_delay;
  421.         uint32_t lcd_ss_id;
  422.         /* panel mode */
  423.         struct drm_display_mode native_mode;
  424.         struct backlight_device *bl_dev;
  425.         int dpms_mode;
  426.         uint8_t backlight_level;
  427.         int panel_mode;
  428.         struct radeon_afmt *afmt;
  429. };
  430.  
  431. struct radeon_encoder_atom_dac {
  432.         enum radeon_tv_std tv_std;
  433. };
  434.  
  435. struct radeon_encoder {
  436.     struct drm_encoder base;
  437.         uint32_t encoder_enum;
  438.         uint32_t encoder_id;
  439.         uint32_t devices;
  440.         uint32_t active_device;
  441.         uint32_t flags;
  442.         uint32_t pixel_clock;
  443.         enum radeon_rmx_type rmx_type;
  444.         enum radeon_underscan_type underscan_type;
  445.         uint32_t underscan_hborder;
  446.         uint32_t underscan_vborder;
  447.         struct drm_display_mode native_mode;
  448.         void *enc_priv;
  449.         int audio_polling_active;
  450.         bool is_ext_encoder;
  451.         u16 caps;
  452. };
  453.  
  454. struct radeon_connector_atom_dig {
  455.         uint32_t igp_lane_info;
  456.         /* displayport */
  457.         u8 dpcd[DP_RECEIVER_CAP_SIZE];
  458.         u8 dp_sink_type;
  459.         int dp_clock;
  460.         int dp_lane_count;
  461.         bool edp_on;
  462. };
  463.  
  464. struct radeon_gpio_rec {
  465.         bool valid;
  466.         u8 id;
  467.         u32 reg;
  468.         u32 mask;
  469.         u32 shift;
  470. };
  471.  
  472. struct radeon_hpd {
  473.         enum radeon_hpd_id hpd;
  474.         u8 plugged_state;
  475.         struct radeon_gpio_rec gpio;
  476. };
  477.  
  478. struct radeon_router {
  479.         u32 router_id;
  480.         struct radeon_i2c_bus_rec i2c_info;
  481.         u8 i2c_addr;
  482.         /* i2c mux */
  483.         bool ddc_valid;
  484.         u8 ddc_mux_type;
  485.         u8 ddc_mux_control_pin;
  486.         u8 ddc_mux_state;
  487.         /* clock/data mux */
  488.         bool cd_valid;
  489.         u8 cd_mux_type;
  490.         u8 cd_mux_control_pin;
  491.         u8 cd_mux_state;
  492. };
  493.  
  494. enum radeon_connector_audio {
  495.         RADEON_AUDIO_DISABLE = 0,
  496.         RADEON_AUDIO_ENABLE = 1,
  497.         RADEON_AUDIO_AUTO = 2
  498. };
  499.  
  500. enum radeon_connector_dither {
  501.         RADEON_FMT_DITHER_DISABLE = 0,
  502.         RADEON_FMT_DITHER_ENABLE = 1,
  503. };
  504.  
  505. struct radeon_connector {
  506.     struct drm_connector base;
  507.         uint32_t connector_id;
  508.         uint32_t devices;
  509.         struct radeon_i2c_chan *ddc_bus;
  510.         /* some systems have an hdmi and vga port with a shared ddc line */
  511.         bool shared_ddc;
  512.         bool use_digital;
  513.         /* we need to mind the EDID between detect
  514.            and get modes due to analog/digital/tvencoder */
  515.         struct edid *edid;
  516.         void *con_priv;
  517.         bool dac_load_detect;
  518.         bool detected_by_load; /* if the connection status was determined by load */
  519.         uint16_t connector_object_id;
  520.         struct radeon_hpd hpd;
  521.         struct radeon_router router;
  522.         struct radeon_i2c_chan *router_bus;
  523.         enum radeon_connector_audio audio;
  524.         enum radeon_connector_dither dither;
  525.         int pixelclock_for_modeset;
  526. };
  527.  
  528. struct radeon_framebuffer {
  529.    struct drm_framebuffer base;
  530.    struct drm_gem_object *obj;
  531. };
  532.  
  533. #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
  534.                                 ((em) == ATOM_ENCODER_MODE_DP_MST))
  535.  
  536. struct atom_clock_dividers {
  537.         u32 post_div;
  538.         union {
  539.                 struct {
  540. #ifdef __BIG_ENDIAN
  541.                         u32 reserved : 6;
  542.                         u32 whole_fb_div : 12;
  543.                         u32 frac_fb_div : 14;
  544. #else
  545.                         u32 frac_fb_div : 14;
  546.                         u32 whole_fb_div : 12;
  547.                         u32 reserved : 6;
  548. #endif
  549.                 };
  550.                 u32 fb_div;
  551.         };
  552.         u32 ref_div;
  553.         bool enable_post_div;
  554.         bool enable_dithen;
  555.         u32 vco_mode;
  556.         u32 real_clock;
  557.         /* added for CI */
  558.         u32 post_divider;
  559.         u32 flags;
  560. };
  561.  
  562. struct atom_mpll_param {
  563.         union {
  564.                 struct {
  565. #ifdef __BIG_ENDIAN
  566.                         u32 reserved : 8;
  567.                         u32 clkfrac : 12;
  568.                         u32 clkf : 12;
  569. #else
  570.                         u32 clkf : 12;
  571.                         u32 clkfrac : 12;
  572.                         u32 reserved : 8;
  573. #endif
  574.                 };
  575.                 u32 fb_div;
  576.         };
  577.         u32 post_div;
  578.         u32 bwcntl;
  579.         u32 dll_speed;
  580.         u32 vco_mode;
  581.         u32 yclk_sel;
  582.         u32 qdr;
  583.         u32 half_rate;
  584. };
  585.  
  586. #define MEM_TYPE_GDDR5  0x50
  587. #define MEM_TYPE_GDDR4  0x40
  588. #define MEM_TYPE_GDDR3  0x30
  589. #define MEM_TYPE_DDR2   0x20
  590. #define MEM_TYPE_GDDR1  0x10
  591. #define MEM_TYPE_DDR3   0xb0
  592. #define MEM_TYPE_MASK   0xf0
  593.  
  594. struct atom_memory_info {
  595.         u8 mem_vendor;
  596.         u8 mem_type;
  597. };
  598.  
  599. #define MAX_AC_TIMING_ENTRIES 16
  600.  
  601. struct atom_memory_clock_range_table
  602. {
  603.         u8 num_entries;
  604.         u8 rsv[3];
  605.         u32 mclk[MAX_AC_TIMING_ENTRIES];
  606. };
  607.  
  608. #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
  609. #define VBIOS_MAX_AC_TIMING_ENTRIES 20
  610.  
  611. struct atom_mc_reg_entry {
  612.         u32 mclk_max;
  613.         u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
  614. };
  615.  
  616. struct atom_mc_register_address {
  617.         u16 s1;
  618.         u8 pre_reg_data;
  619. };
  620.  
  621. struct atom_mc_reg_table {
  622.         u8 last;
  623.         u8 num_entries;
  624.         struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
  625.         struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
  626. };
  627.  
  628. #define MAX_VOLTAGE_ENTRIES 32
  629.  
  630. struct atom_voltage_table_entry
  631. {
  632.         u16 value;
  633.         u32 smio_low;
  634. };
  635.  
  636. struct atom_voltage_table
  637. {
  638.         u32 count;
  639.         u32 mask_low;
  640.         u32 phase_delay;
  641.         struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
  642. };
  643.  
  644.  
  645. extern void
  646. radeon_add_atom_connector(struct drm_device *dev,
  647.                           uint32_t connector_id,
  648.                           uint32_t supported_device,
  649.                           int connector_type,
  650.                           struct radeon_i2c_bus_rec *i2c_bus,
  651.                           uint32_t igp_lane_info,
  652.                           uint16_t connector_object_id,
  653.                           struct radeon_hpd *hpd,
  654.                           struct radeon_router *router);
  655. extern void
  656. radeon_add_legacy_connector(struct drm_device *dev,
  657.                             uint32_t connector_id,
  658.                             uint32_t supported_device,
  659.                             int connector_type,
  660.                             struct radeon_i2c_bus_rec *i2c_bus,
  661.                             uint16_t connector_object_id,
  662.                             struct radeon_hpd *hpd);
  663. extern uint32_t
  664. radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  665.                         uint8_t dac);
  666. extern void radeon_link_encoder_connector(struct drm_device *dev);
  667.  
  668. extern enum radeon_tv_std
  669. radeon_combios_get_tv_info(struct radeon_device *rdev);
  670. extern enum radeon_tv_std
  671. radeon_atombios_get_tv_info(struct radeon_device *rdev);
  672. extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
  673.                                                  u16 *vddc, u16 *vddci, u16 *mvdd);
  674.  
  675. extern void
  676. radeon_combios_connected_scratch_regs(struct drm_connector *connector,
  677.                                       struct drm_encoder *encoder,
  678.                                       bool connected);
  679. extern void
  680. radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
  681.                                        struct drm_encoder *encoder,
  682.                                        bool connected);
  683.  
  684. extern struct drm_connector *
  685. radeon_get_connector_for_encoder(struct drm_encoder *encoder);
  686. extern struct drm_connector *
  687. radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
  688. extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
  689.                                     u32 pixel_clock);
  690.  
  691. extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
  692. extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
  693. extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
  694. extern int radeon_get_monitor_bpc(struct drm_connector *connector);
  695.  
  696. extern struct edid *radeon_connector_edid(struct drm_connector *connector);
  697.  
  698. extern void radeon_connector_hotplug(struct drm_connector *connector);
  699. extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
  700.                                        struct drm_display_mode *mode);
  701. extern void radeon_dp_set_link_config(struct drm_connector *connector,
  702.                                       const struct drm_display_mode *mode);
  703. extern void radeon_dp_link_train(struct drm_encoder *encoder,
  704.                           struct drm_connector *connector);
  705. extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
  706. extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
  707. extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
  708. extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
  709.                                     struct drm_connector *connector);
  710. extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
  711.                                          u8 power_state);
  712. extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
  713. extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
  714. extern void radeon_atom_encoder_init(struct radeon_device *rdev);
  715. extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
  716. extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
  717.                                            int action, uint8_t lane_num,
  718.                                            uint8_t lane_set);
  719. extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
  720. extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
  721. void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
  722.  
  723. extern void radeon_i2c_init(struct radeon_device *rdev);
  724. extern void radeon_i2c_fini(struct radeon_device *rdev);
  725. extern void radeon_combios_i2c_init(struct radeon_device *rdev);
  726. extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
  727. extern void radeon_i2c_add(struct radeon_device *rdev,
  728.                            struct radeon_i2c_bus_rec *rec,
  729.                            const char *name);
  730. extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
  731.                                                  struct radeon_i2c_bus_rec *i2c_bus);
  732. extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
  733.                                                  struct radeon_i2c_bus_rec *rec,
  734.                                                  const char *name);
  735. extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
  736. extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
  737.                                    u8 slave_addr,
  738.                                    u8 addr,
  739.                                    u8 *val);
  740. extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
  741.                                    u8 slave_addr,
  742.                                    u8 addr,
  743.                                    u8 val);
  744. extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
  745. extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
  746. extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
  747.  
  748. extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
  749.  
  750. extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
  751.                                              struct radeon_atom_ss *ss,
  752.                                              int id);
  753. extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
  754.                                              struct radeon_atom_ss *ss,
  755.                                              int id, u32 clock);
  756. extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
  757.                                                           u8 id);
  758.  
  759. extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
  760.                                uint64_t freq,
  761.                                uint32_t *dot_clock_p,
  762.                                uint32_t *fb_div_p,
  763.                                uint32_t *frac_fb_div_p,
  764.                                uint32_t *ref_div_p,
  765.                                uint32_t *post_div_p);
  766.  
  767. extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
  768.                                      u32 freq,
  769.                                      u32 *dot_clock_p,
  770.                                      u32 *fb_div_p,
  771.                                      u32 *frac_fb_div_p,
  772.                                      u32 *ref_div_p,
  773.                                      u32 *post_div_p);
  774.  
  775. extern void radeon_setup_encoder_clones(struct drm_device *dev);
  776.  
  777. struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
  778. struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
  779. struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
  780. struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
  781. struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
  782. extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
  783. extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
  784. extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
  785. extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
  786. extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
  787. extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
  788.  
  789. extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
  790. extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
  791.                   struct drm_framebuffer *old_fb);
  792. extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
  793.                                          struct drm_framebuffer *fb,
  794.                                          int x, int y,
  795.                                          enum mode_set_atomic state);
  796. extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
  797.                                    struct drm_display_mode *mode,
  798.                                    struct drm_display_mode *adjusted_mode,
  799.                                    int x, int y,
  800.                                    struct drm_framebuffer *old_fb);
  801. extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
  802.  
  803. extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
  804.                                  struct drm_framebuffer *old_fb);
  805. extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
  806.                                        struct drm_framebuffer *fb,
  807.                                        int x, int y,
  808.                                        enum mode_set_atomic state);
  809. extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
  810.                                    struct drm_framebuffer *fb,
  811.                                    int x, int y, int atomic);
  812. extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
  813.                                   struct drm_file *file_priv,
  814.                                   uint32_t handle,
  815.                                   uint32_t width,
  816.                                    uint32_t height,
  817.                                    int32_t hot_x,
  818.                                    int32_t hot_y);
  819. extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
  820.                                    int x, int y);
  821. extern void radeon_cursor_reset(struct drm_crtc *crtc);
  822.  
  823. extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
  824.                                       unsigned int flags,
  825.                                       int *vpos, int *hpos, void *stime,
  826.                                       void *etime);
  827.  
  828. extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
  829. extern struct edid *
  830. radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
  831. extern bool radeon_atom_get_clock_info(struct drm_device *dev);
  832. extern bool radeon_combios_get_clock_info(struct drm_device *dev);
  833. extern struct radeon_encoder_atom_dig *
  834. radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
  835. extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
  836.                                    struct radeon_encoder_int_tmds *tmds);
  837. extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
  838.                                            struct radeon_encoder_int_tmds *tmds);
  839. extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
  840.                                             struct radeon_encoder_int_tmds *tmds);
  841. extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
  842.                                                          struct radeon_encoder_ext_tmds *tmds);
  843. extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
  844.                                                        struct radeon_encoder_ext_tmds *tmds);
  845. extern struct radeon_encoder_primary_dac *
  846. radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
  847. extern struct radeon_encoder_tv_dac *
  848. radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
  849. extern struct radeon_encoder_lvds *
  850. radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
  851. extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
  852. extern struct radeon_encoder_tv_dac *
  853. radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
  854. extern struct radeon_encoder_primary_dac *
  855. radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
  856. extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
  857. extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
  858. extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
  859. extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
  860. extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
  861. extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
  862. extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
  863. extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
  864. extern void
  865. radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
  866. extern void
  867. radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
  868. extern void
  869. radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
  870. extern void
  871. radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
  872. extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  873.                                      u16 blue, int regno);
  874. extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  875.                                      u16 *blue, int regno);
  876. int radeon_framebuffer_init(struct drm_device *dev,
  877.                              struct radeon_framebuffer *rfb,
  878.                              struct drm_mode_fb_cmd2 *mode_cmd,
  879.                                                   struct drm_gem_object *obj);
  880.  
  881. int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
  882. bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
  883. bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
  884. void radeon_atombios_init_crtc(struct drm_device *dev,
  885.                                struct radeon_crtc *radeon_crtc);
  886. void radeon_legacy_init_crtc(struct drm_device *dev,
  887.                              struct radeon_crtc *radeon_crtc);
  888.  
  889. void radeon_get_clock_info(struct drm_device *dev);
  890.  
  891. extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
  892. extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
  893.  
  894. void radeon_enc_destroy(struct drm_encoder *encoder);
  895. void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
  896. void radeon_combios_asic_init(struct drm_device *dev);
  897. bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
  898.                                         const struct drm_display_mode *mode,
  899.                                         struct drm_display_mode *adjusted_mode);
  900. void radeon_panel_mode_fixup(struct drm_encoder *encoder,
  901.                              struct drm_display_mode *adjusted_mode);
  902. void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
  903.  
  904. /* legacy tv */
  905. void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
  906.                                       uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
  907.                                       uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
  908. void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
  909.                                   uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
  910.                                   uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
  911. void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
  912.                                   uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
  913.                                   uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
  914. void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
  915.                                struct drm_display_mode *mode,
  916.                                struct drm_display_mode *adjusted_mode);
  917.  
  918. /* fmt blocks */
  919. void avivo_program_fmt(struct drm_encoder *encoder);
  920. void dce3_program_fmt(struct drm_encoder *encoder);
  921. void dce4_program_fmt(struct drm_encoder *encoder);
  922. void dce8_program_fmt(struct drm_encoder *encoder);
  923.  
  924. /* fbdev layer */
  925. int radeon_fbdev_init(struct radeon_device *rdev);
  926. void radeon_fbdev_fini(struct radeon_device *rdev);
  927. void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
  928. int radeon_fbdev_total_size(struct radeon_device *rdev);
  929. bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
  930.  
  931. void radeon_fb_output_poll_changed(struct radeon_device *rdev);
  932.  
  933. void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
  934. void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
  935.  
  936. int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
  937. #endif
  938.