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  1. /*
  2.  * Copyright 2007-8 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the "Software"),
  7.  * to deal in the Software without restriction, including without limitation
  8.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9.  * and/or sell copies of the Software, and to permit persons to whom the
  10.  * Software is furnished to do so, subject to the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice shall be included in
  13.  * all copies or substantial portions of the Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21.  * OTHER DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors: Dave Airlie
  24.  *          Alex Deucher
  25.  */
  26. #include "drmP.h"
  27. #include "drm_crtc_helper.h"
  28. #include "radeon_drm.h"
  29. #include "radeon.h"
  30. #include "atom.h"
  31.  
  32. static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  33. {
  34.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  35.         struct drm_encoder_helper_funcs *encoder_funcs;
  36.  
  37.         encoder_funcs = encoder->helper_private;
  38.         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  39.         radeon_encoder->active_device = 0;
  40. }
  41.  
  42. static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
  43. {
  44.         struct drm_device *dev = encoder->dev;
  45.         struct radeon_device *rdev = dev->dev_private;
  46.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  47.         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  48.         int panel_pwr_delay = 2000;
  49.         DRM_DEBUG("\n");
  50.  
  51.         if (radeon_encoder->enc_priv) {
  52.                 if (rdev->is_atom_bios) {
  53.                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  54.                         panel_pwr_delay = lvds->panel_pwr_delay;
  55.                 } else {
  56.                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  57.                         panel_pwr_delay = lvds->panel_pwr_delay;
  58.                 }
  59.         }
  60.  
  61.         switch (mode) {
  62.         case DRM_MODE_DPMS_ON:
  63.                 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  64.                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  65.                 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  66.                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  67.                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  68.                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  69.                 udelay(1000);
  70.  
  71.                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  72.                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  73.                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  74.  
  75.                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  76.                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
  77.                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
  78.                 udelay(panel_pwr_delay * 1000);
  79.                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  80.                 break;
  81.         case DRM_MODE_DPMS_STANDBY:
  82.         case DRM_MODE_DPMS_SUSPEND:
  83.         case DRM_MODE_DPMS_OFF:
  84.                 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  85.                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
  86.                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  87.                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  88.                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
  89.                 udelay(panel_pwr_delay * 1000);
  90.                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  91.                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  92.                 break;
  93.         }
  94.  
  95.         if (rdev->is_atom_bios)
  96.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  97.         else
  98.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  99. }
  100.  
  101. static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
  102. {
  103.         struct radeon_device *rdev = encoder->dev->dev_private;
  104.  
  105.         if (rdev->is_atom_bios)
  106.                 radeon_atom_output_lock(encoder, true);
  107.         else
  108.                 radeon_combios_output_lock(encoder, true);
  109.         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
  110. }
  111.  
  112. static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
  113. {
  114.         struct radeon_device *rdev = encoder->dev->dev_private;
  115.  
  116.         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
  117.         if (rdev->is_atom_bios)
  118.                 radeon_atom_output_lock(encoder, false);
  119.         else
  120.                 radeon_combios_output_lock(encoder, false);
  121. }
  122.  
  123. static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
  124.                                         struct drm_display_mode *mode,
  125.                                         struct drm_display_mode *adjusted_mode)
  126. {
  127.         struct drm_device *dev = encoder->dev;
  128.         struct radeon_device *rdev = dev->dev_private;
  129.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  130.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  131.         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
  132.  
  133.         DRM_DEBUG("\n");
  134.  
  135.         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  136.         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
  137.  
  138.         lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
  139.         if (rdev->is_atom_bios) {
  140.                 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
  141.                  * need to call that on resume to set up the reg properly.
  142.                  */
  143.                 radeon_encoder->pixel_clock = adjusted_mode->clock;
  144.                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
  145.                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  146.         } else {
  147.                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
  148.                 if (lvds) {
  149.                         DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
  150.                         lvds_gen_cntl = lvds->lvds_gen_cntl;
  151.                         lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
  152.                                               (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
  153.                         lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
  154.                                              (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
  155.                 } else
  156.                         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  157.         }
  158.         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  159.         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
  160.                            RADEON_LVDS_BLON |
  161.                            RADEON_LVDS_EN |
  162.                            RADEON_LVDS_RST_FM);
  163.  
  164.         if (ASIC_IS_R300(rdev))
  165.                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
  166.  
  167.         if (radeon_crtc->crtc_id == 0) {
  168.                 if (ASIC_IS_R300(rdev)) {
  169.                         if (radeon_encoder->rmx_type != RMX_OFF)
  170.                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
  171.                 } else
  172.                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
  173.         } else {
  174.                 if (ASIC_IS_R300(rdev))
  175.                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
  176.                 else
  177.                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
  178.         }
  179.  
  180.         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  181.         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  182.         WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
  183.  
  184.         if (rdev->family == CHIP_RV410)
  185.                 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
  186.  
  187.         if (rdev->is_atom_bios)
  188.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  189.         else
  190.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  191. }
  192.  
  193. static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
  194.                                           struct drm_display_mode *mode,
  195.                                           struct drm_display_mode *adjusted_mode)
  196. {
  197.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  198.  
  199.         /* set the active encoder to connector routing */
  200.         radeon_encoder_set_active_device(encoder);
  201.         drm_mode_set_crtcinfo(adjusted_mode, 0);
  202.  
  203.         /* get the native mode for LVDS */
  204.         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
  205.                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
  206.                 int mode_id = adjusted_mode->base.id;
  207.                 *adjusted_mode = *native_mode;
  208.                 adjusted_mode->hdisplay = mode->hdisplay;
  209.                 adjusted_mode->vdisplay = mode->vdisplay;
  210.                 adjusted_mode->base.id = mode_id;
  211.         }
  212.  
  213.         return true;
  214. }
  215.  
  216. static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
  217.         .dpms = radeon_legacy_lvds_dpms,
  218.         .mode_fixup = radeon_legacy_mode_fixup,
  219.         .prepare = radeon_legacy_lvds_prepare,
  220.         .mode_set = radeon_legacy_lvds_mode_set,
  221.         .commit = radeon_legacy_lvds_commit,
  222.         .disable = radeon_legacy_encoder_disable,
  223. };
  224.  
  225.  
  226. static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
  227.         .destroy = radeon_enc_destroy,
  228. };
  229.  
  230. static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
  231. {
  232.         struct drm_device *dev = encoder->dev;
  233.         struct radeon_device *rdev = dev->dev_private;
  234.         uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  235.         uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
  236.         uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  237.  
  238.         DRM_DEBUG("\n");
  239.  
  240.         switch (mode) {
  241.         case DRM_MODE_DPMS_ON:
  242.                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
  243.                 dac_cntl &= ~RADEON_DAC_PDWN;
  244.                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
  245.                                     RADEON_DAC_PDWN_G |
  246.                                     RADEON_DAC_PDWN_B);
  247.                 break;
  248.         case DRM_MODE_DPMS_STANDBY:
  249.         case DRM_MODE_DPMS_SUSPEND:
  250.         case DRM_MODE_DPMS_OFF:
  251.                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
  252.                 dac_cntl |= RADEON_DAC_PDWN;
  253.                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
  254.                                    RADEON_DAC_PDWN_G |
  255.                                    RADEON_DAC_PDWN_B);
  256.                 break;
  257.         }
  258.  
  259.         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  260.         WREG32(RADEON_DAC_CNTL, dac_cntl);
  261.         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  262.  
  263.         if (rdev->is_atom_bios)
  264.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  265.         else
  266.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  267. }
  268.  
  269. static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
  270. {
  271.         struct radeon_device *rdev = encoder->dev->dev_private;
  272.  
  273.         if (rdev->is_atom_bios)
  274.                 radeon_atom_output_lock(encoder, true);
  275.         else
  276.                 radeon_combios_output_lock(encoder, true);
  277.         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
  278. }
  279.  
  280. static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
  281. {
  282.         struct radeon_device *rdev = encoder->dev->dev_private;
  283.  
  284.         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
  285.  
  286.         if (rdev->is_atom_bios)
  287.                 radeon_atom_output_lock(encoder, false);
  288.         else
  289.                 radeon_combios_output_lock(encoder, false);
  290. }
  291.  
  292. static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
  293.                                                struct drm_display_mode *mode,
  294.                                                struct drm_display_mode *adjusted_mode)
  295. {
  296.         struct drm_device *dev = encoder->dev;
  297.         struct radeon_device *rdev = dev->dev_private;
  298.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  299.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  300.         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
  301.  
  302.         DRM_DEBUG("\n");
  303.  
  304.         if (radeon_crtc->crtc_id == 0) {
  305.                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
  306.                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
  307.                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
  308.                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  309.                 } else {
  310.                         dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
  311.                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  312.                 }
  313.         } else {
  314.                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
  315.                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
  316.                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
  317.                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
  318.                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  319.                 } else {
  320.                         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
  321.                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  322.                 }
  323.         }
  324.  
  325.         dac_cntl = (RADEON_DAC_MASK_ALL |
  326.                     RADEON_DAC_VGA_ADR_EN |
  327.                     /* TODO 6-bits */
  328.                     RADEON_DAC_8BIT_EN);
  329.  
  330.         WREG32_P(RADEON_DAC_CNTL,
  331.                        dac_cntl,
  332.                        RADEON_DAC_RANGE_CNTL |
  333.                        RADEON_DAC_BLANKING);
  334.  
  335.         if (radeon_encoder->enc_priv) {
  336.                 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
  337.                 dac_macro_cntl = p_dac->ps2_pdac_adj;
  338.         } else
  339.                 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  340.         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
  341.         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  342.  
  343.         if (rdev->is_atom_bios)
  344.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  345.         else
  346.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  347. }
  348.  
  349. static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
  350.                                                                   struct drm_connector *connector)
  351. {
  352.         struct drm_device *dev = encoder->dev;
  353.         struct radeon_device *rdev = dev->dev_private;
  354.         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
  355.         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
  356.         enum drm_connector_status found = connector_status_disconnected;
  357.         bool color = true;
  358.  
  359.         /* save the regs we need */
  360.         vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
  361.         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  362.         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  363.         dac_cntl = RREG32(RADEON_DAC_CNTL);
  364.         dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  365.  
  366.         tmp = vclk_ecp_cntl &
  367.                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
  368.         WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
  369.  
  370.         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
  371.         WREG32(RADEON_CRTC_EXT_CNTL, tmp);
  372.  
  373.         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
  374.                 RADEON_DAC_FORCE_DATA_EN;
  375.  
  376.         if (color)
  377.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
  378.         else
  379.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
  380.  
  381.         if (ASIC_IS_R300(rdev))
  382.                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
  383.         else
  384.                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
  385.  
  386.         WREG32(RADEON_DAC_EXT_CNTL, tmp);
  387.  
  388.         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
  389.         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
  390.         WREG32(RADEON_DAC_CNTL, tmp);
  391.  
  392.         tmp &= ~(RADEON_DAC_PDWN_R |
  393.                  RADEON_DAC_PDWN_G |
  394.                  RADEON_DAC_PDWN_B);
  395.  
  396.         WREG32(RADEON_DAC_MACRO_CNTL, tmp);
  397.  
  398.         udelay(2000);
  399.  
  400.         if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
  401.                 found = connector_status_connected;
  402.  
  403.         /* restore the regs we used */
  404.         WREG32(RADEON_DAC_CNTL, dac_cntl);
  405.         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  406.         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  407.         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  408.         WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
  409.  
  410.         return found;
  411. }
  412.  
  413. static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
  414.         .dpms = radeon_legacy_primary_dac_dpms,
  415.         .mode_fixup = radeon_legacy_mode_fixup,
  416.         .prepare = radeon_legacy_primary_dac_prepare,
  417.         .mode_set = radeon_legacy_primary_dac_mode_set,
  418.         .commit = radeon_legacy_primary_dac_commit,
  419.         .detect = radeon_legacy_primary_dac_detect,
  420.         .disable = radeon_legacy_encoder_disable,
  421. };
  422.  
  423.  
  424. static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
  425.         .destroy = radeon_enc_destroy,
  426. };
  427.  
  428. static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
  429. {
  430.         struct drm_device *dev = encoder->dev;
  431.         struct radeon_device *rdev = dev->dev_private;
  432.         uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
  433.         DRM_DEBUG("\n");
  434.  
  435.         switch (mode) {
  436.         case DRM_MODE_DPMS_ON:
  437.                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  438.                 break;
  439.         case DRM_MODE_DPMS_STANDBY:
  440.         case DRM_MODE_DPMS_SUSPEND:
  441.         case DRM_MODE_DPMS_OFF:
  442.                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  443.                 break;
  444.         }
  445.  
  446.         WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
  447.  
  448.         if (rdev->is_atom_bios)
  449.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  450.         else
  451.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  452. }
  453.  
  454. static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
  455. {
  456.         struct radeon_device *rdev = encoder->dev->dev_private;
  457.  
  458.         if (rdev->is_atom_bios)
  459.                 radeon_atom_output_lock(encoder, true);
  460.         else
  461.                 radeon_combios_output_lock(encoder, true);
  462.         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
  463. }
  464.  
  465. static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
  466. {
  467.         struct radeon_device *rdev = encoder->dev->dev_private;
  468.  
  469.         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
  470.  
  471.         if (rdev->is_atom_bios)
  472.                 radeon_atom_output_lock(encoder, true);
  473.         else
  474.                 radeon_combios_output_lock(encoder, true);
  475. }
  476.  
  477. static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
  478.                                             struct drm_display_mode *mode,
  479.                                             struct drm_display_mode *adjusted_mode)
  480. {
  481.         struct drm_device *dev = encoder->dev;
  482.         struct radeon_device *rdev = dev->dev_private;
  483.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  484.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  485.         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
  486.         int i;
  487.  
  488.         DRM_DEBUG("\n");
  489.  
  490.         tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
  491.         tmp &= 0xfffff;
  492.         if (rdev->family == CHIP_RV280) {
  493.                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
  494.                 tmp ^= (1 << 22);
  495.                 tmds_pll_cntl ^= (1 << 22);
  496.         }
  497.  
  498.         if (radeon_encoder->enc_priv) {
  499.                 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
  500.  
  501.                 for (i = 0; i < 4; i++) {
  502.                         if (tmds->tmds_pll[i].freq == 0)
  503.                                 break;
  504.                         if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
  505.                                 tmp = tmds->tmds_pll[i].value ;
  506.                                 break;
  507.                         }
  508.                 }
  509.         }
  510.  
  511.         if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
  512.                 if (tmp & 0xfff00000)
  513.                         tmds_pll_cntl = tmp;
  514.                 else {
  515.                         tmds_pll_cntl &= 0xfff00000;
  516.                         tmds_pll_cntl |= tmp;
  517.                 }
  518.         } else
  519.                 tmds_pll_cntl = tmp;
  520.  
  521.         tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
  522.                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
  523.  
  524.     if (rdev->family == CHIP_R200 ||
  525.         rdev->family == CHIP_R100 ||
  526.         ASIC_IS_R300(rdev))
  527.             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
  528.     else /* RV chips got this bit reversed */
  529.             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
  530.  
  531.     fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
  532.                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
  533.                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
  534.  
  535.     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  536.  
  537.     fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
  538.                      RADEON_FP_DFP_SYNC_SEL |
  539.                      RADEON_FP_CRT_SYNC_SEL |
  540.                      RADEON_FP_CRTC_LOCK_8DOT |
  541.                      RADEON_FP_USE_SHADOW_EN |
  542.                      RADEON_FP_CRTC_USE_SHADOW_VEND |
  543.                      RADEON_FP_CRT_SYNC_ALT);
  544.  
  545.     if (1) /*  FIXME rgbBits == 8 */
  546.             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
  547.     else
  548.             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
  549.  
  550.     if (radeon_crtc->crtc_id == 0) {
  551.             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
  552.                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
  553.                     if (radeon_encoder->rmx_type != RMX_OFF)
  554.                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
  555.                     else
  556.                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
  557.             } else
  558.                     fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
  559.     } else {
  560.             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
  561.                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
  562.                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
  563.             } else
  564.                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
  565.     }
  566.  
  567.     WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
  568.     WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
  569.     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
  570.  
  571.         if (rdev->is_atom_bios)
  572.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  573.         else
  574.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  575. }
  576.  
  577. static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
  578.         .dpms = radeon_legacy_tmds_int_dpms,
  579.         .mode_fixup = radeon_legacy_mode_fixup,
  580.         .prepare = radeon_legacy_tmds_int_prepare,
  581.         .mode_set = radeon_legacy_tmds_int_mode_set,
  582.         .commit = radeon_legacy_tmds_int_commit,
  583.         .disable = radeon_legacy_encoder_disable,
  584. };
  585.  
  586.  
  587. static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
  588.         .destroy = radeon_enc_destroy,
  589. };
  590.  
  591. static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
  592. {
  593.         struct drm_device *dev = encoder->dev;
  594.         struct radeon_device *rdev = dev->dev_private;
  595.         uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  596.         DRM_DEBUG("\n");
  597.  
  598.         switch (mode) {
  599.         case DRM_MODE_DPMS_ON:
  600.                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
  601.                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  602.                 break;
  603.         case DRM_MODE_DPMS_STANDBY:
  604.         case DRM_MODE_DPMS_SUSPEND:
  605.         case DRM_MODE_DPMS_OFF:
  606.                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
  607.                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  608.                 break;
  609.         }
  610.  
  611.         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  612.  
  613.         if (rdev->is_atom_bios)
  614.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  615.         else
  616.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  617. }
  618.  
  619. static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
  620. {
  621.         struct radeon_device *rdev = encoder->dev->dev_private;
  622.  
  623.         if (rdev->is_atom_bios)
  624.                 radeon_atom_output_lock(encoder, true);
  625.         else
  626.                 radeon_combios_output_lock(encoder, true);
  627.         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
  628. }
  629.  
  630. static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
  631. {
  632.         struct radeon_device *rdev = encoder->dev->dev_private;
  633.         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
  634.  
  635.         if (rdev->is_atom_bios)
  636.                 radeon_atom_output_lock(encoder, false);
  637.         else
  638.                 radeon_combios_output_lock(encoder, false);
  639. }
  640.  
  641. static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
  642.                                             struct drm_display_mode *mode,
  643.                                             struct drm_display_mode *adjusted_mode)
  644. {
  645.         struct drm_device *dev = encoder->dev;
  646.         struct radeon_device *rdev = dev->dev_private;
  647.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  648.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  649.         uint32_t fp2_gen_cntl;
  650.  
  651.         DRM_DEBUG("\n");
  652.  
  653.         if (rdev->is_atom_bios) {
  654.                 radeon_encoder->pixel_clock = adjusted_mode->clock;
  655.                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
  656.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  657.         } else {
  658.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  659.  
  660.                 if (1) /*  FIXME rgbBits == 8 */
  661.                         fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
  662.                 else
  663.                         fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
  664.  
  665.                 fp2_gen_cntl &= ~(RADEON_FP2_ON |
  666.                                   RADEON_FP2_DVO_EN |
  667.                                   RADEON_FP2_DVO_RATE_SEL_SDR);
  668.  
  669.                 /* XXX: these are oem specific */
  670.                 if (ASIC_IS_R300(rdev)) {
  671.                         if ((dev->pdev->device == 0x4850) &&
  672.                             (dev->pdev->subsystem_vendor == 0x1028) &&
  673.                             (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
  674.                                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
  675.                         else
  676.                                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
  677.  
  678.                         /*if (mode->clock > 165000)
  679.                           fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
  680.                 }
  681.                 if (!radeon_combios_external_tmds_setup(encoder))
  682.                         radeon_external_tmds_setup(encoder);
  683.         }
  684.  
  685.         if (radeon_crtc->crtc_id == 0) {
  686.                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
  687.                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
  688.                         if (radeon_encoder->rmx_type != RMX_OFF)
  689.                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
  690.                         else
  691.                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
  692.                 } else
  693.                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
  694.         } else {
  695.                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
  696.                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
  697.                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
  698.                 } else
  699.                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
  700.         }
  701.  
  702.         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  703.  
  704.         if (rdev->is_atom_bios)
  705.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  706.         else
  707.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  708. }
  709.  
  710. static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
  711. {
  712.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  713.         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
  714.         if (tmds) {
  715.                 if (tmds->i2c_bus)
  716.                         radeon_i2c_destroy(tmds->i2c_bus);
  717.         }
  718.         kfree(radeon_encoder->enc_priv);
  719.         drm_encoder_cleanup(encoder);
  720.         kfree(radeon_encoder);
  721. }
  722.  
  723. static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
  724.         .dpms = radeon_legacy_tmds_ext_dpms,
  725.         .mode_fixup = radeon_legacy_mode_fixup,
  726.         .prepare = radeon_legacy_tmds_ext_prepare,
  727.         .mode_set = radeon_legacy_tmds_ext_mode_set,
  728.         .commit = radeon_legacy_tmds_ext_commit,
  729.         .disable = radeon_legacy_encoder_disable,
  730. };
  731.  
  732.  
  733. static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
  734.         .destroy = radeon_ext_tmds_enc_destroy,
  735. };
  736.  
  737. static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
  738. {
  739.         struct drm_device *dev = encoder->dev;
  740.         struct radeon_device *rdev = dev->dev_private;
  741.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  742.         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
  743.         uint32_t tv_master_cntl = 0;
  744.         bool is_tv;
  745.         DRM_DEBUG("\n");
  746.  
  747.         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
  748.  
  749.         if (rdev->family == CHIP_R200)
  750.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  751.         else {
  752.                 if (is_tv)
  753.                         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
  754.                 else
  755.                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  756.                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  757.         }
  758.  
  759.         switch (mode) {
  760.         case DRM_MODE_DPMS_ON:
  761.                 if (rdev->family == CHIP_R200) {
  762.                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  763.                 } else {
  764.                         if (is_tv)
  765.                                 tv_master_cntl |= RADEON_TV_ON;
  766.                         else
  767.                         crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
  768.  
  769.                         if (rdev->family == CHIP_R420 ||
  770.                                         rdev->family == CHIP_R423 ||
  771.                                         rdev->family == CHIP_RV410)
  772.                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
  773.                                                 R420_TV_DAC_GDACPD |
  774.                                                 R420_TV_DAC_BDACPD |
  775.                                                 RADEON_TV_DAC_BGSLEEP);
  776.                         else
  777.                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
  778.                                                 RADEON_TV_DAC_GDACPD |
  779.                                                 RADEON_TV_DAC_BDACPD |
  780.                                                 RADEON_TV_DAC_BGSLEEP);
  781.                 }
  782.                 break;
  783.         case DRM_MODE_DPMS_STANDBY:
  784.         case DRM_MODE_DPMS_SUSPEND:
  785.         case DRM_MODE_DPMS_OFF:
  786.                 if (rdev->family == CHIP_R200)
  787.                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  788.                 else {
  789.                         if (is_tv)
  790.                                 tv_master_cntl &= ~RADEON_TV_ON;
  791.                         else
  792.                         crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
  793.  
  794.                         if (rdev->family == CHIP_R420 ||
  795.                                         rdev->family == CHIP_R423 ||
  796.                                         rdev->family == CHIP_RV410)
  797.                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
  798.                                                 R420_TV_DAC_GDACPD |
  799.                                                 R420_TV_DAC_BDACPD |
  800.                                                 RADEON_TV_DAC_BGSLEEP);
  801.                         else
  802.                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
  803.                                                 RADEON_TV_DAC_GDACPD |
  804.                                                 RADEON_TV_DAC_BDACPD |
  805.                                                 RADEON_TV_DAC_BGSLEEP);
  806.                 }
  807.                 break;
  808.         }
  809.  
  810.         if (rdev->family == CHIP_R200) {
  811.                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  812.         } else {
  813.                 if (is_tv)
  814.                         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
  815.                 else
  816.                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  817.                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  818.         }
  819.  
  820.         if (rdev->is_atom_bios)
  821.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  822.         else
  823.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  824. }
  825.  
  826. static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
  827. {
  828.         struct radeon_device *rdev = encoder->dev->dev_private;
  829.  
  830.         if (rdev->is_atom_bios)
  831.                 radeon_atom_output_lock(encoder, true);
  832.         else
  833.                 radeon_combios_output_lock(encoder, true);
  834.         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
  835. }
  836.  
  837. static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
  838. {
  839.         struct radeon_device *rdev = encoder->dev->dev_private;
  840.  
  841.         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
  842.  
  843.         if (rdev->is_atom_bios)
  844.                 radeon_atom_output_lock(encoder, true);
  845.         else
  846.                 radeon_combios_output_lock(encoder, true);
  847. }
  848.  
  849. static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
  850.                 struct drm_display_mode *mode,
  851.                 struct drm_display_mode *adjusted_mode)
  852. {
  853.         struct drm_device *dev = encoder->dev;
  854.         struct radeon_device *rdev = dev->dev_private;
  855.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  856.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  857.         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
  858.         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
  859.         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
  860.         bool is_tv = false;
  861.  
  862.         DRM_DEBUG("\n");
  863.  
  864.         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
  865.  
  866.         if (rdev->family != CHIP_R200) {
  867.                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  868.                 if (rdev->family == CHIP_R420 ||
  869.                                 rdev->family == CHIP_R423 ||
  870.                                 rdev->family == CHIP_RV410) {
  871.                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
  872.                                         RADEON_TV_DAC_BGADJ_MASK |
  873.                                         R420_TV_DAC_DACADJ_MASK |
  874.                                         R420_TV_DAC_RDACPD |
  875.                                         R420_TV_DAC_GDACPD |
  876.                                         R420_TV_DAC_BDACPD |
  877.                                         R420_TV_DAC_TVENABLE);
  878.                 } else {
  879.                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
  880.                                         RADEON_TV_DAC_BGADJ_MASK |
  881.                                         RADEON_TV_DAC_DACADJ_MASK |
  882.                                         RADEON_TV_DAC_RDACPD |
  883.                                         RADEON_TV_DAC_GDACPD |
  884.                                         RADEON_TV_DAC_BDACPD);
  885.                 }
  886.  
  887.                 /*  FIXME TV */
  888.                 if (tv_dac) {
  889.                         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
  890.                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
  891.                                         RADEON_TV_DAC_NHOLD |
  892.                                         RADEON_TV_DAC_STD_PS2 |
  893.                                         tv_dac->ps2_tvdac_adj);
  894.                 } else
  895.                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
  896.                                         RADEON_TV_DAC_NHOLD |
  897.                                         RADEON_TV_DAC_STD_PS2);
  898.  
  899.                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  900.         }
  901.  
  902.         if (ASIC_IS_R300(rdev)) {
  903.                 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
  904.                 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
  905.         }
  906.  
  907.         if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
  908.                 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
  909.         else
  910.                 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
  911.  
  912.         if (rdev->family == CHIP_R200)
  913.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  914.  
  915.         if (is_tv) {
  916.                 uint32_t dac_cntl;
  917.  
  918.                 dac_cntl = RREG32(RADEON_DAC_CNTL);
  919.                 dac_cntl &= ~RADEON_DAC_TVO_EN;
  920.                 WREG32(RADEON_DAC_CNTL, dac_cntl);
  921.  
  922.                 if (ASIC_IS_R300(rdev))
  923.                         gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
  924.  
  925.                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
  926.                 if (radeon_crtc->crtc_id == 0) {
  927.                         if (ASIC_IS_R300(rdev)) {
  928.                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  929.                                 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
  930.                                                      RADEON_DISP_TV_SOURCE_CRTC);
  931.                         }
  932.                         if (rdev->family >= CHIP_R200) {
  933.                                 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
  934.                         } else {
  935.                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
  936.                         }
  937.                 } else {
  938.                         if (ASIC_IS_R300(rdev)) {
  939.                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  940.                                 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
  941.                         }
  942.                         if (rdev->family >= CHIP_R200) {
  943.                                 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
  944.                         } else {
  945.                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
  946.                         }
  947.                 }
  948.                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  949.         } else {
  950.  
  951.         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
  952.  
  953.         if (radeon_crtc->crtc_id == 0) {
  954.                 if (ASIC_IS_R300(rdev)) {
  955.                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  956.                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
  957.                 } else if (rdev->family == CHIP_R200) {
  958.                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
  959.                                           RADEON_FP2_DVO_RATE_SEL_SDR);
  960.                 } else
  961.                         disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
  962.         } else {
  963.                 if (ASIC_IS_R300(rdev)) {
  964.                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  965.                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  966.                 } else if (rdev->family == CHIP_R200) {
  967.                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
  968.                                           RADEON_FP2_DVO_RATE_SEL_SDR);
  969.                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
  970.                 } else
  971.                         disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
  972.         }
  973.         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  974.         }
  975.  
  976.         if (ASIC_IS_R300(rdev)) {
  977.                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  978.                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  979.         }
  980.  
  981.         if (rdev->family >= CHIP_R200)
  982.                 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
  983.         else
  984.                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
  985.  
  986.         if (rdev->family == CHIP_R200)
  987.                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  988.  
  989.         if (is_tv)
  990.                 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
  991.  
  992.         if (rdev->is_atom_bios)
  993.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  994.         else
  995.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  996.  
  997. }
  998.  
  999. static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
  1000.                                   struct drm_connector *connector)
  1001. {
  1002.         struct drm_device *dev = encoder->dev;
  1003.         struct radeon_device *rdev = dev->dev_private;
  1004.         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
  1005.         uint32_t disp_output_cntl, gpiopad_a, tmp;
  1006.         bool found = false;
  1007.  
  1008.         /* save regs needed */
  1009.         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
  1010.         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1011.         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  1012.         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  1013.         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1014.         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
  1015.  
  1016.         WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
  1017.  
  1018.         WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
  1019.  
  1020.         WREG32(RADEON_CRTC2_GEN_CNTL,
  1021.                RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
  1022.  
  1023.         tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1024.         tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  1025.         WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
  1026.  
  1027.         WREG32(RADEON_DAC_EXT_CNTL,
  1028.                RADEON_DAC2_FORCE_BLANK_OFF_EN |
  1029.                RADEON_DAC2_FORCE_DATA_EN |
  1030.                RADEON_DAC_FORCE_DATA_SEL_RGB |
  1031.                (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
  1032.  
  1033.         WREG32(RADEON_TV_DAC_CNTL,
  1034.                RADEON_TV_DAC_STD_NTSC |
  1035.                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
  1036.                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
  1037.  
  1038.         RREG32(RADEON_TV_DAC_CNTL);
  1039.         mdelay(4);
  1040.  
  1041.         WREG32(RADEON_TV_DAC_CNTL,
  1042.                RADEON_TV_DAC_NBLANK |
  1043.                RADEON_TV_DAC_NHOLD |
  1044.                RADEON_TV_MONITOR_DETECT_EN |
  1045.                RADEON_TV_DAC_STD_NTSC |
  1046.                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
  1047.                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
  1048.  
  1049.         RREG32(RADEON_TV_DAC_CNTL);
  1050.         mdelay(6);
  1051.  
  1052.         tmp = RREG32(RADEON_TV_DAC_CNTL);
  1053.         if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
  1054.                 found = true;
  1055.                 DRM_DEBUG("S-video TV connection detected\n");
  1056.         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
  1057.                 found = true;
  1058.                 DRM_DEBUG("Composite TV connection detected\n");
  1059.         }
  1060.  
  1061.         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1062.         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  1063.         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  1064.         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  1065.         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1066.         WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  1067.         return found;
  1068. }
  1069.  
  1070. static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
  1071.                                     struct drm_connector *connector)
  1072. {
  1073.         struct drm_device *dev = encoder->dev;
  1074.         struct radeon_device *rdev = dev->dev_private;
  1075.         uint32_t tv_dac_cntl, dac_cntl2;
  1076.         uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
  1077.         bool found = false;
  1078.  
  1079.         if (ASIC_IS_R300(rdev))
  1080.                 return r300_legacy_tv_detect(encoder, connector);
  1081.  
  1082.         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1083.         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
  1084.         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1085.         config_cntl = RREG32(RADEON_CONFIG_CNTL);
  1086.         tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
  1087.  
  1088.         tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
  1089.         WREG32(RADEON_DAC_CNTL2, tmp);
  1090.  
  1091.         tmp = tv_master_cntl | RADEON_TV_ON;
  1092.         tmp &= ~(RADEON_TV_ASYNC_RST |
  1093.                  RADEON_RESTART_PHASE_FIX |
  1094.                  RADEON_CRT_FIFO_CE_EN |
  1095.                  RADEON_TV_FIFO_CE_EN |
  1096.                  RADEON_RE_SYNC_NOW_SEL_MASK);
  1097.         tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
  1098.         WREG32(RADEON_TV_MASTER_CNTL, tmp);
  1099.  
  1100.         tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
  1101.                 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
  1102.                 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
  1103.  
  1104.         if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
  1105.                 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
  1106.         else
  1107.                 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
  1108.         WREG32(RADEON_TV_DAC_CNTL, tmp);
  1109.  
  1110.         tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
  1111.                 RADEON_RED_MX_FORCE_DAC_DATA |
  1112.                 RADEON_GRN_MX_FORCE_DAC_DATA |
  1113.                 RADEON_BLU_MX_FORCE_DAC_DATA |
  1114.                 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
  1115.         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
  1116.  
  1117.         mdelay(3);
  1118.         tmp = RREG32(RADEON_TV_DAC_CNTL);
  1119.         if (tmp & RADEON_TV_DAC_GDACDET) {
  1120.                 found = true;
  1121.                 DRM_DEBUG("S-video TV connection detected\n");
  1122.         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
  1123.                 found = true;
  1124.                 DRM_DEBUG("Composite TV connection detected\n");
  1125.         }
  1126.  
  1127.         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
  1128.         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1129.         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
  1130.         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1131.         return found;
  1132. }
  1133.  
  1134. static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
  1135.                                                              struct drm_connector *connector)
  1136. {
  1137.         struct drm_device *dev = encoder->dev;
  1138.         struct radeon_device *rdev = dev->dev_private;
  1139.         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
  1140.         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
  1141.         enum drm_connector_status found = connector_status_disconnected;
  1142.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1143.         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
  1144.         bool color = true;
  1145.  
  1146.         if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
  1147.             connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
  1148.             connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
  1149.                 bool tv_detect;
  1150.  
  1151.                 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
  1152.                         return connector_status_disconnected;
  1153.  
  1154.                 tv_detect = radeon_legacy_tv_detect(encoder, connector);
  1155.                 if (tv_detect && tv_dac)
  1156.                         found = connector_status_connected;
  1157.                 return found;
  1158.         }
  1159.  
  1160.         /* don't probe if the encoder is being used for something else not CRT related */
  1161.         if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
  1162.                 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
  1163.                 return connector_status_disconnected;
  1164.         }
  1165.  
  1166.         /* save the regs we need */
  1167.         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  1168.         gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
  1169.         disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
  1170.         disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
  1171.         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  1172.         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1173.         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  1174.         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1175.  
  1176.         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
  1177.                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
  1178.         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
  1179.  
  1180.         if (ASIC_IS_R300(rdev))
  1181.                 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
  1182.  
  1183.         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
  1184.         tmp |= RADEON_CRTC2_CRT2_ON |
  1185.                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
  1186.  
  1187.         WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
  1188.  
  1189.         if (ASIC_IS_R300(rdev)) {
  1190.                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1191.                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  1192.                 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
  1193.         } else {
  1194.                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
  1195.                 WREG32(RADEON_DISP_HW_DEBUG, tmp);
  1196.         }
  1197.  
  1198.         tmp = RADEON_TV_DAC_NBLANK |
  1199.                 RADEON_TV_DAC_NHOLD |
  1200.                 RADEON_TV_MONITOR_DETECT_EN |
  1201.                 RADEON_TV_DAC_STD_PS2;
  1202.  
  1203.         WREG32(RADEON_TV_DAC_CNTL, tmp);
  1204.  
  1205.         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
  1206.                 RADEON_DAC2_FORCE_DATA_EN;
  1207.  
  1208.         if (color)
  1209.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
  1210.         else
  1211.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
  1212.  
  1213.         if (ASIC_IS_R300(rdev))
  1214.                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
  1215.         else
  1216.                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
  1217.  
  1218.         WREG32(RADEON_DAC_EXT_CNTL, tmp);
  1219.  
  1220.         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
  1221.         WREG32(RADEON_DAC_CNTL2, tmp);
  1222.  
  1223.         udelay(10000);
  1224.  
  1225.         if (ASIC_IS_R300(rdev)) {
  1226.                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
  1227.                         found = connector_status_connected;
  1228.         } else {
  1229.                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
  1230.                         found = connector_status_connected;
  1231.         }
  1232.  
  1233.         /* restore regs we used */
  1234.         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1235.         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  1236.         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1237.         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  1238.  
  1239.         if (ASIC_IS_R300(rdev)) {
  1240.                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  1241.                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  1242.         } else {
  1243.                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
  1244.         }
  1245.         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  1246.  
  1247.         return found;
  1248.  
  1249. }
  1250.  
  1251. static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
  1252.         .dpms = radeon_legacy_tv_dac_dpms,
  1253.         .mode_fixup = radeon_legacy_mode_fixup,
  1254.         .prepare = radeon_legacy_tv_dac_prepare,
  1255.         .mode_set = radeon_legacy_tv_dac_mode_set,
  1256.         .commit = radeon_legacy_tv_dac_commit,
  1257.         .detect = radeon_legacy_tv_dac_detect,
  1258.         .disable = radeon_legacy_encoder_disable,
  1259. };
  1260.  
  1261.  
  1262. static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
  1263.         .destroy = radeon_enc_destroy,
  1264. };
  1265.  
  1266.  
  1267. static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
  1268. {
  1269.         struct drm_device *dev = encoder->base.dev;
  1270.         struct radeon_device *rdev = dev->dev_private;
  1271.         struct radeon_encoder_int_tmds *tmds = NULL;
  1272.         bool ret;
  1273.  
  1274.         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
  1275.  
  1276.         if (!tmds)
  1277.                 return NULL;
  1278.  
  1279.         if (rdev->is_atom_bios)
  1280.                 ret = radeon_atombios_get_tmds_info(encoder, tmds);
  1281.         else
  1282.                 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
  1283.  
  1284.         if (ret == false)
  1285.                 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
  1286.  
  1287.         return tmds;
  1288. }
  1289.  
  1290. static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
  1291. {
  1292.         struct drm_device *dev = encoder->base.dev;
  1293.         struct radeon_device *rdev = dev->dev_private;
  1294.         struct radeon_encoder_ext_tmds *tmds = NULL;
  1295.         bool ret;
  1296.  
  1297.         if (rdev->is_atom_bios)
  1298.                 return NULL;
  1299.  
  1300.         tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
  1301.  
  1302.         if (!tmds)
  1303.                 return NULL;
  1304.  
  1305.         ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
  1306.  
  1307.         if (ret == false)
  1308.                 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
  1309.  
  1310.         return tmds;
  1311. }
  1312.  
  1313. void
  1314. radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
  1315. {
  1316.         struct radeon_device *rdev = dev->dev_private;
  1317.         struct drm_encoder *encoder;
  1318.         struct radeon_encoder *radeon_encoder;
  1319.  
  1320.         /* see if we already added it */
  1321.         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1322.                 radeon_encoder = to_radeon_encoder(encoder);
  1323.                 if (radeon_encoder->encoder_id == encoder_id) {
  1324.                         radeon_encoder->devices |= supported_device;
  1325.                         return;
  1326.                 }
  1327.  
  1328.         }
  1329.  
  1330.         /* add a new one */
  1331.         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
  1332.         if (!radeon_encoder)
  1333.                 return;
  1334.  
  1335.         encoder = &radeon_encoder->base;
  1336.         if (rdev->flags & RADEON_SINGLE_CRTC)
  1337.                 encoder->possible_crtcs = 0x1;
  1338.         else
  1339.         encoder->possible_crtcs = 0x3;
  1340.  
  1341.         radeon_encoder->enc_priv = NULL;
  1342.  
  1343.         radeon_encoder->encoder_id = encoder_id;
  1344.         radeon_encoder->devices = supported_device;
  1345.         radeon_encoder->rmx_type = RMX_OFF;
  1346.  
  1347.         switch (radeon_encoder->encoder_id) {
  1348.         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1349.                 encoder->possible_crtcs = 0x1;
  1350.                 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
  1351.                 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
  1352.                 if (rdev->is_atom_bios)
  1353.                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
  1354.                 else
  1355.                         radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
  1356.                 radeon_encoder->rmx_type = RMX_FULL;
  1357.                 break;
  1358.         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1359.                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
  1360.                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
  1361.                 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
  1362.                 break;
  1363.         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1364.                 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
  1365.                 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
  1366.                 if (rdev->is_atom_bios)
  1367.                         radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
  1368.                 else
  1369.                         radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
  1370.                 break;
  1371.         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1372.                 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
  1373.                 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
  1374.                 if (rdev->is_atom_bios)
  1375.                         radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
  1376.                 else
  1377.                         radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
  1378.                 break;
  1379.         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1380.                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
  1381.                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
  1382.                 if (!rdev->is_atom_bios)
  1383.                         radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
  1384.                 break;
  1385.         }
  1386. }
  1387.