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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include "drmP.h"
  29. #include "radeon_drm.h"
  30. #include "radeon.h"
  31. #include "radeon_reg.h"
  32.  
  33. /*
  34.  * Common GART table functions.
  35.  */
  36. int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
  37. {
  38.         void *ptr;
  39.  
  40.     ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
  41.                   &rdev->gart.table_addr);
  42.         if (ptr == NULL) {
  43.                 return -ENOMEM;
  44.         }
  45. #ifdef CONFIG_X86
  46.         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
  47.             rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  48.                 set_memory_uc((unsigned long)ptr,
  49.                               rdev->gart.table_size >> PAGE_SHIFT);
  50.         }
  51. #endif
  52.         rdev->gart.table.ram.ptr = ptr;
  53.         memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size);
  54.         return 0;
  55. }
  56.  
  57. void radeon_gart_table_ram_free(struct radeon_device *rdev)
  58. {
  59.         if (rdev->gart.table.ram.ptr == NULL) {
  60.                 return;
  61.         }
  62. #ifdef CONFIG_X86
  63.         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
  64.             rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  65.                 set_memory_wb((unsigned long)rdev->gart.table.ram.ptr,
  66.                               rdev->gart.table_size >> PAGE_SHIFT);
  67.         }
  68. #endif
  69. //   pci_free_consistent(rdev->pdev, rdev->gart.table_size,
  70. //               (void *)rdev->gart.table.ram.ptr,
  71. //               rdev->gart.table_addr);
  72.         rdev->gart.table.ram.ptr = NULL;
  73.         rdev->gart.table_addr = 0;
  74. }
  75.  
  76. int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
  77. {
  78.     int r;
  79.  
  80.     if (rdev->gart.table.vram.robj == NULL) {
  81.                 r = radeon_bo_create(rdev, NULL, rdev->gart.table_size,
  82.                                         true, RADEON_GEM_DOMAIN_VRAM,
  83.                                         &rdev->gart.table.vram.robj);
  84.         if (r) {
  85.             return r;
  86.         }
  87.     }
  88.         return 0;
  89. }
  90.  
  91. int radeon_gart_table_vram_pin(struct radeon_device *rdev)
  92. {
  93.         uint64_t gpu_addr;
  94.         int r;
  95.  
  96.         r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
  97.         if (unlikely(r != 0))
  98.                 return r;
  99.         r = radeon_bo_pin(rdev->gart.table.vram.robj,
  100.                   RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
  101.     if (r) {
  102.                 radeon_bo_unreserve(rdev->gart.table.vram.robj);
  103.         return r;
  104.     }
  105.         r = radeon_bo_kmap(rdev->gart.table.vram.robj,
  106.                    (void **)&rdev->gart.table.vram.ptr);
  107.         if (r)
  108.                 radeon_bo_unpin(rdev->gart.table.vram.robj);
  109.         radeon_bo_unreserve(rdev->gart.table.vram.robj);
  110.         rdev->gart.table_addr = gpu_addr;
  111.     return r;
  112. }
  113.  
  114. void radeon_gart_table_vram_free(struct radeon_device *rdev)
  115. {
  116.         int r;
  117.  
  118.         if (rdev->gart.table.vram.robj == NULL) {
  119.                 return;
  120.         }
  121.         r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
  122.         if (likely(r == 0)) {
  123.                 radeon_bo_kunmap(rdev->gart.table.vram.robj);
  124.                 radeon_bo_unpin(rdev->gart.table.vram.robj);
  125.                 radeon_bo_unreserve(rdev->gart.table.vram.robj);
  126.         }
  127.         radeon_bo_unref(&rdev->gart.table.vram.robj);
  128. }
  129.  
  130.  
  131.  
  132.  
  133. /*
  134.  * Common gart functions.
  135.  */
  136. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  137.                         int pages)
  138. {
  139.         unsigned t;
  140.         unsigned p;
  141.         int i, j;
  142.  
  143.         if (!rdev->gart.ready) {
  144.                 WARN(1, "trying to unbind memory to unitialized GART !\n");
  145.                 return;
  146.         }
  147.         t = offset / RADEON_GPU_PAGE_SIZE;
  148.         p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
  149.         for (i = 0; i < pages; i++, p++) {
  150.                 if (rdev->gart.pages[p]) {
  151. //           pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
  152. //                      PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  153.                         rdev->gart.pages[p] = NULL;
  154.                         rdev->gart.pages_addr[p] = 0;
  155.                         for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
  156.                                 radeon_gart_set_page(rdev, t, 0);
  157.                         }
  158.                 }
  159.         }
  160.         mb();
  161.         radeon_gart_tlb_flush(rdev);
  162. }
  163.  
  164. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  165.              int pages, u32_t *pagelist)
  166. {
  167.     unsigned t;
  168.     unsigned p;
  169.     uint64_t page_base;
  170.     int i, j;
  171.  
  172.     ENTER();
  173.  
  174.     dbgprintf("offset %x pages %x list %x\n",
  175.                offset, pages, pagelist);
  176.  
  177.     if (!rdev->gart.ready) {
  178.         DRM_ERROR("trying to bind memory to unitialized GART !\n");
  179.         return -EINVAL;
  180.     }
  181.         t = offset / RADEON_GPU_PAGE_SIZE;
  182.         p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
  183.  
  184.     for (i = 0; i < pages; i++, p++) {
  185.         /* we need to support large memory configurations */
  186.         /* assume that unbind have already been call on the range */
  187.  
  188.         rdev->gart.pages_addr[p] = pagelist[i] & ~4095;
  189.  
  190.         //if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) {
  191.         //    /* FIXME: failed to map page (return -ENOMEM?) */
  192.         //    radeon_gart_unbind(rdev, offset, pages);
  193.         //    return -ENOMEM;
  194.         //}
  195.         rdev->gart.pages[p] = pagelist[i];
  196.                 page_base = rdev->gart.pages_addr[p];
  197.                 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
  198.             radeon_gart_set_page(rdev, t, page_base);
  199.                         page_base += RADEON_GPU_PAGE_SIZE;
  200.         }
  201.     }
  202.     mb();
  203.     radeon_gart_tlb_flush(rdev);
  204.     return 0;
  205. }
  206.  
  207. int radeon_gart_init(struct radeon_device *rdev)
  208. {
  209.     if (rdev->gart.pages) {
  210.         return 0;
  211.     }
  212.         /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
  213.         if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
  214.         DRM_ERROR("Page size is smaller than GPU page size!\n");
  215.         return -EINVAL;
  216.     }
  217.     /* Compute table size */
  218.     rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
  219.         rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
  220.     DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
  221.          rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
  222.     /* Allocate pages table */
  223.     rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages,
  224.                    GFP_KERNEL);
  225.     if (rdev->gart.pages == NULL) {
  226.                 radeon_gart_fini(rdev);
  227.         return -ENOMEM;
  228.     }
  229.         rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) *
  230.                     rdev->gart.num_cpu_pages, GFP_KERNEL);
  231.     if (rdev->gart.pages_addr == NULL) {
  232.                 radeon_gart_fini(rdev);
  233.         return -ENOMEM;
  234.     }
  235.     return 0;
  236. }
  237.  
  238. void radeon_gart_fini(struct radeon_device *rdev)
  239. {
  240.         if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
  241.                 /* unbind pages */
  242.                 radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
  243.         }
  244.         rdev->gart.ready = false;
  245.         kfree(rdev->gart.pages);
  246.         kfree(rdev->gart.pages_addr);
  247.         rdev->gart.pages = NULL;
  248.         rdev->gart.pages_addr = NULL;
  249. }
  250.