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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include "drmP.h"
  29. #include "radeon_drm.h"
  30. #include "radeon.h"
  31. #include "radeon_reg.h"
  32.  
  33.  
  34. static inline void *
  35. pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
  36.                       addr_t *dma_handle)
  37. {
  38.  
  39.     size = (size + 0x7FFF) & ~0x7FFF;
  40.  
  41.     *dma_handle = AllocPages(size >> 12);
  42.     return (void*)MapIoMem(*dma_handle, size, PG_SW+PG_NOCACHE);
  43. }
  44.  
  45. /*
  46.  * Common GART table functions.
  47.  */
  48. int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
  49. {
  50.         void *ptr;
  51.  
  52.     ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
  53.                   &rdev->gart.table_addr);
  54.         if (ptr == NULL) {
  55.                 return -ENOMEM;
  56.         }
  57. #ifdef CONFIG_X86
  58.         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
  59.             rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  60.                 set_memory_uc((unsigned long)ptr,
  61.                               rdev->gart.table_size >> PAGE_SHIFT);
  62.         }
  63. #endif
  64.         rdev->gart.table.ram.ptr = ptr;
  65.         memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size);
  66.         return 0;
  67. }
  68.  
  69. void radeon_gart_table_ram_free(struct radeon_device *rdev)
  70. {
  71.         if (rdev->gart.table.ram.ptr == NULL) {
  72.                 return;
  73.         }
  74. #ifdef CONFIG_X86
  75.         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
  76.             rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  77.                 set_memory_wb((unsigned long)rdev->gart.table.ram.ptr,
  78.                               rdev->gart.table_size >> PAGE_SHIFT);
  79.         }
  80. #endif
  81. //   pci_free_consistent(rdev->pdev, rdev->gart.table_size,
  82. //               (void *)rdev->gart.table.ram.ptr,
  83. //               rdev->gart.table_addr);
  84.         rdev->gart.table.ram.ptr = NULL;
  85.         rdev->gart.table_addr = 0;
  86. }
  87.  
  88. int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
  89. {
  90.     int r;
  91.  
  92.     if (rdev->gart.table.vram.robj == NULL) {
  93.                 r = radeon_bo_create(rdev, rdev->gart.table_size,
  94.                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
  95.                                         &rdev->gart.table.vram.robj);
  96.         if (r) {
  97.             return r;
  98.         }
  99.     }
  100.         return 0;
  101. }
  102.  
  103. int radeon_gart_table_vram_pin(struct radeon_device *rdev)
  104. {
  105.         uint64_t gpu_addr;
  106.         int r;
  107.  
  108.         r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
  109.         if (unlikely(r != 0))
  110.                 return r;
  111.         r = radeon_bo_pin(rdev->gart.table.vram.robj,
  112.                   RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
  113.     if (r) {
  114.                 radeon_bo_unreserve(rdev->gart.table.vram.robj);
  115.         return r;
  116.     }
  117.         r = radeon_bo_kmap(rdev->gart.table.vram.robj,
  118.                    (void **)&rdev->gart.table.vram.ptr);
  119.         if (r)
  120.                 radeon_bo_unpin(rdev->gart.table.vram.robj);
  121.         radeon_bo_unreserve(rdev->gart.table.vram.robj);
  122.         rdev->gart.table_addr = gpu_addr;
  123.     return r;
  124. }
  125.  
  126. void radeon_gart_table_vram_free(struct radeon_device *rdev)
  127. {
  128.         int r;
  129.  
  130.         if (rdev->gart.table.vram.robj == NULL) {
  131.                 return;
  132.         }
  133.         r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
  134.         if (likely(r == 0)) {
  135.                 radeon_bo_kunmap(rdev->gart.table.vram.robj);
  136.                 radeon_bo_unpin(rdev->gart.table.vram.robj);
  137.                 radeon_bo_unreserve(rdev->gart.table.vram.robj);
  138.         }
  139.         radeon_bo_unref(&rdev->gart.table.vram.robj);
  140. }
  141.  
  142.  
  143.  
  144.  
  145. /*
  146.  * Common gart functions.
  147.  */
  148. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  149.                         int pages)
  150. {
  151.         unsigned t;
  152.         unsigned p;
  153.         int i, j;
  154.         u64 page_base;
  155.  
  156.         if (!rdev->gart.ready) {
  157.                 WARN(1, "trying to unbind memory to unitialized GART !\n");
  158.                 return;
  159.         }
  160.         t = offset / RADEON_GPU_PAGE_SIZE;
  161.         p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
  162.         for (i = 0; i < pages; i++, p++) {
  163.                 if (rdev->gart.pages[p]) {
  164. //           pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
  165. //                      PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  166.                         rdev->gart.pages[p] = NULL;
  167.                         rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
  168.                         page_base = rdev->gart.pages_addr[p];
  169.                         for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
  170.                                 radeon_gart_set_page(rdev, t, page_base);
  171.                                 page_base += RADEON_GPU_PAGE_SIZE;
  172.                         }
  173.                 }
  174.         }
  175.         mb();
  176.         radeon_gart_tlb_flush(rdev);
  177. }
  178.  
  179. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  180.              int pages, u32_t *pagelist)
  181. {
  182.     unsigned t;
  183.     unsigned p;
  184.     uint64_t page_base;
  185.     int i, j;
  186.  
  187.     ENTER();
  188.  
  189.     dbgprintf("offset %x pages %x list %x\n",
  190.                offset, pages, pagelist);
  191.  
  192.     if (!rdev->gart.ready) {
  193.                 WARN(1, "trying to bind memory to unitialized GART !\n");
  194.         return -EINVAL;
  195.     }
  196.         t = offset / RADEON_GPU_PAGE_SIZE;
  197.         p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
  198.  
  199.     for (i = 0; i < pages; i++, p++) {
  200.         /* we need to support large memory configurations */
  201.         /* assume that unbind have already been call on the range */
  202.  
  203.         rdev->gart.pages_addr[p] = pagelist[i] & ~4095;
  204.  
  205.  
  206.         rdev->gart.pages[p] = pagelist[i];
  207.                 page_base = rdev->gart.pages_addr[p];
  208.                 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
  209.             radeon_gart_set_page(rdev, t, page_base);
  210.                         page_base += RADEON_GPU_PAGE_SIZE;
  211.         }
  212.     }
  213.     mb();
  214.     radeon_gart_tlb_flush(rdev);
  215.     return 0;
  216. }
  217.  
  218. void radeon_gart_restore(struct radeon_device *rdev)
  219. {
  220.         int i, j, t;
  221.         u64 page_base;
  222.  
  223.         for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
  224.                 page_base = rdev->gart.pages_addr[i];
  225.                 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
  226.                         radeon_gart_set_page(rdev, t, page_base);
  227.                         page_base += RADEON_GPU_PAGE_SIZE;
  228.                 }
  229.         }
  230.         mb();
  231.         radeon_gart_tlb_flush(rdev);
  232. }
  233.  
  234. int radeon_gart_init(struct radeon_device *rdev)
  235. {
  236.         int r, i;
  237.  
  238.     if (rdev->gart.pages) {
  239.         return 0;
  240.     }
  241.         /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
  242.         if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
  243.         DRM_ERROR("Page size is smaller than GPU page size!\n");
  244.         return -EINVAL;
  245.     }
  246.         r = radeon_dummy_page_init(rdev);
  247.         if (r)
  248.                 return r;
  249.     /* Compute table size */
  250.     rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
  251.         rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
  252.     DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
  253.          rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
  254.     /* Allocate pages table */
  255.     rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages,
  256.                    GFP_KERNEL);
  257.     if (rdev->gart.pages == NULL) {
  258.                 radeon_gart_fini(rdev);
  259.         return -ENOMEM;
  260.     }
  261.         rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) *
  262.                     rdev->gart.num_cpu_pages, GFP_KERNEL);
  263.     if (rdev->gart.pages_addr == NULL) {
  264.                 radeon_gart_fini(rdev);
  265.         return -ENOMEM;
  266.     }
  267.         /* set GART entry to point to the dummy page by default */
  268.         for (i = 0; i < rdev->gart.num_cpu_pages; i++) {
  269.                 rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
  270.         }
  271.     return 0;
  272. }
  273.  
  274. void radeon_gart_fini(struct radeon_device *rdev)
  275. {
  276.         if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
  277.                 /* unbind pages */
  278.                 radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
  279.         }
  280.         rdev->gart.ready = false;
  281.         kfree(rdev->gart.pages);
  282.         kfree(rdev->gart.pages_addr);
  283.         rdev->gart.pages = NULL;
  284.         rdev->gart.pages_addr = NULL;
  285. }
  286.