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  1. /*
  2.  * Copyright 2009 Jerome Glisse.
  3.  * All Rights Reserved.
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the
  7.  * "Software"), to deal in the Software without restriction, including
  8.  * without limitation the rights to use, copy, modify, merge, publish,
  9.  * distribute, sub license, and/or sell copies of the Software, and to
  10.  * permit persons to whom the Software is furnished to do so, subject to
  11.  * the following conditions:
  12.  *
  13.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15.  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16.  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17.  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18.  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19.  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20.  *
  21.  * The above copyright notice and this permission notice (including the
  22.  * next paragraph) shall be included in all copies or substantial portions
  23.  * of the Software.
  24.  *
  25.  */
  26. /*
  27.  * Authors:
  28.  *    Jerome Glisse <glisse@freedesktop.org>
  29.  *    Dave Airlie
  30.  */
  31. #include <linux/seq_file.h>
  32. #include <asm/atomic.h>
  33. //#include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include <linux/slab.h>
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41.  
  42. static void radeon_fence_write(struct radeon_device *rdev, u32 seq)
  43. {
  44.         if (rdev->wb.enabled) {
  45.                 u32 scratch_index;
  46.                 if (rdev->wb.use_event)
  47.                         scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  48.                 else
  49.                         scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  50.                 rdev->wb.wb[scratch_index/4] = cpu_to_le32(seq);;
  51.         } else
  52.                 WREG32(rdev->fence_drv.scratch_reg, seq);
  53. }
  54.  
  55. static u32 radeon_fence_read(struct radeon_device *rdev)
  56. {
  57.         u32 seq;
  58.  
  59.         if (rdev->wb.enabled) {
  60.                 u32 scratch_index;
  61.                 if (rdev->wb.use_event)
  62.                         scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  63.                 else
  64.                         scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
  65.                 seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
  66.         } else
  67.                 seq = RREG32(rdev->fence_drv.scratch_reg);
  68.         return seq;
  69. }
  70.  
  71. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  72. {
  73.         unsigned long irq_flags;
  74.  
  75.         write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  76.         if (fence->emited) {
  77.                 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  78.                 return 0;
  79.         }
  80.         fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
  81.         if (!rdev->cp.ready)
  82.                 /* FIXME: cp is not running assume everythings is done right
  83.                  * away
  84.                  */
  85.                 radeon_fence_write(rdev, fence->seq);
  86.         else
  87.                 radeon_fence_ring_emit(rdev, fence);
  88.  
  89. //   trace_radeon_fence_emit(rdev->ddev, fence->seq);
  90.         fence->emited = true;
  91.         list_move_tail(&fence->list, &rdev->fence_drv.emited);
  92.         write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  93.         return 0;
  94. }
  95.  
  96. static bool radeon_fence_poll_locked(struct radeon_device *rdev)
  97. {
  98.         struct radeon_fence *fence;
  99.         struct list_head *i, *n;
  100.         uint32_t seq;
  101.         bool wake = false;
  102.         unsigned long cjiffies;
  103.  
  104. #if 0
  105.         seq = radeon_fence_read(rdev);
  106.         if (seq != rdev->fence_drv.last_seq) {
  107.                 rdev->fence_drv.last_seq = seq;
  108.                 rdev->fence_drv.last_jiffies = jiffies;
  109. //       rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  110.         } else {
  111.                 cjiffies = jiffies;
  112.                 if (time_after(cjiffies, rdev->fence_drv.last_jiffies)) {
  113.                         cjiffies -= rdev->fence_drv.last_jiffies;
  114.                         if (time_after(rdev->fence_drv.last_timeout, cjiffies)) {
  115.                                 /* update the timeout */
  116.                                 rdev->fence_drv.last_timeout -= cjiffies;
  117.                         } else {
  118.                                 /* the 500ms timeout is elapsed we should test
  119.                                  * for GPU lockup
  120.                                  */
  121.                                 rdev->fence_drv.last_timeout = 1;
  122.                         }
  123.                 } else {
  124.                         /* wrap around update last jiffies, we will just wait
  125.                          * a little longer
  126.                          */
  127.                         rdev->fence_drv.last_jiffies = cjiffies;
  128.         }
  129.                 return false;
  130.         }
  131.         n = NULL;
  132.         list_for_each(i, &rdev->fence_drv.emited) {
  133.                 fence = list_entry(i, struct radeon_fence, list);
  134.                 if (fence->seq == seq) {
  135.                         n = i;
  136.                         break;
  137.                 }
  138.         }
  139.         /* all fence previous to this one are considered as signaled */
  140.         if (n) {
  141.                 i = n;
  142.                 do {
  143.                         n = i->prev;
  144.                         list_move_tail(i, &rdev->fence_drv.signaled);
  145.                         fence = list_entry(i, struct radeon_fence, list);
  146.                         fence->signaled = true;
  147.                         i = n;
  148.                 } while (i != &rdev->fence_drv.emited);
  149.                 wake = true;
  150.         }
  151. #endif
  152.         return wake;
  153. }
  154.  
  155. static void radeon_fence_destroy(struct kref *kref)
  156. {
  157.         unsigned long irq_flags;
  158.         struct radeon_fence *fence;
  159.  
  160.         fence = container_of(kref, struct radeon_fence, kref);
  161.         write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  162.         list_del(&fence->list);
  163.         fence->emited = false;
  164.         write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  165.         kfree(fence);
  166. }
  167.  
  168. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
  169. {
  170.         unsigned long irq_flags;
  171.  
  172.         *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  173.         if ((*fence) == NULL) {
  174.                 return -ENOMEM;
  175.         }
  176. //      kref_init(&((*fence)->kref));
  177.         (*fence)->rdev = rdev;
  178.         (*fence)->emited = false;
  179.         (*fence)->signaled = false;
  180.         (*fence)->seq = 0;
  181.         INIT_LIST_HEAD(&(*fence)->list);
  182.  
  183.         write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  184.         list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
  185.         write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  186.         return 0;
  187. }
  188.  
  189.  
  190. bool radeon_fence_signaled(struct radeon_fence *fence)
  191. {
  192.         unsigned long irq_flags;
  193.         bool signaled = false;
  194.  
  195.         if (!fence)
  196.                 return true;
  197.  
  198.         if (fence->rdev->gpu_lockup)
  199.                 return true;
  200.  
  201.         write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  202.         signaled = fence->signaled;
  203.         /* if we are shuting down report all fence as signaled */
  204.         if (fence->rdev->shutdown) {
  205.                 signaled = true;
  206.         }
  207.         if (!fence->emited) {
  208.                 WARN(1, "Querying an unemited fence : %p !\n", fence);
  209.                 signaled = true;
  210.         }
  211.         if (!signaled) {
  212.                 radeon_fence_poll_locked(fence->rdev);
  213.                 signaled = fence->signaled;
  214.         }
  215.         write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  216.         return signaled;
  217. }
  218.  
  219. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  220. {
  221.         struct radeon_device *rdev;
  222.         unsigned long irq_flags, timeout;
  223.         u32 seq;
  224.         int r;
  225.  
  226.         if (fence == NULL) {
  227.                 WARN(1, "Querying an invalid fence : %p !\n", fence);
  228.                 return 0;
  229.         }
  230.         rdev = fence->rdev;
  231.         if (radeon_fence_signaled(fence)) {
  232.                 return 0;
  233.         }
  234.  
  235. #if 0
  236.         timeout = rdev->fence_drv.last_timeout;
  237. retry:
  238.         /* save current sequence used to check for GPU lockup */
  239.         seq = rdev->fence_drv.last_seq;
  240. //   trace_radeon_fence_wait_begin(rdev->ddev, seq);
  241.         if (intr) {
  242.                 radeon_irq_kms_sw_irq_get(rdev);
  243.                 r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
  244.                                 radeon_fence_signaled(fence), timeout);
  245.                 radeon_irq_kms_sw_irq_put(rdev);
  246.                 if (unlikely(r < 0)) {
  247.                         return r;
  248.                 }
  249.         } else {
  250.                 radeon_irq_kms_sw_irq_get(rdev);
  251.                 r = wait_event_timeout(rdev->fence_drv.queue,
  252.                          radeon_fence_signaled(fence), timeout);
  253.                 radeon_irq_kms_sw_irq_put(rdev);
  254.         }
  255. //   trace_radeon_fence_wait_end(rdev->ddev, seq);
  256.         if (unlikely(!radeon_fence_signaled(fence))) {
  257.                 /* we were interrupted for some reason and fence isn't
  258.                  * isn't signaled yet, resume wait
  259.                  */
  260.                 if (r) {
  261.                         timeout = r;
  262.                         goto retry;
  263.                 }
  264.                 /* don't protect read access to rdev->fence_drv.last_seq
  265.                  * if we experiencing a lockup the value doesn't change
  266.                  */
  267.                 if (seq == rdev->fence_drv.last_seq && radeon_gpu_is_lockup(rdev)) {
  268.                         /* good news we believe it's a lockup */
  269.                         WARN(1, "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
  270.                              fence->seq, seq);
  271.                         /* FIXME: what should we do ? marking everyone
  272.                          * as signaled for now
  273.                          */
  274.                         rdev->gpu_lockup = true;
  275.                         r = radeon_gpu_reset(rdev);
  276.                         if (r)
  277.                                 return r;
  278.                         radeon_fence_write(rdev, fence->seq);
  279.                         rdev->gpu_lockup = false;
  280.                         }
  281. //       timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  282.                 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  283. //       rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  284. //       rdev->fence_drv.last_jiffies = jiffies;
  285.                 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  286.                 goto retry;
  287.         }
  288. #endif
  289.         return 0;
  290. }
  291.  
  292. #if 0
  293. int radeon_fence_wait_next(struct radeon_device *rdev)
  294. {
  295.         unsigned long irq_flags;
  296.         struct radeon_fence *fence;
  297.         int r;
  298.  
  299.         if (rdev->gpu_lockup) {
  300.                 return 0;
  301.         }
  302.         write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  303.         if (list_empty(&rdev->fence_drv.emited)) {
  304.                 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  305.                 return 0;
  306.         }
  307.         fence = list_entry(rdev->fence_drv.emited.next,
  308.                            struct radeon_fence, list);
  309.         radeon_fence_ref(fence);
  310.         write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  311.         r = radeon_fence_wait(fence, false);
  312.         radeon_fence_unref(&fence);
  313.         return r;
  314. }
  315.  
  316. int radeon_fence_wait_last(struct radeon_device *rdev)
  317. {
  318.         unsigned long irq_flags;
  319.         struct radeon_fence *fence;
  320.         int r;
  321.  
  322.         if (rdev->gpu_lockup) {
  323.                 return 0;
  324.         }
  325.         write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  326.         if (list_empty(&rdev->fence_drv.emited)) {
  327.                 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  328.                 return 0;
  329.         }
  330.         fence = list_entry(rdev->fence_drv.emited.prev,
  331.                            struct radeon_fence, list);
  332.         radeon_fence_ref(fence);
  333.         write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  334.         r = radeon_fence_wait(fence, false);
  335.         radeon_fence_unref(&fence);
  336.         return r;
  337. }
  338.  
  339. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  340. {
  341.         kref_get(&fence->kref);
  342.         return fence;
  343. }
  344.  
  345. #endif
  346.  
  347. void radeon_fence_unref(struct radeon_fence **fence)
  348. {
  349.         struct radeon_fence *tmp = *fence;
  350.  
  351.         *fence = NULL;
  352. }
  353.  
  354. #if 0
  355. void radeon_fence_process(struct radeon_device *rdev)
  356. {
  357.         unsigned long irq_flags;
  358.         bool wake;
  359.  
  360.         write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  361.         wake = radeon_fence_poll_locked(rdev);
  362.         write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  363.         if (wake) {
  364.                 wake_up_all(&rdev->fence_drv.queue);
  365.         }
  366. }
  367.  
  368. #endif
  369.  
  370. int radeon_fence_driver_init(struct radeon_device *rdev)
  371. {
  372.         unsigned long irq_flags;
  373.         int r;
  374.  
  375.         write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  376.         r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
  377.         if (r) {
  378.                 dev_err(rdev->dev, "fence failed to get scratch register\n");
  379.                 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  380.                 return r;
  381.         }
  382.         radeon_fence_write(rdev, 0);
  383.         atomic_set(&rdev->fence_drv.seq, 0);
  384.         INIT_LIST_HEAD(&rdev->fence_drv.created);
  385.         INIT_LIST_HEAD(&rdev->fence_drv.emited);
  386.         INIT_LIST_HEAD(&rdev->fence_drv.signaled);
  387. //   init_waitqueue_head(&rdev->fence_drv.queue);
  388.         rdev->fence_drv.initialized = true;
  389.         write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  390.     return 0;
  391. }
  392.  
  393.  
  394. /*
  395.  * Fence debugfs
  396.  */
  397. #if defined(CONFIG_DEBUG_FS)
  398. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  399. {
  400.         struct drm_info_node *node = (struct drm_info_node *)m->private;
  401.         struct drm_device *dev = node->minor->dev;
  402.         struct radeon_device *rdev = dev->dev_private;
  403.         struct radeon_fence *fence;
  404.  
  405.         seq_printf(m, "Last signaled fence 0x%08X\n",
  406.                    radeon_fence_read(rdev));
  407.         if (!list_empty(&rdev->fence_drv.emited)) {
  408.                    fence = list_entry(rdev->fence_drv.emited.prev,
  409.                                       struct radeon_fence, list);
  410.                    seq_printf(m, "Last emited fence %p with 0x%08X\n",
  411.                               fence,  fence->seq);
  412.         }
  413.         return 0;
  414. }
  415.  
  416. static struct drm_info_list radeon_debugfs_fence_list[] = {
  417.         {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  418. };
  419. #endif
  420.  
  421. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  422. {
  423. #if defined(CONFIG_DEBUG_FS)
  424.         return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  425. #else
  426.         return 0;
  427. #endif
  428. }
  429.