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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. //#include <linux/console.h>
  29. #include <linux/slab.h>
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/radeon_drm.h>
  33. #include "radeon_reg.h"
  34. #include "radeon.h"
  35. #include "atom.h"
  36.  
  37. #include "bitmap.h"
  38. #include "display.h"
  39.  
  40.  
  41. #include <drm/drm_pciids.h>
  42.  
  43.  
  44. int radeon_no_wb   =  1;
  45. int radeon_modeset = -1;
  46. int radeon_dynclks = -1;
  47. int radeon_r4xx_atom = 0;
  48. int radeon_agpmode = 0;
  49. int radeon_vram_limit = 0;
  50. int radeon_gart_size = 512; /* default gart size */
  51. int radeon_benchmarking = 0;
  52. int radeon_testing = 0;
  53. int radeon_connector_table = 0;
  54. int radeon_tv = 1;
  55. int radeon_new_pll = -1;
  56. int radeon_dynpm = -1;
  57. int radeon_audio = 1;
  58. int radeon_hw_i2c = 0;
  59. int radeon_pcie_gen2 = 0;
  60. int radeon_disp_priority = 0;
  61. int radeon_lockup_timeout = 10000;
  62.  
  63.  
  64. int irq_override = 0;
  65.  
  66.  
  67. extern display_t *rdisplay;
  68. struct drm_device *main_drm_device;
  69.  
  70.  
  71. void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms);
  72. int init_display(struct radeon_device *rdev, videomode_t *mode);
  73. int init_display_kms(struct radeon_device *rdev, videomode_t *mode);
  74.  
  75. int get_modes(videomode_t *mode, u32_t *count);
  76. int set_user_mode(videomode_t *mode);
  77. int r100_2D_test(struct radeon_device *rdev);
  78.  
  79.  
  80.  /* Legacy VGA regions */
  81. #define VGA_RSRC_NONE          0x00
  82. #define VGA_RSRC_LEGACY_IO     0x01
  83. #define VGA_RSRC_LEGACY_MEM    0x02
  84. #define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
  85. /* Non-legacy access */
  86. #define VGA_RSRC_NORMAL_IO     0x04
  87. #define VGA_RSRC_NORMAL_MEM    0x08
  88.  
  89.  
  90. static const char radeon_family_name[][16] = {
  91.         "R100",
  92.         "RV100",
  93.         "RS100",
  94.         "RV200",
  95.         "RS200",
  96.         "R200",
  97.         "RV250",
  98.         "RS300",
  99.         "RV280",
  100.         "R300",
  101.         "R350",
  102.         "RV350",
  103.         "RV380",
  104.         "R420",
  105.         "R423",
  106.         "RV410",
  107.         "RS400",
  108.         "RS480",
  109.         "RS600",
  110.         "RS690",
  111.         "RS740",
  112.         "RV515",
  113.         "R520",
  114.         "RV530",
  115.         "RV560",
  116.         "RV570",
  117.         "R580",
  118.         "R600",
  119.         "RV610",
  120.         "RV630",
  121.         "RV670",
  122.         "RV620",
  123.         "RV635",
  124.         "RS780",
  125.         "RS880",
  126.         "RV770",
  127.         "RV730",
  128.         "RV710",
  129.         "RV740",
  130.         "CEDAR",
  131.         "REDWOOD",
  132.         "JUNIPER",
  133.         "CYPRESS",
  134.         "HEMLOCK",
  135.         "PALM",
  136.         "SUMO",
  137.         "SUMO2",
  138.         "BARTS",
  139.         "TURKS",
  140.         "CAICOS",
  141.         "CAYMAN",
  142.         "ARUBA",
  143.         "TAHITI",
  144.         "PITCAIRN",
  145.         "VERDE",
  146.         "LAST",
  147. };
  148.  
  149. /**
  150.  * radeon_surface_init - Clear GPU surface registers.
  151.  *
  152.  * @rdev: radeon_device pointer
  153.  *
  154.  * Clear GPU surface registers (r1xx-r5xx).
  155.  */
  156. void radeon_surface_init(struct radeon_device *rdev)
  157. {
  158.     /* FIXME: check this out */
  159.     if (rdev->family < CHIP_R600) {
  160.         int i;
  161.  
  162.                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  163.            radeon_clear_surface_reg(rdev, i);
  164.         }
  165.                 /* enable surfaces */
  166.                 WREG32(RADEON_SURFACE_CNTL, 0);
  167.     }
  168. }
  169.  
  170. /*
  171.  * GPU scratch registers helpers function.
  172.  */
  173. /**
  174.  * radeon_scratch_init - Init scratch register driver information.
  175.  *
  176.  * @rdev: radeon_device pointer
  177.  *
  178.  * Init CP scratch register driver information (r1xx-r5xx)
  179.  */
  180. void radeon_scratch_init(struct radeon_device *rdev)
  181. {
  182.     int i;
  183.  
  184.     /* FIXME: check this out */
  185.     if (rdev->family < CHIP_R300) {
  186.         rdev->scratch.num_reg = 5;
  187.     } else {
  188.         rdev->scratch.num_reg = 7;
  189.     }
  190.         rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
  191.     for (i = 0; i < rdev->scratch.num_reg; i++) {
  192.         rdev->scratch.free[i] = true;
  193.                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
  194.     }
  195. }
  196.  
  197. /**
  198.  * radeon_scratch_get - Allocate a scratch register
  199.  *
  200.  * @rdev: radeon_device pointer
  201.  * @reg: scratch register mmio offset
  202.  *
  203.  * Allocate a CP scratch register for use by the driver (all asics).
  204.  * Returns 0 on success or -EINVAL on failure.
  205.  */
  206. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  207. {
  208.         int i;
  209.  
  210.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  211.                 if (rdev->scratch.free[i]) {
  212.                         rdev->scratch.free[i] = false;
  213.                         *reg = rdev->scratch.reg[i];
  214.                         return 0;
  215.                 }
  216.         }
  217.         return -EINVAL;
  218. }
  219.  
  220. /**
  221.  * radeon_scratch_free - Free a scratch register
  222.  *
  223.  * @rdev: radeon_device pointer
  224.  * @reg: scratch register mmio offset
  225.  *
  226.  * Free a CP scratch register allocated for use by the driver (all asics)
  227.  */
  228. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  229. {
  230.         int i;
  231.  
  232.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  233.                 if (rdev->scratch.reg[i] == reg) {
  234.                         rdev->scratch.free[i] = true;
  235.                         return;
  236.                 }
  237.         }
  238. }
  239.  
  240. /*
  241.  * radeon_wb_*()
  242.  * Writeback is the the method by which the the GPU updates special pages
  243.  * in memory with the status of certain GPU events (fences, ring pointers,
  244.  * etc.).
  245.  */
  246.  
  247. /**
  248.  * radeon_wb_disable - Disable Writeback
  249.  *
  250.  * @rdev: radeon_device pointer
  251.  *
  252.  * Disables Writeback (all asics).  Used for suspend.
  253.  */
  254. void radeon_wb_disable(struct radeon_device *rdev)
  255. {
  256.         int r;
  257.  
  258.         if (rdev->wb.wb_obj) {
  259.                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
  260.                 if (unlikely(r != 0))
  261.                         return;
  262.                 radeon_bo_kunmap(rdev->wb.wb_obj);
  263.                 radeon_bo_unpin(rdev->wb.wb_obj);
  264.                 radeon_bo_unreserve(rdev->wb.wb_obj);
  265.         }
  266.         rdev->wb.enabled = false;
  267. }
  268.  
  269. /**
  270.  * radeon_wb_fini - Disable Writeback and free memory
  271.  *
  272.  * @rdev: radeon_device pointer
  273.  *
  274.  * Disables Writeback and frees the Writeback memory (all asics).
  275.  * Used at driver shutdown.
  276.  */
  277. void radeon_wb_fini(struct radeon_device *rdev)
  278. {
  279.         radeon_wb_disable(rdev);
  280.         if (rdev->wb.wb_obj) {
  281.                 radeon_bo_unref(&rdev->wb.wb_obj);
  282.                 rdev->wb.wb = NULL;
  283.                 rdev->wb.wb_obj = NULL;
  284.         }
  285. }
  286.  
  287. /**
  288.  * radeon_wb_init- Init Writeback driver info and allocate memory
  289.  *
  290.  * @rdev: radeon_device pointer
  291.  *
  292.  * Disables Writeback and frees the Writeback memory (all asics).
  293.  * Used at driver startup.
  294.  * Returns 0 on success or an -error on failure.
  295.  */
  296. int radeon_wb_init(struct radeon_device *rdev)
  297. {
  298.         int r;
  299.  
  300.         if (rdev->wb.wb_obj == NULL) {
  301.                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
  302.                                      RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
  303.                 if (r) {
  304.                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
  305.                         return r;
  306.                 }
  307.         }
  308.         r = radeon_bo_reserve(rdev->wb.wb_obj, false);
  309.         if (unlikely(r != 0)) {
  310.                 radeon_wb_fini(rdev);
  311.                 return r;
  312.         }
  313.         r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
  314.                           &rdev->wb.gpu_addr);
  315.         if (r) {
  316.                 radeon_bo_unreserve(rdev->wb.wb_obj);
  317.                 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
  318.                 radeon_wb_fini(rdev);
  319.                 return r;
  320.         }
  321.         r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
  322.         radeon_bo_unreserve(rdev->wb.wb_obj);
  323.         if (r) {
  324.                 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
  325.                 radeon_wb_fini(rdev);
  326.                 return r;
  327.         }
  328.  
  329.         /* clear wb memory */
  330.         memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
  331.         /* disable event_write fences */
  332.         rdev->wb.use_event = false;
  333.         /* disabled via module param */
  334.         if (radeon_no_wb == 1) {
  335.                 rdev->wb.enabled = false;
  336.         } else {
  337.                 if (rdev->flags & RADEON_IS_AGP) {
  338.                 /* often unreliable on AGP */
  339.                         rdev->wb.enabled = false;
  340.                 } else if (rdev->family < CHIP_R300) {
  341.                         /* often unreliable on pre-r300 */
  342.                         rdev->wb.enabled = false;
  343.                 } else {
  344.                         rdev->wb.enabled = true;
  345.                         /* event_write fences are only available on r600+ */
  346.                         if (rdev->family >= CHIP_R600) {
  347.                                 rdev->wb.use_event = true;
  348.         }
  349.                 }
  350.         }
  351.         /* always use writeback/events on NI, APUs */
  352.         if (rdev->family >= CHIP_PALM) {
  353.                 rdev->wb.enabled = true;
  354.                 rdev->wb.use_event = true;
  355.         }
  356.  
  357.         dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
  358.  
  359.         return 0;
  360. }
  361.  
  362. /**
  363.  * radeon_vram_location - try to find VRAM location
  364.  * @rdev: radeon device structure holding all necessary informations
  365.  * @mc: memory controller structure holding memory informations
  366.  * @base: base address at which to put VRAM
  367.  *
  368.  * Function will place try to place VRAM at base address provided
  369.  * as parameter (which is so far either PCI aperture address or
  370.  * for IGP TOM base address).
  371.  *
  372.  * If there is not enough space to fit the unvisible VRAM in the 32bits
  373.  * address space then we limit the VRAM size to the aperture.
  374.  *
  375.  * If we are using AGP and if the AGP aperture doesn't allow us to have
  376.  * room for all the VRAM than we restrict the VRAM to the PCI aperture
  377.  * size and print a warning.
  378.  *
  379.  * This function will never fails, worst case are limiting VRAM.
  380.  *
  381.  * Note: GTT start, end, size should be initialized before calling this
  382.  * function on AGP platform.
  383.  *
  384.  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
  385.  * this shouldn't be a problem as we are using the PCI aperture as a reference.
  386.  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
  387.  * not IGP.
  388.  *
  389.  * Note: we use mc_vram_size as on some board we need to program the mc to
  390.  * cover the whole aperture even if VRAM size is inferior to aperture size
  391.  * Novell bug 204882 + along with lots of ubuntu ones
  392.  *
  393.  * Note: when limiting vram it's safe to overwritte real_vram_size because
  394.  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
  395.  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
  396.  * ones)
  397.  *
  398.  * Note: IGP TOM addr should be the same as the aperture addr, we don't
  399.  * explicitly check for that thought.
  400.  *
  401.  * FIXME: when reducing VRAM size align new size on power of 2.
  402.  */
  403. void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
  404. {
  405.         uint64_t limit = (uint64_t)radeon_vram_limit << 20;
  406.  
  407.         mc->vram_start = base;
  408.         if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
  409.                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
  410.                 mc->real_vram_size = mc->aper_size;
  411.                 mc->mc_vram_size = mc->aper_size;
  412.         }
  413.         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  414.         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
  415.                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
  416.                 mc->real_vram_size = mc->aper_size;
  417.                 mc->mc_vram_size = mc->aper_size;
  418.                 }
  419.         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  420.         if (limit && limit < mc->real_vram_size)
  421.                 mc->real_vram_size = limit;
  422.         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
  423.                         mc->mc_vram_size >> 20, mc->vram_start,
  424.                         mc->vram_end, mc->real_vram_size >> 20);
  425. }
  426.  
  427. /**
  428.  * radeon_gtt_location - try to find GTT location
  429.  * @rdev: radeon device structure holding all necessary informations
  430.  * @mc: memory controller structure holding memory informations
  431.  *
  432.  * Function will place try to place GTT before or after VRAM.
  433.  *
  434.  * If GTT size is bigger than space left then we ajust GTT size.
  435.  * Thus function will never fails.
  436.  *
  437.  * FIXME: when reducing GTT size align new size on power of 2.
  438.  */
  439. void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
  440. {
  441.         u64 size_af, size_bf;
  442.  
  443.         size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
  444.         size_bf = mc->vram_start & ~mc->gtt_base_align;
  445.         if (size_bf > size_af) {
  446.                 if (mc->gtt_size > size_bf) {
  447.                         dev_warn(rdev->dev, "limiting GTT\n");
  448.                         mc->gtt_size = size_bf;
  449.                 }
  450.                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
  451.         } else {
  452.                 if (mc->gtt_size > size_af) {
  453.                         dev_warn(rdev->dev, "limiting GTT\n");
  454.                         mc->gtt_size = size_af;
  455.                 }
  456.                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
  457.         }
  458.         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
  459.         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
  460.                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
  461. }
  462.  
  463. /*
  464.  * GPU helpers function.
  465.  */
  466. /**
  467.  * radeon_card_posted - check if the hw has already been initialized
  468.  *
  469.  * @rdev: radeon_device pointer
  470.  *
  471.  * Check if the asic has been initialized (all asics).
  472.  * Used at driver startup.
  473.  * Returns true if initialized or false if not.
  474.  */
  475. bool radeon_card_posted(struct radeon_device *rdev)
  476. {
  477.         uint32_t reg;
  478.  
  479.         /* first check CRTCs */
  480.         if (ASIC_IS_DCE41(rdev)) {
  481.                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
  482.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
  483.                 if (reg & EVERGREEN_CRTC_MASTER_EN)
  484.                         return true;
  485.         } else if (ASIC_IS_DCE4(rdev)) {
  486.                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
  487.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
  488.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
  489.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
  490.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
  491.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
  492.                 if (reg & EVERGREEN_CRTC_MASTER_EN)
  493.                         return true;
  494.         } else if (ASIC_IS_AVIVO(rdev)) {
  495.                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
  496.                       RREG32(AVIVO_D2CRTC_CONTROL);
  497.                 if (reg & AVIVO_CRTC_EN) {
  498.                         return true;
  499.                 }
  500.         } else {
  501.                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
  502.                       RREG32(RADEON_CRTC2_GEN_CNTL);
  503.                 if (reg & RADEON_CRTC_EN) {
  504.                         return true;
  505.                 }
  506.         }
  507.  
  508.         /* then check MEM_SIZE, in case the crtcs are off */
  509.         if (rdev->family >= CHIP_R600)
  510.                 reg = RREG32(R600_CONFIG_MEMSIZE);
  511.         else
  512.                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
  513.  
  514.         if (reg)
  515.                 return true;
  516.  
  517.         return false;
  518.  
  519. }
  520.  
  521. /**
  522.  * radeon_update_bandwidth_info - update display bandwidth params
  523.  *
  524.  * @rdev: radeon_device pointer
  525.  *
  526.  * Used when sclk/mclk are switched or display modes are set.
  527.  * params are used to calculate display watermarks (all asics)
  528.  */
  529. void radeon_update_bandwidth_info(struct radeon_device *rdev)
  530. {
  531.         fixed20_12 a;
  532.         u32 sclk = rdev->pm.current_sclk;
  533.         u32 mclk = rdev->pm.current_mclk;
  534.  
  535.         /* sclk/mclk in Mhz */
  536.                 a.full = dfixed_const(100);
  537.                 rdev->pm.sclk.full = dfixed_const(sclk);
  538.                 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
  539.                 rdev->pm.mclk.full = dfixed_const(mclk);
  540.                 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
  541.  
  542.         if (rdev->flags & RADEON_IS_IGP) {
  543.                 a.full = dfixed_const(16);
  544.                 /* core_bandwidth = sclk(Mhz) * 16 */
  545.                 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
  546.         }
  547. }
  548.  
  549. /**
  550.  * radeon_boot_test_post_card - check and possibly initialize the hw
  551.  *
  552.  * @rdev: radeon_device pointer
  553.  *
  554.  * Check if the asic is initialized and if not, attempt to initialize
  555.  * it (all asics).
  556.  * Returns true if initialized or false if not.
  557.  */
  558. bool radeon_boot_test_post_card(struct radeon_device *rdev)
  559. {
  560.         if (radeon_card_posted(rdev))
  561.                 return true;
  562.  
  563.         if (rdev->bios) {
  564.                 DRM_INFO("GPU not posted. posting now...\n");
  565.                 if (rdev->is_atom_bios)
  566.                         atom_asic_init(rdev->mode_info.atom_context);
  567.                 else
  568.                         radeon_combios_asic_init(rdev->ddev);
  569.                 return true;
  570.         } else {
  571.                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  572.                 return false;
  573.         }
  574. }
  575.  
  576. /**
  577.  * radeon_dummy_page_init - init dummy page used by the driver
  578.  *
  579.  * @rdev: radeon_device pointer
  580.  *
  581.  * Allocate the dummy page used by the driver (all asics).
  582.  * This dummy page is used by the driver as a filler for gart entries
  583.  * when pages are taken out of the GART
  584.  * Returns 0 on sucess, -ENOMEM on failure.
  585.  */
  586. int radeon_dummy_page_init(struct radeon_device *rdev)
  587. {
  588.         if (rdev->dummy_page.page)
  589.                 return 0;
  590.     rdev->dummy_page.page = (void*)AllocPage();
  591.         if (rdev->dummy_page.page == NULL)
  592.                 return -ENOMEM;
  593.     rdev->dummy_page.addr = MapIoMem((addr_t)rdev->dummy_page.page, 4096, 3);
  594.         if (!rdev->dummy_page.addr) {
  595. //       __free_page(rdev->dummy_page.page);
  596.                 rdev->dummy_page.page = NULL;
  597.                 return -ENOMEM;
  598.         }
  599.         return 0;
  600. }
  601.  
  602. /**
  603.  * radeon_dummy_page_fini - free dummy page used by the driver
  604.  *
  605.  * @rdev: radeon_device pointer
  606.  *
  607.  * Frees the dummy page used by the driver (all asics).
  608.  */
  609. void radeon_dummy_page_fini(struct radeon_device *rdev)
  610. {
  611.         if (rdev->dummy_page.page == NULL)
  612.                 return;
  613.     KernelFree((void*)rdev->dummy_page.addr);
  614.         rdev->dummy_page.page = NULL;
  615. }
  616.  
  617.  
  618. /* ATOM accessor methods */
  619. /*
  620.  * ATOM is an interpreted byte code stored in tables in the vbios.  The
  621.  * driver registers callbacks to access registers and the interpreter
  622.  * in the driver parses the tables and executes then to program specific
  623.  * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
  624.  * atombios.h, and atom.c
  625.  */
  626.  
  627. /**
  628.  * cail_pll_read - read PLL register
  629.  *
  630.  * @info: atom card_info pointer
  631.  * @reg: PLL register offset
  632.  *
  633.  * Provides a PLL register accessor for the atom interpreter (r4xx+).
  634.  * Returns the value of the PLL register.
  635.  */
  636. static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
  637. {
  638.     struct radeon_device *rdev = info->dev->dev_private;
  639.     uint32_t r;
  640.  
  641.     r = rdev->pll_rreg(rdev, reg);
  642.     return r;
  643. }
  644.  
  645. /**
  646.  * cail_pll_write - write PLL register
  647.  *
  648.  * @info: atom card_info pointer
  649.  * @reg: PLL register offset
  650.  * @val: value to write to the pll register
  651.  *
  652.  * Provides a PLL register accessor for the atom interpreter (r4xx+).
  653.  */
  654. static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
  655. {
  656.     struct radeon_device *rdev = info->dev->dev_private;
  657.  
  658.     rdev->pll_wreg(rdev, reg, val);
  659. }
  660.  
  661. /**
  662.  * cail_mc_read - read MC (Memory Controller) register
  663.  *
  664.  * @info: atom card_info pointer
  665.  * @reg: MC register offset
  666.  *
  667.  * Provides an MC register accessor for the atom interpreter (r4xx+).
  668.  * Returns the value of the MC register.
  669.  */
  670. static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
  671. {
  672.     struct radeon_device *rdev = info->dev->dev_private;
  673.     uint32_t r;
  674.  
  675.     r = rdev->mc_rreg(rdev, reg);
  676.     return r;
  677. }
  678.  
  679. /**
  680.  * cail_mc_write - write MC (Memory Controller) register
  681.  *
  682.  * @info: atom card_info pointer
  683.  * @reg: MC register offset
  684.  * @val: value to write to the pll register
  685.  *
  686.  * Provides a MC register accessor for the atom interpreter (r4xx+).
  687.  */
  688. static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
  689. {
  690.     struct radeon_device *rdev = info->dev->dev_private;
  691.  
  692.     rdev->mc_wreg(rdev, reg, val);
  693. }
  694.  
  695. /**
  696.  * cail_reg_write - write MMIO register
  697.  *
  698.  * @info: atom card_info pointer
  699.  * @reg: MMIO register offset
  700.  * @val: value to write to the pll register
  701.  *
  702.  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
  703.  */
  704. static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
  705. {
  706.     struct radeon_device *rdev = info->dev->dev_private;
  707.  
  708.     WREG32(reg*4, val);
  709. }
  710.  
  711. /**
  712.  * cail_reg_read - read MMIO register
  713.  *
  714.  * @info: atom card_info pointer
  715.  * @reg: MMIO register offset
  716.  *
  717.  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
  718.  * Returns the value of the MMIO register.
  719.  */
  720. static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
  721. {
  722.     struct radeon_device *rdev = info->dev->dev_private;
  723.     uint32_t r;
  724.  
  725.     r = RREG32(reg*4);
  726.     return r;
  727. }
  728.  
  729. /**
  730.  * cail_ioreg_write - write IO register
  731.  *
  732.  * @info: atom card_info pointer
  733.  * @reg: IO register offset
  734.  * @val: value to write to the pll register
  735.  *
  736.  * Provides a IO register accessor for the atom interpreter (r4xx+).
  737.  */
  738. static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
  739. {
  740.         struct radeon_device *rdev = info->dev->dev_private;
  741.  
  742.         WREG32_IO(reg*4, val);
  743. }
  744.  
  745. /**
  746.  * cail_ioreg_read - read IO register
  747.  *
  748.  * @info: atom card_info pointer
  749.  * @reg: IO register offset
  750.  *
  751.  * Provides an IO register accessor for the atom interpreter (r4xx+).
  752.  * Returns the value of the IO register.
  753.  */
  754. static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
  755. {
  756.         struct radeon_device *rdev = info->dev->dev_private;
  757.         uint32_t r;
  758.  
  759.         r = RREG32_IO(reg*4);
  760.         return r;
  761. }
  762.  
  763. /**
  764.  * radeon_atombios_init - init the driver info and callbacks for atombios
  765.  *
  766.  * @rdev: radeon_device pointer
  767.  *
  768.  * Initializes the driver info and register access callbacks for the
  769.  * ATOM interpreter (r4xx+).
  770.  * Returns 0 on sucess, -ENOMEM on failure.
  771.  * Called at driver startup.
  772.  */
  773. int radeon_atombios_init(struct radeon_device *rdev)
  774. {
  775.         struct card_info *atom_card_info =
  776.             kzalloc(sizeof(struct card_info), GFP_KERNEL);
  777.  
  778.         if (!atom_card_info)
  779.                 return -ENOMEM;
  780.  
  781.         rdev->mode_info.atom_card_info = atom_card_info;
  782.         atom_card_info->dev = rdev->ddev;
  783.         atom_card_info->reg_read = cail_reg_read;
  784.         atom_card_info->reg_write = cail_reg_write;
  785.         /* needed for iio ops */
  786.         if (rdev->rio_mem) {
  787.                 atom_card_info->ioreg_read = cail_ioreg_read;
  788.                 atom_card_info->ioreg_write = cail_ioreg_write;
  789.         } else {
  790.                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
  791.                 atom_card_info->ioreg_read = cail_reg_read;
  792.                 atom_card_info->ioreg_write = cail_reg_write;
  793.         }
  794.         atom_card_info->mc_read = cail_mc_read;
  795.         atom_card_info->mc_write = cail_mc_write;
  796.         atom_card_info->pll_read = cail_pll_read;
  797.         atom_card_info->pll_write = cail_pll_write;
  798.  
  799.         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
  800.         mutex_init(&rdev->mode_info.atom_context->mutex);
  801.     radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
  802.         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
  803.     return 0;
  804. }
  805.  
  806. /**
  807.  * radeon_atombios_fini - free the driver info and callbacks for atombios
  808.  *
  809.  * @rdev: radeon_device pointer
  810.  *
  811.  * Frees the driver info and register access callbacks for the ATOM
  812.  * interpreter (r4xx+).
  813.  * Called at driver shutdown.
  814.  */
  815. void radeon_atombios_fini(struct radeon_device *rdev)
  816. {
  817.         if (rdev->mode_info.atom_context) {
  818.                 kfree(rdev->mode_info.atom_context->scratch);
  819.         kfree(rdev->mode_info.atom_context);
  820.         }
  821.         kfree(rdev->mode_info.atom_card_info);
  822. }
  823.  
  824. /* COMBIOS */
  825. /*
  826.  * COMBIOS is the bios format prior to ATOM. It provides
  827.  * command tables similar to ATOM, but doesn't have a unified
  828.  * parser.  See radeon_combios.c
  829.  */
  830.  
  831. /**
  832.  * radeon_combios_init - init the driver info for combios
  833.  *
  834.  * @rdev: radeon_device pointer
  835.  *
  836.  * Initializes the driver info for combios (r1xx-r3xx).
  837.  * Returns 0 on sucess.
  838.  * Called at driver startup.
  839.  */
  840. int radeon_combios_init(struct radeon_device *rdev)
  841. {
  842.         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
  843.         return 0;
  844. }
  845.  
  846. /**
  847.  * radeon_combios_fini - free the driver info for combios
  848.  *
  849.  * @rdev: radeon_device pointer
  850.  *
  851.  * Frees the driver info for combios (r1xx-r3xx).
  852.  * Called at driver shutdown.
  853.  */
  854. void radeon_combios_fini(struct radeon_device *rdev)
  855. {
  856. }
  857.  
  858. /* if we get transitioned to only one device, take VGA back */
  859. /**
  860.  * radeon_vga_set_decode - enable/disable vga decode
  861.  *
  862.  * @cookie: radeon_device pointer
  863.  * @state: enable/disable vga decode
  864.  *
  865.  * Enable/disable vga decode (all asics).
  866.  * Returns VGA resource flags.
  867.  */
  868. static unsigned int radeon_vga_set_decode(void *cookie, bool state)
  869. {
  870.         struct radeon_device *rdev = cookie;
  871.         radeon_vga_set_state(rdev, state);
  872.         if (state)
  873.                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  874.                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  875.         else
  876.                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  877. }
  878.  
  879. /**
  880.  * radeon_check_pot_argument - check that argument is a power of two
  881.  *
  882.  * @arg: value to check
  883.  *
  884.  * Validates that a certain argument is a power of two (all asics).
  885.  * Returns true if argument is valid.
  886.  */
  887. static bool radeon_check_pot_argument(int arg)
  888. {
  889.         return (arg & (arg - 1)) == 0;
  890. }
  891.  
  892. /**
  893.  * radeon_check_arguments - validate module params
  894.  *
  895.  * @rdev: radeon_device pointer
  896.  *
  897.  * Validates certain module parameters and updates
  898.  * the associated values used by the driver (all asics).
  899.  */
  900. static void radeon_check_arguments(struct radeon_device *rdev)
  901. {
  902.         /* vramlimit must be a power of two */
  903.         if (!radeon_check_pot_argument(radeon_vram_limit)) {
  904.                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
  905.                                 radeon_vram_limit);
  906.                 radeon_vram_limit = 0;
  907.         }
  908.  
  909.         /* gtt size must be power of two and greater or equal to 32M */
  910.         if (radeon_gart_size < 32) {
  911.                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
  912.                                 radeon_gart_size);
  913.                 radeon_gart_size = 512;
  914.  
  915.         } else if (!radeon_check_pot_argument(radeon_gart_size)) {
  916.                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
  917.                                 radeon_gart_size);
  918.                 radeon_gart_size = 512;
  919.         }
  920.         rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
  921.  
  922.         /* AGP mode can only be -1, 1, 2, 4, 8 */
  923.         switch (radeon_agpmode) {
  924.         case -1:
  925.         case 0:
  926.         case 1:
  927.         case 2:
  928.         case 4:
  929.         case 8:
  930.                 break;
  931.         default:
  932.                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
  933.                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
  934.                 radeon_agpmode = 0;
  935.                 break;
  936.         }
  937. }
  938.  
  939. int radeon_device_init(struct radeon_device *rdev,
  940.                struct drm_device *ddev,
  941.                struct pci_dev *pdev,
  942.                uint32_t flags)
  943. {
  944.         int r, i;
  945.         int dma_bits;
  946.  
  947.     rdev->shutdown = false;
  948.     rdev->ddev = ddev;
  949.     rdev->pdev = pdev;
  950.     rdev->flags = flags;
  951.     rdev->family = flags & RADEON_FAMILY_MASK;
  952.     rdev->is_atom_bios = false;
  953.     rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
  954.     rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  955.         rdev->accel_working = false;
  956.         /* set up ring ids */
  957.         for (i = 0; i < RADEON_NUM_RINGS; i++) {
  958.                 rdev->ring[i].idx = i;
  959.         }
  960.  
  961.         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
  962.                 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
  963.                 pdev->subsystem_vendor, pdev->subsystem_device);
  964.  
  965.     /* mutex initialization are all done here so we
  966.      * can recall function without having locking issues */
  967.         mutex_init(&rdev->ring_lock);
  968.         mutex_init(&rdev->dc_hw_i2c_mutex);
  969.         atomic_set(&rdev->ih.lock, 0);
  970.         mutex_init(&rdev->gem.mutex);
  971.         mutex_init(&rdev->pm.mutex);
  972.         mutex_init(&rdev->gpu_clock_mutex);
  973.         init_rwsem(&rdev->pm.mclk_lock);
  974.         init_rwsem(&rdev->exclusive_lock);
  975.         init_waitqueue_head(&rdev->irq.vblank_queue);
  976.         r = radeon_gem_init(rdev);
  977.         if (r)
  978.                 return r;
  979.         /* initialize vm here */
  980.         mutex_init(&rdev->vm_manager.lock);
  981.         /* Adjust VM size here.
  982.          * Currently set to 4GB ((1 << 20) 4k pages).
  983.          * Max GPUVM size for cayman and SI is 40 bits.
  984.          */
  985.         rdev->vm_manager.max_pfn = 1 << 20;
  986.         INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
  987.  
  988.         /* Set asic functions */
  989.         r = radeon_asic_init(rdev);
  990.         if (r)
  991.                 return r;
  992.         radeon_check_arguments(rdev);
  993.  
  994.         /* all of the newer IGP chips have an internal gart
  995.          * However some rs4xx report as AGP, so remove that here.
  996.          */
  997.         if ((rdev->family >= CHIP_RS400) &&
  998.             (rdev->flags & RADEON_IS_IGP)) {
  999.                 rdev->flags &= ~RADEON_IS_AGP;
  1000.         }
  1001.  
  1002.         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
  1003.                 radeon_agp_disable(rdev);
  1004.     }
  1005.  
  1006.         /* set DMA mask + need_dma32 flags.
  1007.          * PCIE - can handle 40-bits.
  1008.          * IGP - can handle 40-bits
  1009.          * AGP - generally dma32 is safest
  1010.          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
  1011.          */
  1012.         rdev->need_dma32 = false;
  1013.         if (rdev->flags & RADEON_IS_AGP)
  1014.                 rdev->need_dma32 = true;
  1015.         if ((rdev->flags & RADEON_IS_PCI) &&
  1016.             (rdev->family <= CHIP_RS740))
  1017.                 rdev->need_dma32 = true;
  1018.  
  1019.         dma_bits = rdev->need_dma32 ? 32 : 40;
  1020.         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
  1021.     if (r) {
  1022.                 rdev->need_dma32 = true;
  1023.                 dma_bits = 32;
  1024.         printk(KERN_WARNING "radeon: No suitable DMA available.\n");
  1025.     }
  1026.  
  1027.     /* Registers mapping */
  1028.     /* TODO: block userspace mapping of io register */
  1029.         spin_lock_init(&rdev->mmio_idx_lock);
  1030.     rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
  1031.     rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
  1032.         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
  1033.     if (rdev->rmmio == NULL) {
  1034.         return -ENOMEM;
  1035.     }
  1036.     DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
  1037.     DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
  1038.  
  1039.         /* io port mapping */
  1040.         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  1041.                 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
  1042.                         rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
  1043.                         rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
  1044.                         break;
  1045.                 }
  1046.         }
  1047.         if (rdev->rio_mem == NULL)
  1048.                 DRM_ERROR("Unable to find PCI I/O BAR\n");
  1049.  
  1050.  
  1051.         r = radeon_init(rdev);
  1052.         if (r)
  1053.         return r;
  1054.  
  1055. //   r = radeon_ib_ring_tests(rdev);
  1056. //   if (r)
  1057. //       DRM_ERROR("ib ring test failed (%d).\n", r);
  1058.  
  1059.         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
  1060.                 /* Acceleration not working on AGP card try again
  1061.                  * with fallback to PCI or PCIE GART
  1062.                  */
  1063.                 radeon_asic_reset(rdev);
  1064.                 radeon_fini(rdev);
  1065.                 radeon_agp_disable(rdev);
  1066.                 r = radeon_init(rdev);
  1067.                 if (r)
  1068.                 return r;
  1069.         }
  1070. //      if (radeon_testing) {
  1071. //              radeon_test_moves(rdev);
  1072. //    }
  1073. //      if ((radeon_testing & 2)) {
  1074. //              radeon_test_syncing(rdev);
  1075. //      }
  1076.    if (radeon_benchmarking) {
  1077.                 radeon_benchmark(rdev, radeon_benchmarking);
  1078.     }
  1079.         return 0;
  1080. }
  1081.  
  1082. /**
  1083.  * radeon_gpu_reset - reset the asic
  1084.  *
  1085.  * @rdev: radeon device pointer
  1086.  *
  1087.  * Attempt the reset the GPU if it has hung (all asics).
  1088.  * Returns 0 for success or an error on failure.
  1089.  */
  1090. int radeon_gpu_reset(struct radeon_device *rdev)
  1091. {
  1092.     unsigned ring_sizes[RADEON_NUM_RINGS];
  1093.     uint32_t *ring_data[RADEON_NUM_RINGS];
  1094.  
  1095.     bool saved = false;
  1096.  
  1097.     int i, r;
  1098.     int resched;
  1099.  
  1100. //    down_write(&rdev->exclusive_lock);
  1101.     radeon_save_bios_scratch_regs(rdev);
  1102.     /* block TTM */
  1103. //    resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
  1104.     radeon_suspend(rdev);
  1105.  
  1106.     for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  1107.         ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
  1108.                            &ring_data[i]);
  1109.         if (ring_sizes[i]) {
  1110.             saved = true;
  1111.             dev_info(rdev->dev, "Saved %d dwords of commands "
  1112.                  "on ring %d.\n", ring_sizes[i], i);
  1113.         }
  1114.     }
  1115.  
  1116. retry:
  1117.     r = radeon_asic_reset(rdev);
  1118.     if (!r) {
  1119.         dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
  1120.         radeon_resume(rdev);
  1121.     }
  1122.  
  1123.     radeon_restore_bios_scratch_regs(rdev);
  1124.     drm_helper_resume_force_mode(rdev->ddev);
  1125.  
  1126.     if (!r) {
  1127.         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  1128.             radeon_ring_restore(rdev, &rdev->ring[i],
  1129.                         ring_sizes[i], ring_data[i]);
  1130.             ring_sizes[i] = 0;
  1131.             ring_data[i] = NULL;
  1132.         }
  1133.  
  1134. //        r = radeon_ib_ring_tests(rdev);
  1135. //        if (r) {
  1136. //            dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
  1137. //            if (saved) {
  1138. //                saved = false;
  1139. //                radeon_suspend(rdev);
  1140. //                goto retry;
  1141. //            }
  1142. //        }
  1143.     } else {
  1144.         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  1145.             kfree(ring_data[i]);
  1146.         }
  1147.     }
  1148.  
  1149. //    ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
  1150.     if (r) {
  1151.         /* bad news, how to tell it to userspace ? */
  1152.         dev_info(rdev->dev, "GPU reset failed\n");
  1153.     }
  1154.  
  1155. //    up_write(&rdev->exclusive_lock);
  1156.     return r;
  1157. }
  1158.  
  1159.  
  1160. /*
  1161.  * Driver load/unload
  1162.  */
  1163. int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  1164. {
  1165.     struct radeon_device *rdev;
  1166.     int r;
  1167.  
  1168.     ENTER();
  1169.  
  1170.     rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  1171.     if (rdev == NULL) {
  1172.         return -ENOMEM;
  1173.     };
  1174.  
  1175.     dev->dev_private = (void *)rdev;
  1176.  
  1177.     /* update BUS flag */
  1178.     if (drm_device_is_agp(dev)) {
  1179.         flags |= RADEON_IS_AGP;
  1180.     } else if (drm_device_is_pcie(dev)) {
  1181.         flags |= RADEON_IS_PCIE;
  1182.     } else {
  1183.         flags |= RADEON_IS_PCI;
  1184.     }
  1185.  
  1186.     /* radeon_device_init should report only fatal error
  1187.      * like memory allocation failure or iomapping failure,
  1188.      * or memory manager initialization failure, it must
  1189.      * properly initialize the GPU MC controller and permit
  1190.      * VRAM allocation
  1191.      */
  1192.     r = radeon_device_init(rdev, dev, dev->pdev, flags);
  1193.     if (r) {
  1194.         DRM_ERROR("Fatal error while trying to initialize radeon.\n");
  1195.         return r;
  1196.     }
  1197.     /* Again modeset_init should fail only on fatal error
  1198.      * otherwise it should provide enough functionalities
  1199.      * for shadowfb to run
  1200.      */
  1201.     if( radeon_modeset )
  1202.     {
  1203.         r = radeon_modeset_init(rdev);
  1204.         if (r) {
  1205.             return r;
  1206.         }
  1207.     };
  1208.     return 0;
  1209. }
  1210.  
  1211. videomode_t usermode;
  1212.  
  1213.  
  1214. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  1215. {
  1216.     static struct drm_device *dev;
  1217.     int ret;
  1218.  
  1219.     ENTER();
  1220.  
  1221.     dev = kzalloc(sizeof(*dev), 0);
  1222.     if (!dev)
  1223.         return -ENOMEM;
  1224.  
  1225.  //   ret = pci_enable_device(pdev);
  1226.  //   if (ret)
  1227.  //       goto err_g1;
  1228.  
  1229.  //   pci_set_master(pdev);
  1230.  
  1231.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  1232.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  1233.  //       goto err_g2;
  1234.  //   }
  1235.  
  1236.     dev->pdev = pdev;
  1237.     dev->pci_device = pdev->device;
  1238.     dev->pci_vendor = pdev->vendor;
  1239.  
  1240.     INIT_LIST_HEAD(&dev->filelist);
  1241.     INIT_LIST_HEAD(&dev->ctxlist);
  1242.     INIT_LIST_HEAD(&dev->vmalist);
  1243.     INIT_LIST_HEAD(&dev->maplist);
  1244.  
  1245.     spin_lock_init(&dev->count_lock);
  1246.     mutex_init(&dev->struct_mutex);
  1247.     mutex_init(&dev->ctxlist_mutex);
  1248.  
  1249.  
  1250.     ret = radeon_driver_load_kms(dev, ent->driver_data );
  1251.     if (ret)
  1252.         goto err_g4;
  1253.  
  1254.     main_drm_device = dev;
  1255.  
  1256.     if( radeon_modeset )
  1257.         init_display_kms(dev->dev_private, &usermode);
  1258.     else
  1259.         init_display(dev->dev_private, &usermode);
  1260.  
  1261.  
  1262.     LEAVE();
  1263.  
  1264.     return 0;
  1265.  
  1266. err_g4:
  1267. //    drm_put_minor(&dev->primary);
  1268. //err_g3:
  1269. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  1270. //        drm_put_minor(&dev->control);
  1271. //err_g2:
  1272. //    pci_disable_device(pdev);
  1273. //err_g1:
  1274.     free(dev);
  1275.  
  1276.     LEAVE();
  1277.  
  1278.     return ret;
  1279. }
  1280.  
  1281. resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
  1282. {
  1283.     return pci_resource_start(dev->pdev, resource);
  1284. }
  1285.  
  1286. resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
  1287. {
  1288.     return pci_resource_len(dev->pdev, resource);
  1289. }
  1290.  
  1291.  
  1292. uint32_t __div64_32(uint64_t *n, uint32_t base)
  1293. {
  1294.         uint64_t rem = *n;
  1295.         uint64_t b = base;
  1296.         uint64_t res, d = 1;
  1297.         uint32_t high = rem >> 32;
  1298.  
  1299.         /* Reduce the thing a bit first */
  1300.         res = 0;
  1301.         if (high >= base) {
  1302.                 high /= base;
  1303.                 res = (uint64_t) high << 32;
  1304.                 rem -= (uint64_t) (high*base) << 32;
  1305.         }
  1306.  
  1307.         while ((int64_t)b > 0 && b < rem) {
  1308.                 b = b+b;
  1309.                 d = d+d;
  1310.         }
  1311.  
  1312.         do {
  1313.                 if (rem >= b) {
  1314.                         rem -= b;
  1315.                         res += d;
  1316.                 }
  1317.                 b >>= 1;
  1318.                 d >>= 1;
  1319.         } while (d);
  1320.  
  1321.         *n = res;
  1322.         return rem;
  1323. }
  1324.  
  1325.  
  1326. static struct pci_device_id pciidlist[] = {
  1327.     radeon_PCI_IDS
  1328. };
  1329.  
  1330.  
  1331. #define CURRENT_API     0x0200      /*      2.00     */
  1332. #define COMPATIBLE_API  0x0100      /*      1.00     */
  1333.  
  1334. #define API_VERSION     (COMPATIBLE_API << 16) | CURRENT_API
  1335.  
  1336. #define SRV_GETVERSION      0
  1337. #define SRV_ENUM_MODES      1
  1338. #define SRV_SET_MODE        2
  1339. #define SRV_GET_CAPS            3
  1340.  
  1341. #define SRV_CREATE_SURFACE      10
  1342. #define SRV_DESTROY_SURFACE     11
  1343. #define SRV_LOCK_SURFACE        12
  1344. #define SRV_UNLOCK_SURFACE      13
  1345. #define SRV_RESIZE_SURFACE      14
  1346. #define SRV_BLIT_BITMAP         15
  1347. #define SRV_BLIT_TEXTURE        16
  1348. #define SRV_BLIT_VIDEO          17
  1349.  
  1350.  
  1351.  
  1352. int r600_video_blit(uint64_t src_offset, int  x, int y,
  1353.                     int w, int h, int pitch);
  1354.  
  1355. #define check_input(size) \
  1356.     if( unlikely((inp==NULL)||(io->inp_size != (size))) )   \
  1357.         break;
  1358.  
  1359. #define check_output(size) \
  1360.     if( unlikely((outp==NULL)||(io->out_size != (size))) )   \
  1361.         break;
  1362.  
  1363. int _stdcall display_handler(ioctl_t *io)
  1364. {
  1365.     int    retval = -1;
  1366.     u32_t *inp;
  1367.     u32_t *outp;
  1368.  
  1369.     inp = io->input;
  1370.     outp = io->output;
  1371.  
  1372.     switch(io->io_code)
  1373.     {
  1374.         case SRV_GETVERSION:
  1375.             check_output(4);
  1376.             *outp  = API_VERSION;
  1377.             retval = 0;
  1378.             break;
  1379.  
  1380.         case SRV_ENUM_MODES:
  1381.             dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
  1382.                        inp, io->inp_size, io->out_size );
  1383.             check_output(4);
  1384.             if( radeon_modeset)
  1385.                 retval = get_modes((videomode_t*)inp, outp);
  1386.             break;
  1387.  
  1388.         case SRV_SET_MODE:
  1389.             dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
  1390.                        inp, io->inp_size);
  1391.             check_input(sizeof(videomode_t));
  1392.             if( radeon_modeset )
  1393.                 retval = set_user_mode((videomode_t*)inp);
  1394.             break;
  1395.  
  1396.         case SRV_GET_CAPS:
  1397.             retval = get_driver_caps((hwcaps_t*)inp);
  1398.             break;
  1399.  
  1400.         case SRV_CREATE_SURFACE:
  1401. //            check_input(8);
  1402.             retval = create_surface(main_drm_device, (struct io_call_10*)inp);
  1403.             break;
  1404.  
  1405.         case SRV_LOCK_SURFACE:
  1406.             retval = lock_surface((struct io_call_12*)inp);
  1407.             break;
  1408.  
  1409.         case SRV_BLIT_BITMAP:
  1410.             srv_blit_bitmap( inp[0], inp[1], inp[2],
  1411.                         inp[3], inp[4], inp[5], inp[6]);
  1412.  
  1413.     };
  1414.  
  1415.     return retval;
  1416. }
  1417.  
  1418. static char  log[256];
  1419. static pci_dev_t device;
  1420.  
  1421. u32_t drvEntry(int action, char *cmdline)
  1422. {
  1423.     struct radeon_device *rdev = NULL;
  1424.  
  1425.     const struct pci_device_id  *ent;
  1426.  
  1427.     int     err;
  1428.     u32_t   retval = 0;
  1429.  
  1430.     if(action != 1)
  1431.         return 0;
  1432.  
  1433.     if( GetService("DISPLAY") != 0 )
  1434.         return 0;
  1435.  
  1436.     if( cmdline && *cmdline )
  1437.         parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
  1438.  
  1439.     if(!dbg_open(log))
  1440.     {
  1441.         strcpy(log, "/TMP1/1/atikms.log");
  1442.  
  1443.         if(!dbg_open(log))
  1444.         {
  1445.             printf("Can't open %s\nExit\n", log);
  1446.             return 0;
  1447.         };
  1448.     }
  1449.     dbgprintf("Radeon RC13 cmdline %s\n", cmdline);
  1450.  
  1451.     enum_pci_devices();
  1452.  
  1453.     ent = find_pci_device(&device, pciidlist);
  1454.  
  1455.     if( unlikely(ent == NULL) )
  1456.     {
  1457.         dbgprintf("device not found\n");
  1458.         return 0;
  1459.     };
  1460.  
  1461.     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
  1462.                                 device.pci_dev.device);
  1463.  
  1464.     err = drm_get_dev(&device.pci_dev, ent);
  1465.  
  1466.     rdev = rdisplay->ddev->dev_private;
  1467.  
  1468.     err = RegService("DISPLAY", display_handler);
  1469.  
  1470.     if( err != 0)
  1471.         dbgprintf("Set DISPLAY handler\n");
  1472.  
  1473.     return err;
  1474. };
  1475.  
  1476. #define PCI_CLASS_REVISION      0x08
  1477. #define PCI_CLASS_DISPLAY_VGA   0x0300
  1478.  
  1479. int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)
  1480. {
  1481.     u16_t vendor, device;
  1482.     u32_t class;
  1483.     int   ret = 0;
  1484.  
  1485.     vendor   = id & 0xffff;
  1486.     device   = (id >> 16) & 0xffff;
  1487.  
  1488.     if(vendor == 0x1002)
  1489.     {
  1490.         class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
  1491.         class >>= 16;
  1492.  
  1493.         if( class == PCI_CLASS_DISPLAY_VGA)
  1494.             ret = 1;
  1495.     }
  1496.     return ret;
  1497. }
  1498.  
  1499. unsigned int hweight32(unsigned int w)
  1500. {
  1501.     unsigned int res = w - ((w >> 1) & 0x55555555);
  1502.     res = (res & 0x33333333) + ((res >> 2) & 0x33333333);
  1503.     res = (res + (res >> 4)) & 0x0F0F0F0F;
  1504.     res = res + (res >> 8);
  1505.     return (res + (res >> 16)) & 0x000000FF;
  1506. }
  1507.  
  1508.