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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. //#include <linux/console.h>
  29. #include <linux/slab.h>
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/radeon_drm.h>
  33. #include "radeon_reg.h"
  34. #include "radeon.h"
  35. #include "atom.h"
  36. #include "display.h"
  37.  
  38. #include <drm/drm_pciids.h>
  39.  
  40.  
  41. int radeon_no_wb   =  1;
  42. int radeon_modeset = -1;
  43. int radeon_dynclks = -1;
  44. int radeon_r4xx_atom = 0;
  45. int radeon_agpmode = 0;
  46. int radeon_vram_limit = 0;
  47. int radeon_gart_size = 512; /* default gart size */
  48. int radeon_benchmarking = 0;
  49. int radeon_testing = 0;
  50. int radeon_connector_table = 0;
  51. int radeon_tv = 1;
  52. int radeon_new_pll = -1;
  53. int radeon_dynpm = -1;
  54. int radeon_audio = 1;
  55. int radeon_hw_i2c = 0;
  56. int radeon_pcie_gen2 = 0;
  57. int radeon_disp_priority = 0;
  58. int radeon_lockup_timeout = 10000;
  59.  
  60.  
  61. int irq_override = 0;
  62.  
  63.  
  64. extern display_t *rdisplay;
  65.  
  66. void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms);
  67. int init_display(struct radeon_device *rdev, videomode_t *mode);
  68. int init_display_kms(struct radeon_device *rdev, videomode_t *mode);
  69.  
  70. int get_modes(videomode_t *mode, u32_t *count);
  71. int set_user_mode(videomode_t *mode);
  72. int r100_2D_test(struct radeon_device *rdev);
  73.  
  74.  
  75.  /* Legacy VGA regions */
  76. #define VGA_RSRC_NONE          0x00
  77. #define VGA_RSRC_LEGACY_IO     0x01
  78. #define VGA_RSRC_LEGACY_MEM    0x02
  79. #define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
  80. /* Non-legacy access */
  81. #define VGA_RSRC_NORMAL_IO     0x04
  82. #define VGA_RSRC_NORMAL_MEM    0x08
  83.  
  84.  
  85. static const char radeon_family_name[][16] = {
  86.         "R100",
  87.         "RV100",
  88.         "RS100",
  89.         "RV200",
  90.         "RS200",
  91.         "R200",
  92.         "RV250",
  93.         "RS300",
  94.         "RV280",
  95.         "R300",
  96.         "R350",
  97.         "RV350",
  98.         "RV380",
  99.         "R420",
  100.         "R423",
  101.         "RV410",
  102.         "RS400",
  103.         "RS480",
  104.         "RS600",
  105.         "RS690",
  106.         "RS740",
  107.         "RV515",
  108.         "R520",
  109.         "RV530",
  110.         "RV560",
  111.         "RV570",
  112.         "R580",
  113.         "R600",
  114.         "RV610",
  115.         "RV630",
  116.         "RV670",
  117.         "RV620",
  118.         "RV635",
  119.         "RS780",
  120.         "RS880",
  121.         "RV770",
  122.         "RV730",
  123.         "RV710",
  124.         "RV740",
  125.         "CEDAR",
  126.         "REDWOOD",
  127.         "JUNIPER",
  128.         "CYPRESS",
  129.         "HEMLOCK",
  130.         "PALM",
  131.         "SUMO",
  132.         "SUMO2",
  133.         "BARTS",
  134.         "TURKS",
  135.         "CAICOS",
  136.         "CAYMAN",
  137.         "ARUBA",
  138.         "TAHITI",
  139.         "PITCAIRN",
  140.         "VERDE",
  141.         "LAST",
  142. };
  143.  
  144. /**
  145.  * radeon_surface_init - Clear GPU surface registers.
  146.  *
  147.  * @rdev: radeon_device pointer
  148.  *
  149.  * Clear GPU surface registers (r1xx-r5xx).
  150.  */
  151. void radeon_surface_init(struct radeon_device *rdev)
  152. {
  153.     /* FIXME: check this out */
  154.     if (rdev->family < CHIP_R600) {
  155.         int i;
  156.  
  157.                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  158.            radeon_clear_surface_reg(rdev, i);
  159.         }
  160.                 /* enable surfaces */
  161.                 WREG32(RADEON_SURFACE_CNTL, 0);
  162.     }
  163. }
  164.  
  165. /*
  166.  * GPU scratch registers helpers function.
  167.  */
  168. /**
  169.  * radeon_scratch_init - Init scratch register driver information.
  170.  *
  171.  * @rdev: radeon_device pointer
  172.  *
  173.  * Init CP scratch register driver information (r1xx-r5xx)
  174.  */
  175. void radeon_scratch_init(struct radeon_device *rdev)
  176. {
  177.     int i;
  178.  
  179.     /* FIXME: check this out */
  180.     if (rdev->family < CHIP_R300) {
  181.         rdev->scratch.num_reg = 5;
  182.     } else {
  183.         rdev->scratch.num_reg = 7;
  184.     }
  185.         rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
  186.     for (i = 0; i < rdev->scratch.num_reg; i++) {
  187.         rdev->scratch.free[i] = true;
  188.                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
  189.     }
  190. }
  191.  
  192. /**
  193.  * radeon_scratch_get - Allocate a scratch register
  194.  *
  195.  * @rdev: radeon_device pointer
  196.  * @reg: scratch register mmio offset
  197.  *
  198.  * Allocate a CP scratch register for use by the driver (all asics).
  199.  * Returns 0 on success or -EINVAL on failure.
  200.  */
  201. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  202. {
  203.         int i;
  204.  
  205.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  206.                 if (rdev->scratch.free[i]) {
  207.                         rdev->scratch.free[i] = false;
  208.                         *reg = rdev->scratch.reg[i];
  209.                         return 0;
  210.                 }
  211.         }
  212.         return -EINVAL;
  213. }
  214.  
  215. /**
  216.  * radeon_scratch_free - Free a scratch register
  217.  *
  218.  * @rdev: radeon_device pointer
  219.  * @reg: scratch register mmio offset
  220.  *
  221.  * Free a CP scratch register allocated for use by the driver (all asics)
  222.  */
  223. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  224. {
  225.         int i;
  226.  
  227.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  228.                 if (rdev->scratch.reg[i] == reg) {
  229.                         rdev->scratch.free[i] = true;
  230.                         return;
  231.                 }
  232.         }
  233. }
  234.  
  235. /*
  236.  * radeon_wb_*()
  237.  * Writeback is the the method by which the the GPU updates special pages
  238.  * in memory with the status of certain GPU events (fences, ring pointers,
  239.  * etc.).
  240.  */
  241.  
  242. /**
  243.  * radeon_wb_disable - Disable Writeback
  244.  *
  245.  * @rdev: radeon_device pointer
  246.  *
  247.  * Disables Writeback (all asics).  Used for suspend.
  248.  */
  249. void radeon_wb_disable(struct radeon_device *rdev)
  250. {
  251.         int r;
  252.  
  253.         if (rdev->wb.wb_obj) {
  254.                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
  255.                 if (unlikely(r != 0))
  256.                         return;
  257.                 radeon_bo_kunmap(rdev->wb.wb_obj);
  258.                 radeon_bo_unpin(rdev->wb.wb_obj);
  259.                 radeon_bo_unreserve(rdev->wb.wb_obj);
  260.         }
  261.         rdev->wb.enabled = false;
  262. }
  263.  
  264. /**
  265.  * radeon_wb_fini - Disable Writeback and free memory
  266.  *
  267.  * @rdev: radeon_device pointer
  268.  *
  269.  * Disables Writeback and frees the Writeback memory (all asics).
  270.  * Used at driver shutdown.
  271.  */
  272. void radeon_wb_fini(struct radeon_device *rdev)
  273. {
  274.         radeon_wb_disable(rdev);
  275.         if (rdev->wb.wb_obj) {
  276.                 radeon_bo_unref(&rdev->wb.wb_obj);
  277.                 rdev->wb.wb = NULL;
  278.                 rdev->wb.wb_obj = NULL;
  279.         }
  280. }
  281.  
  282. /**
  283.  * radeon_wb_init- Init Writeback driver info and allocate memory
  284.  *
  285.  * @rdev: radeon_device pointer
  286.  *
  287.  * Disables Writeback and frees the Writeback memory (all asics).
  288.  * Used at driver startup.
  289.  * Returns 0 on success or an -error on failure.
  290.  */
  291. int radeon_wb_init(struct radeon_device *rdev)
  292. {
  293.         int r;
  294.  
  295.         if (rdev->wb.wb_obj == NULL) {
  296.                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
  297.                                      RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
  298.                 if (r) {
  299.                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
  300.                         return r;
  301.                 }
  302.         }
  303.         r = radeon_bo_reserve(rdev->wb.wb_obj, false);
  304.         if (unlikely(r != 0)) {
  305.                 radeon_wb_fini(rdev);
  306.                 return r;
  307.         }
  308.         r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
  309.                           &rdev->wb.gpu_addr);
  310.         if (r) {
  311.                 radeon_bo_unreserve(rdev->wb.wb_obj);
  312.                 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
  313.                 radeon_wb_fini(rdev);
  314.                 return r;
  315.         }
  316.         r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
  317.         radeon_bo_unreserve(rdev->wb.wb_obj);
  318.         if (r) {
  319.                 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
  320.                 radeon_wb_fini(rdev);
  321.                 return r;
  322.         }
  323.  
  324.         /* clear wb memory */
  325.         memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
  326.         /* disable event_write fences */
  327.         rdev->wb.use_event = false;
  328.         /* disabled via module param */
  329.         if (radeon_no_wb == 1) {
  330.                 rdev->wb.enabled = false;
  331.         } else {
  332.                 if (rdev->flags & RADEON_IS_AGP) {
  333.                 /* often unreliable on AGP */
  334.                         rdev->wb.enabled = false;
  335.                 } else if (rdev->family < CHIP_R300) {
  336.                         /* often unreliable on pre-r300 */
  337.                         rdev->wb.enabled = false;
  338.                 } else {
  339.                         rdev->wb.enabled = true;
  340.                         /* event_write fences are only available on r600+ */
  341.                         if (rdev->family >= CHIP_R600) {
  342.                                 rdev->wb.use_event = true;
  343.         }
  344.                 }
  345.         }
  346.         /* always use writeback/events on NI, APUs */
  347.         if (rdev->family >= CHIP_PALM) {
  348.                 rdev->wb.enabled = true;
  349.                 rdev->wb.use_event = true;
  350.         }
  351.  
  352.         dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
  353.  
  354.         return 0;
  355. }
  356.  
  357. /**
  358.  * radeon_vram_location - try to find VRAM location
  359.  * @rdev: radeon device structure holding all necessary informations
  360.  * @mc: memory controller structure holding memory informations
  361.  * @base: base address at which to put VRAM
  362.  *
  363.  * Function will place try to place VRAM at base address provided
  364.  * as parameter (which is so far either PCI aperture address or
  365.  * for IGP TOM base address).
  366.  *
  367.  * If there is not enough space to fit the unvisible VRAM in the 32bits
  368.  * address space then we limit the VRAM size to the aperture.
  369.  *
  370.  * If we are using AGP and if the AGP aperture doesn't allow us to have
  371.  * room for all the VRAM than we restrict the VRAM to the PCI aperture
  372.  * size and print a warning.
  373.  *
  374.  * This function will never fails, worst case are limiting VRAM.
  375.  *
  376.  * Note: GTT start, end, size should be initialized before calling this
  377.  * function on AGP platform.
  378.  *
  379.  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
  380.  * this shouldn't be a problem as we are using the PCI aperture as a reference.
  381.  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
  382.  * not IGP.
  383.  *
  384.  * Note: we use mc_vram_size as on some board we need to program the mc to
  385.  * cover the whole aperture even if VRAM size is inferior to aperture size
  386.  * Novell bug 204882 + along with lots of ubuntu ones
  387.  *
  388.  * Note: when limiting vram it's safe to overwritte real_vram_size because
  389.  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
  390.  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
  391.  * ones)
  392.  *
  393.  * Note: IGP TOM addr should be the same as the aperture addr, we don't
  394.  * explicitly check for that thought.
  395.  *
  396.  * FIXME: when reducing VRAM size align new size on power of 2.
  397.  */
  398. void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
  399. {
  400.         uint64_t limit = (uint64_t)radeon_vram_limit << 20;
  401.  
  402.         mc->vram_start = base;
  403.         if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
  404.                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
  405.                 mc->real_vram_size = mc->aper_size;
  406.                 mc->mc_vram_size = mc->aper_size;
  407.         }
  408.         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  409.         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
  410.                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
  411.                 mc->real_vram_size = mc->aper_size;
  412.                 mc->mc_vram_size = mc->aper_size;
  413.                 }
  414.         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  415.         if (limit && limit < mc->real_vram_size)
  416.                 mc->real_vram_size = limit;
  417.         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
  418.                         mc->mc_vram_size >> 20, mc->vram_start,
  419.                         mc->vram_end, mc->real_vram_size >> 20);
  420. }
  421.  
  422. /**
  423.  * radeon_gtt_location - try to find GTT location
  424.  * @rdev: radeon device structure holding all necessary informations
  425.  * @mc: memory controller structure holding memory informations
  426.  *
  427.  * Function will place try to place GTT before or after VRAM.
  428.  *
  429.  * If GTT size is bigger than space left then we ajust GTT size.
  430.  * Thus function will never fails.
  431.  *
  432.  * FIXME: when reducing GTT size align new size on power of 2.
  433.  */
  434. void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
  435. {
  436.         u64 size_af, size_bf;
  437.  
  438.         size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
  439.         size_bf = mc->vram_start & ~mc->gtt_base_align;
  440.         if (size_bf > size_af) {
  441.                 if (mc->gtt_size > size_bf) {
  442.                         dev_warn(rdev->dev, "limiting GTT\n");
  443.                         mc->gtt_size = size_bf;
  444.                 }
  445.                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
  446.         } else {
  447.                 if (mc->gtt_size > size_af) {
  448.                         dev_warn(rdev->dev, "limiting GTT\n");
  449.                         mc->gtt_size = size_af;
  450.                 }
  451.                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
  452.         }
  453.         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
  454.         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
  455.                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
  456. }
  457.  
  458. /*
  459.  * GPU helpers function.
  460.  */
  461. /**
  462.  * radeon_card_posted - check if the hw has already been initialized
  463.  *
  464.  * @rdev: radeon_device pointer
  465.  *
  466.  * Check if the asic has been initialized (all asics).
  467.  * Used at driver startup.
  468.  * Returns true if initialized or false if not.
  469.  */
  470. bool radeon_card_posted(struct radeon_device *rdev)
  471. {
  472.         uint32_t reg;
  473.  
  474.         /* first check CRTCs */
  475.         if (ASIC_IS_DCE41(rdev)) {
  476.                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
  477.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
  478.                 if (reg & EVERGREEN_CRTC_MASTER_EN)
  479.                         return true;
  480.         } else if (ASIC_IS_DCE4(rdev)) {
  481.                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
  482.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
  483.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
  484.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
  485.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
  486.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
  487.                 if (reg & EVERGREEN_CRTC_MASTER_EN)
  488.                         return true;
  489.         } else if (ASIC_IS_AVIVO(rdev)) {
  490.                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
  491.                       RREG32(AVIVO_D2CRTC_CONTROL);
  492.                 if (reg & AVIVO_CRTC_EN) {
  493.                         return true;
  494.                 }
  495.         } else {
  496.                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
  497.                       RREG32(RADEON_CRTC2_GEN_CNTL);
  498.                 if (reg & RADEON_CRTC_EN) {
  499.                         return true;
  500.                 }
  501.         }
  502.  
  503.         /* then check MEM_SIZE, in case the crtcs are off */
  504.         if (rdev->family >= CHIP_R600)
  505.                 reg = RREG32(R600_CONFIG_MEMSIZE);
  506.         else
  507.                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
  508.  
  509.         if (reg)
  510.                 return true;
  511.  
  512.         return false;
  513.  
  514. }
  515.  
  516. /**
  517.  * radeon_update_bandwidth_info - update display bandwidth params
  518.  *
  519.  * @rdev: radeon_device pointer
  520.  *
  521.  * Used when sclk/mclk are switched or display modes are set.
  522.  * params are used to calculate display watermarks (all asics)
  523.  */
  524. void radeon_update_bandwidth_info(struct radeon_device *rdev)
  525. {
  526.         fixed20_12 a;
  527.         u32 sclk = rdev->pm.current_sclk;
  528.         u32 mclk = rdev->pm.current_mclk;
  529.  
  530.         /* sclk/mclk in Mhz */
  531.                 a.full = dfixed_const(100);
  532.                 rdev->pm.sclk.full = dfixed_const(sclk);
  533.                 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
  534.                 rdev->pm.mclk.full = dfixed_const(mclk);
  535.                 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
  536.  
  537.         if (rdev->flags & RADEON_IS_IGP) {
  538.                 a.full = dfixed_const(16);
  539.                 /* core_bandwidth = sclk(Mhz) * 16 */
  540.                 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
  541.         }
  542. }
  543.  
  544. /**
  545.  * radeon_boot_test_post_card - check and possibly initialize the hw
  546.  *
  547.  * @rdev: radeon_device pointer
  548.  *
  549.  * Check if the asic is initialized and if not, attempt to initialize
  550.  * it (all asics).
  551.  * Returns true if initialized or false if not.
  552.  */
  553. bool radeon_boot_test_post_card(struct radeon_device *rdev)
  554. {
  555.         if (radeon_card_posted(rdev))
  556.                 return true;
  557.  
  558.         if (rdev->bios) {
  559.                 DRM_INFO("GPU not posted. posting now...\n");
  560.                 if (rdev->is_atom_bios)
  561.                         atom_asic_init(rdev->mode_info.atom_context);
  562.                 else
  563.                         radeon_combios_asic_init(rdev->ddev);
  564.                 return true;
  565.         } else {
  566.                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  567.                 return false;
  568.         }
  569. }
  570.  
  571. /**
  572.  * radeon_dummy_page_init - init dummy page used by the driver
  573.  *
  574.  * @rdev: radeon_device pointer
  575.  *
  576.  * Allocate the dummy page used by the driver (all asics).
  577.  * This dummy page is used by the driver as a filler for gart entries
  578.  * when pages are taken out of the GART
  579.  * Returns 0 on sucess, -ENOMEM on failure.
  580.  */
  581. int radeon_dummy_page_init(struct radeon_device *rdev)
  582. {
  583.         if (rdev->dummy_page.page)
  584.                 return 0;
  585.     rdev->dummy_page.page = (void*)AllocPage();
  586.         if (rdev->dummy_page.page == NULL)
  587.                 return -ENOMEM;
  588.     rdev->dummy_page.addr = MapIoMem((addr_t)rdev->dummy_page.page, 4096, 3);
  589.         if (!rdev->dummy_page.addr) {
  590. //       __free_page(rdev->dummy_page.page);
  591.                 rdev->dummy_page.page = NULL;
  592.                 return -ENOMEM;
  593.         }
  594.         return 0;
  595. }
  596.  
  597. /**
  598.  * radeon_dummy_page_fini - free dummy page used by the driver
  599.  *
  600.  * @rdev: radeon_device pointer
  601.  *
  602.  * Frees the dummy page used by the driver (all asics).
  603.  */
  604. void radeon_dummy_page_fini(struct radeon_device *rdev)
  605. {
  606.         if (rdev->dummy_page.page == NULL)
  607.                 return;
  608.     KernelFree((void*)rdev->dummy_page.addr);
  609.         rdev->dummy_page.page = NULL;
  610. }
  611.  
  612.  
  613. /* ATOM accessor methods */
  614. /*
  615.  * ATOM is an interpreted byte code stored in tables in the vbios.  The
  616.  * driver registers callbacks to access registers and the interpreter
  617.  * in the driver parses the tables and executes then to program specific
  618.  * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
  619.  * atombios.h, and atom.c
  620.  */
  621.  
  622. /**
  623.  * cail_pll_read - read PLL register
  624.  *
  625.  * @info: atom card_info pointer
  626.  * @reg: PLL register offset
  627.  *
  628.  * Provides a PLL register accessor for the atom interpreter (r4xx+).
  629.  * Returns the value of the PLL register.
  630.  */
  631. static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
  632. {
  633.     struct radeon_device *rdev = info->dev->dev_private;
  634.     uint32_t r;
  635.  
  636.     r = rdev->pll_rreg(rdev, reg);
  637.     return r;
  638. }
  639.  
  640. /**
  641.  * cail_pll_write - write PLL register
  642.  *
  643.  * @info: atom card_info pointer
  644.  * @reg: PLL register offset
  645.  * @val: value to write to the pll register
  646.  *
  647.  * Provides a PLL register accessor for the atom interpreter (r4xx+).
  648.  */
  649. static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
  650. {
  651.     struct radeon_device *rdev = info->dev->dev_private;
  652.  
  653.     rdev->pll_wreg(rdev, reg, val);
  654. }
  655.  
  656. /**
  657.  * cail_mc_read - read MC (Memory Controller) register
  658.  *
  659.  * @info: atom card_info pointer
  660.  * @reg: MC register offset
  661.  *
  662.  * Provides an MC register accessor for the atom interpreter (r4xx+).
  663.  * Returns the value of the MC register.
  664.  */
  665. static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
  666. {
  667.     struct radeon_device *rdev = info->dev->dev_private;
  668.     uint32_t r;
  669.  
  670.     r = rdev->mc_rreg(rdev, reg);
  671.     return r;
  672. }
  673.  
  674. /**
  675.  * cail_mc_write - write MC (Memory Controller) register
  676.  *
  677.  * @info: atom card_info pointer
  678.  * @reg: MC register offset
  679.  * @val: value to write to the pll register
  680.  *
  681.  * Provides a MC register accessor for the atom interpreter (r4xx+).
  682.  */
  683. static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
  684. {
  685.     struct radeon_device *rdev = info->dev->dev_private;
  686.  
  687.     rdev->mc_wreg(rdev, reg, val);
  688. }
  689.  
  690. /**
  691.  * cail_reg_write - write MMIO register
  692.  *
  693.  * @info: atom card_info pointer
  694.  * @reg: MMIO register offset
  695.  * @val: value to write to the pll register
  696.  *
  697.  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
  698.  */
  699. static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
  700. {
  701.     struct radeon_device *rdev = info->dev->dev_private;
  702.  
  703.     WREG32(reg*4, val);
  704. }
  705.  
  706. /**
  707.  * cail_reg_read - read MMIO register
  708.  *
  709.  * @info: atom card_info pointer
  710.  * @reg: MMIO register offset
  711.  *
  712.  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
  713.  * Returns the value of the MMIO register.
  714.  */
  715. static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
  716. {
  717.     struct radeon_device *rdev = info->dev->dev_private;
  718.     uint32_t r;
  719.  
  720.     r = RREG32(reg*4);
  721.     return r;
  722. }
  723.  
  724. /**
  725.  * cail_ioreg_write - write IO register
  726.  *
  727.  * @info: atom card_info pointer
  728.  * @reg: IO register offset
  729.  * @val: value to write to the pll register
  730.  *
  731.  * Provides a IO register accessor for the atom interpreter (r4xx+).
  732.  */
  733. static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
  734. {
  735.         struct radeon_device *rdev = info->dev->dev_private;
  736.  
  737.         WREG32_IO(reg*4, val);
  738. }
  739.  
  740. /**
  741.  * cail_ioreg_read - read IO register
  742.  *
  743.  * @info: atom card_info pointer
  744.  * @reg: IO register offset
  745.  *
  746.  * Provides an IO register accessor for the atom interpreter (r4xx+).
  747.  * Returns the value of the IO register.
  748.  */
  749. static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
  750. {
  751.         struct radeon_device *rdev = info->dev->dev_private;
  752.         uint32_t r;
  753.  
  754.         r = RREG32_IO(reg*4);
  755.         return r;
  756. }
  757.  
  758. /**
  759.  * radeon_atombios_init - init the driver info and callbacks for atombios
  760.  *
  761.  * @rdev: radeon_device pointer
  762.  *
  763.  * Initializes the driver info and register access callbacks for the
  764.  * ATOM interpreter (r4xx+).
  765.  * Returns 0 on sucess, -ENOMEM on failure.
  766.  * Called at driver startup.
  767.  */
  768. int radeon_atombios_init(struct radeon_device *rdev)
  769. {
  770.         struct card_info *atom_card_info =
  771.             kzalloc(sizeof(struct card_info), GFP_KERNEL);
  772.  
  773.         if (!atom_card_info)
  774.                 return -ENOMEM;
  775.  
  776.         rdev->mode_info.atom_card_info = atom_card_info;
  777.         atom_card_info->dev = rdev->ddev;
  778.         atom_card_info->reg_read = cail_reg_read;
  779.         atom_card_info->reg_write = cail_reg_write;
  780.         /* needed for iio ops */
  781.         if (rdev->rio_mem) {
  782.                 atom_card_info->ioreg_read = cail_ioreg_read;
  783.                 atom_card_info->ioreg_write = cail_ioreg_write;
  784.         } else {
  785.                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
  786.                 atom_card_info->ioreg_read = cail_reg_read;
  787.                 atom_card_info->ioreg_write = cail_reg_write;
  788.         }
  789.         atom_card_info->mc_read = cail_mc_read;
  790.         atom_card_info->mc_write = cail_mc_write;
  791.         atom_card_info->pll_read = cail_pll_read;
  792.         atom_card_info->pll_write = cail_pll_write;
  793.  
  794.         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
  795.         mutex_init(&rdev->mode_info.atom_context->mutex);
  796.     radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
  797.         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
  798.     return 0;
  799. }
  800.  
  801. /**
  802.  * radeon_atombios_fini - free the driver info and callbacks for atombios
  803.  *
  804.  * @rdev: radeon_device pointer
  805.  *
  806.  * Frees the driver info and register access callbacks for the ATOM
  807.  * interpreter (r4xx+).
  808.  * Called at driver shutdown.
  809.  */
  810. void radeon_atombios_fini(struct radeon_device *rdev)
  811. {
  812.         if (rdev->mode_info.atom_context) {
  813.                 kfree(rdev->mode_info.atom_context->scratch);
  814.         kfree(rdev->mode_info.atom_context);
  815.         }
  816.         kfree(rdev->mode_info.atom_card_info);
  817. }
  818.  
  819. /* COMBIOS */
  820. /*
  821.  * COMBIOS is the bios format prior to ATOM. It provides
  822.  * command tables similar to ATOM, but doesn't have a unified
  823.  * parser.  See radeon_combios.c
  824.  */
  825.  
  826. /**
  827.  * radeon_combios_init - init the driver info for combios
  828.  *
  829.  * @rdev: radeon_device pointer
  830.  *
  831.  * Initializes the driver info for combios (r1xx-r3xx).
  832.  * Returns 0 on sucess.
  833.  * Called at driver startup.
  834.  */
  835. int radeon_combios_init(struct radeon_device *rdev)
  836. {
  837.         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
  838.         return 0;
  839. }
  840.  
  841. /**
  842.  * radeon_combios_fini - free the driver info for combios
  843.  *
  844.  * @rdev: radeon_device pointer
  845.  *
  846.  * Frees the driver info for combios (r1xx-r3xx).
  847.  * Called at driver shutdown.
  848.  */
  849. void radeon_combios_fini(struct radeon_device *rdev)
  850. {
  851. }
  852.  
  853. /* if we get transitioned to only one device, take VGA back */
  854. /**
  855.  * radeon_vga_set_decode - enable/disable vga decode
  856.  *
  857.  * @cookie: radeon_device pointer
  858.  * @state: enable/disable vga decode
  859.  *
  860.  * Enable/disable vga decode (all asics).
  861.  * Returns VGA resource flags.
  862.  */
  863. static unsigned int radeon_vga_set_decode(void *cookie, bool state)
  864. {
  865.         struct radeon_device *rdev = cookie;
  866.         radeon_vga_set_state(rdev, state);
  867.         if (state)
  868.                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  869.                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  870.         else
  871.                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  872. }
  873.  
  874. /**
  875.  * radeon_check_pot_argument - check that argument is a power of two
  876.  *
  877.  * @arg: value to check
  878.  *
  879.  * Validates that a certain argument is a power of two (all asics).
  880.  * Returns true if argument is valid.
  881.  */
  882. static bool radeon_check_pot_argument(int arg)
  883. {
  884.         return (arg & (arg - 1)) == 0;
  885. }
  886.  
  887. /**
  888.  * radeon_check_arguments - validate module params
  889.  *
  890.  * @rdev: radeon_device pointer
  891.  *
  892.  * Validates certain module parameters and updates
  893.  * the associated values used by the driver (all asics).
  894.  */
  895. static void radeon_check_arguments(struct radeon_device *rdev)
  896. {
  897.         /* vramlimit must be a power of two */
  898.         if (!radeon_check_pot_argument(radeon_vram_limit)) {
  899.                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
  900.                                 radeon_vram_limit);
  901.                 radeon_vram_limit = 0;
  902.         }
  903.  
  904.         /* gtt size must be power of two and greater or equal to 32M */
  905.         if (radeon_gart_size < 32) {
  906.                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
  907.                                 radeon_gart_size);
  908.                 radeon_gart_size = 512;
  909.  
  910.         } else if (!radeon_check_pot_argument(radeon_gart_size)) {
  911.                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
  912.                                 radeon_gart_size);
  913.                 radeon_gart_size = 512;
  914.         }
  915.         rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
  916.  
  917.         /* AGP mode can only be -1, 1, 2, 4, 8 */
  918.         switch (radeon_agpmode) {
  919.         case -1:
  920.         case 0:
  921.         case 1:
  922.         case 2:
  923.         case 4:
  924.         case 8:
  925.                 break;
  926.         default:
  927.                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
  928.                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
  929.                 radeon_agpmode = 0;
  930.                 break;
  931.         }
  932. }
  933.  
  934. int radeon_device_init(struct radeon_device *rdev,
  935.                struct drm_device *ddev,
  936.                struct pci_dev *pdev,
  937.                uint32_t flags)
  938. {
  939.         int r, i;
  940.         int dma_bits;
  941.  
  942.     rdev->shutdown = false;
  943.     rdev->ddev = ddev;
  944.     rdev->pdev = pdev;
  945.     rdev->flags = flags;
  946.     rdev->family = flags & RADEON_FAMILY_MASK;
  947.     rdev->is_atom_bios = false;
  948.     rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
  949.     rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  950.         rdev->accel_working = false;
  951.         /* set up ring ids */
  952.         for (i = 0; i < RADEON_NUM_RINGS; i++) {
  953.                 rdev->ring[i].idx = i;
  954.         }
  955.  
  956.         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
  957.                 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
  958.                 pdev->subsystem_vendor, pdev->subsystem_device);
  959.  
  960.     /* mutex initialization are all done here so we
  961.      * can recall function without having locking issues */
  962.         mutex_init(&rdev->ring_lock);
  963.         mutex_init(&rdev->dc_hw_i2c_mutex);
  964.         atomic_set(&rdev->ih.lock, 0);
  965.         mutex_init(&rdev->gem.mutex);
  966.         mutex_init(&rdev->pm.mutex);
  967.         mutex_init(&rdev->gpu_clock_mutex);
  968.         init_rwsem(&rdev->pm.mclk_lock);
  969.         init_rwsem(&rdev->exclusive_lock);
  970.         init_waitqueue_head(&rdev->irq.vblank_queue);
  971.         r = radeon_gem_init(rdev);
  972.         if (r)
  973.                 return r;
  974.         /* initialize vm here */
  975.         mutex_init(&rdev->vm_manager.lock);
  976.         /* Adjust VM size here.
  977.          * Currently set to 4GB ((1 << 20) 4k pages).
  978.          * Max GPUVM size for cayman and SI is 40 bits.
  979.          */
  980.         rdev->vm_manager.max_pfn = 1 << 20;
  981.         INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
  982.  
  983.         /* Set asic functions */
  984.         r = radeon_asic_init(rdev);
  985.         if (r)
  986.                 return r;
  987.         radeon_check_arguments(rdev);
  988.  
  989.         /* all of the newer IGP chips have an internal gart
  990.          * However some rs4xx report as AGP, so remove that here.
  991.          */
  992.         if ((rdev->family >= CHIP_RS400) &&
  993.             (rdev->flags & RADEON_IS_IGP)) {
  994.                 rdev->flags &= ~RADEON_IS_AGP;
  995.         }
  996.  
  997.         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
  998.                 radeon_agp_disable(rdev);
  999.     }
  1000.  
  1001.         /* set DMA mask + need_dma32 flags.
  1002.          * PCIE - can handle 40-bits.
  1003.          * IGP - can handle 40-bits
  1004.          * AGP - generally dma32 is safest
  1005.          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
  1006.          */
  1007.         rdev->need_dma32 = false;
  1008.         if (rdev->flags & RADEON_IS_AGP)
  1009.                 rdev->need_dma32 = true;
  1010.         if ((rdev->flags & RADEON_IS_PCI) &&
  1011.             (rdev->family <= CHIP_RS740))
  1012.                 rdev->need_dma32 = true;
  1013.  
  1014.         dma_bits = rdev->need_dma32 ? 32 : 40;
  1015.         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
  1016.     if (r) {
  1017.                 rdev->need_dma32 = true;
  1018.                 dma_bits = 32;
  1019.         printk(KERN_WARNING "radeon: No suitable DMA available.\n");
  1020.     }
  1021.  
  1022.     /* Registers mapping */
  1023.     /* TODO: block userspace mapping of io register */
  1024.     rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
  1025.     rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
  1026.         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
  1027.     if (rdev->rmmio == NULL) {
  1028.         return -ENOMEM;
  1029.     }
  1030.     DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
  1031.     DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
  1032.  
  1033.         /* io port mapping */
  1034.         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  1035.                 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
  1036.                         rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
  1037.                         rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
  1038.                         break;
  1039.                 }
  1040.         }
  1041.         if (rdev->rio_mem == NULL)
  1042.                 DRM_ERROR("Unable to find PCI I/O BAR\n");
  1043.  
  1044.  
  1045.         r = radeon_init(rdev);
  1046.         if (r)
  1047.         return r;
  1048.  
  1049.         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
  1050.                 /* Acceleration not working on AGP card try again
  1051.                  * with fallback to PCI or PCIE GART
  1052.                  */
  1053.                 radeon_asic_reset(rdev);
  1054.                 radeon_fini(rdev);
  1055.                 radeon_agp_disable(rdev);
  1056.                 r = radeon_init(rdev);
  1057.                 if (r)
  1058.                 return r;
  1059.         }
  1060. //      if (radeon_testing) {
  1061. //              radeon_test_moves(rdev);
  1062. //    }
  1063. //      if ((radeon_testing & 2)) {
  1064. //              radeon_test_syncing(rdev);
  1065. //      }
  1066.    if (radeon_benchmarking) {
  1067.                 radeon_benchmark(rdev, radeon_benchmarking);
  1068.     }
  1069.         return 0;
  1070. }
  1071.  
  1072. /**
  1073.  * radeon_gpu_reset - reset the asic
  1074.  *
  1075.  * @rdev: radeon device pointer
  1076.  *
  1077.  * Attempt the reset the GPU if it has hung (all asics).
  1078.  * Returns 0 for success or an error on failure.
  1079.  */
  1080. int radeon_gpu_reset(struct radeon_device *rdev)
  1081. {
  1082.     unsigned ring_sizes[RADEON_NUM_RINGS];
  1083.     uint32_t *ring_data[RADEON_NUM_RINGS];
  1084.  
  1085.     bool saved = false;
  1086.  
  1087.     int i, r;
  1088.     int resched;
  1089.  
  1090. //    down_write(&rdev->exclusive_lock);
  1091.     radeon_save_bios_scratch_regs(rdev);
  1092.     /* block TTM */
  1093. //    resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
  1094.     radeon_suspend(rdev);
  1095.  
  1096.     for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  1097.         ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
  1098.                            &ring_data[i]);
  1099.         if (ring_sizes[i]) {
  1100.             saved = true;
  1101.             dev_info(rdev->dev, "Saved %d dwords of commands "
  1102.                  "on ring %d.\n", ring_sizes[i], i);
  1103.         }
  1104.     }
  1105.  
  1106. retry:
  1107.     r = radeon_asic_reset(rdev);
  1108.     if (!r) {
  1109.         dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
  1110.         radeon_resume(rdev);
  1111.     }
  1112.  
  1113.     radeon_restore_bios_scratch_regs(rdev);
  1114.     drm_helper_resume_force_mode(rdev->ddev);
  1115.  
  1116.     if (!r) {
  1117.         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  1118.             radeon_ring_restore(rdev, &rdev->ring[i],
  1119.                         ring_sizes[i], ring_data[i]);
  1120.             ring_sizes[i] = 0;
  1121.             ring_data[i] = NULL;
  1122.         }
  1123.  
  1124.         r = radeon_ib_ring_tests(rdev);
  1125.         if (r) {
  1126.             dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
  1127.             if (saved) {
  1128.                 saved = false;
  1129.                 radeon_suspend(rdev);
  1130.                 goto retry;
  1131.             }
  1132.         }
  1133.     } else {
  1134.         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  1135.             kfree(ring_data[i]);
  1136.         }
  1137.     }
  1138.  
  1139. //    ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
  1140.     if (r) {
  1141.         /* bad news, how to tell it to userspace ? */
  1142.         dev_info(rdev->dev, "GPU reset failed\n");
  1143.     }
  1144.  
  1145. //    up_write(&rdev->exclusive_lock);
  1146.     return r;
  1147. }
  1148.  
  1149.  
  1150.  
  1151. /*
  1152.  * Driver load/unload
  1153.  */
  1154. int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  1155. {
  1156.     struct radeon_device *rdev;
  1157.     int r;
  1158.  
  1159.     ENTER();
  1160.  
  1161.     rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  1162.     if (rdev == NULL) {
  1163.         return -ENOMEM;
  1164.     };
  1165.  
  1166.     dev->dev_private = (void *)rdev;
  1167.  
  1168.     /* update BUS flag */
  1169.     if (drm_device_is_agp(dev)) {
  1170.         flags |= RADEON_IS_AGP;
  1171.     } else if (drm_device_is_pcie(dev)) {
  1172.         flags |= RADEON_IS_PCIE;
  1173.     } else {
  1174.         flags |= RADEON_IS_PCI;
  1175.     }
  1176.  
  1177.     /* radeon_device_init should report only fatal error
  1178.      * like memory allocation failure or iomapping failure,
  1179.      * or memory manager initialization failure, it must
  1180.      * properly initialize the GPU MC controller and permit
  1181.      * VRAM allocation
  1182.      */
  1183.     r = radeon_device_init(rdev, dev, dev->pdev, flags);
  1184.     if (r) {
  1185.         DRM_ERROR("Fatal error while trying to initialize radeon.\n");
  1186.         return r;
  1187.     }
  1188.     /* Again modeset_init should fail only on fatal error
  1189.      * otherwise it should provide enough functionalities
  1190.      * for shadowfb to run
  1191.      */
  1192.     if( radeon_modeset )
  1193.     {
  1194.         r = radeon_modeset_init(rdev);
  1195.         if (r) {
  1196.             return r;
  1197.         }
  1198.     };
  1199.     return 0;
  1200. }
  1201.  
  1202. videomode_t usermode;
  1203.  
  1204.  
  1205. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  1206. {
  1207.     static struct drm_device *dev;
  1208.     int ret;
  1209.  
  1210.     ENTER();
  1211.  
  1212.     dev = kzalloc(sizeof(*dev), 0);
  1213.     if (!dev)
  1214.         return -ENOMEM;
  1215.  
  1216.  //   ret = pci_enable_device(pdev);
  1217.  //   if (ret)
  1218.  //       goto err_g1;
  1219.  
  1220.  //   pci_set_master(pdev);
  1221.  
  1222.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  1223.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  1224.  //       goto err_g2;
  1225.  //   }
  1226.  
  1227.     dev->pdev = pdev;
  1228.     dev->pci_device = pdev->device;
  1229.     dev->pci_vendor = pdev->vendor;
  1230.  
  1231.     INIT_LIST_HEAD(&dev->filelist);
  1232.     INIT_LIST_HEAD(&dev->ctxlist);
  1233.     INIT_LIST_HEAD(&dev->vmalist);
  1234.     INIT_LIST_HEAD(&dev->maplist);
  1235.  
  1236.     spin_lock_init(&dev->count_lock);
  1237.     mutex_init(&dev->struct_mutex);
  1238.     mutex_init(&dev->ctxlist_mutex);
  1239.  
  1240.  
  1241.     ret = radeon_driver_load_kms(dev, ent->driver_data );
  1242.     if (ret)
  1243.         goto err_g4;
  1244.  
  1245.     if( radeon_modeset )
  1246.         init_display_kms(dev->dev_private, &usermode);
  1247.     else
  1248.         init_display(dev->dev_private, &usermode);
  1249.  
  1250.  
  1251.     LEAVE();
  1252.  
  1253.     return 0;
  1254.  
  1255. err_g4:
  1256. //    drm_put_minor(&dev->primary);
  1257. //err_g3:
  1258. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  1259. //        drm_put_minor(&dev->control);
  1260. //err_g2:
  1261. //    pci_disable_device(pdev);
  1262. //err_g1:
  1263.     free(dev);
  1264.  
  1265.     LEAVE();
  1266.  
  1267.     return ret;
  1268. }
  1269.  
  1270. resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
  1271. {
  1272.     return pci_resource_start(dev->pdev, resource);
  1273. }
  1274.  
  1275. resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
  1276. {
  1277.     return pci_resource_len(dev->pdev, resource);
  1278. }
  1279.  
  1280.  
  1281. uint32_t __div64_32(uint64_t *n, uint32_t base)
  1282. {
  1283.         uint64_t rem = *n;
  1284.         uint64_t b = base;
  1285.         uint64_t res, d = 1;
  1286.         uint32_t high = rem >> 32;
  1287.  
  1288.         /* Reduce the thing a bit first */
  1289.         res = 0;
  1290.         if (high >= base) {
  1291.                 high /= base;
  1292.                 res = (uint64_t) high << 32;
  1293.                 rem -= (uint64_t) (high*base) << 32;
  1294.         }
  1295.  
  1296.         while ((int64_t)b > 0 && b < rem) {
  1297.                 b = b+b;
  1298.                 d = d+d;
  1299.         }
  1300.  
  1301.         do {
  1302.                 if (rem >= b) {
  1303.                         rem -= b;
  1304.                         res += d;
  1305.                 }
  1306.                 b >>= 1;
  1307.                 d >>= 1;
  1308.         } while (d);
  1309.  
  1310.         *n = res;
  1311.         return rem;
  1312. }
  1313.  
  1314.  
  1315. static struct pci_device_id pciidlist[] = {
  1316.     radeon_PCI_IDS
  1317. };
  1318.  
  1319.  
  1320. #define API_VERSION     0x01000100
  1321.  
  1322. #define SRV_GETVERSION      0
  1323. #define SRV_ENUM_MODES      1
  1324. #define SRV_SET_MODE        2
  1325.  
  1326. #define SRV_CREATE_VIDEO    9
  1327. #define SRV_BLIT_VIDEO     10
  1328. #define SRV_CREATE_BITMAP  11
  1329.  
  1330.  
  1331. int r600_video_blit(uint64_t src_offset, int  x, int y,
  1332.                     int w, int h, int pitch);
  1333.  
  1334. #define check_input(size) \
  1335.     if( unlikely((inp==NULL)||(io->inp_size != (size))) )   \
  1336.         break;
  1337.  
  1338. #define check_output(size) \
  1339.     if( unlikely((outp==NULL)||(io->out_size != (size))) )   \
  1340.         break;
  1341.  
  1342. int _stdcall display_handler(ioctl_t *io)
  1343. {
  1344.     int    retval = -1;
  1345.     u32_t *inp;
  1346.     u32_t *outp;
  1347.  
  1348.     inp = io->input;
  1349.     outp = io->output;
  1350.  
  1351.     switch(io->io_code)
  1352.     {
  1353.         case SRV_GETVERSION:
  1354.             check_output(4);
  1355.             *outp  = API_VERSION;
  1356.             retval = 0;
  1357.             break;
  1358.  
  1359.         case SRV_ENUM_MODES:
  1360.             dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
  1361.                        inp, io->inp_size, io->out_size );
  1362.             check_output(4);
  1363.             if( radeon_modeset)
  1364.                 retval = get_modes((videomode_t*)inp, outp);
  1365.             break;
  1366.  
  1367.         case SRV_SET_MODE:
  1368.             dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
  1369.                        inp, io->inp_size);
  1370.             check_input(sizeof(videomode_t));
  1371.             if( radeon_modeset )
  1372.                 retval = set_user_mode((videomode_t*)inp);
  1373.             break;
  1374.  
  1375.         case SRV_CREATE_VIDEO:
  1376. //            retval = r600_create_video(inp[0], inp[1], outp);
  1377.             break;
  1378.  
  1379.         case SRV_BLIT_VIDEO:
  1380. //            r600_video_blit( ((uint64_t*)inp)[0], inp[2], inp[3],
  1381. //                    inp[4], inp[5], inp[6]);
  1382.  
  1383.             retval = 0;
  1384.             break;
  1385.  
  1386.         case SRV_CREATE_BITMAP:
  1387.             check_input(8);
  1388.             check_output(4);
  1389. //            retval = create_bitmap(outp, inp[0], inp[1]);
  1390.             break;
  1391.  
  1392.     };
  1393.  
  1394.     return retval;
  1395. }
  1396.  
  1397. static char  log[256];
  1398. static pci_dev_t device;
  1399.  
  1400. u32_t drvEntry(int action, char *cmdline)
  1401. {
  1402.     struct radeon_device *rdev = NULL;
  1403.  
  1404.     const struct pci_device_id  *ent;
  1405.  
  1406.     int     err;
  1407.     u32_t   retval = 0;
  1408.  
  1409.     if(action != 1)
  1410.         return 0;
  1411.  
  1412.     if( GetService("DISPLAY") != 0 )
  1413.         return 0;
  1414.  
  1415.     if( cmdline && *cmdline )
  1416.         parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
  1417.  
  1418.     if(!dbg_open(log))
  1419.     {
  1420.         strcpy(log, "/RD/1/DRIVERS/atikms.log");
  1421.  
  1422.         if(!dbg_open(log))
  1423.         {
  1424.             printf("Can't open %s\nExit\n", log);
  1425.             return 0;
  1426.         };
  1427.     }
  1428.     dbgprintf("Radeon RC12 preview 1 cmdline %s\n", cmdline);
  1429.  
  1430.     enum_pci_devices();
  1431.  
  1432.     ent = find_pci_device(&device, pciidlist);
  1433.  
  1434.     if( unlikely(ent == NULL) )
  1435.     {
  1436.         dbgprintf("device not found\n");
  1437.         return 0;
  1438.     };
  1439.  
  1440.     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
  1441.                                 device.pci_dev.device);
  1442.  
  1443.     err = drm_get_dev(&device.pci_dev, ent);
  1444.  
  1445.     rdev = rdisplay->ddev->dev_private;
  1446.  
  1447.     err = RegService("DISPLAY", display_handler);
  1448.  
  1449.     if( err != 0)
  1450.         dbgprintf("Set DISPLAY handler\n");
  1451.  
  1452.     return err;
  1453. };
  1454.  
  1455. void drm_vblank_post_modeset(struct drm_device *dev, int crtc)
  1456. {};
  1457.  
  1458. void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
  1459. {};
  1460.  
  1461.  
  1462. #define PCI_CLASS_REVISION      0x08
  1463. #define PCI_CLASS_DISPLAY_VGA   0x0300
  1464.  
  1465. int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)
  1466. {
  1467.     u16_t vendor, device;
  1468.     u32_t class;
  1469.     int   ret = 0;
  1470.  
  1471.     vendor   = id & 0xffff;
  1472.     device   = (id >> 16) & 0xffff;
  1473.  
  1474.     if(vendor == 0x1002)
  1475.     {
  1476.         class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
  1477.         class >>= 16;
  1478.  
  1479.         if( class == PCI_CLASS_DISPLAY_VGA)
  1480.             ret = 1;
  1481.     }
  1482.     return ret;
  1483. }
  1484.