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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. //#include <linux/console.h>
  29.  
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/radeon_drm.h>
  33. #include "radeon_reg.h"
  34. #include "radeon.h"
  35. #include "radeon_asic.h"
  36. #include "atom.h"
  37. #include "display.h"
  38.  
  39. #include <drm/drm_pciids.h>
  40.  
  41.  
  42. int radeon_no_wb;
  43. int radeon_modeset = -1;
  44. int radeon_dynclks = -1;
  45. int radeon_r4xx_atom = 0;
  46. int radeon_agpmode = 0;
  47. int radeon_vram_limit = 0;
  48. int radeon_gart_size = 512; /* default gart size */
  49. int radeon_benchmarking = 0;
  50. int radeon_testing = 0;
  51. int radeon_connector_table = 0;
  52. int radeon_tv = 1;
  53. int radeon_new_pll = -1;
  54. int radeon_dynpm = -1;
  55. int radeon_audio = 1;
  56.  
  57.  
  58. extern display_t *rdisplay;
  59.  
  60. void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms);
  61. int init_display(struct radeon_device *rdev, videomode_t *mode);
  62. int init_display_kms(struct radeon_device *rdev, videomode_t *mode);
  63.  
  64. int get_modes(videomode_t *mode, int *count);
  65. int set_user_mode(videomode_t *mode);
  66. int r100_2D_test(struct radeon_device *rdev);
  67.  
  68.  
  69.  /* Legacy VGA regions */
  70. #define VGA_RSRC_NONE          0x00
  71. #define VGA_RSRC_LEGACY_IO     0x01
  72. #define VGA_RSRC_LEGACY_MEM    0x02
  73. #define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
  74. /* Non-legacy access */
  75. #define VGA_RSRC_NORMAL_IO     0x04
  76. #define VGA_RSRC_NORMAL_MEM    0x08
  77.  
  78.  
  79.  
  80. /*
  81.  * Clear GPU surface registers.
  82.  */
  83. void radeon_surface_init(struct radeon_device *rdev)
  84. {
  85.     /* FIXME: check this out */
  86.     if (rdev->family < CHIP_R600) {
  87.         int i;
  88.  
  89.                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  90.            radeon_clear_surface_reg(rdev, i);
  91.         }
  92.                 /* enable surfaces */
  93.                 WREG32(RADEON_SURFACE_CNTL, 0);
  94.     }
  95. }
  96.  
  97. /*
  98.  * GPU scratch registers helpers function.
  99.  */
  100. void radeon_scratch_init(struct radeon_device *rdev)
  101. {
  102.     int i;
  103.  
  104.     /* FIXME: check this out */
  105.     if (rdev->family < CHIP_R300) {
  106.         rdev->scratch.num_reg = 5;
  107.     } else {
  108.         rdev->scratch.num_reg = 7;
  109.     }
  110.     for (i = 0; i < rdev->scratch.num_reg; i++) {
  111.         rdev->scratch.free[i] = true;
  112.         rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
  113.     }
  114. }
  115.  
  116. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  117. {
  118.         int i;
  119.  
  120.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  121.                 if (rdev->scratch.free[i]) {
  122.                         rdev->scratch.free[i] = false;
  123.                         *reg = rdev->scratch.reg[i];
  124.                         return 0;
  125.                 }
  126.         }
  127.         return -EINVAL;
  128. }
  129.  
  130. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  131. {
  132.         int i;
  133.  
  134.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  135.                 if (rdev->scratch.reg[i] == reg) {
  136.                         rdev->scratch.free[i] = true;
  137.                         return;
  138.                 }
  139.         }
  140. }
  141.  
  142. /**
  143.  * radeon_vram_location - try to find VRAM location
  144.  * @rdev: radeon device structure holding all necessary informations
  145.  * @mc: memory controller structure holding memory informations
  146.  * @base: base address at which to put VRAM
  147.  *
  148.  * Function will place try to place VRAM at base address provided
  149.  * as parameter (which is so far either PCI aperture address or
  150.  * for IGP TOM base address).
  151.  *
  152.  * If there is not enough space to fit the unvisible VRAM in the 32bits
  153.  * address space then we limit the VRAM size to the aperture.
  154.  *
  155.  * If we are using AGP and if the AGP aperture doesn't allow us to have
  156.  * room for all the VRAM than we restrict the VRAM to the PCI aperture
  157.  * size and print a warning.
  158.  *
  159.  * This function will never fails, worst case are limiting VRAM.
  160.  *
  161.  * Note: GTT start, end, size should be initialized before calling this
  162.  * function on AGP platform.
  163.  *
  164.  * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
  165.  * this shouldn't be a problem as we are using the PCI aperture as a reference.
  166.  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
  167.  * not IGP.
  168.  *
  169.  * Note: we use mc_vram_size as on some board we need to program the mc to
  170.  * cover the whole aperture even if VRAM size is inferior to aperture size
  171.  * Novell bug 204882 + along with lots of ubuntu ones
  172.  *
  173.  * Note: when limiting vram it's safe to overwritte real_vram_size because
  174.  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
  175.  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
  176.  * ones)
  177.  *
  178.  * Note: IGP TOM addr should be the same as the aperture addr, we don't
  179.  * explicitly check for that thought.
  180.  *
  181.  * FIXME: when reducing VRAM size align new size on power of 2.
  182.  */
  183. void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
  184. {
  185.         mc->vram_start = base;
  186.         if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
  187.                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
  188.                 mc->real_vram_size = mc->aper_size;
  189.                 mc->mc_vram_size = mc->aper_size;
  190.         }
  191.         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  192.         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) {
  193.                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
  194.                 mc->real_vram_size = mc->aper_size;
  195.                 mc->mc_vram_size = mc->aper_size;
  196.                 }
  197.         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  198.         dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
  199.                         mc->mc_vram_size >> 20, mc->vram_start,
  200.                         mc->vram_end, mc->real_vram_size >> 20);
  201. }
  202.  
  203. /**
  204.  * radeon_gtt_location - try to find GTT location
  205.  * @rdev: radeon device structure holding all necessary informations
  206.  * @mc: memory controller structure holding memory informations
  207.  *
  208.  * Function will place try to place GTT before or after VRAM.
  209.  *
  210.  * If GTT size is bigger than space left then we ajust GTT size.
  211.  * Thus function will never fails.
  212.  *
  213.  * FIXME: when reducing GTT size align new size on power of 2.
  214.  */
  215. void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
  216. {
  217.         u64 size_af, size_bf;
  218.  
  219.         size_af = 0xFFFFFFFF - mc->vram_end;
  220.         size_bf = mc->vram_start;
  221.         if (size_bf > size_af) {
  222.                 if (mc->gtt_size > size_bf) {
  223.                         dev_warn(rdev->dev, "limiting GTT\n");
  224.                         mc->gtt_size = size_bf;
  225.                 }
  226.                 mc->gtt_start = mc->vram_start - mc->gtt_size;
  227.         } else {
  228.                 if (mc->gtt_size > size_af) {
  229.                         dev_warn(rdev->dev, "limiting GTT\n");
  230.                         mc->gtt_size = size_af;
  231.                 }
  232.                 mc->gtt_start = mc->vram_end + 1;
  233.         }
  234.         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
  235.         dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
  236.                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
  237. }
  238.  
  239. /*
  240.  * GPU helpers function.
  241.  */
  242. bool radeon_card_posted(struct radeon_device *rdev)
  243. {
  244.         uint32_t reg;
  245.  
  246.         /* first check CRTCs */
  247.         if (ASIC_IS_DCE4(rdev)) {
  248.                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
  249.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
  250.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
  251.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
  252.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
  253.                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
  254.                 if (reg & EVERGREEN_CRTC_MASTER_EN)
  255.                         return true;
  256.         } else if (ASIC_IS_AVIVO(rdev)) {
  257.                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
  258.                       RREG32(AVIVO_D2CRTC_CONTROL);
  259.                 if (reg & AVIVO_CRTC_EN) {
  260.                         return true;
  261.                 }
  262.         } else {
  263.                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
  264.                       RREG32(RADEON_CRTC2_GEN_CNTL);
  265.                 if (reg & RADEON_CRTC_EN) {
  266.                         return true;
  267.                 }
  268.         }
  269.  
  270.         /* then check MEM_SIZE, in case the crtcs are off */
  271.         if (rdev->family >= CHIP_R600)
  272.                 reg = RREG32(R600_CONFIG_MEMSIZE);
  273.         else
  274.                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
  275.  
  276.         if (reg)
  277.                 return true;
  278.  
  279.         return false;
  280.  
  281. }
  282.  
  283. bool radeon_boot_test_post_card(struct radeon_device *rdev)
  284. {
  285.         if (radeon_card_posted(rdev))
  286.                 return true;
  287.  
  288.         if (rdev->bios) {
  289.                 DRM_INFO("GPU not posted. posting now...\n");
  290.                 if (rdev->is_atom_bios)
  291.                         atom_asic_init(rdev->mode_info.atom_context);
  292.                 else
  293.                         radeon_combios_asic_init(rdev->ddev);
  294.                 return true;
  295.         } else {
  296.                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  297.                 return false;
  298.         }
  299. }
  300.  
  301. int radeon_dummy_page_init(struct radeon_device *rdev)
  302. {
  303.         if (rdev->dummy_page.page)
  304.                 return 0;
  305.     rdev->dummy_page.page = AllocPage();
  306.         if (rdev->dummy_page.page == NULL)
  307.                 return -ENOMEM;
  308.     rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);
  309.         if (!rdev->dummy_page.addr) {
  310. //       __free_page(rdev->dummy_page.page);
  311.                 rdev->dummy_page.page = NULL;
  312.                 return -ENOMEM;
  313.         }
  314.         return 0;
  315. }
  316.  
  317. void radeon_dummy_page_fini(struct radeon_device *rdev)
  318. {
  319.         if (rdev->dummy_page.page == NULL)
  320.                 return;
  321.     KernelFree(rdev->dummy_page.addr);
  322.         rdev->dummy_page.page = NULL;
  323. }
  324.  
  325.  
  326. /*
  327.  * Registers accessors functions.
  328.  */
  329. uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  330. {
  331.     DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  332.     BUG_ON(1);
  333.     return 0;
  334. }
  335.  
  336. void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  337. {
  338.     DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  339.           reg, v);
  340.     BUG_ON(1);
  341. }
  342.  
  343. void radeon_register_accessor_init(struct radeon_device *rdev)
  344. {
  345.     rdev->mc_rreg = &radeon_invalid_rreg;
  346.     rdev->mc_wreg = &radeon_invalid_wreg;
  347.     rdev->pll_rreg = &radeon_invalid_rreg;
  348.     rdev->pll_wreg = &radeon_invalid_wreg;
  349.     rdev->pciep_rreg = &radeon_invalid_rreg;
  350.     rdev->pciep_wreg = &radeon_invalid_wreg;
  351.  
  352.     /* Don't change order as we are overridding accessor. */
  353.     if (rdev->family < CHIP_RV515) {
  354.                 rdev->pcie_reg_mask = 0xff;
  355.         } else {
  356.                 rdev->pcie_reg_mask = 0x7ff;
  357.     }
  358.     /* FIXME: not sure here */
  359.     if (rdev->family <= CHIP_R580) {
  360.         rdev->pll_rreg = &r100_pll_rreg;
  361.         rdev->pll_wreg = &r100_pll_wreg;
  362.     }
  363.         if (rdev->family >= CHIP_R420) {
  364.                 rdev->mc_rreg = &r420_mc_rreg;
  365.                 rdev->mc_wreg = &r420_mc_wreg;
  366.         }
  367.     if (rdev->family >= CHIP_RV515) {
  368.         rdev->mc_rreg = &rv515_mc_rreg;
  369.         rdev->mc_wreg = &rv515_mc_wreg;
  370.     }
  371.     if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  372.         rdev->mc_rreg = &rs400_mc_rreg;
  373.         rdev->mc_wreg = &rs400_mc_wreg;
  374.     }
  375.     if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  376.         rdev->mc_rreg = &rs690_mc_rreg;
  377.         rdev->mc_wreg = &rs690_mc_wreg;
  378.     }
  379.     if (rdev->family == CHIP_RS600) {
  380.         rdev->mc_rreg = &rs600_mc_rreg;
  381.         rdev->mc_wreg = &rs600_mc_wreg;
  382.     }
  383.         if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
  384.                 rdev->pciep_rreg = &r600_pciep_rreg;
  385.                 rdev->pciep_wreg = &r600_pciep_wreg;
  386.         }
  387. }
  388.  
  389.  
  390. /*
  391.  * ASIC
  392.  */
  393. int radeon_asic_init(struct radeon_device *rdev)
  394. {
  395.     radeon_register_accessor_init(rdev);
  396.         switch (rdev->family) {
  397.         case CHIP_R100:
  398.         case CHIP_RV100:
  399.         case CHIP_RS100:
  400.         case CHIP_RV200:
  401.         case CHIP_RS200:
  402.                 rdev->asic = &r100_asic;
  403.                 break;
  404.         case CHIP_R200:
  405.         case CHIP_RV250:
  406.         case CHIP_RS300:
  407.         case CHIP_RV280:
  408.                 rdev->asic = &r200_asic;
  409.                 break;
  410.         case CHIP_R300:
  411.         case CHIP_R350:
  412.         case CHIP_RV350:
  413.         case CHIP_RV380:
  414.                 if (rdev->flags & RADEON_IS_PCIE)
  415.                         rdev->asic = &r300_asic_pcie;
  416.                 else
  417.         rdev->asic = &r300_asic;
  418.                 break;
  419.         case CHIP_R420:
  420.         case CHIP_R423:
  421.         case CHIP_RV410:
  422.         rdev->asic = &r420_asic;
  423.                 break;
  424.         case CHIP_RS400:
  425.         case CHIP_RS480:
  426.        rdev->asic = &rs400_asic;
  427.                 break;
  428.         case CHIP_RS600:
  429.         rdev->asic = &rs600_asic;
  430.                 break;
  431.         case CHIP_RS690:
  432.         case CHIP_RS740:
  433.         rdev->asic = &rs690_asic;
  434.                 break;
  435.         case CHIP_RV515:
  436.         rdev->asic = &rv515_asic;
  437.                 break;
  438.         case CHIP_R520:
  439.         case CHIP_RV530:
  440.         case CHIP_RV560:
  441.         case CHIP_RV570:
  442.         case CHIP_R580:
  443.         rdev->asic = &r520_asic;
  444.                 break;
  445.         case CHIP_R600:
  446.         case CHIP_RV610:
  447.         case CHIP_RV630:
  448.         case CHIP_RV620:
  449.         case CHIP_RV635:
  450.         case CHIP_RV670:
  451.         case CHIP_RS780:
  452.         case CHIP_RS880:
  453.                 rdev->asic = &r600_asic;
  454.                 break;
  455.         case CHIP_RV770:
  456.         case CHIP_RV730:
  457.         case CHIP_RV710:
  458.         case CHIP_RV740:
  459.                 rdev->asic = &rv770_asic;
  460.                 break;
  461.         case CHIP_CEDAR:
  462.         case CHIP_REDWOOD:
  463.         case CHIP_JUNIPER:
  464.         case CHIP_CYPRESS:
  465.         case CHIP_HEMLOCK:
  466.                 rdev->asic = &evergreen_asic;
  467.                 break;
  468.         default:
  469.                 /* FIXME: not supported yet */
  470.                 return -EINVAL;
  471.         }
  472.  
  473.         if (rdev->flags & RADEON_IS_IGP) {
  474.                 rdev->asic->get_memory_clock = NULL;
  475.                 rdev->asic->set_memory_clock = NULL;
  476.         }
  477.  
  478.         return 0;
  479. }
  480.  
  481.  
  482. /*
  483.  * Wrapper around modesetting bits.
  484.  */
  485. int radeon_clocks_init(struct radeon_device *rdev)
  486. {
  487.         int r;
  488.  
  489.     r = radeon_static_clocks_init(rdev->ddev);
  490.         if (r) {
  491.                 return r;
  492.         }
  493.         DRM_INFO("Clocks initialized !\n");
  494.         return 0;
  495. }
  496.  
  497. void radeon_clocks_fini(struct radeon_device *rdev)
  498. {
  499. }
  500.  
  501. /* ATOM accessor methods */
  502. static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
  503. {
  504.     struct radeon_device *rdev = info->dev->dev_private;
  505.     uint32_t r;
  506.  
  507.     r = rdev->pll_rreg(rdev, reg);
  508.     return r;
  509. }
  510.  
  511. static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
  512. {
  513.     struct radeon_device *rdev = info->dev->dev_private;
  514.  
  515.     rdev->pll_wreg(rdev, reg, val);
  516. }
  517.  
  518. static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
  519. {
  520.     struct radeon_device *rdev = info->dev->dev_private;
  521.     uint32_t r;
  522.  
  523.     r = rdev->mc_rreg(rdev, reg);
  524.     return r;
  525. }
  526.  
  527. static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
  528. {
  529.     struct radeon_device *rdev = info->dev->dev_private;
  530.  
  531.     rdev->mc_wreg(rdev, reg, val);
  532. }
  533.  
  534. static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
  535. {
  536.     struct radeon_device *rdev = info->dev->dev_private;
  537.  
  538.     WREG32(reg*4, val);
  539. }
  540.  
  541. static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
  542. {
  543.     struct radeon_device *rdev = info->dev->dev_private;
  544.     uint32_t r;
  545.  
  546.     r = RREG32(reg*4);
  547.     return r;
  548. }
  549.  
  550. int radeon_atombios_init(struct radeon_device *rdev)
  551. {
  552.         struct card_info *atom_card_info =
  553.             kzalloc(sizeof(struct card_info), GFP_KERNEL);
  554.  
  555.         if (!atom_card_info)
  556.                 return -ENOMEM;
  557.  
  558.         rdev->mode_info.atom_card_info = atom_card_info;
  559.         atom_card_info->dev = rdev->ddev;
  560.         atom_card_info->reg_read = cail_reg_read;
  561.         atom_card_info->reg_write = cail_reg_write;
  562.         atom_card_info->mc_read = cail_mc_read;
  563.         atom_card_info->mc_write = cail_mc_write;
  564.         atom_card_info->pll_read = cail_pll_read;
  565.         atom_card_info->pll_write = cail_pll_write;
  566.  
  567.         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
  568.     radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
  569.         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
  570.     return 0;
  571. }
  572.  
  573. void radeon_atombios_fini(struct radeon_device *rdev)
  574. {
  575.         if (rdev->mode_info.atom_context) {
  576.                 kfree(rdev->mode_info.atom_context->scratch);
  577.         kfree(rdev->mode_info.atom_context);
  578.         }
  579.         kfree(rdev->mode_info.atom_card_info);
  580. }
  581.  
  582. int radeon_combios_init(struct radeon_device *rdev)
  583. {
  584.         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
  585.         return 0;
  586. }
  587.  
  588. void radeon_combios_fini(struct radeon_device *rdev)
  589. {
  590. }
  591.  
  592. /* if we get transitioned to only one device, tak VGA back */
  593. static unsigned int radeon_vga_set_decode(void *cookie, bool state)
  594. {
  595.         struct radeon_device *rdev = cookie;
  596.         radeon_vga_set_state(rdev, state);
  597.         if (state)
  598.                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  599.                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  600.         else
  601.                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  602. }
  603.  
  604. void radeon_agp_disable(struct radeon_device *rdev)
  605. {
  606.         rdev->flags &= ~RADEON_IS_AGP;
  607.         if (rdev->family >= CHIP_R600) {
  608.                 DRM_INFO("Forcing AGP to PCIE mode\n");
  609.                 rdev->flags |= RADEON_IS_PCIE;
  610.         } else if (rdev->family >= CHIP_RV515 ||
  611.                         rdev->family == CHIP_RV380 ||
  612.                         rdev->family == CHIP_RV410 ||
  613.                         rdev->family == CHIP_R423) {
  614.                 DRM_INFO("Forcing AGP to PCIE mode\n");
  615.                 rdev->flags |= RADEON_IS_PCIE;
  616.                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
  617.                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
  618.         } else {
  619.                 DRM_INFO("Forcing AGP to PCI mode\n");
  620.                 rdev->flags |= RADEON_IS_PCI;
  621.                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
  622.                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
  623.         }
  624.         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  625. }
  626.  
  627. void radeon_check_arguments(struct radeon_device *rdev)
  628. {
  629.         /* vramlimit must be a power of two */
  630.         switch (radeon_vram_limit) {
  631.         case 0:
  632.         case 4:
  633.         case 8:
  634.         case 16:
  635.         case 32:
  636.         case 64:
  637.         case 128:
  638.         case 256:
  639.         case 512:
  640.         case 1024:
  641.         case 2048:
  642.         case 4096:
  643.                 break;
  644.         default:
  645.                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
  646.                                 radeon_vram_limit);
  647.                 radeon_vram_limit = 0;
  648.                 break;
  649.         }
  650.         radeon_vram_limit = radeon_vram_limit << 20;
  651.         /* gtt size must be power of two and greater or equal to 32M */
  652.         switch (radeon_gart_size) {
  653.         case 4:
  654.         case 8:
  655.         case 16:
  656.                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
  657.                                 radeon_gart_size);
  658.                 radeon_gart_size = 512;
  659.                 break;
  660.         case 32:
  661.         case 64:
  662.         case 128:
  663.         case 256:
  664.         case 512:
  665.         case 1024:
  666.         case 2048:
  667.         case 4096:
  668.                 break;
  669.         default:
  670.                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
  671.                                 radeon_gart_size);
  672.                 radeon_gart_size = 512;
  673.                 break;
  674.         }
  675.         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  676.         /* AGP mode can only be -1, 1, 2, 4, 8 */
  677.         switch (radeon_agpmode) {
  678.         case -1:
  679.         case 0:
  680.         case 1:
  681.         case 2:
  682.         case 4:
  683.         case 8:
  684.                 break;
  685.         default:
  686.                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
  687.                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
  688.                 radeon_agpmode = 0;
  689.                 break;
  690.         }
  691. }
  692.  
  693. int radeon_device_init(struct radeon_device *rdev,
  694.                struct drm_device *ddev,
  695.                struct pci_dev *pdev,
  696.                uint32_t flags)
  697. {
  698.         int r;
  699.         int dma_bits;
  700.  
  701.     DRM_INFO("radeon: Initializing kernel modesetting.\n");
  702.     rdev->shutdown = false;
  703.     rdev->ddev = ddev;
  704.     rdev->pdev = pdev;
  705.     rdev->flags = flags;
  706.     rdev->family = flags & RADEON_FAMILY_MASK;
  707.     rdev->is_atom_bios = false;
  708.     rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
  709.     rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  710.     rdev->gpu_lockup = false;
  711.         rdev->accel_working = false;
  712.     /* mutex initialization are all done here so we
  713.      * can recall function without having locking issues */
  714.  //   mutex_init(&rdev->cs_mutex);
  715.  //   mutex_init(&rdev->ib_pool.mutex);
  716.  //   mutex_init(&rdev->cp.mutex);
  717.  //   rwlock_init(&rdev->fence_drv.lock);
  718.  
  719.         /* Set asic functions */
  720.         r = radeon_asic_init(rdev);
  721.         if (r)
  722.                 return r;
  723.         radeon_check_arguments(rdev);
  724.  
  725.         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
  726.                 radeon_agp_disable(rdev);
  727.     }
  728.  
  729.         /* set DMA mask + need_dma32 flags.
  730.          * PCIE - can handle 40-bits.
  731.          * IGP - can handle 40-bits (in theory)
  732.          * AGP - generally dma32 is safest
  733.          * PCI - only dma32
  734.          */
  735.         rdev->need_dma32 = false;
  736.         if (rdev->flags & RADEON_IS_AGP)
  737.                 rdev->need_dma32 = true;
  738.         if (rdev->flags & RADEON_IS_PCI)
  739.                 rdev->need_dma32 = true;
  740.  
  741.         dma_bits = rdev->need_dma32 ? 32 : 40;
  742.         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
  743.     if (r) {
  744.         printk(KERN_WARNING "radeon: No suitable DMA available.\n");
  745.     }
  746.  
  747.     /* Registers mapping */
  748.     /* TODO: block userspace mapping of io register */
  749.     rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
  750.  
  751.     rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
  752.  
  753.     rdev->rmmio =  (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
  754.                                    PG_SW+PG_NOCACHE);
  755.  
  756.     if (rdev->rmmio == NULL) {
  757.         return -ENOMEM;
  758.     }
  759.     DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
  760.     DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
  761.  
  762.         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
  763.         /* this will fail for cards that aren't VGA class devices, just
  764.          * ignore it */
  765. //      r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
  766. //      if (r) {
  767. //              return -EINVAL;
  768. //      }
  769.  
  770.         r = radeon_init(rdev);
  771.         if (r)
  772.             return r;
  773.  
  774.         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
  775.                 /* Acceleration not working on AGP card try again
  776.                  * with fallback to PCI or PCIE GART
  777.                  */
  778.                 radeon_gpu_reset(rdev);
  779.                 radeon_fini(rdev);
  780.                 radeon_agp_disable(rdev);
  781.                 r = radeon_init(rdev);
  782.                 if (r)
  783.                 return r;
  784.         }
  785. //      if (radeon_testing) {
  786. //              radeon_test_moves(rdev);
  787. //    }
  788. //      if (radeon_benchmarking) {
  789. //              radeon_benchmark(rdev);
  790. //    }
  791.         return 0;
  792. }
  793.  
  794.  
  795. /*
  796.  * Driver load/unload
  797.  */
  798. int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  799. {
  800.     struct radeon_device *rdev;
  801.     int r;
  802.  
  803.     ENTER();
  804.  
  805.     rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  806.     if (rdev == NULL) {
  807.         return -ENOMEM;
  808.     };
  809.  
  810.     dev->dev_private = (void *)rdev;
  811.  
  812.     /* update BUS flag */
  813.     if (drm_device_is_agp(dev)) {
  814.         flags |= RADEON_IS_AGP;
  815.     } else if (drm_device_is_pcie(dev)) {
  816.         flags |= RADEON_IS_PCIE;
  817.     } else {
  818.         flags |= RADEON_IS_PCI;
  819.     }
  820.  
  821.     /* radeon_device_init should report only fatal error
  822.      * like memory allocation failure or iomapping failure,
  823.      * or memory manager initialization failure, it must
  824.      * properly initialize the GPU MC controller and permit
  825.      * VRAM allocation
  826.      */
  827.     r = radeon_device_init(rdev, dev, dev->pdev, flags);
  828.     if (r) {
  829.         DRM_ERROR("Fatal error while trying to initialize radeon.\n");
  830.         return r;
  831.     }
  832.     /* Again modeset_init should fail only on fatal error
  833.      * otherwise it should provide enough functionalities
  834.      * for shadowfb to run
  835.      */
  836.     if( radeon_modeset )
  837.     {
  838.         r = radeon_modeset_init(rdev);
  839.         if (r) {
  840.             return r;
  841.         }
  842.     };
  843.     return 0;
  844. }
  845.  
  846. videomode_t usermode;
  847.  
  848.  
  849. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  850. {
  851.     static struct drm_device *dev;
  852.     int ret;
  853.  
  854.     ENTER();
  855.  
  856.     dev = kzalloc(sizeof(*dev), 0);
  857.     if (!dev)
  858.         return -ENOMEM;
  859.  
  860.  //   ret = pci_enable_device(pdev);
  861.  //   if (ret)
  862.  //       goto err_g1;
  863.  
  864.  //   pci_set_master(pdev);
  865.  
  866.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  867.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  868.  //       goto err_g2;
  869.  //   }
  870.  
  871.     dev->pdev = pdev;
  872.     dev->pci_device = pdev->device;
  873.     dev->pci_vendor = pdev->vendor;
  874.  
  875.     ret = radeon_driver_load_kms(dev, ent->driver_data );
  876.     if (ret)
  877.         goto err_g4;
  878.  
  879.     if( radeon_modeset )
  880.         init_display_kms(dev->dev_private, &usermode);
  881.     else
  882.         init_display(dev->dev_private, &usermode);
  883.  
  884.     LEAVE();
  885.  
  886.     return 0;
  887.  
  888. err_g4:
  889. //    drm_put_minor(&dev->primary);
  890. //err_g3:
  891. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  892. //        drm_put_minor(&dev->control);
  893. //err_g2:
  894. //    pci_disable_device(pdev);
  895. //err_g1:
  896.     free(dev);
  897.  
  898.     LEAVE();
  899.  
  900.     return ret;
  901. }
  902.  
  903. resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
  904. {
  905.     return pci_resource_start(dev->pdev, resource);
  906. }
  907.  
  908. resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
  909. {
  910.     return pci_resource_len(dev->pdev, resource);
  911. }
  912.  
  913.  
  914. uint32_t __div64_32(uint64_t *n, uint32_t base)
  915. {
  916.         uint64_t rem = *n;
  917.         uint64_t b = base;
  918.         uint64_t res, d = 1;
  919.         uint32_t high = rem >> 32;
  920.  
  921.         /* Reduce the thing a bit first */
  922.         res = 0;
  923.         if (high >= base) {
  924.                 high /= base;
  925.                 res = (uint64_t) high << 32;
  926.                 rem -= (uint64_t) (high*base) << 32;
  927.         }
  928.  
  929.         while ((int64_t)b > 0 && b < rem) {
  930.                 b = b+b;
  931.                 d = d+d;
  932.         }
  933.  
  934.         do {
  935.                 if (rem >= b) {
  936.                         rem -= b;
  937.                         res += d;
  938.                 }
  939.                 b >>= 1;
  940.                 d >>= 1;
  941.         } while (d);
  942.  
  943.         *n = res;
  944.         return rem;
  945. }
  946.  
  947.  
  948. static struct pci_device_id pciidlist[] = {
  949.     radeon_PCI_IDS
  950. };
  951.  
  952.  
  953. #define API_VERSION     0x01000100
  954.  
  955. #define SRV_GETVERSION  0
  956. #define SRV_ENUM_MODES  1
  957. #define SRV_SET_MODE    2
  958.  
  959. int _stdcall display_handler(ioctl_t *io)
  960. {
  961.     int    retval = -1;
  962.     u32_t *inp;
  963.     u32_t *outp;
  964.  
  965.     inp = io->input;
  966.     outp = io->output;
  967.  
  968.     switch(io->io_code)
  969.     {
  970.         case SRV_GETVERSION:
  971.             if(io->out_size==4)
  972.             {
  973.                 *outp  = API_VERSION;
  974.                 retval = 0;
  975.             }
  976.             break;
  977.  
  978.         case SRV_ENUM_MODES:
  979.             dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
  980.                        inp, io->inp_size, io->out_size );
  981.  
  982.             if( radeon_modeset &&
  983.                 (outp != NULL) && (io->out_size == 4) &&
  984.                 (io->inp_size == *outp * sizeof(videomode_t)) )
  985.             {
  986.                 retval = get_modes((videomode_t*)inp, outp);
  987.             };
  988.             break;
  989.  
  990.         case SRV_SET_MODE:
  991.             dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
  992.                        inp, io->inp_size);
  993.  
  994.             if(  radeon_modeset   &&
  995.                 (inp != NULL) &&
  996.                 (io->inp_size == sizeof(videomode_t)) )
  997.             {
  998.                 retval = set_user_mode((videomode_t*)inp);
  999.             };
  1000.             break;
  1001.     };
  1002.  
  1003.     return retval;
  1004. }
  1005.  
  1006. static char  log[256];
  1007. static pci_dev_t device;
  1008.  
  1009. u32_t drvEntry(int action, char *cmdline)
  1010. {
  1011.     struct radeon_device *rdev = NULL;
  1012.  
  1013.     struct pci_device_id  *ent;
  1014.  
  1015.     int     err;
  1016.     u32_t   retval = 0;
  1017.  
  1018.     if(action != 1)
  1019.         return 0;
  1020.  
  1021.     if( GetService("DISPLAY") != 0 )
  1022.         return 0;
  1023.  
  1024.     if( cmdline && *cmdline )
  1025.         parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
  1026.  
  1027.     if(!dbg_open(log))
  1028.     {
  1029.         strcpy(log, "/rd/1/drivers/atikms.log");
  1030.  
  1031.         if(!dbg_open(log))
  1032.         {
  1033.             printf("Can't open %s\nExit\n", log);
  1034.             return 0;
  1035.         };
  1036.     }
  1037.     dbgprintf("Radeon RC10 cmdline %s\n", cmdline);
  1038.  
  1039.     enum_pci_devices();
  1040.  
  1041.     ent = find_pci_device(&device, pciidlist);
  1042.  
  1043.     if( unlikely(ent == NULL) )
  1044.     {
  1045.         dbgprintf("device not found\n");
  1046.         return 0;
  1047.     };
  1048.  
  1049.     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
  1050.                                 device.pci_dev.device);
  1051.  
  1052.     err = drm_get_dev(&device.pci_dev, ent);
  1053.  
  1054.     rdev = rdisplay->ddev->dev_private;
  1055.  
  1056.     if( (rdev->asic == &r600_asic) ||
  1057.         (rdev->asic == &rv770_asic))
  1058.         r600_2D_test(rdev);
  1059.     else if (rdev->asic != &evergreen_asic)
  1060.         r100_2D_test(rdev);
  1061.  
  1062.     err = RegService("DISPLAY", display_handler);
  1063.  
  1064.     if( err != 0)
  1065.         dbgprintf("Set DISPLAY handler\n");
  1066.  
  1067.     return err;
  1068. };
  1069.  
  1070. void drm_vblank_post_modeset(struct drm_device *dev, int crtc)
  1071. {};
  1072.  
  1073. void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
  1074. {};
  1075.  
  1076.