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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. //#include <linux/console.h>
  29.  
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/radeon_drm.h>
  33. #include "radeon_reg.h"
  34. #include "radeon.h"
  35. #include "radeon_asic.h"
  36. #include "atom.h"
  37.  
  38. #include <drm/drm_pciids.h>
  39.  
  40.  
  41. int radeon_dynclks          = -1;
  42. int radeon_r4xx_atom        = 0;
  43. int radeon_agpmode          = -1;
  44. int radeon_gart_size        = 512; /* default gart size */
  45. int radeon_benchmarking     = 0;
  46. int radeon_connector_table  = 0;
  47. int radeon_tv               = 0;
  48. int radeon_modeset          = 1;
  49. int radeon_new_pll          = 1;
  50. int radeon_vram_limit       = 0;
  51. int radeon_audio            = 0;
  52.  
  53.  
  54. void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms);
  55. int init_display(struct radeon_device *rdev, videomode_t *mode);
  56. int init_display_kms(struct radeon_device *rdev, videomode_t *mode);
  57.  
  58. int get_modes(videomode_t *mode, int *count);
  59. int set_user_mode(videomode_t *mode);
  60.  
  61.  
  62.  /* Legacy VGA regions */
  63. #define VGA_RSRC_NONE          0x00
  64. #define VGA_RSRC_LEGACY_IO     0x01
  65. #define VGA_RSRC_LEGACY_MEM    0x02
  66. #define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
  67. /* Non-legacy access */
  68. #define VGA_RSRC_NORMAL_IO     0x04
  69. #define VGA_RSRC_NORMAL_MEM    0x08
  70.  
  71.  
  72.  
  73. /*
  74.  * Clear GPU surface registers.
  75.  */
  76. void radeon_surface_init(struct radeon_device *rdev)
  77. {
  78.     /* FIXME: check this out */
  79.     if (rdev->family < CHIP_R600) {
  80.         int i;
  81.  
  82.                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  83.            radeon_clear_surface_reg(rdev, i);
  84.         }
  85.                 /* enable surfaces */
  86.                 WREG32(RADEON_SURFACE_CNTL, 0);
  87.     }
  88. }
  89.  
  90. /*
  91.  * GPU scratch registers helpers function.
  92.  */
  93. void radeon_scratch_init(struct radeon_device *rdev)
  94. {
  95.     int i;
  96.  
  97.     /* FIXME: check this out */
  98.     if (rdev->family < CHIP_R300) {
  99.         rdev->scratch.num_reg = 5;
  100.     } else {
  101.         rdev->scratch.num_reg = 7;
  102.     }
  103.     for (i = 0; i < rdev->scratch.num_reg; i++) {
  104.         rdev->scratch.free[i] = true;
  105.         rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
  106.     }
  107. }
  108.  
  109. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  110. {
  111.         int i;
  112.  
  113.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  114.                 if (rdev->scratch.free[i]) {
  115.                         rdev->scratch.free[i] = false;
  116.                         *reg = rdev->scratch.reg[i];
  117.                         return 0;
  118.                 }
  119.         }
  120.         return -EINVAL;
  121. }
  122.  
  123. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  124. {
  125.         int i;
  126.  
  127.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  128.                 if (rdev->scratch.reg[i] == reg) {
  129.                         rdev->scratch.free[i] = true;
  130.                         return;
  131.                 }
  132.         }
  133. }
  134.  
  135. /*
  136.  * MC common functions
  137.  */
  138. int radeon_mc_setup(struct radeon_device *rdev)
  139. {
  140.         uint32_t tmp;
  141.  
  142.         /* Some chips have an "issue" with the memory controller, the
  143.          * location must be aligned to the size. We just align it down,
  144.          * too bad if we walk over the top of system memory, we don't
  145.          * use DMA without a remapped anyway.
  146.          * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
  147.          */
  148.         /* FGLRX seems to setup like this, VRAM a 0, then GART.
  149.          */
  150.         /*
  151.          * Note: from R6xx the address space is 40bits but here we only
  152.          * use 32bits (still have to see a card which would exhaust 4G
  153.          * address space).
  154.          */
  155.         if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
  156.                 /* vram location was already setup try to put gtt after
  157.                  * if it fits */
  158.                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
  159.                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
  160.                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
  161.                         rdev->mc.gtt_location = tmp;
  162.                 } else {
  163.                         if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
  164.                                 printk(KERN_ERR "[drm] GTT too big to fit "
  165.                                        "before or after vram location.\n");
  166.                                 return -EINVAL;
  167.                         }
  168.                         rdev->mc.gtt_location = 0;
  169.                 }
  170.         } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
  171.                 /* gtt location was already setup try to put vram before
  172.                  * if it fits */
  173.                 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
  174.                         rdev->mc.vram_location = 0;
  175.                 } else {
  176.                         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
  177.                         tmp += (rdev->mc.mc_vram_size - 1);
  178.                         tmp &= ~(rdev->mc.mc_vram_size - 1);
  179.                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
  180.                                 rdev->mc.vram_location = tmp;
  181.                         } else {
  182.                                 printk(KERN_ERR "[drm] vram too big to fit "
  183.                                        "before or after GTT location.\n");
  184.                                 return -EINVAL;
  185.                         }
  186.                 }
  187.         } else {
  188.                 rdev->mc.vram_location = 0;
  189.                 tmp = rdev->mc.mc_vram_size;
  190.                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
  191.                 rdev->mc.gtt_location = tmp;
  192.         }
  193.         rdev->mc.vram_start = rdev->mc.vram_location;
  194.         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
  195.         rdev->mc.gtt_start = rdev->mc.gtt_location;
  196.         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  197.         DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
  198.         DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
  199.                  (unsigned)rdev->mc.vram_location,
  200.                  (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
  201.         DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
  202.         DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
  203.                  (unsigned)rdev->mc.gtt_location,
  204.                  (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
  205.         return 0;
  206. }
  207.  
  208.  
  209. /*
  210.  * GPU helpers function.
  211.  */
  212. bool radeon_card_posted(struct radeon_device *rdev)
  213. {
  214.         uint32_t reg;
  215.  
  216.         /* first check CRTCs */
  217.         if (ASIC_IS_AVIVO(rdev)) {
  218.                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
  219.                       RREG32(AVIVO_D2CRTC_CONTROL);
  220.                 if (reg & AVIVO_CRTC_EN) {
  221.                         return true;
  222.                 }
  223.         } else {
  224.                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
  225.                       RREG32(RADEON_CRTC2_GEN_CNTL);
  226.                 if (reg & RADEON_CRTC_EN) {
  227.                         return true;
  228.                 }
  229.         }
  230.  
  231.         /* then check MEM_SIZE, in case the crtcs are off */
  232.         if (rdev->family >= CHIP_R600)
  233.                 reg = RREG32(R600_CONFIG_MEMSIZE);
  234.         else
  235.                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
  236.  
  237.         if (reg)
  238.                 return true;
  239.  
  240.         return false;
  241.  
  242. }
  243.  
  244. bool radeon_boot_test_post_card(struct radeon_device *rdev)
  245. {
  246.         if (radeon_card_posted(rdev))
  247.                 return true;
  248.  
  249.         if (rdev->bios) {
  250.                 DRM_INFO("GPU not posted. posting now...\n");
  251.                 if (rdev->is_atom_bios)
  252.                         atom_asic_init(rdev->mode_info.atom_context);
  253.                 else
  254.                         radeon_combios_asic_init(rdev->ddev);
  255.                 return true;
  256.         } else {
  257.                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  258.                 return false;
  259.         }
  260. }
  261.  
  262. int radeon_dummy_page_init(struct radeon_device *rdev)
  263. {
  264.     rdev->dummy_page.page = AllocPage();
  265.         if (rdev->dummy_page.page == NULL)
  266.                 return -ENOMEM;
  267.     rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);
  268.         if (!rdev->dummy_page.addr) {
  269. //       __free_page(rdev->dummy_page.page);
  270.                 rdev->dummy_page.page = NULL;
  271.                 return -ENOMEM;
  272.         }
  273.         return 0;
  274. }
  275.  
  276. void radeon_dummy_page_fini(struct radeon_device *rdev)
  277. {
  278.         if (rdev->dummy_page.page == NULL)
  279.                 return;
  280.     KernelFree(rdev->dummy_page.addr);
  281.         rdev->dummy_page.page = NULL;
  282. }
  283.  
  284.  
  285. /*
  286.  * Registers accessors functions.
  287.  */
  288. uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  289. {
  290.     DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  291.     BUG_ON(1);
  292.     return 0;
  293. }
  294.  
  295. void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  296. {
  297.     DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  298.           reg, v);
  299.     BUG_ON(1);
  300. }
  301.  
  302. void radeon_register_accessor_init(struct radeon_device *rdev)
  303. {
  304.     rdev->mc_rreg = &radeon_invalid_rreg;
  305.     rdev->mc_wreg = &radeon_invalid_wreg;
  306.     rdev->pll_rreg = &radeon_invalid_rreg;
  307.     rdev->pll_wreg = &radeon_invalid_wreg;
  308.     rdev->pciep_rreg = &radeon_invalid_rreg;
  309.     rdev->pciep_wreg = &radeon_invalid_wreg;
  310.  
  311.     /* Don't change order as we are overridding accessor. */
  312.     if (rdev->family < CHIP_RV515) {
  313.                 rdev->pcie_reg_mask = 0xff;
  314.         } else {
  315.                 rdev->pcie_reg_mask = 0x7ff;
  316.     }
  317.     /* FIXME: not sure here */
  318.     if (rdev->family <= CHIP_R580) {
  319.         rdev->pll_rreg = &r100_pll_rreg;
  320.         rdev->pll_wreg = &r100_pll_wreg;
  321.     }
  322.         if (rdev->family >= CHIP_R420) {
  323.                 rdev->mc_rreg = &r420_mc_rreg;
  324.                 rdev->mc_wreg = &r420_mc_wreg;
  325.         }
  326.     if (rdev->family >= CHIP_RV515) {
  327.         rdev->mc_rreg = &rv515_mc_rreg;
  328.         rdev->mc_wreg = &rv515_mc_wreg;
  329.     }
  330.     if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  331.         rdev->mc_rreg = &rs400_mc_rreg;
  332.         rdev->mc_wreg = &rs400_mc_wreg;
  333.     }
  334.     if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  335.         rdev->mc_rreg = &rs690_mc_rreg;
  336.         rdev->mc_wreg = &rs690_mc_wreg;
  337.     }
  338.     if (rdev->family == CHIP_RS600) {
  339.         rdev->mc_rreg = &rs600_mc_rreg;
  340.         rdev->mc_wreg = &rs600_mc_wreg;
  341.     }
  342.         if (rdev->family >= CHIP_R600) {
  343.                 rdev->pciep_rreg = &r600_pciep_rreg;
  344.                 rdev->pciep_wreg = &r600_pciep_wreg;
  345.         }
  346. }
  347.  
  348.  
  349. /*
  350.  * ASIC
  351.  */
  352. int radeon_asic_init(struct radeon_device *rdev)
  353. {
  354.     radeon_register_accessor_init(rdev);
  355.         switch (rdev->family) {
  356.         case CHIP_R100:
  357.         case CHIP_RV100:
  358.         case CHIP_RS100:
  359.         case CHIP_RV200:
  360.         case CHIP_RS200:
  361.         case CHIP_R200:
  362.         case CHIP_RV250:
  363.         case CHIP_RS300:
  364.         case CHIP_RV280:
  365.         rdev->asic = &r100_asic;
  366.                 break;
  367.         case CHIP_R300:
  368.         case CHIP_R350:
  369.         case CHIP_RV350:
  370.         case CHIP_RV380:
  371.         rdev->asic = &r300_asic;
  372.                 if (rdev->flags & RADEON_IS_PCIE) {
  373.                         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
  374.                         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
  375.                 }
  376.                 break;
  377.         case CHIP_R420:
  378.         case CHIP_R423:
  379.         case CHIP_RV410:
  380.         rdev->asic = &r420_asic;
  381.                 break;
  382.         case CHIP_RS400:
  383.         case CHIP_RS480:
  384.        rdev->asic = &rs400_asic;
  385.                 break;
  386.         case CHIP_RS600:
  387.         rdev->asic = &rs600_asic;
  388.                 break;
  389.         case CHIP_RS690:
  390.         case CHIP_RS740:
  391.         rdev->asic = &rs690_asic;
  392.                 break;
  393.         case CHIP_RV515:
  394.         rdev->asic = &rv515_asic;
  395.                 break;
  396.         case CHIP_R520:
  397.         case CHIP_RV530:
  398.         case CHIP_RV560:
  399.         case CHIP_RV570:
  400.         case CHIP_R580:
  401.         rdev->asic = &r520_asic;
  402.                 break;
  403.         case CHIP_R600:
  404.         case CHIP_RV610:
  405.         case CHIP_RV630:
  406.         case CHIP_RV620:
  407.         case CHIP_RV635:
  408.         case CHIP_RV670:
  409.         case CHIP_RS780:
  410.         case CHIP_RS880:
  411.                 rdev->asic = &r600_asic;
  412.                 break;
  413.         case CHIP_RV770:
  414.         case CHIP_RV730:
  415.         case CHIP_RV710:
  416.         case CHIP_RV740:
  417.                 rdev->asic = &rv770_asic;
  418.                 break;
  419.         default:
  420.                 /* FIXME: not supported yet */
  421.                 return -EINVAL;
  422.         }
  423.  
  424.         if (rdev->flags & RADEON_IS_IGP) {
  425.                 rdev->asic->get_memory_clock = NULL;
  426.                 rdev->asic->set_memory_clock = NULL;
  427.         }
  428.  
  429.         return 0;
  430. }
  431.  
  432.  
  433. /*
  434.  * Wrapper around modesetting bits.
  435.  */
  436. int radeon_clocks_init(struct radeon_device *rdev)
  437. {
  438.         int r;
  439.  
  440.     r = radeon_static_clocks_init(rdev->ddev);
  441.         if (r) {
  442.                 return r;
  443.         }
  444.         DRM_INFO("Clocks initialized !\n");
  445.         return 0;
  446. }
  447.  
  448. void radeon_clocks_fini(struct radeon_device *rdev)
  449. {
  450. }
  451.  
  452. /* ATOM accessor methods */
  453. static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
  454. {
  455.     struct radeon_device *rdev = info->dev->dev_private;
  456.     uint32_t r;
  457.  
  458.     r = rdev->pll_rreg(rdev, reg);
  459.     return r;
  460. }
  461.  
  462. static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
  463. {
  464.     struct radeon_device *rdev = info->dev->dev_private;
  465.  
  466.     rdev->pll_wreg(rdev, reg, val);
  467. }
  468.  
  469. static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
  470. {
  471.     struct radeon_device *rdev = info->dev->dev_private;
  472.     uint32_t r;
  473.  
  474.     r = rdev->mc_rreg(rdev, reg);
  475.     return r;
  476. }
  477.  
  478. static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
  479. {
  480.     struct radeon_device *rdev = info->dev->dev_private;
  481.  
  482.     rdev->mc_wreg(rdev, reg, val);
  483. }
  484.  
  485. static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
  486. {
  487.     struct radeon_device *rdev = info->dev->dev_private;
  488.  
  489.     WREG32(reg*4, val);
  490. }
  491.  
  492. static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
  493. {
  494.     struct radeon_device *rdev = info->dev->dev_private;
  495.     uint32_t r;
  496.  
  497.     r = RREG32(reg*4);
  498.     return r;
  499. }
  500.  
  501. int radeon_atombios_init(struct radeon_device *rdev)
  502. {
  503.         struct card_info *atom_card_info =
  504.             kzalloc(sizeof(struct card_info), GFP_KERNEL);
  505.  
  506.         if (!atom_card_info)
  507.                 return -ENOMEM;
  508.  
  509.         rdev->mode_info.atom_card_info = atom_card_info;
  510.         atom_card_info->dev = rdev->ddev;
  511.         atom_card_info->reg_read = cail_reg_read;
  512.         atom_card_info->reg_write = cail_reg_write;
  513.         atom_card_info->mc_read = cail_mc_read;
  514.         atom_card_info->mc_write = cail_mc_write;
  515.         atom_card_info->pll_read = cail_pll_read;
  516.         atom_card_info->pll_write = cail_pll_write;
  517.  
  518.         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
  519.     radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
  520.         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
  521.     return 0;
  522. }
  523.  
  524. void radeon_atombios_fini(struct radeon_device *rdev)
  525. {
  526.         if (rdev->mode_info.atom_context) {
  527.                 kfree(rdev->mode_info.atom_context->scratch);
  528.         kfree(rdev->mode_info.atom_context);
  529.         }
  530.         kfree(rdev->mode_info.atom_card_info);
  531. }
  532.  
  533. int radeon_combios_init(struct radeon_device *rdev)
  534. {
  535.         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
  536.         return 0;
  537. }
  538.  
  539. void radeon_combios_fini(struct radeon_device *rdev)
  540. {
  541. }
  542.  
  543. /* if we get transitioned to only one device, tak VGA back */
  544. static unsigned int radeon_vga_set_decode(void *cookie, bool state)
  545. {
  546.         struct radeon_device *rdev = cookie;
  547.         radeon_vga_set_state(rdev, state);
  548.         if (state)
  549.                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  550.                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  551.         else
  552.                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  553. }
  554.  
  555. void radeon_agp_disable(struct radeon_device *rdev)
  556. {
  557.         rdev->flags &= ~RADEON_IS_AGP;
  558.         if (rdev->family >= CHIP_R600) {
  559.                 DRM_INFO("Forcing AGP to PCIE mode\n");
  560.                 rdev->flags |= RADEON_IS_PCIE;
  561.         } else if (rdev->family >= CHIP_RV515 ||
  562.                         rdev->family == CHIP_RV380 ||
  563.                         rdev->family == CHIP_RV410 ||
  564.                         rdev->family == CHIP_R423) {
  565.                 DRM_INFO("Forcing AGP to PCIE mode\n");
  566.                 rdev->flags |= RADEON_IS_PCIE;
  567.                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
  568.                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
  569.         } else {
  570.                 DRM_INFO("Forcing AGP to PCI mode\n");
  571.                 rdev->flags |= RADEON_IS_PCI;
  572.                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
  573.                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
  574.         }
  575.         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  576. }
  577.  
  578. void radeon_check_arguments(struct radeon_device *rdev)
  579. {
  580.         /* vramlimit must be a power of two */
  581.         switch (radeon_vram_limit) {
  582.         case 0:
  583.         case 4:
  584.         case 8:
  585.         case 16:
  586.         case 32:
  587.         case 64:
  588.         case 128:
  589.         case 256:
  590.         case 512:
  591.         case 1024:
  592.         case 2048:
  593.         case 4096:
  594.                 break;
  595.         default:
  596.                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
  597.                                 radeon_vram_limit);
  598.                 radeon_vram_limit = 0;
  599.                 break;
  600.         }
  601.         radeon_vram_limit = radeon_vram_limit << 20;
  602.         /* gtt size must be power of two and greater or equal to 32M */
  603.         switch (radeon_gart_size) {
  604.         case 4:
  605.         case 8:
  606.         case 16:
  607.                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
  608.                                 radeon_gart_size);
  609.                 radeon_gart_size = 512;
  610.                 break;
  611.         case 32:
  612.         case 64:
  613.         case 128:
  614.         case 256:
  615.         case 512:
  616.         case 1024:
  617.         case 2048:
  618.         case 4096:
  619.                 break;
  620.         default:
  621.                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
  622.                                 radeon_gart_size);
  623.                 radeon_gart_size = 512;
  624.                 break;
  625.         }
  626.         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  627.         /* AGP mode can only be -1, 1, 2, 4, 8 */
  628.         switch (radeon_agpmode) {
  629.         case -1:
  630.         case 0:
  631.         case 1:
  632.         case 2:
  633.         case 4:
  634.         case 8:
  635.                 break;
  636.         default:
  637.                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
  638.                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
  639.                 radeon_agpmode = 0;
  640.                 break;
  641.         }
  642. }
  643.  
  644. int radeon_device_init(struct radeon_device *rdev,
  645.                struct drm_device *ddev,
  646.                struct pci_dev *pdev,
  647.                uint32_t flags)
  648. {
  649.         int r;
  650.         int dma_bits;
  651.  
  652.     DRM_INFO("radeon: Initializing kernel modesetting.\n");
  653.     rdev->shutdown = false;
  654.     rdev->ddev = ddev;
  655.     rdev->pdev = pdev;
  656.     rdev->flags = flags;
  657.     rdev->family = flags & RADEON_FAMILY_MASK;
  658.     rdev->is_atom_bios = false;
  659.     rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
  660.     rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  661.     rdev->gpu_lockup = false;
  662.         rdev->accel_working = false;
  663.     /* mutex initialization are all done here so we
  664.      * can recall function without having locking issues */
  665.  //   mutex_init(&rdev->cs_mutex);
  666.  //   mutex_init(&rdev->ib_pool.mutex);
  667.  //   mutex_init(&rdev->cp.mutex);
  668.  //   rwlock_init(&rdev->fence_drv.lock);
  669.  
  670.         /* Set asic functions */
  671.         r = radeon_asic_init(rdev);
  672.         if (r)
  673.                 return r;
  674.         radeon_check_arguments(rdev);
  675.  
  676.         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
  677.                 radeon_agp_disable(rdev);
  678.     }
  679.  
  680.         /* set DMA mask + need_dma32 flags.
  681.          * PCIE - can handle 40-bits.
  682.          * IGP - can handle 40-bits (in theory)
  683.          * AGP - generally dma32 is safest
  684.          * PCI - only dma32
  685.          */
  686.         rdev->need_dma32 = false;
  687.         if (rdev->flags & RADEON_IS_AGP)
  688.                 rdev->need_dma32 = true;
  689.         if (rdev->flags & RADEON_IS_PCI)
  690.                 rdev->need_dma32 = true;
  691.  
  692.         dma_bits = rdev->need_dma32 ? 32 : 40;
  693.         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
  694.     if (r) {
  695.         printk(KERN_WARNING "radeon: No suitable DMA available.\n");
  696.     }
  697.  
  698.     /* Registers mapping */
  699.     /* TODO: block userspace mapping of io register */
  700.     rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
  701.  
  702.     rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
  703.  
  704.     rdev->rmmio =  (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
  705.                                    PG_SW+PG_NOCACHE);
  706.  
  707.     if (rdev->rmmio == NULL) {
  708.         return -ENOMEM;
  709.     }
  710.     DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
  711.     DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
  712.  
  713.         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
  714. //      r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
  715. //      if (r) {
  716. //              return -EINVAL;
  717. //      }
  718.  
  719.         r = radeon_init(rdev);
  720.         if (r)
  721.             return r;
  722.  
  723.         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
  724.                 /* Acceleration not working on AGP card try again
  725.                  * with fallback to PCI or PCIE GART
  726.                  */
  727.                 radeon_gpu_reset(rdev);
  728.                 radeon_fini(rdev);
  729.                 radeon_agp_disable(rdev);
  730.                 r = radeon_init(rdev);
  731.                 if (r)
  732.                 return r;
  733.         }
  734. //      if (radeon_testing) {
  735. //              radeon_test_moves(rdev);
  736. //    }
  737. //      if (radeon_benchmarking) {
  738. //              radeon_benchmark(rdev);
  739. //    }
  740.         return 0;
  741. }
  742.  
  743.  
  744. /*
  745.  * Driver load/unload
  746.  */
  747. int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  748. {
  749.     struct radeon_device *rdev;
  750.     int r;
  751.  
  752.     ENTER();
  753.  
  754.     rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  755.     if (rdev == NULL) {
  756.         return -ENOMEM;
  757.     };
  758.  
  759.     dev->dev_private = (void *)rdev;
  760.  
  761.     /* update BUS flag */
  762.     if (drm_device_is_agp(dev)) {
  763.         flags |= RADEON_IS_AGP;
  764.     } else if (drm_device_is_pcie(dev)) {
  765.         flags |= RADEON_IS_PCIE;
  766.     } else {
  767.         flags |= RADEON_IS_PCI;
  768.     }
  769.  
  770.     /* radeon_device_init should report only fatal error
  771.      * like memory allocation failure or iomapping failure,
  772.      * or memory manager initialization failure, it must
  773.      * properly initialize the GPU MC controller and permit
  774.      * VRAM allocation
  775.      */
  776.     r = radeon_device_init(rdev, dev, dev->pdev, flags);
  777.     if (r) {
  778.         DRM_ERROR("Fatal error while trying to initialize radeon.\n");
  779.         return r;
  780.     }
  781.     /* Again modeset_init should fail only on fatal error
  782.      * otherwise it should provide enough functionalities
  783.      * for shadowfb to run
  784.      */
  785.     if( radeon_modeset )
  786.     {
  787.         r = radeon_modeset_init(rdev);
  788.         if (r) {
  789.             return r;
  790.         }
  791.     };
  792.     return 0;
  793. }
  794.  
  795. videomode_t usermode;
  796.  
  797.  
  798. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  799. {
  800.     static struct drm_device *dev;
  801.     int ret;
  802.  
  803.     ENTER();
  804.  
  805.     dev = kzalloc(sizeof(*dev), 0);
  806.     if (!dev)
  807.         return -ENOMEM;
  808.  
  809.  //   ret = pci_enable_device(pdev);
  810.  //   if (ret)
  811.  //       goto err_g1;
  812.  
  813.  //   pci_set_master(pdev);
  814.  
  815.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  816.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  817.  //       goto err_g2;
  818.  //   }
  819.  
  820.     dev->pdev = pdev;
  821.     dev->pci_device = pdev->device;
  822.     dev->pci_vendor = pdev->vendor;
  823.  
  824.     ret = radeon_driver_load_kms(dev, ent->driver_data );
  825.     if (ret)
  826.         goto err_g4;
  827.  
  828.     if( radeon_modeset )
  829.         init_display_kms(dev->dev_private, &usermode);
  830.     else
  831.         init_display(dev->dev_private, &usermode);
  832.  
  833.     LEAVE();
  834.  
  835.     return 0;
  836.  
  837. err_g4:
  838. //    drm_put_minor(&dev->primary);
  839. //err_g3:
  840. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  841. //        drm_put_minor(&dev->control);
  842. //err_g2:
  843. //    pci_disable_device(pdev);
  844. //err_g1:
  845.     free(dev);
  846.  
  847.     LEAVE();
  848.  
  849.     return ret;
  850. }
  851.  
  852. resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
  853. {
  854.     return pci_resource_start(dev->pdev, resource);
  855. }
  856.  
  857. resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
  858. {
  859.     return pci_resource_len(dev->pdev, resource);
  860. }
  861.  
  862.  
  863. uint32_t __div64_32(uint64_t *n, uint32_t base)
  864. {
  865.         uint64_t rem = *n;
  866.         uint64_t b = base;
  867.         uint64_t res, d = 1;
  868.         uint32_t high = rem >> 32;
  869.  
  870.         /* Reduce the thing a bit first */
  871.         res = 0;
  872.         if (high >= base) {
  873.                 high /= base;
  874.                 res = (uint64_t) high << 32;
  875.                 rem -= (uint64_t) (high*base) << 32;
  876.         }
  877.  
  878.         while ((int64_t)b > 0 && b < rem) {
  879.                 b = b+b;
  880.                 d = d+d;
  881.         }
  882.  
  883.         do {
  884.                 if (rem >= b) {
  885.                         rem -= b;
  886.                         res += d;
  887.                 }
  888.                 b >>= 1;
  889.                 d >>= 1;
  890.         } while (d);
  891.  
  892.         *n = res;
  893.         return rem;
  894. }
  895.  
  896.  
  897. static struct pci_device_id pciidlist[] = {
  898.     radeon_PCI_IDS
  899. };
  900.  
  901.  
  902. #define API_VERSION     0x01000100
  903.  
  904. #define SRV_GETVERSION  0
  905. #define SRV_ENUM_MODES  1
  906. #define SRV_SET_MODE    2
  907.  
  908. int _stdcall display_handler(ioctl_t *io)
  909. {
  910.     int    retval = -1;
  911.     u32_t *inp;
  912.     u32_t *outp;
  913.  
  914.     inp = io->input;
  915.     outp = io->output;
  916.  
  917.     switch(io->io_code)
  918.     {
  919.         case SRV_GETVERSION:
  920.             if(io->out_size==4)
  921.             {
  922.                 *outp  = API_VERSION;
  923.                 retval = 0;
  924.             }
  925.             break;
  926.  
  927.         case SRV_ENUM_MODES:
  928.             dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
  929.                        inp, io->inp_size, io->out_size );
  930.  
  931.             if( radeon_modeset &&
  932.                 (outp != NULL) && (io->out_size == 4) &&
  933.                 (io->inp_size == *outp * sizeof(videomode_t)) )
  934.             {
  935.                 retval = get_modes((videomode_t*)inp, outp);
  936.             };
  937.             break;
  938.  
  939.         case SRV_SET_MODE:
  940.             dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
  941.                        inp, io->inp_size);
  942.  
  943.             if(  radeon_modeset   &&
  944.                 (inp != NULL) &&
  945.                 (io->inp_size == sizeof(videomode_t)) )
  946.             {
  947.                 retval = set_user_mode((videomode_t*)inp);
  948.             };
  949.             break;
  950.     };
  951.  
  952.     return retval;
  953. }
  954.  
  955. static char  log[256];
  956. static pci_dev_t device;
  957.  
  958. u32_t drvEntry(int action, char *cmdline)
  959. {
  960.     struct pci_device_id  *ent;
  961.  
  962.     int     err;
  963.     u32_t   retval = 0;
  964.  
  965.     if(action != 1)
  966.         return 0;
  967.  
  968.     if( GetService("DISPLAY") != 0 )
  969.         return 0;
  970.  
  971.     if( cmdline && *cmdline )
  972.         parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
  973.  
  974.     if(!dbg_open(log))
  975.     {
  976.         strcpy(log, "/rd/1/drivers/atikms.log");
  977.  
  978.         if(!dbg_open(log))
  979.         {
  980.             printf("Can't open %s\nExit\n", log);
  981.             return 0;
  982.         };
  983.     }
  984.     dbgprintf("Radeon RC9 cmdline %s\n", cmdline);
  985.  
  986.     enum_pci_devices();
  987.  
  988.     ent = find_pci_device(&device, pciidlist);
  989.  
  990.     if( unlikely(ent == NULL) )
  991.     {
  992.         dbgprintf("device not found\n");
  993.         return 0;
  994.     };
  995.  
  996.     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
  997.                                 device.pci_dev.device);
  998.  
  999.     err = drm_get_dev(&device.pci_dev, ent);
  1000.  
  1001.     err = RegService("DISPLAY", display_handler);
  1002.  
  1003.     if( err != 0)
  1004.         dbgprintf("Set DISPLAY handler\n");
  1005.  
  1006.     return err;
  1007. };
  1008.