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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include "drmP.h"
  29. #include "radeon_reg.h"
  30. #include "radeon.h"
  31. #include "atom.h"
  32.  
  33. /*
  34.  * BIOS.
  35.  */
  36.  
  37. /* If you boot an IGP board with a discrete card as the primary,
  38.  * the IGP rom is not accessible via the rom bar as the IGP rom is
  39.  * part of the system bios.  On boot, the system bios puts a
  40.  * copy of the igp rom at the start of vram if a discrete card is
  41.  * present.
  42.  */
  43. static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  44. {
  45.         uint8_t __iomem *bios;
  46.         resource_size_t vram_base;
  47.         resource_size_t size = 256 * 1024; /* ??? */
  48.  
  49.         rdev->bios = NULL;
  50.         vram_base = drm_get_resource_start(rdev->ddev, 0);
  51.         bios = ioremap(vram_base, size);
  52.         if (!bios) {
  53.                 return false;
  54.         }
  55.  
  56.         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  57.                 iounmap(bios);
  58.                 return false;
  59.         }
  60.         rdev->bios = kmalloc(size, GFP_KERNEL);
  61.         if (rdev->bios == NULL) {
  62.                 iounmap(bios);
  63.                 return false;
  64.         }
  65.         memcpy(rdev->bios, bios, size);
  66.         iounmap(bios);
  67.         return true;
  68. }
  69.  
  70. static bool radeon_read_bios(struct radeon_device *rdev)
  71. {
  72.         uint8_t __iomem *bios;
  73.     size_t    size;
  74.  
  75.         rdev->bios = NULL;
  76.         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  77.         bios = pci_map_rom(rdev->pdev, &size);
  78.         if (!bios) {
  79.                 return false;
  80.         }
  81.  
  82.         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  83. //       pci_unmap_rom(rdev->pdev, bios);
  84.                 return false;
  85.         }
  86.         rdev->bios = kmalloc(size, GFP_KERNEL);
  87.         if (rdev->bios == NULL) {
  88. //        pci_unmap_rom(rdev->pdev, bios);
  89.                 return false;
  90.         }
  91.         memcpy(rdev->bios, bios, size);
  92. //    pci_unmap_rom(rdev->pdev, bios);
  93.         return true;
  94. }
  95.  
  96. /* ATRM is used to get the BIOS on the discrete cards in
  97.  * dual-gpu systems.
  98.  */
  99. static bool radeon_atrm_get_bios(struct radeon_device *rdev)
  100. {
  101.         int ret;
  102.         int size = 64 * 1024;
  103.         int i;
  104.  
  105.         if (!radeon_atrm_supported(rdev->pdev))
  106.                 return false;
  107.  
  108.         rdev->bios = kmalloc(size, GFP_KERNEL);
  109.         if (!rdev->bios) {
  110.                 DRM_ERROR("Unable to allocate bios\n");
  111.                 return false;
  112.         }
  113.  
  114.         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
  115.                 ret = radeon_atrm_get_bios_chunk(rdev->bios,
  116.                                                  (i * ATRM_BIOS_PAGE),
  117.                                                  ATRM_BIOS_PAGE);
  118.                 if (ret <= 0)
  119.                         break;
  120.         }
  121.  
  122.         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
  123.                 kfree(rdev->bios);
  124.                 return false;
  125.         }
  126.         return true;
  127. }
  128. static bool r700_read_disabled_bios(struct radeon_device *rdev)
  129. {
  130.         uint32_t viph_control;
  131.         uint32_t bus_cntl;
  132.         uint32_t d1vga_control;
  133.         uint32_t d2vga_control;
  134.         uint32_t vga_render_control;
  135.         uint32_t rom_cntl;
  136.         uint32_t cg_spll_func_cntl = 0;
  137.         uint32_t cg_spll_status;
  138.         bool r;
  139.  
  140.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  141.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  142.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  143.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  144.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  145.         rom_cntl = RREG32(R600_ROM_CNTL);
  146.  
  147.         /* disable VIP */
  148.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  149.         /* enable the rom */
  150.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  151.         /* Disable VGA mode */
  152.         WREG32(AVIVO_D1VGA_CONTROL,
  153.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  154.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  155.         WREG32(AVIVO_D2VGA_CONTROL,
  156.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  157.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  158.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  159.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  160.  
  161.         if (rdev->family == CHIP_RV730) {
  162.                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
  163.  
  164.                 /* enable bypass mode */
  165.                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
  166.                                                 R600_SPLL_BYPASS_EN));
  167.  
  168.                 /* wait for SPLL_CHG_STATUS to change to 1 */
  169.                 cg_spll_status = 0;
  170.                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  171.                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  172.  
  173.                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
  174.         } else
  175.                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
  176.  
  177.         r = radeon_read_bios(rdev);
  178.  
  179.         /* restore regs */
  180.         if (rdev->family == CHIP_RV730) {
  181.                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
  182.  
  183.                 /* wait for SPLL_CHG_STATUS to change to 1 */
  184.                 cg_spll_status = 0;
  185.                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  186.                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  187.         }
  188.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  189.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  190.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  191.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  192.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  193.         WREG32(R600_ROM_CNTL, rom_cntl);
  194.         return r;
  195. }
  196.  
  197. static bool r600_read_disabled_bios(struct radeon_device *rdev)
  198. {
  199.         uint32_t viph_control;
  200.         uint32_t bus_cntl;
  201.         uint32_t d1vga_control;
  202.         uint32_t d2vga_control;
  203.         uint32_t vga_render_control;
  204.         uint32_t rom_cntl;
  205.         uint32_t general_pwrmgt;
  206.         uint32_t low_vid_lower_gpio_cntl;
  207.         uint32_t medium_vid_lower_gpio_cntl;
  208.         uint32_t high_vid_lower_gpio_cntl;
  209.         uint32_t ctxsw_vid_lower_gpio_cntl;
  210.         uint32_t lower_gpio_enable;
  211.         bool r;
  212.  
  213.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  214.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  215.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  216.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  217.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  218.         rom_cntl = RREG32(R600_ROM_CNTL);
  219.         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
  220.         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
  221.         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
  222.         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
  223.         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
  224.         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
  225.  
  226.         /* disable VIP */
  227.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  228.         /* enable the rom */
  229.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  230.         /* Disable VGA mode */
  231.         WREG32(AVIVO_D1VGA_CONTROL,
  232.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  233.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  234.         WREG32(AVIVO_D2VGA_CONTROL,
  235.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  236.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  237.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  238.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  239.  
  240.         WREG32(R600_ROM_CNTL,
  241.                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
  242.                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
  243.                 R600_SCK_OVERWRITE));
  244.  
  245.         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
  246.         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
  247.                (low_vid_lower_gpio_cntl & ~0x400));
  248.         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
  249.                (medium_vid_lower_gpio_cntl & ~0x400));
  250.         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
  251.                (high_vid_lower_gpio_cntl & ~0x400));
  252.         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
  253.                (ctxsw_vid_lower_gpio_cntl & ~0x400));
  254.         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
  255.  
  256.         r = radeon_read_bios(rdev);
  257.  
  258.         /* restore regs */
  259.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  260.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  261.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  262.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  263.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  264.         WREG32(R600_ROM_CNTL, rom_cntl);
  265.         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
  266.         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
  267.         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
  268.         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
  269.         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
  270.         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
  271.         return r;
  272. }
  273.  
  274. static bool avivo_read_disabled_bios(struct radeon_device *rdev)
  275. {
  276.         uint32_t seprom_cntl1;
  277.         uint32_t viph_control;
  278.         uint32_t bus_cntl;
  279.         uint32_t d1vga_control;
  280.         uint32_t d2vga_control;
  281.         uint32_t vga_render_control;
  282.         uint32_t gpiopad_a;
  283.         uint32_t gpiopad_en;
  284.         uint32_t gpiopad_mask;
  285.         bool r;
  286.  
  287.         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  288.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  289.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  290.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  291.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  292.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  293.         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
  294.         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
  295.         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
  296.  
  297.         WREG32(RADEON_SEPROM_CNTL1,
  298.                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  299.                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  300.         WREG32(RADEON_GPIOPAD_A, 0);
  301.         WREG32(RADEON_GPIOPAD_EN, 0);
  302.         WREG32(RADEON_GPIOPAD_MASK, 0);
  303.  
  304.         /* disable VIP */
  305.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  306.  
  307.         /* enable the rom */
  308.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  309.  
  310.         /* Disable VGA mode */
  311.         WREG32(AVIVO_D1VGA_CONTROL,
  312.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  313.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  314.         WREG32(AVIVO_D2VGA_CONTROL,
  315.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  316.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  317.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  318.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  319.  
  320.         r = radeon_read_bios(rdev);
  321.  
  322.         /* restore regs */
  323.         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  324.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  325.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  326.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  327.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  328.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  329.         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
  330.         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
  331.         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
  332.         return r;
  333. }
  334.  
  335. static bool legacy_read_disabled_bios(struct radeon_device *rdev)
  336. {
  337.         uint32_t seprom_cntl1;
  338.         uint32_t viph_control;
  339.         uint32_t bus_cntl;
  340.         uint32_t crtc_gen_cntl;
  341.         uint32_t crtc2_gen_cntl;
  342.         uint32_t crtc_ext_cntl;
  343.         uint32_t fp2_gen_cntl;
  344.         bool r;
  345.  
  346.         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  347.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  348.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  349.         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
  350.         crtc2_gen_cntl = 0;
  351.         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  352.         fp2_gen_cntl = 0;
  353.  
  354.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  355.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  356.         }
  357.  
  358.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  359.                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  360.         }
  361.  
  362.         WREG32(RADEON_SEPROM_CNTL1,
  363.                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  364.                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  365.  
  366.         /* disable VIP */
  367.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  368.  
  369.         /* enable the rom */
  370.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  371.  
  372.         /* Turn off mem requests and CRTC for both controllers */
  373.         WREG32(RADEON_CRTC_GEN_CNTL,
  374.                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
  375.                 (RADEON_CRTC_DISP_REQ_EN_B |
  376.                  RADEON_CRTC_EXT_DISP_EN)));
  377.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  378.                 WREG32(RADEON_CRTC2_GEN_CNTL,
  379.                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
  380.                         RADEON_CRTC2_DISP_REQ_EN_B));
  381.         }
  382.         /* Turn off CRTC */
  383.         WREG32(RADEON_CRTC_EXT_CNTL,
  384.                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
  385.                 (RADEON_CRTC_SYNC_TRISTAT |
  386.                  RADEON_CRTC_DISPLAY_DIS)));
  387.  
  388.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  389.                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
  390.         }
  391.  
  392.         r = radeon_read_bios(rdev);
  393.  
  394.         /* restore regs */
  395.         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  396.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  397.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  398.         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
  399.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  400.                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  401.         }
  402.         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  403.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  404.                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  405.         }
  406.         return r;
  407. }
  408.  
  409. static bool radeon_read_disabled_bios(struct radeon_device *rdev)
  410. {
  411.         if (rdev->flags & RADEON_IS_IGP)
  412.                 return igp_read_bios_from_vram(rdev);
  413.         else if (rdev->family >= CHIP_RV770)
  414.                 return r700_read_disabled_bios(rdev);
  415.         else if (rdev->family >= CHIP_R600)
  416.                 return r600_read_disabled_bios(rdev);
  417.         else if (rdev->family >= CHIP_RS600)
  418.                 return avivo_read_disabled_bios(rdev);
  419.         else
  420.                 return legacy_read_disabled_bios(rdev);
  421. }
  422.  
  423.  
  424. bool radeon_get_bios(struct radeon_device *rdev)
  425. {
  426.         bool r;
  427.         uint16_t tmp;
  428.  
  429.         r = radeon_atrm_get_bios(rdev);
  430.         if (r == false)
  431.                 r = igp_read_bios_from_vram(rdev);
  432.                 if (r == false)
  433.                         r = radeon_read_bios(rdev);
  434.         if (r == false) {
  435.                 r = radeon_read_disabled_bios(rdev);
  436.         }
  437.         if (r == false || rdev->bios == NULL) {
  438.                 DRM_ERROR("Unable to locate a BIOS ROM\n");
  439.                 rdev->bios = NULL;
  440.                 return false;
  441.         }
  442.         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
  443.                 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
  444.                 goto free_bios;
  445.         }
  446.  
  447.         tmp = RBIOS16(0x18);
  448.         if (RBIOS8(tmp + 0x14) != 0x0) {
  449.                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
  450.                 goto free_bios;
  451.         }
  452.  
  453.         rdev->bios_header_start = RBIOS16(0x48);
  454.         if (!rdev->bios_header_start) {
  455.                 goto free_bios;
  456.         }
  457.         tmp = rdev->bios_header_start + 4;
  458.         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
  459.             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
  460.                 rdev->is_atom_bios = true;
  461.         } else {
  462.                 rdev->is_atom_bios = false;
  463.         }
  464.  
  465.         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
  466.         return true;
  467. free_bios:
  468.         kfree(rdev->bios);
  469.         rdev->bios = NULL;
  470.         return false;
  471. }
  472.