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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include "drmP.h"
  29. #include "radeon_reg.h"
  30. #include "radeon.h"
  31. #include "atom.h"
  32.  
  33. /*
  34.  * BIOS.
  35.  */
  36.  
  37. /* If you boot an IGP board with a discrete card as the primary,
  38.  * the IGP rom is not accessible via the rom bar as the IGP rom is
  39.  * part of the system bios.  On boot, the system bios puts a
  40.  * copy of the igp rom at the start of vram if a discrete card is
  41.  * present.
  42.  */
  43. static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  44. {
  45.         uint8_t __iomem *bios;
  46.         resource_size_t vram_base;
  47.         resource_size_t size = 256 * 1024; /* ??? */
  48.  
  49.         rdev->bios = NULL;
  50.         vram_base = drm_get_resource_start(rdev->ddev, 0);
  51.         bios = ioremap(vram_base, size);
  52.         if (!bios) {
  53.                 return false;
  54.         }
  55.  
  56.         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  57.                 iounmap(bios);
  58.                 return false;
  59.         }
  60.         rdev->bios = kmalloc(size, GFP_KERNEL);
  61.         if (rdev->bios == NULL) {
  62.                 iounmap(bios);
  63.                 return false;
  64.         }
  65.         memcpy(rdev->bios, bios, size);
  66.         iounmap(bios);
  67.         return true;
  68. }
  69.  
  70. static bool radeon_read_bios(struct radeon_device *rdev)
  71. {
  72.         uint8_t __iomem *bios;
  73.     size_t    size;
  74.  
  75.         rdev->bios = NULL;
  76.         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  77.         bios = pci_map_rom(rdev->pdev, &size);
  78.         if (!bios) {
  79.                 return false;
  80.         }
  81.  
  82.         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  83. //       pci_unmap_rom(rdev->pdev, bios);
  84.                 return false;
  85.         }
  86.         rdev->bios = kmalloc(size, GFP_KERNEL);
  87.         if (rdev->bios == NULL) {
  88. //        pci_unmap_rom(rdev->pdev, bios);
  89.                 return false;
  90.         }
  91.         memcpy(rdev->bios, bios, size);
  92. //    pci_unmap_rom(rdev->pdev, bios);
  93.         return true;
  94. }
  95.  
  96. static bool r700_read_disabled_bios(struct radeon_device *rdev)
  97. {
  98.         uint32_t viph_control;
  99.         uint32_t bus_cntl;
  100.         uint32_t d1vga_control;
  101.         uint32_t d2vga_control;
  102.         uint32_t vga_render_control;
  103.         uint32_t rom_cntl;
  104.         uint32_t cg_spll_func_cntl = 0;
  105.         uint32_t cg_spll_status;
  106.         bool r;
  107.  
  108.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  109.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  110.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  111.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  112.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  113.         rom_cntl = RREG32(R600_ROM_CNTL);
  114.  
  115.         /* disable VIP */
  116.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  117.         /* enable the rom */
  118.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  119.         /* Disable VGA mode */
  120.         WREG32(AVIVO_D1VGA_CONTROL,
  121.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  122.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  123.         WREG32(AVIVO_D2VGA_CONTROL,
  124.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  125.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  126.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  127.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  128.  
  129.         if (rdev->family == CHIP_RV730) {
  130.                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
  131.  
  132.                 /* enable bypass mode */
  133.                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
  134.                                                 R600_SPLL_BYPASS_EN));
  135.  
  136.                 /* wait for SPLL_CHG_STATUS to change to 1 */
  137.                 cg_spll_status = 0;
  138.                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  139.                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  140.  
  141.                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
  142.         } else
  143.                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
  144.  
  145.         r = radeon_read_bios(rdev);
  146.  
  147.         /* restore regs */
  148.         if (rdev->family == CHIP_RV730) {
  149.                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
  150.  
  151.                 /* wait for SPLL_CHG_STATUS to change to 1 */
  152.                 cg_spll_status = 0;
  153.                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  154.                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  155.         }
  156.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  157.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  158.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  159.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  160.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  161.         WREG32(R600_ROM_CNTL, rom_cntl);
  162.         return r;
  163. }
  164.  
  165. static bool r600_read_disabled_bios(struct radeon_device *rdev)
  166. {
  167.         uint32_t viph_control;
  168.         uint32_t bus_cntl;
  169.         uint32_t d1vga_control;
  170.         uint32_t d2vga_control;
  171.         uint32_t vga_render_control;
  172.         uint32_t rom_cntl;
  173.         uint32_t general_pwrmgt;
  174.         uint32_t low_vid_lower_gpio_cntl;
  175.         uint32_t medium_vid_lower_gpio_cntl;
  176.         uint32_t high_vid_lower_gpio_cntl;
  177.         uint32_t ctxsw_vid_lower_gpio_cntl;
  178.         uint32_t lower_gpio_enable;
  179.         bool r;
  180.  
  181.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  182.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  183.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  184.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  185.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  186.         rom_cntl = RREG32(R600_ROM_CNTL);
  187.         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
  188.         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
  189.         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
  190.         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
  191.         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
  192.         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
  193.  
  194.         /* disable VIP */
  195.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  196.         /* enable the rom */
  197.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  198.         /* Disable VGA mode */
  199.         WREG32(AVIVO_D1VGA_CONTROL,
  200.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  201.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  202.         WREG32(AVIVO_D2VGA_CONTROL,
  203.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  204.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  205.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  206.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  207.  
  208.         WREG32(R600_ROM_CNTL,
  209.                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
  210.                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
  211.                 R600_SCK_OVERWRITE));
  212.  
  213.         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
  214.         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
  215.                (low_vid_lower_gpio_cntl & ~0x400));
  216.         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
  217.                (medium_vid_lower_gpio_cntl & ~0x400));
  218.         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
  219.                (high_vid_lower_gpio_cntl & ~0x400));
  220.         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
  221.                (ctxsw_vid_lower_gpio_cntl & ~0x400));
  222.         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
  223.  
  224.         r = radeon_read_bios(rdev);
  225.  
  226.         /* restore regs */
  227.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  228.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  229.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  230.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  231.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  232.         WREG32(R600_ROM_CNTL, rom_cntl);
  233.         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
  234.         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
  235.         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
  236.         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
  237.         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
  238.         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
  239.         return r;
  240. }
  241.  
  242. static bool avivo_read_disabled_bios(struct radeon_device *rdev)
  243. {
  244.         uint32_t seprom_cntl1;
  245.         uint32_t viph_control;
  246.         uint32_t bus_cntl;
  247.         uint32_t d1vga_control;
  248.         uint32_t d2vga_control;
  249.         uint32_t vga_render_control;
  250.         uint32_t gpiopad_a;
  251.         uint32_t gpiopad_en;
  252.         uint32_t gpiopad_mask;
  253.         bool r;
  254.  
  255.         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  256.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  257.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  258.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  259.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  260.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  261.         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
  262.         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
  263.         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
  264.  
  265.         WREG32(RADEON_SEPROM_CNTL1,
  266.                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  267.                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  268.         WREG32(RADEON_GPIOPAD_A, 0);
  269.         WREG32(RADEON_GPIOPAD_EN, 0);
  270.         WREG32(RADEON_GPIOPAD_MASK, 0);
  271.  
  272.         /* disable VIP */
  273.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  274.  
  275.         /* enable the rom */
  276.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  277.  
  278.         /* Disable VGA mode */
  279.         WREG32(AVIVO_D1VGA_CONTROL,
  280.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  281.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  282.         WREG32(AVIVO_D2VGA_CONTROL,
  283.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  284.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  285.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  286.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  287.  
  288.         r = radeon_read_bios(rdev);
  289.  
  290.         /* restore regs */
  291.         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  292.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  293.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  294.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  295.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  296.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  297.         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
  298.         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
  299.         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
  300.         return r;
  301. }
  302.  
  303. static bool legacy_read_disabled_bios(struct radeon_device *rdev)
  304. {
  305.         uint32_t seprom_cntl1;
  306.         uint32_t viph_control;
  307.         uint32_t bus_cntl;
  308.         uint32_t crtc_gen_cntl;
  309.         uint32_t crtc2_gen_cntl;
  310.         uint32_t crtc_ext_cntl;
  311.         uint32_t fp2_gen_cntl;
  312.         bool r;
  313.  
  314.         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  315.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  316.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  317.         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
  318.         crtc2_gen_cntl = 0;
  319.         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  320.         fp2_gen_cntl = 0;
  321.  
  322.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  323.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  324.         }
  325.  
  326.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  327.                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  328.         }
  329.  
  330.         WREG32(RADEON_SEPROM_CNTL1,
  331.                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  332.                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  333.  
  334.         /* disable VIP */
  335.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  336.  
  337.         /* enable the rom */
  338.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  339.  
  340.         /* Turn off mem requests and CRTC for both controllers */
  341.         WREG32(RADEON_CRTC_GEN_CNTL,
  342.                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
  343.                 (RADEON_CRTC_DISP_REQ_EN_B |
  344.                  RADEON_CRTC_EXT_DISP_EN)));
  345.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  346.                 WREG32(RADEON_CRTC2_GEN_CNTL,
  347.                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
  348.                         RADEON_CRTC2_DISP_REQ_EN_B));
  349.         }
  350.         /* Turn off CRTC */
  351.         WREG32(RADEON_CRTC_EXT_CNTL,
  352.                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
  353.                 (RADEON_CRTC_SYNC_TRISTAT |
  354.                  RADEON_CRTC_DISPLAY_DIS)));
  355.  
  356.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  357.                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
  358.         }
  359.  
  360.         r = radeon_read_bios(rdev);
  361.  
  362.         /* restore regs */
  363.         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  364.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  365.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  366.         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
  367.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  368.                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  369.         }
  370.         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  371.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  372.                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  373.         }
  374.         return r;
  375. }
  376.  
  377. static bool radeon_read_disabled_bios(struct radeon_device *rdev)
  378. {
  379.         if (rdev->flags & RADEON_IS_IGP)
  380.                 return igp_read_bios_from_vram(rdev);
  381.         else if (rdev->family >= CHIP_RV770)
  382.                 return r700_read_disabled_bios(rdev);
  383.         else if (rdev->family >= CHIP_R600)
  384.                 return r600_read_disabled_bios(rdev);
  385.         else if (rdev->family >= CHIP_RS600)
  386.                 return avivo_read_disabled_bios(rdev);
  387.         else
  388.                 return legacy_read_disabled_bios(rdev);
  389. }
  390.  
  391. bool radeon_get_bios(struct radeon_device *rdev)
  392. {
  393.         bool r;
  394.         uint16_t tmp;
  395.  
  396.         if (rdev->flags & RADEON_IS_IGP) {
  397.                 r = igp_read_bios_from_vram(rdev);
  398.                 if (r == false)
  399.                         r = radeon_read_bios(rdev);
  400.         } else
  401.         r = radeon_read_bios(rdev);
  402.         if (r == false) {
  403.                 r = radeon_read_disabled_bios(rdev);
  404.         }
  405.         if (r == false || rdev->bios == NULL) {
  406.                 DRM_ERROR("Unable to locate a BIOS ROM\n");
  407.                 rdev->bios = NULL;
  408.                 return false;
  409.         }
  410.         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
  411.                 goto free_bios;
  412.         }
  413.  
  414.         rdev->bios_header_start = RBIOS16(0x48);
  415.         if (!rdev->bios_header_start) {
  416.                 goto free_bios;
  417.         }
  418.         tmp = rdev->bios_header_start + 4;
  419.         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
  420.             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
  421.                 rdev->is_atom_bios = true;
  422.         } else {
  423.                 rdev->is_atom_bios = false;
  424.         }
  425.  
  426.         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
  427.         return true;
  428. free_bios:
  429.         kfree(rdev->bios);
  430.         rdev->bios = NULL;
  431.         return false;
  432. }
  433.