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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include "drmP.h"
  29. #include "radeon_reg.h"
  30. #include "radeon.h"
  31. #include "atom.h"
  32.  
  33. /*
  34.  * BIOS.
  35.  */
  36.  
  37. /* If you boot an IGP board with a discrete card as the primary,
  38.  * the IGP rom is not accessible via the rom bar as the IGP rom is
  39.  * part of the system bios.  On boot, the system bios puts a
  40.  * copy of the igp rom at the start of vram if a discrete card is
  41.  * present.
  42.  */
  43. static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  44. {
  45.         uint8_t __iomem *bios;
  46.         resource_size_t vram_base;
  47.         resource_size_t size = 256 * 1024; /* ??? */
  48.  
  49.         rdev->bios = NULL;
  50.         vram_base = drm_get_resource_start(rdev->ddev, 0);
  51.         bios = ioremap(vram_base, size);
  52.         if (!bios) {
  53.                 DRM_ERROR("Unable to mmap vram\n");
  54.                 return false;
  55.         }
  56.  
  57.         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  58.                 iounmap(bios);
  59.                 DRM_ERROR("bad rom signature\n");
  60.                 return false;
  61.         }
  62.         rdev->bios = kmalloc(size, GFP_KERNEL);
  63.         if (rdev->bios == NULL) {
  64.                 iounmap(bios);
  65.                 DRM_ERROR("kmalloc failed\n");
  66.                 return false;
  67.         }
  68.         memcpy(rdev->bios, bios, size);
  69.         iounmap(bios);
  70.         return true;
  71. }
  72.  
  73. static bool radeon_read_bios(struct radeon_device *rdev)
  74. {
  75.         uint8_t __iomem *bios;
  76.     size_t    size;
  77.  
  78.         rdev->bios = NULL;
  79.         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  80.         bios = pci_map_rom(rdev->pdev, &size);
  81.         if (!bios) {
  82.                 return false;
  83.         }
  84.  
  85.         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  86. //       pci_unmap_rom(rdev->pdev, bios);
  87.                 return false;
  88.         }
  89.         rdev->bios = kmalloc(size, GFP_KERNEL);
  90.         if (rdev->bios == NULL) {
  91. //       pci_unmap_rom(rdev->pdev, bios);
  92.                 return false;
  93.         }
  94.         memcpy(rdev->bios, bios, size);
  95. //   pci_unmap_rom(rdev->pdev, bios);
  96.         return true;
  97. }
  98.  
  99. static bool r700_read_disabled_bios(struct radeon_device *rdev)
  100. {
  101.         uint32_t viph_control;
  102.         uint32_t bus_cntl;
  103.         uint32_t d1vga_control;
  104.         uint32_t d2vga_control;
  105.         uint32_t vga_render_control;
  106.         uint32_t rom_cntl;
  107.         uint32_t cg_spll_func_cntl = 0;
  108.         uint32_t cg_spll_status;
  109.         bool r;
  110.  
  111.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  112.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  113.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  114.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  115.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  116.         rom_cntl = RREG32(R600_ROM_CNTL);
  117.  
  118.         /* disable VIP */
  119.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  120.         /* enable the rom */
  121.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  122.         /* Disable VGA mode */
  123.         WREG32(AVIVO_D1VGA_CONTROL,
  124.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  125.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  126.         WREG32(AVIVO_D2VGA_CONTROL,
  127.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  128.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  129.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  130.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  131.  
  132.         if (rdev->family == CHIP_RV730) {
  133.                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
  134.  
  135.                 /* enable bypass mode */
  136.                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
  137.                                                 R600_SPLL_BYPASS_EN));
  138.  
  139.                 /* wait for SPLL_CHG_STATUS to change to 1 */
  140.                 cg_spll_status = 0;
  141.                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  142.                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  143.  
  144.                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
  145.         } else
  146.                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
  147.  
  148.         r = radeon_read_bios(rdev);
  149.  
  150.         /* restore regs */
  151.         if (rdev->family == CHIP_RV730) {
  152.                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
  153.  
  154.                 /* wait for SPLL_CHG_STATUS to change to 1 */
  155.                 cg_spll_status = 0;
  156.                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  157.                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  158.         }
  159.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  160.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  161.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  162.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  163.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  164.         WREG32(R600_ROM_CNTL, rom_cntl);
  165.         return r;
  166. }
  167.  
  168. static bool r600_read_disabled_bios(struct radeon_device *rdev)
  169. {
  170.         uint32_t viph_control;
  171.         uint32_t bus_cntl;
  172.         uint32_t d1vga_control;
  173.         uint32_t d2vga_control;
  174.         uint32_t vga_render_control;
  175.         uint32_t rom_cntl;
  176.         uint32_t general_pwrmgt;
  177.         uint32_t low_vid_lower_gpio_cntl;
  178.         uint32_t medium_vid_lower_gpio_cntl;
  179.         uint32_t high_vid_lower_gpio_cntl;
  180.         uint32_t ctxsw_vid_lower_gpio_cntl;
  181.         uint32_t lower_gpio_enable;
  182.         bool r;
  183.  
  184.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  185.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  186.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  187.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  188.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  189.         rom_cntl = RREG32(R600_ROM_CNTL);
  190.         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
  191.         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
  192.         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
  193.         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
  194.         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
  195.         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
  196.  
  197.         /* disable VIP */
  198.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  199.         /* enable the rom */
  200.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  201.         /* Disable VGA mode */
  202.         WREG32(AVIVO_D1VGA_CONTROL,
  203.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  204.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  205.         WREG32(AVIVO_D2VGA_CONTROL,
  206.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  207.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  208.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  209.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  210.  
  211.         WREG32(R600_ROM_CNTL,
  212.                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
  213.                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
  214.                 R600_SCK_OVERWRITE));
  215.  
  216.         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
  217.         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
  218.                (low_vid_lower_gpio_cntl & ~0x400));
  219.         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
  220.                (medium_vid_lower_gpio_cntl & ~0x400));
  221.         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
  222.                (high_vid_lower_gpio_cntl & ~0x400));
  223.         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
  224.                (ctxsw_vid_lower_gpio_cntl & ~0x400));
  225.         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
  226.  
  227.         r = radeon_read_bios(rdev);
  228.  
  229.         /* restore regs */
  230.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  231.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  232.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  233.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  234.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  235.         WREG32(R600_ROM_CNTL, rom_cntl);
  236.         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
  237.         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
  238.         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
  239.         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
  240.         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
  241.         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
  242.         return r;
  243. }
  244.  
  245. static bool avivo_read_disabled_bios(struct radeon_device *rdev)
  246. {
  247.         uint32_t seprom_cntl1;
  248.         uint32_t viph_control;
  249.         uint32_t bus_cntl;
  250.         uint32_t d1vga_control;
  251.         uint32_t d2vga_control;
  252.         uint32_t vga_render_control;
  253.         uint32_t gpiopad_a;
  254.         uint32_t gpiopad_en;
  255.         uint32_t gpiopad_mask;
  256.         bool r;
  257.  
  258.         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  259.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  260.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  261.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  262.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  263.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  264.         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
  265.         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
  266.         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
  267.  
  268.         WREG32(RADEON_SEPROM_CNTL1,
  269.                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  270.                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  271.         WREG32(RADEON_GPIOPAD_A, 0);
  272.         WREG32(RADEON_GPIOPAD_EN, 0);
  273.         WREG32(RADEON_GPIOPAD_MASK, 0);
  274.  
  275.         /* disable VIP */
  276.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  277.  
  278.         /* enable the rom */
  279.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  280.  
  281.         /* Disable VGA mode */
  282.         WREG32(AVIVO_D1VGA_CONTROL,
  283.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  284.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  285.         WREG32(AVIVO_D2VGA_CONTROL,
  286.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  287.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  288.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  289.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  290.  
  291.         r = radeon_read_bios(rdev);
  292.  
  293.         /* restore regs */
  294.         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  295.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  296.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  297.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  298.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  299.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  300.         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
  301.         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
  302.         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
  303.         return r;
  304. }
  305.  
  306. static bool legacy_read_disabled_bios(struct radeon_device *rdev)
  307. {
  308.         uint32_t seprom_cntl1;
  309.         uint32_t viph_control;
  310.         uint32_t bus_cntl;
  311.         uint32_t crtc_gen_cntl;
  312.         uint32_t crtc2_gen_cntl;
  313.         uint32_t crtc_ext_cntl;
  314.         uint32_t fp2_gen_cntl;
  315.         bool r;
  316.  
  317.         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  318.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  319.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  320.         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
  321.         crtc2_gen_cntl = 0;
  322.         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  323.         fp2_gen_cntl = 0;
  324.  
  325.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  326.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  327.         }
  328.  
  329.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  330.                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  331.         }
  332.  
  333.         WREG32(RADEON_SEPROM_CNTL1,
  334.                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  335.                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  336.  
  337.         /* disable VIP */
  338.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  339.  
  340.         /* enable the rom */
  341.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  342.  
  343.         /* Turn off mem requests and CRTC for both controllers */
  344.         WREG32(RADEON_CRTC_GEN_CNTL,
  345.                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
  346.                 (RADEON_CRTC_DISP_REQ_EN_B |
  347.                  RADEON_CRTC_EXT_DISP_EN)));
  348.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  349.                 WREG32(RADEON_CRTC2_GEN_CNTL,
  350.                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
  351.                         RADEON_CRTC2_DISP_REQ_EN_B));
  352.         }
  353.         /* Turn off CRTC */
  354.         WREG32(RADEON_CRTC_EXT_CNTL,
  355.                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
  356.                 (RADEON_CRTC_SYNC_TRISTAT |
  357.                  RADEON_CRTC_DISPLAY_DIS)));
  358.  
  359.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  360.                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
  361.         }
  362.  
  363.         r = radeon_read_bios(rdev);
  364.  
  365.         /* restore regs */
  366.         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  367.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  368.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  369.         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
  370.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  371.                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  372.         }
  373.         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  374.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  375.                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  376.         }
  377.         return r;
  378. }
  379.  
  380. static bool radeon_read_disabled_bios(struct radeon_device *rdev)
  381. {
  382.         if (rdev->flags & RADEON_IS_IGP)
  383.                 return igp_read_bios_from_vram(rdev);
  384.         else if (rdev->family >= CHIP_RV770)
  385.                 return r700_read_disabled_bios(rdev);
  386.         else if (rdev->family >= CHIP_R600)
  387.                 return r600_read_disabled_bios(rdev);
  388.         else if (rdev->family >= CHIP_RS600)
  389.                 return avivo_read_disabled_bios(rdev);
  390.         else
  391.                 return legacy_read_disabled_bios(rdev);
  392. }
  393.  
  394. bool radeon_get_bios(struct radeon_device *rdev)
  395. {
  396.         bool r;
  397.         uint16_t tmp;
  398.  
  399.         if (rdev->flags & RADEON_IS_IGP) {
  400.                 r = igp_read_bios_from_vram(rdev);
  401.                 if (r == false)
  402.                         r = radeon_read_bios(rdev);
  403.         } else
  404.         r = radeon_read_bios(rdev);
  405.         if (r == false) {
  406.                 r = radeon_read_disabled_bios(rdev);
  407.         }
  408.         if (r == false || rdev->bios == NULL) {
  409.                 DRM_ERROR("Unable to locate a BIOS ROM\n");
  410.                 rdev->bios = NULL;
  411.                 return false;
  412.         }
  413.         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
  414.                 goto free_bios;
  415.         }
  416.  
  417.         rdev->bios_header_start = RBIOS16(0x48);
  418.         if (!rdev->bios_header_start) {
  419.                 goto free_bios;
  420.         }
  421.         tmp = rdev->bios_header_start + 4;
  422.         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
  423.             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
  424.                 rdev->is_atom_bios = true;
  425.         } else {
  426.                 rdev->is_atom_bios = false;
  427.         }
  428.  
  429.         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
  430.         return true;
  431. free_bios:
  432.         kfree(rdev->bios);
  433.         rdev->bios = NULL;
  434.         return false;
  435. }
  436.