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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include "drmP.h"
  29. #include "radeon_reg.h"
  30. #include "radeon.h"
  31. #include "atom.h"
  32.  
  33. /*
  34.  * BIOS.
  35.  */
  36. static bool radeon_read_bios(struct radeon_device *rdev)
  37. {
  38.     uint8_t  *bios;
  39.     size_t    size;
  40.  
  41.         rdev->bios = NULL;
  42.     bios = (uint8_t*)pci_map_rom(rdev->pdev, &size);
  43.         if (!bios) {
  44.                 return false;
  45.         }
  46.  
  47.         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  48. //       pci_unmap_rom(rdev->pdev, bios);
  49.                 return false;
  50.         }
  51.     rdev->bios = malloc(size);
  52.         if (rdev->bios == NULL) {
  53. //       pci_unmap_rom(rdev->pdev, bios);
  54.                 return false;
  55.         }
  56.         memcpy(rdev->bios, bios, size);
  57. //   pci_unmap_rom(rdev->pdev, bios);
  58.         return true;
  59. }
  60.  
  61. #if 0
  62.  
  63. static bool r700_read_disabled_bios(struct radeon_device *rdev)
  64. {
  65.         uint32_t viph_control;
  66.         uint32_t bus_cntl;
  67.         uint32_t d1vga_control;
  68.         uint32_t d2vga_control;
  69.         uint32_t vga_render_control;
  70.         uint32_t rom_cntl;
  71.         uint32_t cg_spll_func_cntl = 0;
  72.         uint32_t cg_spll_status;
  73.         bool r;
  74.  
  75.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  76.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  77.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  78.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  79.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  80.         rom_cntl = RREG32(R600_ROM_CNTL);
  81.  
  82.         /* disable VIP */
  83.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  84.         /* enable the rom */
  85.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  86.         /* Disable VGA mode */
  87.         WREG32(AVIVO_D1VGA_CONTROL,
  88.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  89.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  90.         WREG32(AVIVO_D2VGA_CONTROL,
  91.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  92.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  93.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  94.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  95.  
  96.         if (rdev->family == CHIP_RV730) {
  97.                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
  98.  
  99.                 /* enable bypass mode */
  100.                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
  101.                                                 R600_SPLL_BYPASS_EN));
  102.  
  103.                 /* wait for SPLL_CHG_STATUS to change to 1 */
  104.                 cg_spll_status = 0;
  105.                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  106.                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  107.  
  108.                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
  109.         } else
  110.                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
  111.  
  112.         r = radeon_read_bios(rdev);
  113.  
  114.         /* restore regs */
  115.         if (rdev->family == CHIP_RV730) {
  116.                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
  117.  
  118.                 /* wait for SPLL_CHG_STATUS to change to 1 */
  119.                 cg_spll_status = 0;
  120.                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  121.                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  122.         }
  123.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  124.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  125.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  126.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  127.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  128.         WREG32(R600_ROM_CNTL, rom_cntl);
  129.         return r;
  130. }
  131.  
  132. static bool r600_read_disabled_bios(struct radeon_device *rdev)
  133. {
  134.         uint32_t viph_control;
  135.         uint32_t bus_cntl;
  136.         uint32_t d1vga_control;
  137.         uint32_t d2vga_control;
  138.         uint32_t vga_render_control;
  139.         uint32_t rom_cntl;
  140.         uint32_t general_pwrmgt;
  141.         uint32_t low_vid_lower_gpio_cntl;
  142.         uint32_t medium_vid_lower_gpio_cntl;
  143.         uint32_t high_vid_lower_gpio_cntl;
  144.         uint32_t ctxsw_vid_lower_gpio_cntl;
  145.         uint32_t lower_gpio_enable;
  146.         bool r;
  147.  
  148.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  149.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  150.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  151.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  152.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  153.         rom_cntl = RREG32(R600_ROM_CNTL);
  154.         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
  155.         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
  156.         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
  157.         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
  158.         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
  159.         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
  160.  
  161.         /* disable VIP */
  162.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  163.         /* enable the rom */
  164.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  165.         /* Disable VGA mode */
  166.         WREG32(AVIVO_D1VGA_CONTROL,
  167.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  168.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  169.         WREG32(AVIVO_D2VGA_CONTROL,
  170.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  171.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  172.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  173.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  174.  
  175.         WREG32(R600_ROM_CNTL,
  176.                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
  177.                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
  178.                 R600_SCK_OVERWRITE));
  179.  
  180.         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
  181.         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
  182.                (low_vid_lower_gpio_cntl & ~0x400));
  183.         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
  184.                (medium_vid_lower_gpio_cntl & ~0x400));
  185.         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
  186.                (high_vid_lower_gpio_cntl & ~0x400));
  187.         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
  188.                (ctxsw_vid_lower_gpio_cntl & ~0x400));
  189.         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
  190.  
  191.         r = radeon_read_bios(rdev);
  192.  
  193.         /* restore regs */
  194.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  195.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  196.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  197.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  198.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  199.         WREG32(R600_ROM_CNTL, rom_cntl);
  200.         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
  201.         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
  202.         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
  203.         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
  204.         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
  205.         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
  206.         return r;
  207. }
  208.  
  209. static bool avivo_read_disabled_bios(struct radeon_device *rdev)
  210. {
  211.         uint32_t seprom_cntl1;
  212.         uint32_t viph_control;
  213.         uint32_t bus_cntl;
  214.         uint32_t d1vga_control;
  215.         uint32_t d2vga_control;
  216.         uint32_t vga_render_control;
  217.         uint32_t gpiopad_a;
  218.         uint32_t gpiopad_en;
  219.         uint32_t gpiopad_mask;
  220.         bool r;
  221.  
  222.         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  223.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  224.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  225.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  226.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  227.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  228.         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
  229.         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
  230.         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
  231.  
  232.         WREG32(RADEON_SEPROM_CNTL1,
  233.                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  234.                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  235.         WREG32(RADEON_GPIOPAD_A, 0);
  236.         WREG32(RADEON_GPIOPAD_EN, 0);
  237.         WREG32(RADEON_GPIOPAD_MASK, 0);
  238.  
  239.         /* disable VIP */
  240.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  241.  
  242.         /* enable the rom */
  243.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  244.  
  245.         /* Disable VGA mode */
  246.         WREG32(AVIVO_D1VGA_CONTROL,
  247.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  248.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  249.         WREG32(AVIVO_D2VGA_CONTROL,
  250.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  251.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  252.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  253.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  254.  
  255.         r = radeon_read_bios(rdev);
  256.  
  257.         /* restore regs */
  258.         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  259.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  260.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  261.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  262.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  263.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  264.         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
  265.         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
  266.         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
  267.         return r;
  268. }
  269.  
  270. static bool legacy_read_disabled_bios(struct radeon_device *rdev)
  271. {
  272.         uint32_t seprom_cntl1;
  273.         uint32_t viph_control;
  274.         uint32_t bus_cntl;
  275.         uint32_t crtc_gen_cntl;
  276.         uint32_t crtc2_gen_cntl;
  277.         uint32_t crtc_ext_cntl;
  278.         uint32_t fp2_gen_cntl;
  279.         bool r;
  280.  
  281.         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  282.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  283.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  284.         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
  285.         crtc2_gen_cntl = 0;
  286.         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  287.         fp2_gen_cntl = 0;
  288.  
  289.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  290.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  291.         }
  292.  
  293.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  294.                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  295.         }
  296.  
  297.         WREG32(RADEON_SEPROM_CNTL1,
  298.                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  299.                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  300.  
  301.         /* disable VIP */
  302.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  303.  
  304.         /* enable the rom */
  305.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  306.  
  307.         /* Turn off mem requests and CRTC for both controllers */
  308.         WREG32(RADEON_CRTC_GEN_CNTL,
  309.                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
  310.                 (RADEON_CRTC_DISP_REQ_EN_B |
  311.                  RADEON_CRTC_EXT_DISP_EN)));
  312.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  313.                 WREG32(RADEON_CRTC2_GEN_CNTL,
  314.                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
  315.                         RADEON_CRTC2_DISP_REQ_EN_B));
  316.         }
  317.         /* Turn off CRTC */
  318.         WREG32(RADEON_CRTC_EXT_CNTL,
  319.                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
  320.                 (RADEON_CRTC_SYNC_TRISTAT |
  321.                  RADEON_CRTC_DISPLAY_DIS)));
  322.  
  323.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  324.                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
  325.         }
  326.  
  327.         r = radeon_read_bios(rdev);
  328.  
  329.         /* restore regs */
  330.         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  331.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  332.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  333.         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
  334.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  335.                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  336.         }
  337.         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  338.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  339.                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  340.         }
  341.         return r;
  342. }
  343.  
  344. static bool radeon_read_disabled_bios(struct radeon_device *rdev)
  345. {
  346.         if (rdev->family >= CHIP_RV770)
  347.                 return r700_read_disabled_bios(rdev);
  348.         else if (rdev->family >= CHIP_R600)
  349.                 return r600_read_disabled_bios(rdev);
  350.         else if (rdev->family >= CHIP_RS600)
  351.                 return avivo_read_disabled_bios(rdev);
  352.         else
  353.                 return legacy_read_disabled_bios(rdev);
  354. }
  355.  
  356.  
  357. #endif
  358.  
  359. bool radeon_get_bios(struct radeon_device *rdev)
  360. {
  361.         bool r;
  362.         uint16_t tmp;
  363.  
  364.     dbgprintf("%s\n\r",__FUNCTION__);
  365.  
  366.         r = radeon_read_bios(rdev);
  367. //   if (r == false) {
  368. //       r = radeon_read_disabled_bios(rdev);
  369. //   }
  370.         if (r == false || rdev->bios == NULL) {
  371.                 DRM_ERROR("Unable to locate a BIOS ROM\n");
  372.                 rdev->bios = NULL;
  373.                 return false;
  374.         }
  375.         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
  376.                 goto free_bios;
  377.         }
  378.  
  379.         rdev->bios_header_start = RBIOS16(0x48);
  380.         if (!rdev->bios_header_start) {
  381.                 goto free_bios;
  382.         }
  383.         tmp = rdev->bios_header_start + 4;
  384.         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
  385.             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
  386.                 rdev->is_atom_bios = true;
  387.         } else {
  388.                 rdev->is_atom_bios = false;
  389.         }
  390.  
  391.     dbgprintf("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
  392.         return true;
  393. free_bios:
  394.         kfree(rdev->bios);
  395.         rdev->bios = NULL;
  396.         return false;
  397. }
  398.