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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_ASIC_H__
  29. #define __RADEON_ASIC_H__
  30.  
  31. /*
  32.  * common functions
  33.  */
  34. uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
  35. void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  36. uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
  37. void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  38.  
  39. uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
  40. void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  41. uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
  42. void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  43. void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  44.  
  45. void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  46. u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
  47. void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  48. u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
  49.  
  50. /*
  51.  * r100,rv100,rs100,rv200,rs200
  52.  */
  53. struct r100_mc_save {
  54.         u32     GENMO_WT;
  55.         u32     CRTC_EXT_CNTL;
  56.         u32     CRTC_GEN_CNTL;
  57.         u32     CRTC2_GEN_CNTL;
  58.         u32     CUR_OFFSET;
  59.         u32     CUR2_OFFSET;
  60. };
  61. int r100_init(struct radeon_device *rdev);
  62. void r100_fini(struct radeon_device *rdev);
  63. int r100_suspend(struct radeon_device *rdev);
  64. int r100_resume(struct radeon_device *rdev);
  65. void r100_vga_set_state(struct radeon_device *rdev, bool state);
  66. bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  67. int r100_asic_reset(struct radeon_device *rdev);
  68. u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
  69. void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  70. void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
  71.                             uint64_t addr, uint32_t flags);
  72. void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
  73. int r100_irq_set(struct radeon_device *rdev);
  74. int r100_irq_process(struct radeon_device *rdev);
  75. void r100_fence_ring_emit(struct radeon_device *rdev,
  76.                           struct radeon_fence *fence);
  77. bool r100_semaphore_ring_emit(struct radeon_device *rdev,
  78.                               struct radeon_ring *cp,
  79.                               struct radeon_semaphore *semaphore,
  80.                               bool emit_wait);
  81. int r100_cs_parse(struct radeon_cs_parser *p);
  82. void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  83. uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  84. struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
  85.                    uint64_t src_offset,
  86.                    uint64_t dst_offset,
  87.                    unsigned num_gpu_pages,
  88.                                     struct reservation_object *resv);
  89. int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  90.                          uint32_t tiling_flags, uint32_t pitch,
  91.                          uint32_t offset, uint32_t obj_size);
  92. void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
  93. void r100_bandwidth_update(struct radeon_device *rdev);
  94. void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  95. int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  96. void r100_hpd_init(struct radeon_device *rdev);
  97. void r100_hpd_fini(struct radeon_device *rdev);
  98. bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  99. void r100_hpd_set_polarity(struct radeon_device *rdev,
  100.                            enum radeon_hpd_id hpd);
  101. int r100_debugfs_rbbm_init(struct radeon_device *rdev);
  102. int r100_debugfs_cp_init(struct radeon_device *rdev);
  103. void r100_cp_disable(struct radeon_device *rdev);
  104. int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  105. void r100_cp_fini(struct radeon_device *rdev);
  106. int r100_pci_gart_init(struct radeon_device *rdev);
  107. void r100_pci_gart_fini(struct radeon_device *rdev);
  108. int r100_pci_gart_enable(struct radeon_device *rdev);
  109. void r100_pci_gart_disable(struct radeon_device *rdev);
  110. int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  111. int r100_gui_wait_for_idle(struct radeon_device *rdev);
  112. int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  113. void r100_irq_disable(struct radeon_device *rdev);
  114. void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
  115. void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
  116. void r100_vram_init_sizes(struct radeon_device *rdev);
  117. int r100_cp_reset(struct radeon_device *rdev);
  118. void r100_vga_render_disable(struct radeon_device *rdev);
  119. void r100_restore_sanity(struct radeon_device *rdev);
  120. int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  121.                                          struct radeon_cs_packet *pkt,
  122.                                          struct radeon_bo *robj);
  123. int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  124.                           struct radeon_cs_packet *pkt,
  125.                           const unsigned *auth, unsigned n,
  126.                           radeon_packet0_check_t check);
  127. int r100_cs_packet_parse(struct radeon_cs_parser *p,
  128.                          struct radeon_cs_packet *pkt,
  129.                          unsigned idx);
  130. void r100_enable_bm(struct radeon_device *rdev);
  131. void r100_set_common_regs(struct radeon_device *rdev);
  132. void r100_bm_disable(struct radeon_device *rdev);
  133. extern bool r100_gui_idle(struct radeon_device *rdev);
  134. extern void r100_pm_misc(struct radeon_device *rdev);
  135. extern void r100_pm_prepare(struct radeon_device *rdev);
  136. extern void r100_pm_finish(struct radeon_device *rdev);
  137. extern void r100_pm_init_profile(struct radeon_device *rdev);
  138. extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
  139. extern void r100_page_flip(struct radeon_device *rdev, int crtc,
  140.                            u64 crtc_base);
  141. extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc);
  142. extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
  143. extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
  144.  
  145. u32 r100_gfx_get_rptr(struct radeon_device *rdev,
  146.                       struct radeon_ring *ring);
  147. u32 r100_gfx_get_wptr(struct radeon_device *rdev,
  148.                       struct radeon_ring *ring);
  149. void r100_gfx_set_wptr(struct radeon_device *rdev,
  150.                        struct radeon_ring *ring);
  151.  
  152. /*
  153.  * r200,rv250,rs300,rv280
  154.  */
  155. struct radeon_fence *r200_copy_dma(struct radeon_device *rdev,
  156.                         uint64_t src_offset,
  157.                         uint64_t dst_offset,
  158.                          unsigned num_gpu_pages,
  159.                                    struct reservation_object *resv);
  160. void r200_set_safe_registers(struct radeon_device *rdev);
  161.  
  162. /*
  163.  * r300,r350,rv350,rv380
  164.  */
  165. extern int r300_init(struct radeon_device *rdev);
  166. extern void r300_fini(struct radeon_device *rdev);
  167. extern int r300_suspend(struct radeon_device *rdev);
  168. extern int r300_resume(struct radeon_device *rdev);
  169. extern int r300_asic_reset(struct radeon_device *rdev);
  170. extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
  171. extern void r300_fence_ring_emit(struct radeon_device *rdev,
  172.                           struct radeon_fence *fence);
  173. extern int r300_cs_parse(struct radeon_cs_parser *p);
  174. extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
  175. extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
  176.                                      uint64_t addr, uint32_t flags);
  177. extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
  178. extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
  179. extern void r300_set_reg_safe(struct radeon_device *rdev);
  180. extern void r300_mc_program(struct radeon_device *rdev);
  181. extern void r300_mc_init(struct radeon_device *rdev);
  182. extern void r300_clock_startup(struct radeon_device *rdev);
  183. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  184. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
  185. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
  186. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
  187. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
  188. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  189.  
  190. /*
  191.  * r420,r423,rv410
  192.  */
  193. extern int r420_init(struct radeon_device *rdev);
  194. extern void r420_fini(struct radeon_device *rdev);
  195. extern int r420_suspend(struct radeon_device *rdev);
  196. extern int r420_resume(struct radeon_device *rdev);
  197. extern void r420_pm_init_profile(struct radeon_device *rdev);
  198. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
  199. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  200. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  201. extern void r420_pipes_init(struct radeon_device *rdev);
  202.  
  203. /*
  204.  * rs400,rs480
  205.  */
  206. extern int rs400_init(struct radeon_device *rdev);
  207. extern void rs400_fini(struct radeon_device *rdev);
  208. extern int rs400_suspend(struct radeon_device *rdev);
  209. extern int rs400_resume(struct radeon_device *rdev);
  210. void rs400_gart_tlb_flush(struct radeon_device *rdev);
  211. void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
  212.                          uint64_t addr, uint32_t flags);
  213. uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  214. void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  215. int rs400_gart_init(struct radeon_device *rdev);
  216. int rs400_gart_enable(struct radeon_device *rdev);
  217. void rs400_gart_adjust_size(struct radeon_device *rdev);
  218. void rs400_gart_disable(struct radeon_device *rdev);
  219. void rs400_gart_fini(struct radeon_device *rdev);
  220. extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
  221.  
  222. /*
  223.  * rs600.
  224.  */
  225. extern int rs600_asic_reset(struct radeon_device *rdev);
  226. extern int rs600_init(struct radeon_device *rdev);
  227. extern void rs600_fini(struct radeon_device *rdev);
  228. extern int rs600_suspend(struct radeon_device *rdev);
  229. extern int rs600_resume(struct radeon_device *rdev);
  230. int rs600_irq_set(struct radeon_device *rdev);
  231. int rs600_irq_process(struct radeon_device *rdev);
  232. void rs600_irq_disable(struct radeon_device *rdev);
  233. u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
  234. void rs600_gart_tlb_flush(struct radeon_device *rdev);
  235. void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
  236.                          uint64_t addr, uint32_t flags);
  237. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  238. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  239. void rs600_bandwidth_update(struct radeon_device *rdev);
  240. void rs600_hpd_init(struct radeon_device *rdev);
  241. void rs600_hpd_fini(struct radeon_device *rdev);
  242. bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  243. void rs600_hpd_set_polarity(struct radeon_device *rdev,
  244.                             enum radeon_hpd_id hpd);
  245. extern void rs600_pm_misc(struct radeon_device *rdev);
  246. extern void rs600_pm_prepare(struct radeon_device *rdev);
  247. extern void rs600_pm_finish(struct radeon_device *rdev);
  248. extern void rs600_page_flip(struct radeon_device *rdev, int crtc,
  249.                             u64 crtc_base);
  250. extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc);
  251. void rs600_set_safe_registers(struct radeon_device *rdev);
  252. extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
  253. extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  254.  
  255. /*
  256.  * rs690,rs740
  257.  */
  258. int rs690_init(struct radeon_device *rdev);
  259. void rs690_fini(struct radeon_device *rdev);
  260. int rs690_resume(struct radeon_device *rdev);
  261. int rs690_suspend(struct radeon_device *rdev);
  262. uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  263. void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  264. void rs690_bandwidth_update(struct radeon_device *rdev);
  265. void rs690_line_buffer_adjust(struct radeon_device *rdev,
  266.                                         struct drm_display_mode *mode1,
  267.                                         struct drm_display_mode *mode2);
  268. extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
  269.  
  270. /*
  271.  * rv515
  272.  */
  273. struct rv515_mc_save {
  274.         u32 vga_render_control;
  275.         u32 vga_hdp_control;
  276.         bool crtc_enabled[2];
  277. };
  278.  
  279. int rv515_init(struct radeon_device *rdev);
  280. void rv515_fini(struct radeon_device *rdev);
  281. uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  282. void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  283. void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
  284. void rv515_bandwidth_update(struct radeon_device *rdev);
  285. int rv515_resume(struct radeon_device *rdev);
  286. int rv515_suspend(struct radeon_device *rdev);
  287. void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  288. void rv515_vga_render_disable(struct radeon_device *rdev);
  289. void rv515_set_safe_registers(struct radeon_device *rdev);
  290. void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
  291. void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
  292. void rv515_clock_startup(struct radeon_device *rdev);
  293. void rv515_debugfs(struct radeon_device *rdev);
  294. int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  295.  
  296. /*
  297.  * r520,rv530,rv560,rv570,r580
  298.  */
  299. int r520_init(struct radeon_device *rdev);
  300. int r520_resume(struct radeon_device *rdev);
  301. int r520_mc_wait_for_idle(struct radeon_device *rdev);
  302.  
  303. /*
  304.  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
  305.  */
  306. int r600_init(struct radeon_device *rdev);
  307. void r600_fini(struct radeon_device *rdev);
  308. int r600_suspend(struct radeon_device *rdev);
  309. int r600_resume(struct radeon_device *rdev);
  310. void r600_vga_set_state(struct radeon_device *rdev, bool state);
  311. int r600_wb_init(struct radeon_device *rdev);
  312. void r600_wb_fini(struct radeon_device *rdev);
  313. void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  314. uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
  315. void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  316. int r600_cs_parse(struct radeon_cs_parser *p);
  317. int r600_dma_cs_parse(struct radeon_cs_parser *p);
  318. void r600_fence_ring_emit(struct radeon_device *rdev,
  319.                           struct radeon_fence *fence);
  320. bool r600_semaphore_ring_emit(struct radeon_device *rdev,
  321.                               struct radeon_ring *cp,
  322.                               struct radeon_semaphore *semaphore,
  323.                               bool emit_wait);
  324. void r600_dma_fence_ring_emit(struct radeon_device *rdev,
  325.                               struct radeon_fence *fence);
  326. bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
  327.                                   struct radeon_ring *ring,
  328.                                   struct radeon_semaphore *semaphore,
  329.                                   bool emit_wait);
  330. void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  331. bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
  332. bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  333. int r600_asic_reset(struct radeon_device *rdev);
  334. int r600_set_surface_reg(struct radeon_device *rdev, int reg,
  335.                          uint32_t tiling_flags, uint32_t pitch,
  336.                          uint32_t offset, uint32_t obj_size);
  337. void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
  338. int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  339. int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  340. void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  341. int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  342. int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  343. struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
  344.                    uint64_t src_offset, uint64_t dst_offset,
  345.                                      unsigned num_gpu_pages,
  346.                                      struct reservation_object *resv);
  347. struct radeon_fence *r600_copy_dma(struct radeon_device *rdev,
  348.                   uint64_t src_offset, uint64_t dst_offset,
  349.                                    unsigned num_gpu_pages,
  350.                                    struct reservation_object *resv);
  351. void r600_hpd_init(struct radeon_device *rdev);
  352. void r600_hpd_fini(struct radeon_device *rdev);
  353. bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  354. void r600_hpd_set_polarity(struct radeon_device *rdev,
  355.                            enum radeon_hpd_id hpd);
  356. extern void r600_mmio_hdp_flush(struct radeon_device *rdev);
  357. extern bool r600_gui_idle(struct radeon_device *rdev);
  358. extern void r600_pm_misc(struct radeon_device *rdev);
  359. extern void r600_pm_init_profile(struct radeon_device *rdev);
  360. extern void rs780_pm_init_profile(struct radeon_device *rdev);
  361. extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  362. extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  363. extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
  364. extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
  365. extern int r600_get_pcie_lanes(struct radeon_device *rdev);
  366. bool r600_card_posted(struct radeon_device *rdev);
  367. void r600_cp_stop(struct radeon_device *rdev);
  368. int r600_cp_start(struct radeon_device *rdev);
  369. void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
  370. int r600_cp_resume(struct radeon_device *rdev);
  371. void r600_cp_fini(struct radeon_device *rdev);
  372. int r600_count_pipe_bits(uint32_t val);
  373. int r600_mc_wait_for_idle(struct radeon_device *rdev);
  374. int r600_pcie_gart_init(struct radeon_device *rdev);
  375. void r600_scratch_init(struct radeon_device *rdev);
  376. int r600_init_microcode(struct radeon_device *rdev);
  377. u32 r600_gfx_get_rptr(struct radeon_device *rdev,
  378.                       struct radeon_ring *ring);
  379. u32 r600_gfx_get_wptr(struct radeon_device *rdev,
  380.                       struct radeon_ring *ring);
  381. void r600_gfx_set_wptr(struct radeon_device *rdev,
  382.                        struct radeon_ring *ring);
  383. /* r600 irq */
  384. int r600_irq_process(struct radeon_device *rdev);
  385. int r600_irq_init(struct radeon_device *rdev);
  386. void r600_irq_fini(struct radeon_device *rdev);
  387. void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
  388. int r600_irq_set(struct radeon_device *rdev);
  389. void r600_irq_suspend(struct radeon_device *rdev);
  390. void r600_disable_interrupts(struct radeon_device *rdev);
  391. void r600_rlc_stop(struct radeon_device *rdev);
  392. /* r600 audio */
  393. int r600_audio_init(struct radeon_device *rdev);
  394. void r600_audio_fini(struct radeon_device *rdev);
  395. void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
  396. void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
  397.                                     size_t size);
  398. void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);
  399. void r600_hdmi_audio_workaround(struct drm_encoder *encoder);
  400. int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
  401. void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
  402. void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
  403. void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  404. int r600_mc_wait_for_idle(struct radeon_device *rdev);
  405. u32 r600_get_xclk(struct radeon_device *rdev);
  406. uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
  407. int rv6xx_get_temp(struct radeon_device *rdev);
  408. int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  409. int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
  410. void r600_dpm_post_set_power_state(struct radeon_device *rdev);
  411. int r600_dpm_late_enable(struct radeon_device *rdev);
  412. /* r600 dma */
  413. uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
  414.                            struct radeon_ring *ring);
  415. uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
  416.                            struct radeon_ring *ring);
  417. void r600_dma_set_wptr(struct radeon_device *rdev,
  418.                        struct radeon_ring *ring);
  419. /* rv6xx dpm */
  420. int rv6xx_dpm_init(struct radeon_device *rdev);
  421. int rv6xx_dpm_enable(struct radeon_device *rdev);
  422. void rv6xx_dpm_disable(struct radeon_device *rdev);
  423. int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
  424. void rv6xx_setup_asic(struct radeon_device *rdev);
  425. void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
  426. void rv6xx_dpm_fini(struct radeon_device *rdev);
  427. u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
  428. u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
  429. void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
  430.                                  struct radeon_ps *ps);
  431. void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  432.                                                        struct seq_file *m);
  433. int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
  434.                                       enum radeon_dpm_forced_level level);
  435. /* rs780 dpm */
  436. int rs780_dpm_init(struct radeon_device *rdev);
  437. int rs780_dpm_enable(struct radeon_device *rdev);
  438. void rs780_dpm_disable(struct radeon_device *rdev);
  439. int rs780_dpm_set_power_state(struct radeon_device *rdev);
  440. void rs780_dpm_setup_asic(struct radeon_device *rdev);
  441. void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
  442. void rs780_dpm_fini(struct radeon_device *rdev);
  443. u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
  444. u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
  445. void rs780_dpm_print_power_state(struct radeon_device *rdev,
  446.                                  struct radeon_ps *ps);
  447. void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  448.                                                        struct seq_file *m);
  449. int rs780_dpm_force_performance_level(struct radeon_device *rdev,
  450.                                       enum radeon_dpm_forced_level level);
  451.  
  452. /*
  453.  * rv770,rv730,rv710,rv740
  454.  */
  455. int rv770_init(struct radeon_device *rdev);
  456. void rv770_fini(struct radeon_device *rdev);
  457. int rv770_suspend(struct radeon_device *rdev);
  458. int rv770_resume(struct radeon_device *rdev);
  459. void rv770_pm_misc(struct radeon_device *rdev);
  460. void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
  461. bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc);
  462. void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
  463. void r700_cp_stop(struct radeon_device *rdev);
  464. void r700_cp_fini(struct radeon_device *rdev);
  465. struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,
  466.                   uint64_t src_offset, uint64_t dst_offset,
  467.                   unsigned num_gpu_pages,
  468.                                     struct reservation_object *resv);
  469. u32 rv770_get_xclk(struct radeon_device *rdev);
  470. int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  471. int rv770_get_temp(struct radeon_device *rdev);
  472. /* hdmi */
  473. void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  474. /* rv7xx pm */
  475. int rv770_dpm_init(struct radeon_device *rdev);
  476. int rv770_dpm_enable(struct radeon_device *rdev);
  477. int rv770_dpm_late_enable(struct radeon_device *rdev);
  478. void rv770_dpm_disable(struct radeon_device *rdev);
  479. int rv770_dpm_set_power_state(struct radeon_device *rdev);
  480. void rv770_dpm_setup_asic(struct radeon_device *rdev);
  481. void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
  482. void rv770_dpm_fini(struct radeon_device *rdev);
  483. u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
  484. u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
  485. void rv770_dpm_print_power_state(struct radeon_device *rdev,
  486.                                  struct radeon_ps *ps);
  487. void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  488.                                                        struct seq_file *m);
  489. int rv770_dpm_force_performance_level(struct radeon_device *rdev,
  490.                                       enum radeon_dpm_forced_level level);
  491. bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
  492.  
  493. /*
  494.  * evergreen
  495.  */
  496. struct evergreen_mc_save {
  497.         u32 vga_render_control;
  498.         u32 vga_hdp_control;
  499.         bool crtc_enabled[RADEON_MAX_CRTCS];
  500. };
  501.  
  502. void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
  503. int evergreen_init(struct radeon_device *rdev);
  504. void evergreen_fini(struct radeon_device *rdev);
  505. int evergreen_suspend(struct radeon_device *rdev);
  506. int evergreen_resume(struct radeon_device *rdev);
  507. bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  508. bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  509. int evergreen_asic_reset(struct radeon_device *rdev);
  510. void evergreen_bandwidth_update(struct radeon_device *rdev);
  511. void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  512. void evergreen_hpd_init(struct radeon_device *rdev);
  513. void evergreen_hpd_fini(struct radeon_device *rdev);
  514. bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  515. void evergreen_hpd_set_polarity(struct radeon_device *rdev,
  516.                                 enum radeon_hpd_id hpd);
  517. u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
  518. int evergreen_irq_set(struct radeon_device *rdev);
  519. int evergreen_irq_process(struct radeon_device *rdev);
  520. extern int evergreen_cs_parse(struct radeon_cs_parser *p);
  521. extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
  522. extern void evergreen_pm_misc(struct radeon_device *rdev);
  523. extern void evergreen_pm_prepare(struct radeon_device *rdev);
  524. extern void evergreen_pm_finish(struct radeon_device *rdev);
  525. extern void sumo_pm_init_profile(struct radeon_device *rdev);
  526. extern void btc_pm_init_profile(struct radeon_device *rdev);
  527. int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  528. int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  529. extern void evergreen_page_flip(struct radeon_device *rdev, int crtc,
  530.                                 u64 crtc_base);
  531. extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc);
  532. extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
  533. void evergreen_disable_interrupt_state(struct radeon_device *rdev);
  534. int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
  535. void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
  536.                                    struct radeon_fence *fence);
  537. void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
  538.                                    struct radeon_ib *ib);
  539. struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev,
  540.                        uint64_t src_offset, uint64_t dst_offset,
  541.                        unsigned num_gpu_pages,
  542.                                         struct reservation_object *resv);
  543. void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
  544. void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  545. int evergreen_get_temp(struct radeon_device *rdev);
  546. int sumo_get_temp(struct radeon_device *rdev);
  547. int tn_get_temp(struct radeon_device *rdev);
  548. int cypress_dpm_init(struct radeon_device *rdev);
  549. void cypress_dpm_setup_asic(struct radeon_device *rdev);
  550. int cypress_dpm_enable(struct radeon_device *rdev);
  551. void cypress_dpm_disable(struct radeon_device *rdev);
  552. int cypress_dpm_set_power_state(struct radeon_device *rdev);
  553. void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
  554. void cypress_dpm_fini(struct radeon_device *rdev);
  555. bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
  556. int btc_dpm_init(struct radeon_device *rdev);
  557. void btc_dpm_setup_asic(struct radeon_device *rdev);
  558. int btc_dpm_enable(struct radeon_device *rdev);
  559. void btc_dpm_disable(struct radeon_device *rdev);
  560. int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
  561. int btc_dpm_set_power_state(struct radeon_device *rdev);
  562. void btc_dpm_post_set_power_state(struct radeon_device *rdev);
  563. void btc_dpm_fini(struct radeon_device *rdev);
  564. u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
  565. u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
  566. bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
  567. void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  568.                                                      struct seq_file *m);
  569. int sumo_dpm_init(struct radeon_device *rdev);
  570. int sumo_dpm_enable(struct radeon_device *rdev);
  571. int sumo_dpm_late_enable(struct radeon_device *rdev);
  572. void sumo_dpm_disable(struct radeon_device *rdev);
  573. int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
  574. int sumo_dpm_set_power_state(struct radeon_device *rdev);
  575. void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
  576. void sumo_dpm_setup_asic(struct radeon_device *rdev);
  577. void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
  578. void sumo_dpm_fini(struct radeon_device *rdev);
  579. u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
  580. u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
  581. void sumo_dpm_print_power_state(struct radeon_device *rdev,
  582.                                 struct radeon_ps *ps);
  583. void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  584.                                                       struct seq_file *m);
  585. int sumo_dpm_force_performance_level(struct radeon_device *rdev,
  586.                                      enum radeon_dpm_forced_level level);
  587.  
  588. /*
  589.  * cayman
  590.  */
  591. void cayman_fence_ring_emit(struct radeon_device *rdev,
  592.                             struct radeon_fence *fence);
  593. void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
  594. int cayman_init(struct radeon_device *rdev);
  595. void cayman_fini(struct radeon_device *rdev);
  596. int cayman_suspend(struct radeon_device *rdev);
  597. int cayman_resume(struct radeon_device *rdev);
  598. int cayman_asic_reset(struct radeon_device *rdev);
  599. void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  600. int cayman_vm_init(struct radeon_device *rdev);
  601. void cayman_vm_fini(struct radeon_device *rdev);
  602. void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
  603.                      unsigned vm_id, uint64_t pd_addr);
  604. uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
  605. int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
  606. int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
  607. void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
  608.                                 struct radeon_ib *ib);
  609. bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
  610. bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
  611.  
  612. void cayman_dma_vm_copy_pages(struct radeon_device *rdev,
  613.                               struct radeon_ib *ib,
  614.                               uint64_t pe, uint64_t src,
  615.                               unsigned count);
  616. void cayman_dma_vm_write_pages(struct radeon_device *rdev,
  617.                                struct radeon_ib *ib,
  618.                                uint64_t pe,
  619.                                uint64_t addr, unsigned count,
  620.                                uint32_t incr, uint32_t flags);
  621. void cayman_dma_vm_set_pages(struct radeon_device *rdev,
  622.                             struct radeon_ib *ib,
  623.                             uint64_t pe,
  624.                             uint64_t addr, unsigned count,
  625.                             uint32_t incr, uint32_t flags);
  626. void cayman_dma_vm_pad_ib(struct radeon_ib *ib);
  627.  
  628. void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
  629.                          unsigned vm_id, uint64_t pd_addr);
  630.  
  631. u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
  632.                         struct radeon_ring *ring);
  633. u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
  634.                         struct radeon_ring *ring);
  635. void cayman_gfx_set_wptr(struct radeon_device *rdev,
  636.                          struct radeon_ring *ring);
  637. uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
  638.                              struct radeon_ring *ring);
  639. uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
  640.                              struct radeon_ring *ring);
  641. void cayman_dma_set_wptr(struct radeon_device *rdev,
  642.                          struct radeon_ring *ring);
  643.  
  644. int ni_dpm_init(struct radeon_device *rdev);
  645. void ni_dpm_setup_asic(struct radeon_device *rdev);
  646. int ni_dpm_enable(struct radeon_device *rdev);
  647. void ni_dpm_disable(struct radeon_device *rdev);
  648. int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
  649. int ni_dpm_set_power_state(struct radeon_device *rdev);
  650. void ni_dpm_post_set_power_state(struct radeon_device *rdev);
  651. void ni_dpm_fini(struct radeon_device *rdev);
  652. u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
  653. u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
  654. void ni_dpm_print_power_state(struct radeon_device *rdev,
  655.                               struct radeon_ps *ps);
  656. void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  657.                                                     struct seq_file *m);
  658. int ni_dpm_force_performance_level(struct radeon_device *rdev,
  659.                                    enum radeon_dpm_forced_level level);
  660. bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
  661. int trinity_dpm_init(struct radeon_device *rdev);
  662. int trinity_dpm_enable(struct radeon_device *rdev);
  663. int trinity_dpm_late_enable(struct radeon_device *rdev);
  664. void trinity_dpm_disable(struct radeon_device *rdev);
  665. int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
  666. int trinity_dpm_set_power_state(struct radeon_device *rdev);
  667. void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
  668. void trinity_dpm_setup_asic(struct radeon_device *rdev);
  669. void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
  670. void trinity_dpm_fini(struct radeon_device *rdev);
  671. u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
  672. u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
  673. void trinity_dpm_print_power_state(struct radeon_device *rdev,
  674.                                    struct radeon_ps *ps);
  675. void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  676.                                                          struct seq_file *m);
  677. int trinity_dpm_force_performance_level(struct radeon_device *rdev,
  678.                                         enum radeon_dpm_forced_level level);
  679. void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
  680.  
  681. /* DCE6 - SI */
  682. void dce6_bandwidth_update(struct radeon_device *rdev);
  683. int dce6_audio_init(struct radeon_device *rdev);
  684. void dce6_audio_fini(struct radeon_device *rdev);
  685.  
  686. /*
  687.  * si
  688.  */
  689. void si_fence_ring_emit(struct radeon_device *rdev,
  690.                         struct radeon_fence *fence);
  691. void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
  692. int si_init(struct radeon_device *rdev);
  693. void si_fini(struct radeon_device *rdev);
  694. int si_suspend(struct radeon_device *rdev);
  695. int si_resume(struct radeon_device *rdev);
  696. bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  697. bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  698. int si_asic_reset(struct radeon_device *rdev);
  699. void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  700. int si_irq_set(struct radeon_device *rdev);
  701. int si_irq_process(struct radeon_device *rdev);
  702. int si_vm_init(struct radeon_device *rdev);
  703. void si_vm_fini(struct radeon_device *rdev);
  704. void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
  705.                  unsigned vm_id, uint64_t pd_addr);
  706. int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
  707. struct radeon_fence *si_copy_dma(struct radeon_device *rdev,
  708.                 uint64_t src_offset, uint64_t dst_offset,
  709.                 unsigned num_gpu_pages,
  710.                                  struct reservation_object *resv);
  711.  
  712. void si_dma_vm_copy_pages(struct radeon_device *rdev,
  713.                           struct radeon_ib *ib,
  714.                           uint64_t pe, uint64_t src,
  715.                           unsigned count);
  716. void si_dma_vm_write_pages(struct radeon_device *rdev,
  717.                         struct radeon_ib *ib,
  718.                         uint64_t pe,
  719.                         uint64_t addr, unsigned count,
  720.                         uint32_t incr, uint32_t flags);
  721. void si_dma_vm_set_pages(struct radeon_device *rdev,
  722.                          struct radeon_ib *ib,
  723.                          uint64_t pe,
  724.                          uint64_t addr, unsigned count,
  725.                          uint32_t incr, uint32_t flags);
  726.  
  727. void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
  728.                      unsigned vm_id, uint64_t pd_addr);
  729. u32 si_get_xclk(struct radeon_device *rdev);
  730. uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
  731. int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  732. int si_get_temp(struct radeon_device *rdev);
  733. int si_dpm_init(struct radeon_device *rdev);
  734. void si_dpm_setup_asic(struct radeon_device *rdev);
  735. int si_dpm_enable(struct radeon_device *rdev);
  736. int si_dpm_late_enable(struct radeon_device *rdev);
  737. void si_dpm_disable(struct radeon_device *rdev);
  738. int si_dpm_pre_set_power_state(struct radeon_device *rdev);
  739. int si_dpm_set_power_state(struct radeon_device *rdev);
  740. void si_dpm_post_set_power_state(struct radeon_device *rdev);
  741. void si_dpm_fini(struct radeon_device *rdev);
  742. void si_dpm_display_configuration_changed(struct radeon_device *rdev);
  743. void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  744.                                                     struct seq_file *m);
  745. int si_dpm_force_performance_level(struct radeon_device *rdev,
  746.                                    enum radeon_dpm_forced_level level);
  747.  
  748. /* DCE8 - CIK */
  749. void dce8_bandwidth_update(struct radeon_device *rdev);
  750.  
  751. /*
  752.  * cik
  753.  */
  754. uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
  755. u32 cik_get_xclk(struct radeon_device *rdev);
  756. uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
  757. void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  758. int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  759. int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
  760. void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
  761.                               struct radeon_fence *fence);
  762. bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
  763.                                   struct radeon_ring *ring,
  764.                                   struct radeon_semaphore *semaphore,
  765.                                   bool emit_wait);
  766. void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  767. struct radeon_fence *cik_copy_dma(struct radeon_device *rdev,
  768.                  uint64_t src_offset, uint64_t dst_offset,
  769.                  unsigned num_gpu_pages,
  770.                                   struct reservation_object *resv);
  771. struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
  772.                    uint64_t src_offset, uint64_t dst_offset,
  773.                    unsigned num_gpu_pages,
  774.                                     struct reservation_object *resv);
  775. int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
  776. int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  777. bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
  778. void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
  779.                              struct radeon_fence *fence);
  780. void cik_fence_compute_ring_emit(struct radeon_device *rdev,
  781.                                  struct radeon_fence *fence);
  782. bool cik_semaphore_ring_emit(struct radeon_device *rdev,
  783.                              struct radeon_ring *cp,
  784.                              struct radeon_semaphore *semaphore,
  785.                              bool emit_wait);
  786. void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
  787. int cik_init(struct radeon_device *rdev);
  788. void cik_fini(struct radeon_device *rdev);
  789. int cik_suspend(struct radeon_device *rdev);
  790. int cik_resume(struct radeon_device *rdev);
  791. bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  792. int cik_asic_reset(struct radeon_device *rdev);
  793. void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  794. int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
  795. int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  796. int cik_irq_set(struct radeon_device *rdev);
  797. int cik_irq_process(struct radeon_device *rdev);
  798. int cik_vm_init(struct radeon_device *rdev);
  799. void cik_vm_fini(struct radeon_device *rdev);
  800. void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
  801.                   unsigned vm_id, uint64_t pd_addr);
  802.  
  803. void cik_sdma_vm_copy_pages(struct radeon_device *rdev,
  804.                             struct radeon_ib *ib,
  805.                             uint64_t pe, uint64_t src,
  806.                             unsigned count);
  807. void cik_sdma_vm_write_pages(struct radeon_device *rdev,
  808.                      struct radeon_ib *ib,
  809.                      uint64_t pe,
  810.                      uint64_t addr, unsigned count,
  811.                      uint32_t incr, uint32_t flags);
  812. void cik_sdma_vm_set_pages(struct radeon_device *rdev,
  813.                            struct radeon_ib *ib,
  814.                            uint64_t pe,
  815.                            uint64_t addr, unsigned count,
  816.                            uint32_t incr, uint32_t flags);
  817. void cik_sdma_vm_pad_ib(struct radeon_ib *ib);
  818.  
  819. void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
  820.                       unsigned vm_id, uint64_t pd_addr);
  821. int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
  822. u32 cik_gfx_get_rptr(struct radeon_device *rdev,
  823.                               struct radeon_ring *ring);
  824. u32 cik_gfx_get_wptr(struct radeon_device *rdev,
  825.                               struct radeon_ring *ring);
  826. void cik_gfx_set_wptr(struct radeon_device *rdev,
  827.                       struct radeon_ring *ring);
  828. u32 cik_compute_get_rptr(struct radeon_device *rdev,
  829.                          struct radeon_ring *ring);
  830. u32 cik_compute_get_wptr(struct radeon_device *rdev,
  831.                          struct radeon_ring *ring);
  832. void cik_compute_set_wptr(struct radeon_device *rdev,
  833.                           struct radeon_ring *ring);
  834. u32 cik_sdma_get_rptr(struct radeon_device *rdev,
  835.                       struct radeon_ring *ring);
  836. u32 cik_sdma_get_wptr(struct radeon_device *rdev,
  837.                       struct radeon_ring *ring);
  838. void cik_sdma_set_wptr(struct radeon_device *rdev,
  839.                                struct radeon_ring *ring);
  840. int ci_get_temp(struct radeon_device *rdev);
  841. int kv_get_temp(struct radeon_device *rdev);
  842.  
  843. int ci_dpm_init(struct radeon_device *rdev);
  844. int ci_dpm_enable(struct radeon_device *rdev);
  845. int ci_dpm_late_enable(struct radeon_device *rdev);
  846. void ci_dpm_disable(struct radeon_device *rdev);
  847. int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
  848. int ci_dpm_set_power_state(struct radeon_device *rdev);
  849. void ci_dpm_post_set_power_state(struct radeon_device *rdev);
  850. void ci_dpm_setup_asic(struct radeon_device *rdev);
  851. void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
  852. void ci_dpm_fini(struct radeon_device *rdev);
  853. u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
  854. u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
  855. void ci_dpm_print_power_state(struct radeon_device *rdev,
  856.                               struct radeon_ps *ps);
  857. void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  858.                                                     struct seq_file *m);
  859. int ci_dpm_force_performance_level(struct radeon_device *rdev,
  860.                                    enum radeon_dpm_forced_level level);
  861. bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
  862. void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
  863.  
  864. int kv_dpm_init(struct radeon_device *rdev);
  865. int kv_dpm_enable(struct radeon_device *rdev);
  866. int kv_dpm_late_enable(struct radeon_device *rdev);
  867. void kv_dpm_disable(struct radeon_device *rdev);
  868. int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
  869. int kv_dpm_set_power_state(struct radeon_device *rdev);
  870. void kv_dpm_post_set_power_state(struct radeon_device *rdev);
  871. void kv_dpm_setup_asic(struct radeon_device *rdev);
  872. void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
  873. void kv_dpm_fini(struct radeon_device *rdev);
  874. u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
  875. u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
  876. void kv_dpm_print_power_state(struct radeon_device *rdev,
  877.                               struct radeon_ps *ps);
  878. void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  879.                                                     struct seq_file *m);
  880. int kv_dpm_force_performance_level(struct radeon_device *rdev,
  881.                                    enum radeon_dpm_forced_level level);
  882. void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
  883. void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
  884.  
  885. /* uvd v1.0 */
  886. uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
  887.                            struct radeon_ring *ring);
  888. uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
  889.                            struct radeon_ring *ring);
  890. void uvd_v1_0_set_wptr(struct radeon_device *rdev,
  891.                        struct radeon_ring *ring);
  892. int uvd_v1_0_resume(struct radeon_device *rdev);
  893.  
  894. int uvd_v1_0_init(struct radeon_device *rdev);
  895. void uvd_v1_0_fini(struct radeon_device *rdev);
  896. int uvd_v1_0_start(struct radeon_device *rdev);
  897. void uvd_v1_0_stop(struct radeon_device *rdev);
  898.  
  899. int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
  900. void uvd_v1_0_fence_emit(struct radeon_device *rdev,
  901.                          struct radeon_fence *fence);
  902. int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  903. bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
  904.                              struct radeon_ring *ring,
  905.                              struct radeon_semaphore *semaphore,
  906.                              bool emit_wait);
  907. void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  908.  
  909. /* uvd v2.2 */
  910. int uvd_v2_2_resume(struct radeon_device *rdev);
  911. void uvd_v2_2_fence_emit(struct radeon_device *rdev,
  912.                          struct radeon_fence *fence);
  913.  
  914. /* uvd v3.1 */
  915. bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
  916.                              struct radeon_ring *ring,
  917.                              struct radeon_semaphore *semaphore,
  918.                              bool emit_wait);
  919.  
  920. /* uvd v4.2 */
  921. int uvd_v4_2_resume(struct radeon_device *rdev);
  922.  
  923. /* vce v1.0 */
  924. uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
  925.                            struct radeon_ring *ring);
  926. uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
  927.                            struct radeon_ring *ring);
  928. void vce_v1_0_set_wptr(struct radeon_device *rdev,
  929.                        struct radeon_ring *ring);
  930. int vce_v1_0_init(struct radeon_device *rdev);
  931. int vce_v1_0_start(struct radeon_device *rdev);
  932.  
  933. /* vce v2.0 */
  934. int vce_v2_0_resume(struct radeon_device *rdev);
  935.  
  936. #endif
  937.