Subversion Repositories Kolibri OS

Rev

Rev 1125 | Rev 1221 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_ASIC_H__
  29. #define __RADEON_ASIC_H__
  30.  
  31. /*
  32.  * common functions
  33.  */
  34. void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  35. void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  36.  
  37. void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  38. void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  39. void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  40.  
  41. /*
  42.  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  43.  */
  44. int r100_init(struct radeon_device *rdev);
  45. uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
  46. void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  47. void r100_errata(struct radeon_device *rdev);
  48. void r100_vram_info(struct radeon_device *rdev);
  49. int r100_gpu_reset(struct radeon_device *rdev);
  50. int r100_mc_init(struct radeon_device *rdev);
  51. void r100_mc_fini(struct radeon_device *rdev);
  52. int r100_wb_init(struct radeon_device *rdev);
  53. void r100_wb_fini(struct radeon_device *rdev);
  54. int r100_gart_enable(struct radeon_device *rdev);
  55. void r100_pci_gart_disable(struct radeon_device *rdev);
  56. void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  57. int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  58. int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  59. void r100_cp_fini(struct radeon_device *rdev);
  60. void r100_cp_disable(struct radeon_device *rdev);
  61. void r100_ring_start(struct radeon_device *rdev);
  62. int r100_irq_set(struct radeon_device *rdev);
  63. int r100_irq_process(struct radeon_device *rdev);
  64. void r100_fence_ring_emit(struct radeon_device *rdev,
  65.                           struct radeon_fence *fence);
  66. int r100_cs_parse(struct radeon_cs_parser *p);
  67. void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  68. uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  69. int r100_copy_blit(struct radeon_device *rdev,
  70.                    uint64_t src_offset,
  71.                    uint64_t dst_offset,
  72.                    unsigned num_pages,
  73.                    struct radeon_fence *fence);
  74.  
  75.  
  76. static struct radeon_asic r100_asic = {
  77.         .init = &r100_init,
  78.         .errata = &r100_errata,
  79.         .vram_info = &r100_vram_info,
  80.         .gpu_reset = &r100_gpu_reset,
  81.         .mc_init = &r100_mc_init,
  82.         .mc_fini = &r100_mc_fini,
  83. //   .wb_init = &r100_wb_init,
  84. //   .wb_fini = &r100_wb_fini,
  85.         .gart_enable = &r100_gart_enable,
  86.         .gart_disable = &r100_pci_gart_disable,
  87.         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
  88.         .gart_set_page = &r100_pci_gart_set_page,
  89.         .cp_init = &r100_cp_init,
  90. //   .cp_fini = &r100_cp_fini,
  91. //   .cp_disable = &r100_cp_disable,
  92.         .ring_start = &r100_ring_start,
  93. //   .irq_set = &r100_irq_set,
  94. //   .irq_process = &r100_irq_process,
  95.  //  .fence_ring_emit = &r100_fence_ring_emit,
  96.  //  .cs_parse = &r100_cs_parse,
  97.  //  .copy_blit = &r100_copy_blit,
  98.  //  .copy_dma = NULL,
  99.  //  .copy = &r100_copy_blit,
  100. //   .set_engine_clock = &radeon_legacy_set_engine_clock,
  101. //   .set_memory_clock = NULL,
  102. //   .set_pcie_lanes = NULL,
  103. //   .set_clock_gating = &radeon_legacy_set_clock_gating,
  104. };
  105.  
  106.  
  107. /*
  108.  * r300,r350,rv350,rv380
  109.  */
  110. int r300_init(struct radeon_device *rdev);
  111. void r300_errata(struct radeon_device *rdev);
  112. void r300_vram_info(struct radeon_device *rdev);
  113. int r300_gpu_reset(struct radeon_device *rdev);
  114. int r300_mc_init(struct radeon_device *rdev);
  115. void r300_mc_fini(struct radeon_device *rdev);
  116. void r300_ring_start(struct radeon_device *rdev);
  117. void r300_fence_ring_emit(struct radeon_device *rdev,
  118.                           struct radeon_fence *fence);
  119. int r300_cs_parse(struct radeon_cs_parser *p);
  120. int r300_gart_enable(struct radeon_device *rdev);
  121. void rv370_pcie_gart_disable(struct radeon_device *rdev);
  122. void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
  123. int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  124. uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
  125. void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  126. void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
  127. int r300_copy_dma(struct radeon_device *rdev,
  128.                   uint64_t src_offset,
  129.                   uint64_t dst_offset,
  130.                   unsigned num_pages,
  131.                   struct radeon_fence *fence);
  132.  
  133.  
  134. static struct radeon_asic r300_asic = {
  135.         .init = &r300_init,
  136.         .errata = &r300_errata,
  137.         .vram_info = &r300_vram_info,
  138.         .gpu_reset = &r300_gpu_reset,
  139.         .mc_init = &r300_mc_init,
  140.         .mc_fini = &r300_mc_fini,
  141. //   .wb_init = &r100_wb_init,
  142. //   .wb_fini = &r100_wb_fini,
  143.         .gart_enable = &r300_gart_enable,
  144.         .gart_disable = &r100_pci_gart_disable,
  145.         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
  146.         .gart_set_page = &r100_pci_gart_set_page,
  147.         .cp_init = &r100_cp_init,
  148. //   .cp_fini = &r100_cp_fini,
  149. //   .cp_disable = &r100_cp_disable,
  150.         .ring_start = &r300_ring_start,
  151. //   .irq_set = &r100_irq_set,
  152. //   .irq_process = &r100_irq_process,
  153.  //  .fence_ring_emit = &r300_fence_ring_emit,
  154.  //  .cs_parse = &r300_cs_parse,
  155.  //  .copy_blit = &r100_copy_blit,
  156.  //  .copy_dma = &r300_copy_dma,
  157.  //  .copy = &r100_copy_blit,
  158.  //  .set_engine_clock = &radeon_legacy_set_engine_clock,
  159.  //  .set_memory_clock = NULL,
  160. //   .set_pcie_lanes = &rv370_set_pcie_lanes,
  161. //   .set_clock_gating = &radeon_legacy_set_clock_gating,
  162. };
  163.  
  164.  
  165. /*
  166.  * r420,r423,rv410
  167.  */
  168. void r420_errata(struct radeon_device *rdev);
  169. void r420_vram_info(struct radeon_device *rdev);
  170. int r420_mc_init(struct radeon_device *rdev);
  171. void r420_mc_fini(struct radeon_device *rdev);
  172. static struct radeon_asic r420_asic = {
  173.         .init = &r300_init,
  174.         .errata = &r420_errata,
  175.         .vram_info = &r420_vram_info,
  176.         .gpu_reset = &r300_gpu_reset,
  177.         .mc_init = &r420_mc_init,
  178.         .mc_fini = &r420_mc_fini,
  179. //   .wb_init = &r100_wb_init,
  180. //   .wb_fini = &r100_wb_fini,
  181.         .gart_enable = &r300_gart_enable,
  182.         .gart_disable = &rv370_pcie_gart_disable,
  183.         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
  184.         .gart_set_page = &rv370_pcie_gart_set_page,
  185.         .cp_init = &r100_cp_init,
  186. //   .cp_fini = &r100_cp_fini,
  187. //   .cp_disable = &r100_cp_disable,
  188.         .ring_start = &r300_ring_start,
  189. //   .irq_set = &r100_irq_set,
  190. //   .irq_process = &r100_irq_process,
  191. //   .fence_ring_emit = &r300_fence_ring_emit,
  192. //   .cs_parse = &r300_cs_parse,
  193. //   .copy_blit = &r100_copy_blit,
  194. //   .copy_dma = &r300_copy_dma,
  195. //   .copy = &r100_copy_blit,
  196. //   .set_engine_clock = &radeon_atom_set_engine_clock,
  197. //   .set_memory_clock = &radeon_atom_set_memory_clock,
  198. //   .set_pcie_lanes = &rv370_set_pcie_lanes,
  199. //   .set_clock_gating = &radeon_atom_set_clock_gating,
  200. };
  201.  
  202.  
  203. /*
  204.  * rs400,rs480
  205.  */
  206. void rs400_errata(struct radeon_device *rdev);
  207. void rs400_vram_info(struct radeon_device *rdev);
  208. int rs400_mc_init(struct radeon_device *rdev);
  209. void rs400_mc_fini(struct radeon_device *rdev);
  210. int rs400_gart_enable(struct radeon_device *rdev);
  211. void rs400_gart_disable(struct radeon_device *rdev);
  212. void rs400_gart_tlb_flush(struct radeon_device *rdev);
  213. int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  214. uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  215. void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  216. static struct radeon_asic rs400_asic = {
  217.         .init = &r300_init,
  218.         .errata = &rs400_errata,
  219.         .vram_info = &rs400_vram_info,
  220.         .gpu_reset = &r300_gpu_reset,
  221.         .mc_init = &rs400_mc_init,
  222.         .mc_fini = &rs400_mc_fini,
  223. //   .wb_init = &r100_wb_init,
  224. //   .wb_fini = &r100_wb_fini,
  225.         .gart_enable = &rs400_gart_enable,
  226.         .gart_disable = &rs400_gart_disable,
  227.         .gart_tlb_flush = &rs400_gart_tlb_flush,
  228.         .gart_set_page = &rs400_gart_set_page,
  229.         .cp_init = &r100_cp_init,
  230. //   .cp_fini = &r100_cp_fini,
  231. //   .cp_disable = &r100_cp_disable,
  232.         .ring_start = &r300_ring_start,
  233. //   .irq_set = &r100_irq_set,
  234. //   .irq_process = &r100_irq_process,
  235. //   .fence_ring_emit = &r300_fence_ring_emit,
  236. //   .cs_parse = &r300_cs_parse,
  237. //   .copy_blit = &r100_copy_blit,
  238. //   .copy_dma = &r300_copy_dma,
  239. //   .copy = &r100_copy_blit,
  240. //   .set_engine_clock = &radeon_legacy_set_engine_clock,
  241. //   .set_memory_clock = NULL,
  242. //   .set_pcie_lanes = NULL,
  243. //   .set_clock_gating = &radeon_legacy_set_clock_gating,
  244. };
  245.  
  246.  
  247. /*
  248.  * rs600.
  249.  */
  250. void rs600_errata(struct radeon_device *rdev);
  251. void rs600_vram_info(struct radeon_device *rdev);
  252. int rs600_mc_init(struct radeon_device *rdev);
  253. void rs600_mc_fini(struct radeon_device *rdev);
  254. int rs600_irq_set(struct radeon_device *rdev);
  255. int rs600_gart_enable(struct radeon_device *rdev);
  256. void rs600_gart_disable(struct radeon_device *rdev);
  257. void rs600_gart_tlb_flush(struct radeon_device *rdev);
  258. int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  259. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  260. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  261.  
  262. static struct radeon_asic rs600_asic = {
  263.         .init = &r300_init,
  264.         .errata = &rs600_errata,
  265.         .vram_info = &rs600_vram_info,
  266.         .gpu_reset = &r300_gpu_reset,
  267.         .mc_init = &rs600_mc_init,
  268.         .mc_fini = &rs600_mc_fini,
  269. //   .wb_init = &r100_wb_init,
  270. //   .wb_fini = &r100_wb_fini,
  271.         .gart_enable = &rs600_gart_enable,
  272.         .gart_disable = &rs600_gart_disable,
  273.         .gart_tlb_flush = &rs600_gart_tlb_flush,
  274.         .gart_set_page = &rs600_gart_set_page,
  275.         .cp_init = &r100_cp_init,
  276. //   .cp_fini = &r100_cp_fini,
  277. //   .cp_disable = &r100_cp_disable,
  278.         .ring_start = &r300_ring_start,
  279. //   .irq_set = &rs600_irq_set,
  280. //   .irq_process = &r100_irq_process,
  281. //   .fence_ring_emit = &r300_fence_ring_emit,
  282. //   .cs_parse = &r300_cs_parse,
  283. //   .copy_blit = &r100_copy_blit,
  284. //   .copy_dma = &r300_copy_dma,
  285. //   .copy = &r100_copy_blit,
  286. //   .set_engine_clock = &radeon_atom_set_engine_clock,
  287. //   .set_memory_clock = &radeon_atom_set_memory_clock,
  288. //   .set_pcie_lanes = NULL,
  289. //   .set_clock_gating = &radeon_atom_set_clock_gating,
  290. };
  291.  
  292.  
  293. /*
  294.  * rs690,rs740
  295.  */
  296. void rs690_errata(struct radeon_device *rdev);
  297. void rs690_vram_info(struct radeon_device *rdev);
  298. int rs690_mc_init(struct radeon_device *rdev);
  299. void rs690_mc_fini(struct radeon_device *rdev);
  300. uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  301. void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  302. static struct radeon_asic rs690_asic = {
  303.         .init = &r300_init,
  304.         .errata = &rs690_errata,
  305.         .vram_info = &rs690_vram_info,
  306.         .gpu_reset = &r300_gpu_reset,
  307.         .mc_init = &rs690_mc_init,
  308.         .mc_fini = &rs690_mc_fini,
  309. //   .wb_init = &r100_wb_init,
  310. //   .wb_fini = &r100_wb_fini,
  311.         .gart_enable = &rs400_gart_enable,
  312.         .gart_disable = &rs400_gart_disable,
  313.         .gart_tlb_flush = &rs400_gart_tlb_flush,
  314.         .gart_set_page = &rs400_gart_set_page,
  315.         .cp_init = &r100_cp_init,
  316. //   .cp_fini = &r100_cp_fini,
  317. //   .cp_disable = &r100_cp_disable,
  318.         .ring_start = &r300_ring_start,
  319. //   .irq_set = &rs600_irq_set,
  320. //   .irq_process = &r100_irq_process,
  321.  //  .fence_ring_emit = &r300_fence_ring_emit,
  322.  //  .cs_parse = &r300_cs_parse,
  323.  //  .copy_blit = &r100_copy_blit,
  324.  //  .copy_dma = &r300_copy_dma,
  325. //   .copy = &r300_copy_dma,
  326. //   .set_engine_clock = &radeon_atom_set_engine_clock,
  327. //   .set_memory_clock = &radeon_atom_set_memory_clock,
  328. //   .set_pcie_lanes = NULL,
  329. //   .set_clock_gating = &radeon_atom_set_clock_gating,
  330. };
  331.  
  332. /*
  333.  * rv515
  334.  */
  335. int rv515_init(struct radeon_device *rdev);
  336. void rv515_errata(struct radeon_device *rdev);
  337. void rv515_vram_info(struct radeon_device *rdev);
  338. int rv515_gpu_reset(struct radeon_device *rdev);
  339. int rv515_mc_init(struct radeon_device *rdev);
  340. void rv515_mc_fini(struct radeon_device *rdev);
  341. uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
  342. void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  343. void rv515_ring_start(struct radeon_device *rdev);
  344. uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
  345. void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  346.  
  347.  
  348. static struct radeon_asic rv515_asic = {
  349.         .init = &rv515_init,
  350.         .errata = &rv515_errata,
  351.         .vram_info = &rv515_vram_info,
  352.         .gpu_reset = &rv515_gpu_reset,
  353.         .mc_init = &rv515_mc_init,
  354.         .mc_fini = &rv515_mc_fini,
  355. //   .wb_init = &r100_wb_init,
  356. //   .wb_fini = &r100_wb_fini,
  357.         .gart_enable = &r300_gart_enable,
  358.         .gart_disable = &rv370_pcie_gart_disable,
  359.         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
  360.         .gart_set_page = &rv370_pcie_gart_set_page,
  361.         .cp_init = &r100_cp_init,
  362. //   .cp_fini = &r100_cp_fini,
  363. //   .cp_disable = &r100_cp_disable,
  364.     .ring_start = &rv515_ring_start,
  365. //   .irq_set = &r100_irq_set,
  366. //   .irq_process = &r100_irq_process,
  367. //   .fence_ring_emit = &r300_fence_ring_emit,
  368. //   .cs_parse = &r300_cs_parse,
  369. //   .copy_blit = &r100_copy_blit,
  370. //   .copy_dma = &r300_copy_dma,
  371. //   .copy = &r100_copy_blit,
  372. //   .set_engine_clock = &radeon_atom_set_engine_clock,
  373. //   .set_memory_clock = &radeon_atom_set_memory_clock,
  374. //   .set_pcie_lanes = &rv370_set_pcie_lanes,
  375. //   .set_clock_gating = &radeon_atom_set_clock_gating,
  376. };
  377.  
  378.  
  379. /*
  380.  * r520,rv530,rv560,rv570,r580
  381.  */
  382. void r520_errata(struct radeon_device *rdev);
  383. void r520_vram_info(struct radeon_device *rdev);
  384. int r520_mc_init(struct radeon_device *rdev);
  385. void r520_mc_fini(struct radeon_device *rdev);
  386.  
  387. static struct radeon_asic r520_asic = {
  388.         .init = &rv515_init,
  389.     .errata = &r520_errata,
  390.     .vram_info = &r520_vram_info,
  391.     .gpu_reset = &rv515_gpu_reset,
  392.     .mc_init = &r520_mc_init,
  393.     .mc_fini = &r520_mc_fini,
  394. //    .wb_init = &r100_wb_init,
  395. //    .wb_fini = &r100_wb_fini,
  396.     .gart_enable = &r300_gart_enable,
  397.     .gart_disable = &rv370_pcie_gart_disable,
  398.     .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
  399.     .gart_set_page = &rv370_pcie_gart_set_page,
  400.     .cp_init = &r100_cp_init,
  401. //    .cp_fini = &r100_cp_fini,
  402. //   .cp_disable = &r100_cp_disable,
  403.     .ring_start = &rv515_ring_start,
  404. //   .irq_set = &r100_irq_set,
  405. //   .irq_process = &r100_irq_process,
  406. //   .fence_ring_emit = &r300_fence_ring_emit,
  407. //   .cs_parse = &r300_cs_parse,
  408. //   .copy_blit = &r100_copy_blit,
  409. //   .copy_dma = &r300_copy_dma,
  410. //   .copy = &r100_copy_blit,
  411. //   .set_engine_clock = &radeon_atom_set_engine_clock,
  412. //   .set_memory_clock = &radeon_atom_set_memory_clock,
  413. //   .set_pcie_lanes = &rv370_set_pcie_lanes,
  414. //   .set_clock_gating = &radeon_atom_set_clock_gating,
  415. };
  416.  
  417. /*
  418.  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710
  419.  */
  420. uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
  421. void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  422.  
  423. #endif
  424.