Subversion Repositories Kolibri OS

Rev

Rev 2004 | Rev 2007 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28.  
  29. //#include <linux/console.h>
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/radeon_drm.h>
  33. //#include <linux/vgaarb.h>
  34. //#include <linux/vga_switcheroo.h>
  35. #include "radeon_reg.h"
  36. #include "radeon.h"
  37. #include "radeon_asic.h"
  38. #include "atom.h"
  39.  
  40. /*
  41.  * Registers accessors functions.
  42.  */
  43. static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  44. {
  45.         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  46.         BUG_ON(1);
  47.         return 0;
  48. }
  49.  
  50. static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  51. {
  52.         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  53.                   reg, v);
  54.         BUG_ON(1);
  55. }
  56.  
  57. static void radeon_register_accessor_init(struct radeon_device *rdev)
  58. {
  59.         rdev->mc_rreg = &radeon_invalid_rreg;
  60.         rdev->mc_wreg = &radeon_invalid_wreg;
  61.         rdev->pll_rreg = &radeon_invalid_rreg;
  62.         rdev->pll_wreg = &radeon_invalid_wreg;
  63.         rdev->pciep_rreg = &radeon_invalid_rreg;
  64.         rdev->pciep_wreg = &radeon_invalid_wreg;
  65.  
  66.         /* Don't change order as we are overridding accessor. */
  67.         if (rdev->family < CHIP_RV515) {
  68.                 rdev->pcie_reg_mask = 0xff;
  69.         } else {
  70.                 rdev->pcie_reg_mask = 0x7ff;
  71.         }
  72.         /* FIXME: not sure here */
  73.         if (rdev->family <= CHIP_R580) {
  74.                 rdev->pll_rreg = &r100_pll_rreg;
  75.                 rdev->pll_wreg = &r100_pll_wreg;
  76.         }
  77.         if (rdev->family >= CHIP_R420) {
  78.                 rdev->mc_rreg = &r420_mc_rreg;
  79.                 rdev->mc_wreg = &r420_mc_wreg;
  80.         }
  81.         if (rdev->family >= CHIP_RV515) {
  82.                 rdev->mc_rreg = &rv515_mc_rreg;
  83.                 rdev->mc_wreg = &rv515_mc_wreg;
  84.         }
  85.         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  86.                 rdev->mc_rreg = &rs400_mc_rreg;
  87.                 rdev->mc_wreg = &rs400_mc_wreg;
  88.         }
  89.         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  90.                 rdev->mc_rreg = &rs690_mc_rreg;
  91.                 rdev->mc_wreg = &rs690_mc_wreg;
  92.         }
  93.         if (rdev->family == CHIP_RS600) {
  94.                 rdev->mc_rreg = &rs600_mc_rreg;
  95.                 rdev->mc_wreg = &rs600_mc_wreg;
  96.         }
  97.         if (rdev->family >= CHIP_R600) {
  98.                 rdev->pciep_rreg = &r600_pciep_rreg;
  99.                 rdev->pciep_wreg = &r600_pciep_wreg;
  100.         }
  101. }
  102.  
  103.  
  104. /* helper to disable agp */
  105. void radeon_agp_disable(struct radeon_device *rdev)
  106. {
  107.         rdev->flags &= ~RADEON_IS_AGP;
  108.         if (rdev->family >= CHIP_R600) {
  109.                 DRM_INFO("Forcing AGP to PCIE mode\n");
  110.                 rdev->flags |= RADEON_IS_PCIE;
  111.         } else if (rdev->family >= CHIP_RV515 ||
  112.                         rdev->family == CHIP_RV380 ||
  113.                         rdev->family == CHIP_RV410 ||
  114.                         rdev->family == CHIP_R423) {
  115.                 DRM_INFO("Forcing AGP to PCIE mode\n");
  116.                 rdev->flags |= RADEON_IS_PCIE;
  117.                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
  118.                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
  119.         } else {
  120.                 DRM_INFO("Forcing AGP to PCI mode\n");
  121.                 rdev->flags |= RADEON_IS_PCI;
  122.                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
  123.                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
  124.         }
  125.         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  126. }
  127.  
  128. /*
  129.  * ASIC
  130.  */
  131. static struct radeon_asic r100_asic = {
  132.         .init = &r100_init,
  133. //      .fini = &r100_fini,
  134. //      .suspend = &r100_suspend,
  135. //      .resume = &r100_resume,
  136. //      .vga_set_state = &r100_vga_set_state,
  137.         .gpu_is_lockup = &r100_gpu_is_lockup,
  138.         .asic_reset = &r100_asic_reset,
  139.         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
  140.         .gart_set_page = &r100_pci_gart_set_page,
  141.         .cp_commit = &r100_cp_commit,
  142.         .ring_start = &r100_ring_start,
  143.         .ring_test = &r100_ring_test,
  144.         .ring_ib_execute = &r100_ring_ib_execute,
  145.         .irq_set = &r100_irq_set,
  146.         .irq_process = &r100_irq_process,
  147. //      .get_vblank_counter = &r100_get_vblank_counter,
  148.         .fence_ring_emit = &r100_fence_ring_emit,
  149. //      .cs_parse = &r100_cs_parse,
  150.         .copy_blit = &r100_copy_blit,
  151.         .copy_dma = NULL,
  152.         .copy = &r100_copy_blit,
  153.         .get_engine_clock = &radeon_legacy_get_engine_clock,
  154.         .set_engine_clock = &radeon_legacy_set_engine_clock,
  155.         .get_memory_clock = &radeon_legacy_get_memory_clock,
  156.         .set_memory_clock = NULL,
  157.         .get_pcie_lanes = NULL,
  158.         .set_pcie_lanes = NULL,
  159.         .set_clock_gating = &radeon_legacy_set_clock_gating,
  160.         .set_surface_reg = r100_set_surface_reg,
  161.         .clear_surface_reg = r100_clear_surface_reg,
  162.         .bandwidth_update = &r100_bandwidth_update,
  163.         .hpd_init = &r100_hpd_init,
  164.         .hpd_fini = &r100_hpd_fini,
  165.         .hpd_sense = &r100_hpd_sense,
  166.         .hpd_set_polarity = &r100_hpd_set_polarity,
  167.         .ioctl_wait_idle = NULL,
  168. };
  169.  
  170. static struct radeon_asic r200_asic = {
  171.         .init = &r100_init,
  172. //      .fini = &r100_fini,
  173. //      .suspend = &r100_suspend,
  174. //      .resume = &r100_resume,
  175. //      .vga_set_state = &r100_vga_set_state,
  176.         .gpu_is_lockup = &r100_gpu_is_lockup,
  177.         .asic_reset = &r100_asic_reset,
  178.         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
  179.         .gart_set_page = &r100_pci_gart_set_page,
  180.         .cp_commit = &r100_cp_commit,
  181.         .ring_start = &r100_ring_start,
  182.         .ring_test = &r100_ring_test,
  183.         .ring_ib_execute = &r100_ring_ib_execute,
  184.         .irq_set = &r100_irq_set,
  185.         .irq_process = &r100_irq_process,
  186. //      .get_vblank_counter = &r100_get_vblank_counter,
  187.         .fence_ring_emit = &r100_fence_ring_emit,
  188. //      .cs_parse = &r100_cs_parse,
  189.         .copy_blit = &r100_copy_blit,
  190.         .copy_dma = &r200_copy_dma,
  191.         .copy = &r100_copy_blit,
  192.         .get_engine_clock = &radeon_legacy_get_engine_clock,
  193.         .set_engine_clock = &radeon_legacy_set_engine_clock,
  194.         .get_memory_clock = &radeon_legacy_get_memory_clock,
  195.         .set_memory_clock = NULL,
  196.         .set_pcie_lanes = NULL,
  197.         .set_clock_gating = &radeon_legacy_set_clock_gating,
  198.         .set_surface_reg = r100_set_surface_reg,
  199.         .clear_surface_reg = r100_clear_surface_reg,
  200.         .bandwidth_update = &r100_bandwidth_update,
  201.         .hpd_init = &r100_hpd_init,
  202.         .hpd_fini = &r100_hpd_fini,
  203.         .hpd_sense = &r100_hpd_sense,
  204.         .hpd_set_polarity = &r100_hpd_set_polarity,
  205.         .ioctl_wait_idle = NULL,
  206. };
  207.  
  208. static struct radeon_asic r300_asic = {
  209.         .init = &r300_init,
  210. //      .fini = &r300_fini,
  211. //      .suspend = &r300_suspend,
  212. //      .resume = &r300_resume,
  213. //      .vga_set_state = &r100_vga_set_state,
  214.         .asic_reset = &r300_asic_reset,
  215.         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
  216.         .gart_set_page = &r100_pci_gart_set_page,
  217.         .cp_commit = &r100_cp_commit,
  218.         .ring_start = &r300_ring_start,
  219.         .ring_test = &r100_ring_test,
  220.         .ring_ib_execute = &r100_ring_ib_execute,
  221.         .irq_set = &r100_irq_set,
  222.         .irq_process = &r100_irq_process,
  223. //      .get_vblank_counter = &r100_get_vblank_counter,
  224.         .fence_ring_emit = &r300_fence_ring_emit,
  225. //      .cs_parse = &r300_cs_parse,
  226.         .copy_blit = &r100_copy_blit,
  227.         .copy_dma = &r200_copy_dma,
  228.         .copy = &r100_copy_blit,
  229.         .get_engine_clock = &radeon_legacy_get_engine_clock,
  230.         .set_engine_clock = &radeon_legacy_set_engine_clock,
  231.         .get_memory_clock = &radeon_legacy_get_memory_clock,
  232.         .set_memory_clock = NULL,
  233.         .get_pcie_lanes = &rv370_get_pcie_lanes,
  234.         .set_pcie_lanes = &rv370_set_pcie_lanes,
  235.         .set_clock_gating = &radeon_legacy_set_clock_gating,
  236.         .set_surface_reg = r100_set_surface_reg,
  237.         .clear_surface_reg = r100_clear_surface_reg,
  238.         .bandwidth_update = &r100_bandwidth_update,
  239.         .hpd_init = &r100_hpd_init,
  240.         .hpd_fini = &r100_hpd_fini,
  241.         .hpd_sense = &r100_hpd_sense,
  242.         .hpd_set_polarity = &r100_hpd_set_polarity,
  243.         .ioctl_wait_idle = NULL,
  244. };
  245.  
  246. static struct radeon_asic r300_asic_pcie = {
  247.         .init = &r300_init,
  248. //      .fini = &r300_fini,
  249. //      .suspend = &r300_suspend,
  250. //      .resume = &r300_resume,
  251. //      .vga_set_state = &r100_vga_set_state,
  252.         .asic_reset = &r300_asic_reset,
  253.         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
  254.         .gart_set_page = &rv370_pcie_gart_set_page,
  255.         .cp_commit = &r100_cp_commit,
  256.         .ring_start = &r300_ring_start,
  257.         .ring_test = &r100_ring_test,
  258.         .ring_ib_execute = &r100_ring_ib_execute,
  259.         .irq_set = &r100_irq_set,
  260.         .irq_process = &r100_irq_process,
  261. //      .get_vblank_counter = &r100_get_vblank_counter,
  262.         .fence_ring_emit = &r300_fence_ring_emit,
  263. //      .cs_parse = &r300_cs_parse,
  264.         .copy_blit = &r100_copy_blit,
  265.         .copy_dma = &r200_copy_dma,
  266.         .copy = &r100_copy_blit,
  267.         .get_engine_clock = &radeon_legacy_get_engine_clock,
  268.         .set_engine_clock = &radeon_legacy_set_engine_clock,
  269.         .get_memory_clock = &radeon_legacy_get_memory_clock,
  270.         .set_memory_clock = NULL,
  271.         .set_pcie_lanes = &rv370_set_pcie_lanes,
  272.         .set_clock_gating = &radeon_legacy_set_clock_gating,
  273.         .set_surface_reg = r100_set_surface_reg,
  274.         .clear_surface_reg = r100_clear_surface_reg,
  275.         .bandwidth_update = &r100_bandwidth_update,
  276.         .hpd_init = &r100_hpd_init,
  277.         .hpd_fini = &r100_hpd_fini,
  278.         .hpd_sense = &r100_hpd_sense,
  279.         .hpd_set_polarity = &r100_hpd_set_polarity,
  280.         .ioctl_wait_idle = NULL,
  281. };
  282.  
  283. static struct radeon_asic r420_asic = {
  284.         .init = &r420_init,
  285. //      .fini = &r420_fini,
  286. //      .suspend = &r420_suspend,
  287. //      .resume = &r420_resume,
  288. //      .vga_set_state = &r100_vga_set_state,
  289.         .asic_reset = &r300_asic_reset,
  290.         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
  291.         .gart_set_page = &rv370_pcie_gart_set_page,
  292.         .cp_commit = &r100_cp_commit,
  293.         .ring_start = &r300_ring_start,
  294.         .ring_test = &r100_ring_test,
  295.         .ring_ib_execute = &r100_ring_ib_execute,
  296.         .irq_set = &r100_irq_set,
  297.         .irq_process = &r100_irq_process,
  298. //      .get_vblank_counter = &r100_get_vblank_counter,
  299.         .fence_ring_emit = &r300_fence_ring_emit,
  300. //      .cs_parse = &r300_cs_parse,
  301.         .copy_blit = &r100_copy_blit,
  302.         .copy_dma = &r200_copy_dma,
  303.         .copy = &r100_copy_blit,
  304.         .get_engine_clock = &radeon_atom_get_engine_clock,
  305.         .set_engine_clock = &radeon_atom_set_engine_clock,
  306.         .get_memory_clock = &radeon_atom_get_memory_clock,
  307.         .set_memory_clock = &radeon_atom_set_memory_clock,
  308.         .get_pcie_lanes = &rv370_get_pcie_lanes,
  309.         .set_pcie_lanes = &rv370_set_pcie_lanes,
  310.         .set_clock_gating = &radeon_atom_set_clock_gating,
  311.         .set_surface_reg = r100_set_surface_reg,
  312.         .clear_surface_reg = r100_clear_surface_reg,
  313.         .bandwidth_update = &r100_bandwidth_update,
  314.         .hpd_init = &r100_hpd_init,
  315.         .hpd_fini = &r100_hpd_fini,
  316.         .hpd_sense = &r100_hpd_sense,
  317.         .hpd_set_polarity = &r100_hpd_set_polarity,
  318.         .ioctl_wait_idle = NULL,
  319. };
  320.  
  321. static struct radeon_asic rs400_asic = {
  322.         .init = &rs400_init,
  323. //      .fini = &rs400_fini,
  324. //      .suspend = &rs400_suspend,
  325. //      .resume = &rs400_resume,
  326. //      .vga_set_state = &r100_vga_set_state,
  327.         .asic_reset = &r300_asic_reset,
  328.         .gart_tlb_flush = &rs400_gart_tlb_flush,
  329.         .gart_set_page = &rs400_gart_set_page,
  330.         .cp_commit = &r100_cp_commit,
  331.         .ring_start = &r300_ring_start,
  332.         .ring_test = &r100_ring_test,
  333.         .ring_ib_execute = &r100_ring_ib_execute,
  334.         .irq_set = &r100_irq_set,
  335.         .irq_process = &r100_irq_process,
  336. //      .get_vblank_counter = &r100_get_vblank_counter,
  337.         .fence_ring_emit = &r300_fence_ring_emit,
  338. //      .cs_parse = &r300_cs_parse,
  339.         .copy_blit = &r100_copy_blit,
  340.         .copy_dma = &r200_copy_dma,
  341.         .copy = &r100_copy_blit,
  342.         .get_engine_clock = &radeon_legacy_get_engine_clock,
  343.         .set_engine_clock = &radeon_legacy_set_engine_clock,
  344.         .get_memory_clock = &radeon_legacy_get_memory_clock,
  345.         .set_memory_clock = NULL,
  346.         .get_pcie_lanes = NULL,
  347.         .set_pcie_lanes = NULL,
  348.         .set_clock_gating = &radeon_legacy_set_clock_gating,
  349.         .set_surface_reg = r100_set_surface_reg,
  350.         .clear_surface_reg = r100_clear_surface_reg,
  351.         .bandwidth_update = &r100_bandwidth_update,
  352.         .hpd_init = &r100_hpd_init,
  353.         .hpd_fini = &r100_hpd_fini,
  354.         .hpd_sense = &r100_hpd_sense,
  355.         .hpd_set_polarity = &r100_hpd_set_polarity,
  356.         .ioctl_wait_idle = NULL,
  357. };
  358.  
  359. static struct radeon_asic rs600_asic = {
  360.         .init = &rs600_init,
  361. //      .fini = &rs600_fini,
  362. //      .suspend = &rs600_suspend,
  363. //      .resume = &rs600_resume,
  364. //      .vga_set_state = &r100_vga_set_state,
  365.         .asic_reset = &rs600_asic_reset,
  366.         .gart_tlb_flush = &rs600_gart_tlb_flush,
  367.         .gart_set_page = &rs600_gart_set_page,
  368.         .cp_commit = &r100_cp_commit,
  369.         .ring_start = &r300_ring_start,
  370.         .ring_test = &r100_ring_test,
  371.         .ring_ib_execute = &r100_ring_ib_execute,
  372.         .irq_set = &rs600_irq_set,
  373.         .irq_process = &rs600_irq_process,
  374. //      .get_vblank_counter = &rs600_get_vblank_counter,
  375.         .fence_ring_emit = &r300_fence_ring_emit,
  376. //   .cs_parse = &r300_cs_parse,
  377.     .copy_blit = &r100_copy_blit,
  378.         .copy_dma = &r200_copy_dma,
  379.     .copy = &r100_copy_blit,
  380.         .get_engine_clock = &radeon_atom_get_engine_clock,
  381.         .set_engine_clock = &radeon_atom_set_engine_clock,
  382.         .get_memory_clock = &radeon_atom_get_memory_clock,
  383.         .set_memory_clock = &radeon_atom_set_memory_clock,
  384.         .get_pcie_lanes = NULL,
  385.         .set_pcie_lanes = NULL,
  386.         .set_clock_gating = &radeon_atom_set_clock_gating,
  387.         .set_surface_reg = r100_set_surface_reg,
  388.         .clear_surface_reg = r100_clear_surface_reg,
  389.         .bandwidth_update = &rs600_bandwidth_update,
  390.         .hpd_init = &rs600_hpd_init,
  391.         .hpd_fini = &rs600_hpd_fini,
  392.         .hpd_sense = &rs600_hpd_sense,
  393.         .hpd_set_polarity = &rs600_hpd_set_polarity,
  394.         .ioctl_wait_idle = NULL,
  395. };
  396.  
  397. static struct radeon_asic rs690_asic = {
  398.         .init = &rs690_init,
  399. //      .fini = &rs690_fini,
  400. //      .suspend = &rs690_suspend,
  401. //      .resume = &rs690_resume,
  402. //      .vga_set_state = &r100_vga_set_state,
  403.         .asic_reset = &rs600_asic_reset,
  404.         .gart_tlb_flush = &rs400_gart_tlb_flush,
  405.         .gart_set_page = &rs400_gart_set_page,
  406.         .cp_commit = &r100_cp_commit,
  407.         .ring_start = &r300_ring_start,
  408.         .ring_test = &r100_ring_test,
  409.         .ring_ib_execute = &r100_ring_ib_execute,
  410.         .irq_set = &rs600_irq_set,
  411.         .irq_process = &rs600_irq_process,
  412. //      .get_vblank_counter = &rs600_get_vblank_counter,
  413.         .fence_ring_emit = &r300_fence_ring_emit,
  414. //      .cs_parse = &r300_cs_parse,
  415.         .copy_blit = &r100_copy_blit,
  416.         .copy_dma = &r200_copy_dma,
  417.         .copy = &r200_copy_dma,
  418.         .get_engine_clock = &radeon_atom_get_engine_clock,
  419.         .set_engine_clock = &radeon_atom_set_engine_clock,
  420.         .get_memory_clock = &radeon_atom_get_memory_clock,
  421.         .set_memory_clock = &radeon_atom_set_memory_clock,
  422.         .get_pcie_lanes = NULL,
  423.         .set_pcie_lanes = NULL,
  424.         .set_clock_gating = &radeon_atom_set_clock_gating,
  425.         .set_surface_reg = r100_set_surface_reg,
  426.         .clear_surface_reg = r100_clear_surface_reg,
  427.         .bandwidth_update = &rs690_bandwidth_update,
  428.         .hpd_init = &rs600_hpd_init,
  429.         .hpd_fini = &rs600_hpd_fini,
  430.         .hpd_sense = &rs600_hpd_sense,
  431.         .hpd_set_polarity = &rs600_hpd_set_polarity,
  432.         .ioctl_wait_idle = NULL,
  433. };
  434.  
  435. static struct radeon_asic rv515_asic = {
  436.         .init = &rv515_init,
  437. //      .fini = &rv515_fini,
  438. //      .suspend = &rv515_suspend,
  439. //      .resume = &rv515_resume,
  440. //      .vga_set_state = &r100_vga_set_state,
  441.         .asic_reset = &rs600_asic_reset,
  442.         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
  443.         .gart_set_page = &rv370_pcie_gart_set_page,
  444.         .cp_commit = &r100_cp_commit,
  445.         .ring_start = &rv515_ring_start,
  446.         .ring_test = &r100_ring_test,
  447.         .ring_ib_execute = &r100_ring_ib_execute,
  448.         .irq_set = &rs600_irq_set,
  449.         .irq_process = &rs600_irq_process,
  450. //      .get_vblank_counter = &rs600_get_vblank_counter,
  451.         .fence_ring_emit = &r300_fence_ring_emit,
  452. //      .cs_parse = &r300_cs_parse,
  453.         .copy_blit = &r100_copy_blit,
  454.         .copy_dma = &r200_copy_dma,
  455.         .copy = &r100_copy_blit,
  456.         .get_engine_clock = &radeon_atom_get_engine_clock,
  457.         .set_engine_clock = &radeon_atom_set_engine_clock,
  458.         .get_memory_clock = &radeon_atom_get_memory_clock,
  459.         .set_memory_clock = &radeon_atom_set_memory_clock,
  460.         .get_pcie_lanes = &rv370_get_pcie_lanes,
  461.         .set_pcie_lanes = &rv370_set_pcie_lanes,
  462.         .set_clock_gating = &radeon_atom_set_clock_gating,
  463.         .set_surface_reg = r100_set_surface_reg,
  464.         .clear_surface_reg = r100_clear_surface_reg,
  465.         .bandwidth_update = &rv515_bandwidth_update,
  466.         .hpd_init = &rs600_hpd_init,
  467.         .hpd_fini = &rs600_hpd_fini,
  468.         .hpd_sense = &rs600_hpd_sense,
  469.         .hpd_set_polarity = &rs600_hpd_set_polarity,
  470.         .ioctl_wait_idle = NULL,
  471. };
  472.  
  473. static struct radeon_asic r520_asic = {
  474.         .init = &r520_init,
  475. //      .fini = &rv515_fini,
  476. //      .suspend = &rv515_suspend,
  477. //      .resume = &r520_resume,
  478. //      .vga_set_state = &r100_vga_set_state,
  479.         .asic_reset = &rs600_asic_reset,
  480.         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
  481.         .gart_set_page = &rv370_pcie_gart_set_page,
  482.         .cp_commit = &r100_cp_commit,
  483.         .ring_start = &rv515_ring_start,
  484.         .ring_test = &r100_ring_test,
  485.         .ring_ib_execute = &r100_ring_ib_execute,
  486.         .irq_set = &rs600_irq_set,
  487.         .irq_process = &rs600_irq_process,
  488. //      .get_vblank_counter = &rs600_get_vblank_counter,
  489.         .fence_ring_emit = &r300_fence_ring_emit,
  490. //      .cs_parse = &r300_cs_parse,
  491.         .copy_blit = &r100_copy_blit,
  492.         .copy_dma = &r200_copy_dma,
  493.         .copy = &r100_copy_blit,
  494.         .get_engine_clock = &radeon_atom_get_engine_clock,
  495.         .set_engine_clock = &radeon_atom_set_engine_clock,
  496.         .get_memory_clock = &radeon_atom_get_memory_clock,
  497.         .set_memory_clock = &radeon_atom_set_memory_clock,
  498.         .get_pcie_lanes = &rv370_get_pcie_lanes,
  499.         .set_pcie_lanes = &rv370_set_pcie_lanes,
  500.         .set_clock_gating = &radeon_atom_set_clock_gating,
  501.         .set_surface_reg = r100_set_surface_reg,
  502.         .clear_surface_reg = r100_clear_surface_reg,
  503.         .bandwidth_update = &rv515_bandwidth_update,
  504.         .hpd_init = &rs600_hpd_init,
  505.         .hpd_fini = &rs600_hpd_fini,
  506.         .hpd_sense = &rs600_hpd_sense,
  507.         .hpd_set_polarity = &rs600_hpd_set_polarity,
  508.         .ioctl_wait_idle = NULL,
  509. };
  510.  
  511. static struct radeon_asic r600_asic = {
  512.         .init = &r600_init,
  513. //      .fini = &r600_fini,
  514. //      .suspend = &r600_suspend,
  515. //      .resume = &r600_resume,
  516.         .cp_commit = &r600_cp_commit,
  517.         .vga_set_state = &r600_vga_set_state,
  518.         .asic_reset = &r600_asic_reset,
  519.         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
  520.         .gart_set_page = &rs600_gart_set_page,
  521.         .ring_test = &r600_ring_test,
  522.         .ring_ib_execute = &r600_ring_ib_execute,
  523.         .irq_set = &r600_irq_set,
  524.         .irq_process = &r600_irq_process,
  525.         .fence_ring_emit = &r600_fence_ring_emit,
  526. //      .cs_parse = &r600_cs_parse,
  527.         .copy_blit = &r600_copy_blit,
  528.         .copy_dma = &r600_copy_blit,
  529.         .copy = &r600_copy_blit,
  530.         .get_engine_clock = &radeon_atom_get_engine_clock,
  531.         .set_engine_clock = &radeon_atom_set_engine_clock,
  532.         .get_memory_clock = &radeon_atom_get_memory_clock,
  533.         .set_memory_clock = &radeon_atom_set_memory_clock,
  534.         .get_pcie_lanes = &r600_get_pcie_lanes,
  535.         .set_pcie_lanes = &r600_set_pcie_lanes,
  536.         .set_clock_gating = NULL,
  537.         .set_surface_reg = r600_set_surface_reg,
  538.         .clear_surface_reg = r600_clear_surface_reg,
  539.         .bandwidth_update = &rv515_bandwidth_update,
  540.         .hpd_init = &r600_hpd_init,
  541.         .hpd_fini = &r600_hpd_fini,
  542.         .hpd_sense = &r600_hpd_sense,
  543.         .hpd_set_polarity = &r600_hpd_set_polarity,
  544. //      .ioctl_wait_idle = r600_ioctl_wait_idle,
  545. };
  546.  
  547. static struct radeon_asic rs780_asic = {
  548.         .init = &r600_init,
  549. //      .fini = &r600_fini,
  550. //      .suspend = &r600_suspend,
  551. //      .resume = &r600_resume,
  552.         .cp_commit = &r600_cp_commit,
  553.         .gpu_is_lockup = &r600_gpu_is_lockup,
  554.         .vga_set_state = &r600_vga_set_state,
  555.         .asic_reset = &r600_asic_reset,
  556.         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
  557.         .gart_set_page = &rs600_gart_set_page,
  558.         .ring_test = &r600_ring_test,
  559.         .ring_ib_execute = &r600_ring_ib_execute,
  560.         .irq_set = &r600_irq_set,
  561.         .irq_process = &r600_irq_process,
  562.         .fence_ring_emit = &r600_fence_ring_emit,
  563. //      .cs_parse = &r600_cs_parse,
  564.         .copy_blit = &r600_copy_blit,
  565.         .copy_dma = &r600_copy_blit,
  566.         .copy = &r600_copy_blit,
  567.         .get_engine_clock = &radeon_atom_get_engine_clock,
  568.         .set_engine_clock = &radeon_atom_set_engine_clock,
  569.         .get_memory_clock = NULL,
  570.         .set_memory_clock = NULL,
  571.         .get_pcie_lanes = NULL,
  572.         .set_pcie_lanes = NULL,
  573.         .set_clock_gating = NULL,
  574.         .set_surface_reg = r600_set_surface_reg,
  575.         .clear_surface_reg = r600_clear_surface_reg,
  576.         .bandwidth_update = &rs690_bandwidth_update,
  577.         .hpd_init = &r600_hpd_init,
  578.         .hpd_fini = &r600_hpd_fini,
  579.         .hpd_sense = &r600_hpd_sense,
  580.         .hpd_set_polarity = &r600_hpd_set_polarity,
  581. };
  582.  
  583. static struct radeon_asic rv770_asic = {
  584.         .init = &rv770_init,
  585. //      .fini = &rv770_fini,
  586. //      .suspend = &rv770_suspend,
  587. //      .resume = &rv770_resume,
  588.         .cp_commit = &r600_cp_commit,
  589.         .asic_reset = &r600_asic_reset,
  590.         .vga_set_state = &r600_vga_set_state,
  591.         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
  592.         .gart_set_page = &rs600_gart_set_page,
  593.         .ring_test = &r600_ring_test,
  594.         .ring_ib_execute = &r600_ring_ib_execute,
  595.         .irq_set = &r600_irq_set,
  596.         .irq_process = &r600_irq_process,
  597.         .fence_ring_emit = &r600_fence_ring_emit,
  598. //      .cs_parse = &r600_cs_parse,
  599.         .copy_blit = &r600_copy_blit,
  600.         .copy_dma = &r600_copy_blit,
  601.         .copy = &r600_copy_blit,
  602.         .get_engine_clock = &radeon_atom_get_engine_clock,
  603.         .set_engine_clock = &radeon_atom_set_engine_clock,
  604.         .get_memory_clock = &radeon_atom_get_memory_clock,
  605.         .set_memory_clock = &radeon_atom_set_memory_clock,
  606.         .get_pcie_lanes = &r600_get_pcie_lanes,
  607.         .set_pcie_lanes = &r600_set_pcie_lanes,
  608.         .set_clock_gating = &radeon_atom_set_clock_gating,
  609.         .set_surface_reg = r600_set_surface_reg,
  610.         .clear_surface_reg = r600_clear_surface_reg,
  611.         .bandwidth_update = &rv515_bandwidth_update,
  612.         .hpd_init = &r600_hpd_init,
  613.         .hpd_fini = &r600_hpd_fini,
  614.         .hpd_sense = &r600_hpd_sense,
  615.         .hpd_set_polarity = &r600_hpd_set_polarity,
  616. };
  617.  
  618. static struct radeon_asic evergreen_asic = {
  619.         .init = &evergreen_init,
  620. //      .fini = &evergreen_fini,
  621. //      .suspend = &evergreen_suspend,
  622. //      .resume = &evergreen_resume,
  623.         .cp_commit = &r600_cp_commit,
  624.         .asic_reset = &evergreen_asic_reset,
  625.         .vga_set_state = &r600_vga_set_state,
  626.         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
  627.         .gart_set_page = &rs600_gart_set_page,
  628.         .ring_test = &r600_ring_test,
  629.         .ring_ib_execute = &evergreen_ring_ib_execute,
  630.         .irq_set = &evergreen_irq_set,
  631.         .irq_process = &evergreen_irq_process,
  632.         .fence_ring_emit = &r600_fence_ring_emit,
  633. //      .cs_parse = &evergreen_cs_parse,
  634.         .copy_blit = &evergreen_copy_blit,
  635.         .copy_dma = &evergreen_copy_blit,
  636.         .copy = &evergreen_copy_blit,
  637.         .get_engine_clock = &radeon_atom_get_engine_clock,
  638.         .set_engine_clock = &radeon_atom_set_engine_clock,
  639.         .get_memory_clock = &radeon_atom_get_memory_clock,
  640.         .set_memory_clock = &radeon_atom_set_memory_clock,
  641.         .get_pcie_lanes = &r600_get_pcie_lanes,
  642.         .set_pcie_lanes = &r600_set_pcie_lanes,
  643.         .set_clock_gating = NULL,
  644.         .set_surface_reg = r600_set_surface_reg,
  645.         .clear_surface_reg = r600_clear_surface_reg,
  646.         .bandwidth_update = &evergreen_bandwidth_update,
  647.         .hpd_init = &evergreen_hpd_init,
  648.         .hpd_fini = &evergreen_hpd_fini,
  649.         .hpd_sense = &evergreen_hpd_sense,
  650.         .hpd_set_polarity = &evergreen_hpd_set_polarity,
  651.  
  652. };
  653.  
  654. static struct radeon_asic sumo_asic = {
  655.         .init = &evergreen_init,
  656. //      .fini = &evergreen_fini,
  657. //      .suspend = &evergreen_suspend,
  658. //      .resume = &evergreen_resume,
  659.         .cp_commit = &r600_cp_commit,
  660.         .asic_reset = &evergreen_asic_reset,
  661.         .vga_set_state = &r600_vga_set_state,
  662.         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
  663.         .gart_set_page = &rs600_gart_set_page,
  664.         .ring_test = &r600_ring_test,
  665.         .ring_ib_execute = &evergreen_ring_ib_execute,
  666.         .irq_set = &evergreen_irq_set,
  667.         .irq_process = &evergreen_irq_process,
  668.         .fence_ring_emit = &r600_fence_ring_emit,
  669. //      .cs_parse = &r600_cs_parse,
  670.         .copy_blit = &evergreen_copy_blit,
  671.         .copy_dma = &evergreen_copy_blit,
  672.         .copy = &evergreen_copy_blit,
  673.         .get_engine_clock = &radeon_atom_get_engine_clock,
  674.         .set_engine_clock = &radeon_atom_set_engine_clock,
  675.         .get_memory_clock = NULL,
  676.         .set_memory_clock = NULL,
  677.         .get_pcie_lanes = NULL,
  678.         .set_pcie_lanes = NULL,
  679.         .set_clock_gating = NULL,
  680.         .set_surface_reg = r600_set_surface_reg,
  681.         .clear_surface_reg = r600_clear_surface_reg,
  682.         .bandwidth_update = &evergreen_bandwidth_update,
  683.         .hpd_init = &evergreen_hpd_init,
  684.         .hpd_fini = &evergreen_hpd_fini,
  685.         .hpd_sense = &evergreen_hpd_sense,
  686.         .hpd_set_polarity = &evergreen_hpd_set_polarity,
  687. };
  688.  
  689. static struct radeon_asic btc_asic = {
  690.         .init = &evergreen_init,
  691. //      .fini = &evergreen_fini,
  692. //      .suspend = &evergreen_suspend,
  693. //      .resume = &evergreen_resume,
  694.         .cp_commit = &r600_cp_commit,
  695.         .asic_reset = &evergreen_asic_reset,
  696.         .vga_set_state = &r600_vga_set_state,
  697.         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
  698.         .gart_set_page = &rs600_gart_set_page,
  699.         .ring_test = &r600_ring_test,
  700.         .ring_ib_execute = &evergreen_ring_ib_execute,
  701.         .irq_set = &evergreen_irq_set,
  702.         .irq_process = &evergreen_irq_process,
  703.         .fence_ring_emit = &r600_fence_ring_emit,
  704. //      .cs_parse = &evergreen_cs_parse,
  705.         .copy_blit = &evergreen_copy_blit,
  706.         .copy_dma = &evergreen_copy_blit,
  707.         .copy = &evergreen_copy_blit,
  708.         .get_engine_clock = &radeon_atom_get_engine_clock,
  709.         .set_engine_clock = &radeon_atom_set_engine_clock,
  710.         .get_memory_clock = &radeon_atom_get_memory_clock,
  711.         .set_memory_clock = &radeon_atom_set_memory_clock,
  712.         .get_pcie_lanes = NULL,
  713.         .set_pcie_lanes = NULL,
  714.         .set_clock_gating = NULL,
  715.         .set_surface_reg = r600_set_surface_reg,
  716.         .clear_surface_reg = r600_clear_surface_reg,
  717.         .bandwidth_update = &evergreen_bandwidth_update,
  718.         .hpd_init = &evergreen_hpd_init,
  719.         .hpd_fini = &evergreen_hpd_fini,
  720.         .hpd_sense = &evergreen_hpd_sense,
  721.         .hpd_set_polarity = &evergreen_hpd_set_polarity,
  722. };
  723.  
  724. static struct radeon_asic cayman_asic = {
  725.         .init = &cayman_init,
  726. //      .fini = &evergreen_fini,
  727. //      .suspend = &evergreen_suspend,
  728. //      .resume = &evergreen_resume,
  729.         .cp_commit = &r600_cp_commit,
  730.         .asic_reset = &cayman_asic_reset,
  731.         .vga_set_state = &r600_vga_set_state,
  732.         .gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
  733.         .gart_set_page = &rs600_gart_set_page,
  734.         .ring_test = &r600_ring_test,
  735.         .ring_ib_execute = &evergreen_ring_ib_execute,
  736.         .irq_set = &evergreen_irq_set,
  737.         .irq_process = &evergreen_irq_process,
  738.         .fence_ring_emit = &r600_fence_ring_emit,
  739. //      .cs_parse = &evergreen_cs_parse,
  740.         .copy_blit = &evergreen_copy_blit,
  741.         .copy_dma = &evergreen_copy_blit,
  742.         .copy = &evergreen_copy_blit,
  743.         .get_engine_clock = &radeon_atom_get_engine_clock,
  744.         .set_engine_clock = &radeon_atom_set_engine_clock,
  745.         .get_memory_clock = &radeon_atom_get_memory_clock,
  746.         .set_memory_clock = &radeon_atom_set_memory_clock,
  747.         .get_pcie_lanes = NULL,
  748.         .set_pcie_lanes = NULL,
  749.         .set_clock_gating = NULL,
  750.         .set_surface_reg = r600_set_surface_reg,
  751.         .clear_surface_reg = r600_clear_surface_reg,
  752.         .bandwidth_update = &evergreen_bandwidth_update,
  753.         .hpd_init = &evergreen_hpd_init,
  754.         .hpd_fini = &evergreen_hpd_fini,
  755.         .hpd_sense = &evergreen_hpd_sense,
  756.         .hpd_set_polarity = &evergreen_hpd_set_polarity,
  757. };
  758.  
  759. int radeon_asic_init(struct radeon_device *rdev)
  760. {
  761.         radeon_register_accessor_init(rdev);
  762.  
  763.         /* set the number of crtcs */
  764.         if (rdev->flags & RADEON_SINGLE_CRTC)
  765.                 rdev->num_crtc = 1;
  766.         else
  767.                 rdev->num_crtc = 2;
  768.  
  769.         switch (rdev->family) {
  770.         case CHIP_R100:
  771.         case CHIP_RV100:
  772.         case CHIP_RS100:
  773.         case CHIP_RV200:
  774.         case CHIP_RS200:
  775.                 rdev->asic = &r100_asic;
  776.                 break;
  777.         case CHIP_R200:
  778.         case CHIP_RV250:
  779.         case CHIP_RS300:
  780.         case CHIP_RV280:
  781.                 rdev->asic = &r200_asic;
  782.                 break;
  783.         case CHIP_R300:
  784.         case CHIP_R350:
  785.         case CHIP_RV350:
  786.         case CHIP_RV380:
  787.                 if (rdev->flags & RADEON_IS_PCIE)
  788.                         rdev->asic = &r300_asic_pcie;
  789.                 else
  790.                         rdev->asic = &r300_asic;
  791.                 break;
  792.         case CHIP_R420:
  793.         case CHIP_R423:
  794.         case CHIP_RV410:
  795.                 rdev->asic = &r420_asic;
  796.                 /* handle macs */
  797.                 if (rdev->bios == NULL) {
  798.                         rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
  799.                         rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
  800.                         rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
  801.                         rdev->asic->set_memory_clock = NULL;
  802.                 }
  803.                 break;
  804.         case CHIP_RS400:
  805.         case CHIP_RS480:
  806.                 rdev->asic = &rs400_asic;
  807.                 break;
  808.         case CHIP_RS600:
  809.                 rdev->asic = &rs600_asic;
  810.                 break;
  811.         case CHIP_RS690:
  812.         case CHIP_RS740:
  813.                 rdev->asic = &rs690_asic;
  814.                 break;
  815.         case CHIP_RV515:
  816.                 rdev->asic = &rv515_asic;
  817.                 break;
  818.         case CHIP_R520:
  819.         case CHIP_RV530:
  820.         case CHIP_RV560:
  821.         case CHIP_RV570:
  822.         case CHIP_R580:
  823.                 rdev->asic = &r520_asic;
  824.                 break;
  825.         case CHIP_R600:
  826.         case CHIP_RV610:
  827.         case CHIP_RV630:
  828.         case CHIP_RV620:
  829.         case CHIP_RV635:
  830.         case CHIP_RV670:
  831.                 rdev->asic = &r600_asic;
  832.                 break;
  833.         case CHIP_RS780:
  834.         case CHIP_RS880:
  835.                 rdev->asic = &rs780_asic;
  836.                 break;
  837.         case CHIP_RV770:
  838.         case CHIP_RV730:
  839.         case CHIP_RV710:
  840.         case CHIP_RV740:
  841.                 rdev->asic = &rv770_asic;
  842.                 break;
  843.         case CHIP_CEDAR:
  844.         case CHIP_REDWOOD:
  845.         case CHIP_JUNIPER:
  846.         case CHIP_CYPRESS:
  847.         case CHIP_HEMLOCK:
  848.                 /* set num crtcs */
  849.                 if (rdev->family == CHIP_CEDAR)
  850.                         rdev->num_crtc = 4;
  851.                 else
  852.                         rdev->num_crtc = 6;
  853.                 rdev->asic = &evergreen_asic;
  854.                 break;
  855.         case CHIP_PALM:
  856.         case CHIP_SUMO:
  857.         case CHIP_SUMO2:
  858.                 rdev->asic = &sumo_asic;
  859.                 break;
  860.         case CHIP_BARTS:
  861.         case CHIP_TURKS:
  862.         case CHIP_CAICOS:
  863.                 /* set num crtcs */
  864.                 if (rdev->family == CHIP_CAICOS)
  865.                         rdev->num_crtc = 4;
  866.                 else
  867.                         rdev->num_crtc = 6;
  868.                 rdev->asic = &btc_asic;
  869.                 break;
  870.         case CHIP_CAYMAN:
  871.                 rdev->asic = &cayman_asic;
  872.                 /* set num crtcs */
  873.                 rdev->num_crtc = 6;
  874.                 break;
  875.         default:
  876.                 /* FIXME: not supported yet */
  877.                 return -EINVAL;
  878.         }
  879.  
  880.         if (rdev->flags & RADEON_IS_IGP) {
  881.                 rdev->asic->get_memory_clock = NULL;
  882.                 rdev->asic->set_memory_clock = NULL;
  883.         }
  884.  
  885.         return 0;
  886. }
  887.  
  888.