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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30.  
  31. /* TODO: Here are things that needs to be done :
  32.  *      - surface allocator & initializer : (bit like scratch reg) should
  33.  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34.  *        related to surface
  35.  *      - WB : write back stuff (do it bit like scratch reg things)
  36.  *      - Vblank : look at Jesse's rework and what we should do
  37.  *      - r600/r700: gart & cp
  38.  *      - cs : clean cs ioctl use bitmap & things like that.
  39.  *      - power management stuff
  40.  *      - Barrier in gart code
  41.  *      - Unmappabled vram ?
  42.  *      - TESTING, TESTING, TESTING
  43.  */
  44.  
  45. /* Initialization path:
  46.  *  We expect that acceleration initialization might fail for various
  47.  *  reasons even thought we work hard to make it works on most
  48.  *  configurations. In order to still have a working userspace in such
  49.  *  situation the init path must succeed up to the memory controller
  50.  *  initialization point. Failure before this point are considered as
  51.  *  fatal error. Here is the init callchain :
  52.  *      radeon_device_init  perform common structure, mutex initialization
  53.  *      asic_init           setup the GPU memory layout and perform all
  54.  *                          one time initialization (failure in this
  55.  *                          function are considered fatal)
  56.  *      asic_startup        setup the GPU acceleration, in order to
  57.  *                          follow guideline the first thing this
  58.  *                          function should do is setting the GPU
  59.  *                          memory controller (only MC setup failure
  60.  *                          are considered as fatal)
  61.  */
  62.  
  63. #include <asm/atomic.h>
  64. #include <linux/wait.h>
  65. #include <linux/list.h>
  66. #include <linux/kref.h>
  67. #include <asm/div64.h>
  68.  
  69. #include <ttm/ttm_bo_api.h>
  70. #include <ttm/ttm_bo_driver.h>
  71. #include <ttm/ttm_placement.h>
  72. #include <ttm/ttm_module.h>
  73.  
  74. #include <linux/irqreturn.h>
  75. #include <pci.h>
  76.  
  77. #include <errno-base.h>
  78.  
  79. #include "radeon_family.h"
  80. #include "radeon_mode.h"
  81. #include "radeon_reg.h"
  82.  
  83. #include <syscall.h>
  84.  
  85. /*
  86.  * Modules parameters.
  87.  */
  88. extern int radeon_no_wb;
  89. extern int radeon_modeset;
  90. extern int radeon_dynclks;
  91. extern int radeon_r4xx_atom;
  92. extern int radeon_agpmode;
  93. extern int radeon_vram_limit;
  94. extern int radeon_gart_size;
  95. extern int radeon_benchmarking;
  96. extern int radeon_testing;
  97. extern int radeon_connector_table;
  98. extern int radeon_tv;
  99. extern int radeon_audio;
  100. extern int radeon_disp_priority;
  101. extern int radeon_hw_i2c;
  102. extern int radeon_pcie_gen2;
  103. extern int radeon_msi;
  104. extern int radeon_lockup_timeout;
  105.  
  106.  
  107.  
  108. typedef struct pm_message {
  109.     int event;
  110. } pm_message_t;
  111.  
  112. typedef struct
  113. {
  114.   int width;
  115.   int height;
  116.   int bpp;
  117.   int freq;
  118. }videomode_t;
  119.  
  120.  
  121.  
  122. static inline u32 ioread32(const volatile void __iomem *addr)
  123. {
  124.     return in32((u32)addr);
  125. }
  126.  
  127. static inline void iowrite32(uint32_t b, volatile void __iomem *addr)
  128. {
  129.     out32((u32)addr, b);
  130. }
  131.  
  132.  
  133. /*
  134.  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  135.  * symbol;
  136.  */
  137. #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  138. #define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
  139. /* RADEON_IB_POOL_SIZE must be a power of 2 */
  140. #define RADEON_IB_POOL_SIZE             16
  141. #define RADEON_DEBUGFS_MAX_COMPONENTS   32
  142. #define RADEONFB_CONN_LIMIT             4
  143. #define RADEON_BIOS_NUM_SCRATCH         8
  144.  
  145. /* max number of rings */
  146. #define RADEON_NUM_RINGS                        5
  147.  
  148. /* fence seq are set to this number when signaled */
  149. #define RADEON_FENCE_SIGNALED_SEQ               0LL
  150.  
  151. /* internal ring indices */
  152. /* r1xx+ has gfx CP ring */
  153. #define RADEON_RING_TYPE_GFX_INDEX  0
  154.  
  155. /* cayman has 2 compute CP rings */
  156. #define CAYMAN_RING_TYPE_CP1_INDEX 1
  157. #define CAYMAN_RING_TYPE_CP2_INDEX 2
  158.  
  159. /* R600+ has an async dma ring */
  160. #define R600_RING_TYPE_DMA_INDEX                3
  161. /* cayman add a second async dma ring */
  162. #define CAYMAN_RING_TYPE_DMA1_INDEX             4
  163.  
  164. /* hardcode those limit for now */
  165. #define RADEON_VA_IB_OFFSET                     (1 << 20)
  166. #define RADEON_VA_RESERVED_SIZE         (8 << 20)
  167. #define RADEON_IB_VM_MAX_SIZE           (64 << 10)
  168.  
  169. /* reset flags */
  170. #define RADEON_RESET_GFX                        (1 << 0)
  171. #define RADEON_RESET_COMPUTE                    (1 << 1)
  172. #define RADEON_RESET_DMA                        (1 << 2)
  173.  
  174. /*
  175.  * Errata workarounds.
  176.  */
  177. enum radeon_pll_errata {
  178.     CHIP_ERRATA_R300_CG             = 0x00000001,
  179.     CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  180.     CHIP_ERRATA_PLL_DELAY           = 0x00000004
  181. };
  182.  
  183.  
  184. struct radeon_device;
  185.  
  186.  
  187. /*
  188.  * BIOS.
  189.  */
  190. bool radeon_get_bios(struct radeon_device *rdev);
  191.  
  192. /*
  193.  * Dummy page
  194.  */
  195. struct radeon_dummy_page {
  196.         struct page     *page;
  197.         dma_addr_t      addr;
  198. };
  199. int radeon_dummy_page_init(struct radeon_device *rdev);
  200. void radeon_dummy_page_fini(struct radeon_device *rdev);
  201.  
  202.  
  203. /*
  204.  * Clocks
  205.  */
  206. struct radeon_clock {
  207.         struct radeon_pll p1pll;
  208.         struct radeon_pll p2pll;
  209.         struct radeon_pll dcpll;
  210.         struct radeon_pll spll;
  211.         struct radeon_pll mpll;
  212.         /* 10 Khz units */
  213.         uint32_t default_mclk;
  214.         uint32_t default_sclk;
  215.         uint32_t default_dispclk;
  216.         uint32_t dp_extclk;
  217.         uint32_t max_pixel_clock;
  218. };
  219.  
  220. /*
  221.  * Power management
  222.  */
  223. int radeon_pm_init(struct radeon_device *rdev);
  224. void radeon_pm_fini(struct radeon_device *rdev);
  225. void radeon_pm_compute_clocks(struct radeon_device *rdev);
  226. void radeon_pm_suspend(struct radeon_device *rdev);
  227. void radeon_pm_resume(struct radeon_device *rdev);
  228. void radeon_combios_get_power_modes(struct radeon_device *rdev);
  229. void radeon_atombios_get_power_modes(struct radeon_device *rdev);
  230. void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
  231. void rs690_pm_info(struct radeon_device *rdev);
  232. extern int rv6xx_get_temp(struct radeon_device *rdev);
  233. extern int rv770_get_temp(struct radeon_device *rdev);
  234. extern int evergreen_get_temp(struct radeon_device *rdev);
  235. extern int sumo_get_temp(struct radeon_device *rdev);
  236. extern int si_get_temp(struct radeon_device *rdev);
  237. extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
  238.                                     unsigned *bankh, unsigned *mtaspect,
  239.                                     unsigned *tile_split);
  240.  
  241. /*
  242.  * Fences.
  243.  */
  244. struct radeon_fence_driver {
  245.         uint32_t                        scratch_reg;
  246.         uint64_t                        gpu_addr;
  247.         volatile uint32_t               *cpu_addr;
  248.         /* sync_seq is protected by ring emission lock */
  249.         uint64_t                        sync_seq[RADEON_NUM_RINGS];
  250.         atomic64_t                      last_seq;
  251.         unsigned long                   last_activity;
  252.         bool                            initialized;
  253. };
  254.  
  255. struct radeon_fence {
  256.     struct radeon_device   *rdev;
  257.     struct kref             kref;
  258.         /* protected by radeon_fence.lock */
  259.         uint64_t                        seq;
  260.         /* RB, DMA, etc. */
  261.         unsigned                        ring;
  262. };
  263.  
  264. int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
  265. int radeon_fence_driver_init(struct radeon_device *rdev);
  266. void radeon_fence_driver_fini(struct radeon_device *rdev);
  267. void radeon_fence_driver_force_completion(struct radeon_device *rdev);
  268. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
  269. void radeon_fence_process(struct radeon_device *rdev, int ring);
  270. bool radeon_fence_signaled(struct radeon_fence *fence);
  271. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  272. int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
  273. int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
  274. int radeon_fence_wait_any(struct radeon_device *rdev,
  275.                           struct radeon_fence **fences,
  276.                           bool intr);
  277. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  278. void radeon_fence_unref(struct radeon_fence **fence);
  279. unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
  280. bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
  281. void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
  282. static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
  283.                                                       struct radeon_fence *b)
  284. {
  285.         if (!a) {
  286.                 return b;
  287.         }
  288.  
  289.         if (!b) {
  290.                 return a;
  291.         }
  292.  
  293.         BUG_ON(a->ring != b->ring);
  294.  
  295.         if (a->seq > b->seq) {
  296.                 return a;
  297.         } else {
  298.                 return b;
  299.         }
  300. }
  301.  
  302. static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
  303.                                            struct radeon_fence *b)
  304. {
  305.         if (!a) {
  306.                 return false;
  307.         }
  308.  
  309.         if (!b) {
  310.                 return true;
  311.         }
  312.  
  313.         BUG_ON(a->ring != b->ring);
  314.  
  315.         return a->seq < b->seq;
  316. }
  317.  
  318. /*
  319.  * Tiling registers
  320.  */
  321. struct radeon_surface_reg {
  322.         struct radeon_bo *bo;
  323. };
  324.  
  325. #define RADEON_GEM_MAX_SURFACES 8
  326.  
  327. /*
  328.  * TTM.
  329.  */
  330. struct radeon_mman {
  331.         struct ttm_bo_global_ref        bo_global_ref;
  332. //      struct drm_global_reference     mem_global_ref;
  333.         struct ttm_bo_device            bdev;
  334.         bool                            mem_global_referenced;
  335.         bool                            initialized;
  336. };
  337.  
  338. /* bo virtual address in a specific vm */
  339. struct radeon_bo_va {
  340.         /* protected by bo being reserved */
  341.         struct list_head                bo_list;
  342.         uint64_t                        soffset;
  343.         uint64_t                        eoffset;
  344.         uint32_t                        flags;
  345.         bool                            valid;
  346.         unsigned                        ref_count;
  347.  
  348.         /* protected by vm mutex */
  349.         struct list_head                vm_list;
  350.  
  351.         /* constant after initialization */
  352.         struct radeon_vm                *vm;
  353.         struct radeon_bo                *bo;
  354. };
  355.  
  356. struct radeon_bo {
  357.         /* Protected by gem.mutex */
  358.         struct list_head                list;
  359.         /* Protected by tbo.reserved */
  360.         u32                             placements[3];
  361.         u32                             busy_placements[3];
  362.         struct ttm_placement            placement;
  363.         struct ttm_buffer_object        tbo;
  364.         struct ttm_bo_kmap_obj          kmap;
  365.     unsigned                    pin_count;
  366.     void                       *kptr;
  367.     void                       *uptr;
  368.     u32                         cpu_addr;
  369.     u32                         tiling_flags;
  370.     u32                         pitch;
  371.     int                         surface_reg;
  372.         /* list of all virtual address to which this bo
  373.          * is associated to
  374.          */
  375.         struct list_head                va;
  376.         /* Constant after initialization */
  377.         struct radeon_device            *rdev;
  378.         struct drm_gem_object           gem_base;
  379.  
  380.     u32                          domain;
  381.         int vmapping_count;
  382. };
  383. #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
  384.  
  385. struct radeon_bo_list {
  386.         struct radeon_bo        *bo;
  387.         uint64_t                gpu_offset;
  388.         unsigned                rdomain;
  389.         unsigned                wdomain;
  390.         u32                     tiling_flags;
  391. };
  392.  
  393. /* sub-allocation manager, it has to be protected by another lock.
  394.  * By conception this is an helper for other part of the driver
  395.  * like the indirect buffer or semaphore, which both have their
  396.  * locking.
  397.  *
  398.  * Principe is simple, we keep a list of sub allocation in offset
  399.  * order (first entry has offset == 0, last entry has the highest
  400.  * offset).
  401.  *
  402.  * When allocating new object we first check if there is room at
  403.  * the end total_size - (last_object_offset + last_object_size) >=
  404.  * alloc_size. If so we allocate new object there.
  405.  *
  406.  * When there is not enough room at the end, we start waiting for
  407.  * each sub object until we reach object_offset+object_size >=
  408.  * alloc_size, this object then become the sub object we return.
  409.  *
  410.  * Alignment can't be bigger than page size.
  411.  *
  412.  * Hole are not considered for allocation to keep things simple.
  413.  * Assumption is that there won't be hole (all object on same
  414.  * alignment).
  415.  */
  416. struct radeon_sa_manager {
  417.         wait_queue_head_t       wq;
  418.         struct radeon_bo        *bo;
  419.         struct list_head        *hole;
  420.         struct list_head        flist[RADEON_NUM_RINGS];
  421.         struct list_head        olist;
  422.         unsigned                size;
  423.         uint64_t                gpu_addr;
  424.         void                    *cpu_ptr;
  425.         uint32_t                domain;
  426. };
  427.  
  428. struct radeon_sa_bo;
  429.  
  430. /* sub-allocation buffer */
  431. struct radeon_sa_bo {
  432.         struct list_head                olist;
  433.         struct list_head                flist;
  434.         struct radeon_sa_manager        *manager;
  435.         unsigned                        soffset;
  436.         unsigned                        eoffset;
  437.         struct radeon_fence             *fence;
  438. };
  439.  
  440. /*
  441.  * GEM objects.
  442.  */
  443. struct radeon_gem {
  444.         struct mutex            mutex;
  445.         struct list_head        objects;
  446. };
  447.  
  448. int radeon_gem_init(struct radeon_device *rdev);
  449. void radeon_gem_fini(struct radeon_device *rdev);
  450. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  451.                              int alignment, int initial_domain,
  452.                              bool discardable, bool kernel,
  453.                              struct drm_gem_object **obj);
  454.  
  455. int radeon_mode_dumb_create(struct drm_file *file_priv,
  456.                             struct drm_device *dev,
  457.                             struct drm_mode_create_dumb *args);
  458. int radeon_mode_dumb_mmap(struct drm_file *filp,
  459.                           struct drm_device *dev,
  460.                           uint32_t handle, uint64_t *offset_p);
  461. int radeon_mode_dumb_destroy(struct drm_file *file_priv,
  462.                              struct drm_device *dev,
  463.                              uint32_t handle);
  464.  
  465. /*
  466.  * Semaphores.
  467.  */
  468. /* everything here is constant */
  469. struct radeon_semaphore {
  470.         struct radeon_sa_bo             *sa_bo;
  471.         signed                          waiters;
  472.         uint64_t                        gpu_addr;
  473. };
  474.  
  475. int radeon_semaphore_create(struct radeon_device *rdev,
  476.                             struct radeon_semaphore **semaphore);
  477. void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
  478.                                   struct radeon_semaphore *semaphore);
  479. void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
  480.                                 struct radeon_semaphore *semaphore);
  481. int radeon_semaphore_sync_rings(struct radeon_device *rdev,
  482.                                 struct radeon_semaphore *semaphore,
  483.                                 int signaler, int waiter);
  484. void radeon_semaphore_free(struct radeon_device *rdev,
  485.                            struct radeon_semaphore **semaphore,
  486.                            struct radeon_fence *fence);
  487.  
  488. /*
  489.  * GART structures, functions & helpers
  490.  */
  491. struct radeon_mc;
  492.  
  493. #define RADEON_GPU_PAGE_SIZE 4096
  494. #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
  495. #define RADEON_GPU_PAGE_SHIFT 12
  496. #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
  497.  
  498. struct radeon_gart {
  499.     dma_addr_t          table_addr;
  500.         struct radeon_bo                *robj;
  501.         void                            *ptr;
  502.     unsigned            num_gpu_pages;
  503.     unsigned            num_cpu_pages;
  504.     unsigned            table_size;
  505.     struct page         **pages;
  506.     dma_addr_t          *pages_addr;
  507.     bool                ready;
  508. };
  509.  
  510. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  511. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  512. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  513. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  514. int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  515. void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
  516. int radeon_gart_init(struct radeon_device *rdev);
  517. void radeon_gart_fini(struct radeon_device *rdev);
  518. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  519.                         int pages);
  520. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  521.              int pages, u32 *pagelist,
  522.                      dma_addr_t *dma_addr);
  523. void radeon_gart_restore(struct radeon_device *rdev);
  524.  
  525.  
  526. /*
  527.  * GPU MC structures, functions & helpers
  528.  */
  529. struct radeon_mc {
  530.     resource_size_t     aper_size;
  531.     resource_size_t     aper_base;
  532.     resource_size_t     agp_base;
  533.         /* for some chips with <= 32MB we need to lie
  534.          * about vram size near mc fb location */
  535.         u64                     mc_vram_size;
  536.         u64                     visible_vram_size;
  537.         u64                     gtt_size;
  538.         u64                     gtt_start;
  539.         u64                     gtt_end;
  540.         u64                     vram_start;
  541.         u64                     vram_end;
  542.     unsigned            vram_width;
  543.         u64                     real_vram_size;
  544.     int                 vram_mtrr;
  545.     bool                vram_is_ddr;
  546.         bool                    igp_sideport_enabled;
  547.         u64                     gtt_base_align;
  548. };
  549.  
  550. bool radeon_combios_sideport_present(struct radeon_device *rdev);
  551. bool radeon_atombios_sideport_present(struct radeon_device *rdev);
  552.  
  553. /*
  554.  * GPU scratch registers structures, functions & helpers
  555.  */
  556. struct radeon_scratch {
  557.     unsigned        num_reg;
  558.         uint32_t                reg_base;
  559.     bool            free[32];
  560.     uint32_t        reg[32];
  561. };
  562.  
  563. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  564. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  565.  
  566.  
  567. /*
  568.  * IRQS.
  569.  */
  570. struct r500_irq_stat_regs {
  571.         u32 disp_int;
  572.         u32 hdmi0_status;
  573. };
  574.  
  575. struct r600_irq_stat_regs {
  576.         u32 disp_int;
  577.         u32 disp_int_cont;
  578.         u32 disp_int_cont2;
  579.         u32 d1grph_int;
  580.         u32 d2grph_int;
  581.         u32 hdmi0_status;
  582.         u32 hdmi1_status;
  583. };
  584.  
  585. struct evergreen_irq_stat_regs {
  586.         u32 disp_int;
  587.         u32 disp_int_cont;
  588.         u32 disp_int_cont2;
  589.         u32 disp_int_cont3;
  590.         u32 disp_int_cont4;
  591.         u32 disp_int_cont5;
  592.         u32 d1grph_int;
  593.         u32 d2grph_int;
  594.         u32 d3grph_int;
  595.         u32 d4grph_int;
  596.         u32 d5grph_int;
  597.         u32 d6grph_int;
  598.         u32 afmt_status1;
  599.         u32 afmt_status2;
  600.         u32 afmt_status3;
  601.         u32 afmt_status4;
  602.         u32 afmt_status5;
  603.         u32 afmt_status6;
  604. };
  605.  
  606. union radeon_irq_stat_regs {
  607.         struct r500_irq_stat_regs r500;
  608.         struct r600_irq_stat_regs r600;
  609.         struct evergreen_irq_stat_regs evergreen;
  610. };
  611.  
  612. #define RADEON_MAX_HPD_PINS 6
  613. #define RADEON_MAX_CRTCS 6
  614. #define RADEON_MAX_AFMT_BLOCKS 6
  615.  
  616. struct radeon_irq {
  617.         bool            installed;
  618.         spinlock_t                      lock;
  619.         atomic_t                        ring_int[RADEON_NUM_RINGS];
  620.         bool                            crtc_vblank_int[RADEON_MAX_CRTCS];
  621.         atomic_t                        pflip[RADEON_MAX_CRTCS];
  622.     wait_queue_head_t   vblank_queue;
  623.         bool                            hpd[RADEON_MAX_HPD_PINS];
  624.         bool                            afmt[RADEON_MAX_AFMT_BLOCKS];
  625.         union radeon_irq_stat_regs stat_regs;
  626. };
  627.  
  628. int radeon_irq_kms_init(struct radeon_device *rdev);
  629. void radeon_irq_kms_fini(struct radeon_device *rdev);
  630. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
  631. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
  632. void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
  633. void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
  634. void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
  635. void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
  636. void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
  637. void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
  638.  
  639. /*
  640.  * CP & rings.
  641.  */
  642.  
  643. struct radeon_ib {
  644.         struct radeon_sa_bo             *sa_bo;
  645.         uint32_t                length_dw;
  646.     uint64_t            gpu_addr;
  647.         uint32_t                *ptr;
  648.         int                             ring;
  649.         struct radeon_fence     *fence;
  650.         struct radeon_vm                *vm;
  651.         bool                    is_const_ib;
  652.         struct radeon_fence             *sync_to[RADEON_NUM_RINGS];
  653.         struct radeon_semaphore         *semaphore;
  654. };
  655.  
  656. struct radeon_ring {
  657.         struct radeon_bo        *ring_obj;
  658.         volatile uint32_t       *ring;
  659.     unsigned            rptr;
  660.         unsigned                rptr_offs;
  661.         unsigned                rptr_reg;
  662.         unsigned                rptr_save_reg;
  663.         u64                     next_rptr_gpu_addr;
  664.         volatile u32            *next_rptr_cpu_addr;
  665.     unsigned            wptr;
  666.     unsigned            wptr_old;
  667.         unsigned                wptr_reg;
  668.     unsigned            ring_size;
  669.     unsigned            ring_free_dw;
  670.     int                 count_dw;
  671.         unsigned long           last_activity;
  672.         unsigned                last_rptr;
  673.     uint64_t            gpu_addr;
  674.     uint32_t            align_mask;
  675.     uint32_t            ptr_mask;
  676.     bool                ready;
  677.         u32                     ptr_reg_shift;
  678.         u32                     ptr_reg_mask;
  679.         u32                     nop;
  680.         u32                     idx;
  681. };
  682.  
  683. /*
  684.  * VM
  685.  */
  686.  
  687. /* maximum number of VMIDs */
  688. #define RADEON_NUM_VM   16
  689.  
  690. /* defines number of bits in page table versus page directory,
  691.  * a page is 4KB so we have 12 bits offset, 9 bits in the page
  692.  * table and the remaining 19 bits are in the page directory */
  693. #define RADEON_VM_BLOCK_SIZE   9
  694.  
  695. /* number of entries in page table */
  696. #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
  697.  
  698. struct radeon_vm {
  699.         struct list_head                list;
  700.         struct list_head                va;
  701.         unsigned                        id;
  702.  
  703.         /* contains the page directory */
  704.         struct radeon_sa_bo             *page_directory;
  705.         uint64_t                        pd_gpu_addr;
  706.  
  707.         /* array of page tables, one for each page directory entry */
  708.         struct radeon_sa_bo             **page_tables;
  709.  
  710.         struct mutex                    mutex;
  711.         /* last fence for cs using this vm */
  712.         struct radeon_fence             *fence;
  713.         /* last flush or NULL if we still need to flush */
  714.         struct radeon_fence             *last_flush;
  715. };
  716.  
  717. struct radeon_vm_manager {
  718.         struct mutex                    lock;
  719.         struct list_head                lru_vm;
  720.         struct radeon_fence             *active[RADEON_NUM_VM];
  721.         struct radeon_sa_manager        sa_manager;
  722.         uint32_t                        max_pfn;
  723.         /* number of VMIDs */
  724.         unsigned                        nvm;
  725.         /* vram base address for page table entry  */
  726.         u64                             vram_base_offset;
  727.         /* is vm enabled? */
  728.         bool                            enabled;
  729. };
  730.  
  731. /*
  732.  * file private structure
  733.  */
  734. struct radeon_fpriv {
  735.         struct radeon_vm                vm;
  736. };
  737.  
  738. /*
  739.  * R6xx+ IH ring
  740.  */
  741. struct r600_ih {
  742.         struct radeon_bo        *ring_obj;
  743.         volatile uint32_t       *ring;
  744.     unsigned            rptr;
  745.     unsigned            ring_size;
  746.     uint64_t            gpu_addr;
  747.     uint32_t            ptr_mask;
  748.         atomic_t                lock;
  749.     bool                enabled;
  750. };
  751.  
  752. struct r600_blit_cp_primitives {
  753.         void (*set_render_target)(struct radeon_device *rdev, int format,
  754.                                   int w, int h, u64 gpu_addr);
  755.         void (*cp_set_surface_sync)(struct radeon_device *rdev,
  756.                                     u32 sync_type, u32 size,
  757.                                     u64 mc_addr);
  758.         void (*set_shaders)(struct radeon_device *rdev);
  759.         void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
  760.         void (*set_tex_resource)(struct radeon_device *rdev,
  761.                                  int format, int w, int h, int pitch,
  762.                                  u64 gpu_addr, u32 size);
  763.         void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
  764.                              int x2, int y2);
  765.         void (*draw_auto)(struct radeon_device *rdev);
  766.         void (*set_default_state)(struct radeon_device *rdev);
  767. };
  768.  
  769. struct r600_blit {
  770.         struct radeon_bo        *shader_obj;
  771.         struct r600_blit_cp_primitives primitives;
  772.         int max_dim;
  773.         int ring_size_common;
  774.         int ring_size_per_loop;
  775.         u64 shader_gpu_addr;
  776.         u32 vs_offset, ps_offset;
  777.         u32 state_offset;
  778.         u32 state_len;
  779. };
  780.  
  781. /*
  782.  * SI RLC stuff
  783.  */
  784. struct si_rlc {
  785.         /* for power gating */
  786.         struct radeon_bo        *save_restore_obj;
  787.         uint64_t                save_restore_gpu_addr;
  788.         /* for clear state */
  789.         struct radeon_bo        *clear_state_obj;
  790.         uint64_t                clear_state_gpu_addr;
  791. };
  792.  
  793. int radeon_ib_get(struct radeon_device *rdev, int ring,
  794.                   struct radeon_ib *ib, struct radeon_vm *vm,
  795.                   unsigned size);
  796. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
  797. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
  798.                        struct radeon_ib *const_ib);
  799. int radeon_ib_pool_init(struct radeon_device *rdev);
  800. void radeon_ib_pool_fini(struct radeon_device *rdev);
  801. int radeon_ib_ring_tests(struct radeon_device *rdev);
  802. /* Ring access between begin & end cannot sleep */
  803. bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
  804.                                       struct radeon_ring *ring);
  805. void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
  806. int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
  807. int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
  808. void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
  809. void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
  810. void radeon_ring_undo(struct radeon_ring *ring);
  811. void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
  812. int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  813. void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
  814. void radeon_ring_lockup_update(struct radeon_ring *ring);
  815. bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
  816. unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
  817.                             uint32_t **data);
  818. int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
  819.                         unsigned size, uint32_t *data);
  820. int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
  821.                      unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
  822.                      u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
  823. void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
  824.  
  825.  
  826. /* r600 async dma */
  827. void r600_dma_stop(struct radeon_device *rdev);
  828. int r600_dma_resume(struct radeon_device *rdev);
  829. void r600_dma_fini(struct radeon_device *rdev);
  830.  
  831. void cayman_dma_stop(struct radeon_device *rdev);
  832. int cayman_dma_resume(struct radeon_device *rdev);
  833. void cayman_dma_fini(struct radeon_device *rdev);
  834.  
  835. /*
  836.  * CS.
  837.  */
  838. struct radeon_cs_reloc {
  839. //      struct drm_gem_object           *gobj;
  840.         struct radeon_bo                *robj;
  841.         struct radeon_bo_list           lobj;
  842.     uint32_t                handle;
  843.     uint32_t                flags;
  844. };
  845.  
  846. struct radeon_cs_chunk {
  847.         uint32_t                chunk_id;
  848.         uint32_t                length_dw;
  849.         int kpage_idx[2];
  850.         uint32_t                *kpage[2];
  851.         uint32_t                *kdata;
  852.         void __user *user_ptr;
  853.         int last_copied_page;
  854.         int last_page_index;
  855. };
  856.  
  857. struct radeon_cs_parser {
  858.         struct device           *dev;
  859.         struct radeon_device    *rdev;
  860.         struct drm_file         *filp;
  861.         /* chunks */
  862.         unsigned                nchunks;
  863.         struct radeon_cs_chunk  *chunks;
  864.         uint64_t                *chunks_array;
  865.         /* IB */
  866.         unsigned                idx;
  867.         /* relocations */
  868.         unsigned                nrelocs;
  869.         struct radeon_cs_reloc  *relocs;
  870.         struct radeon_cs_reloc  **relocs_ptr;
  871.         struct list_head        validated;
  872.         unsigned                dma_reloc_idx;
  873.         /* indices of various chunks */
  874.         int                     chunk_ib_idx;
  875.         int                     chunk_relocs_idx;
  876.         int                     chunk_flags_idx;
  877.         int                     chunk_const_ib_idx;
  878.         struct radeon_ib        ib;
  879.         struct radeon_ib        const_ib;
  880.         void                    *track;
  881.         unsigned                family;
  882.         int parser_error;
  883.         u32                     cs_flags;
  884.         u32                     ring;
  885.         s32                     priority;
  886. };
  887.  
  888. extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
  889. extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
  890.  
  891. struct radeon_cs_packet {
  892.         unsigned        idx;
  893.         unsigned        type;
  894.         unsigned        reg;
  895.         unsigned        opcode;
  896.         int             count;
  897.         unsigned        one_reg_wr;
  898. };
  899.  
  900. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  901.                                       struct radeon_cs_packet *pkt,
  902.                                       unsigned idx, unsigned reg);
  903. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  904.                                       struct radeon_cs_packet *pkt);
  905.  
  906.  
  907. /*
  908.  * AGP
  909.  */
  910. int radeon_agp_init(struct radeon_device *rdev);
  911. void radeon_agp_resume(struct radeon_device *rdev);
  912. void radeon_agp_suspend(struct radeon_device *rdev);
  913. void radeon_agp_fini(struct radeon_device *rdev);
  914.  
  915.  
  916. /*
  917.  * Writeback
  918.  */
  919. struct radeon_wb {
  920.         struct radeon_bo        *wb_obj;
  921.         volatile uint32_t       *wb;
  922.         uint64_t                gpu_addr;
  923.         bool                    enabled;
  924.         bool                    use_event;
  925. };
  926.  
  927. #define RADEON_WB_SCRATCH_OFFSET 0
  928. #define RADEON_WB_RING0_NEXT_RPTR 256
  929. #define RADEON_WB_CP_RPTR_OFFSET 1024
  930. #define RADEON_WB_CP1_RPTR_OFFSET 1280
  931. #define RADEON_WB_CP2_RPTR_OFFSET 1536
  932. #define R600_WB_DMA_RPTR_OFFSET   1792
  933. #define R600_WB_IH_WPTR_OFFSET   2048
  934. #define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
  935. #define R600_WB_EVENT_OFFSET     3072
  936.  
  937. /**
  938.  * struct radeon_pm - power management datas
  939.  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
  940.  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  941.  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
  942.  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
  943.  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
  944.  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
  945.  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  946.  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
  947.  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
  948.  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
  949.  * @needed_bandwidth:   current bandwidth needs
  950.  *
  951.  * It keeps track of various data needed to take powermanagement decision.
  952.  * Bandwidth need is used to determine minimun clock of the GPU and memory.
  953.  * Equation between gpu/memory clock and available bandwidth is hw dependent
  954.  * (type of memory, bus size, efficiency, ...)
  955.  */
  956.  
  957. enum radeon_pm_method {
  958.         PM_METHOD_PROFILE,
  959.         PM_METHOD_DYNPM,
  960. };
  961.  
  962. enum radeon_dynpm_state {
  963.         DYNPM_STATE_DISABLED,
  964.         DYNPM_STATE_MINIMUM,
  965.         DYNPM_STATE_PAUSED,
  966.         DYNPM_STATE_ACTIVE,
  967.         DYNPM_STATE_SUSPENDED,
  968. };
  969. enum radeon_dynpm_action {
  970.         DYNPM_ACTION_NONE,
  971.         DYNPM_ACTION_MINIMUM,
  972.         DYNPM_ACTION_DOWNCLOCK,
  973.         DYNPM_ACTION_UPCLOCK,
  974.         DYNPM_ACTION_DEFAULT
  975. };
  976.  
  977. enum radeon_voltage_type {
  978.         VOLTAGE_NONE = 0,
  979.         VOLTAGE_GPIO,
  980.         VOLTAGE_VDDC,
  981.         VOLTAGE_SW
  982. };
  983.  
  984. enum radeon_pm_state_type {
  985.         POWER_STATE_TYPE_DEFAULT,
  986.         POWER_STATE_TYPE_POWERSAVE,
  987.         POWER_STATE_TYPE_BATTERY,
  988.         POWER_STATE_TYPE_BALANCED,
  989.         POWER_STATE_TYPE_PERFORMANCE,
  990. };
  991.  
  992. enum radeon_pm_profile_type {
  993.         PM_PROFILE_DEFAULT,
  994.         PM_PROFILE_AUTO,
  995.         PM_PROFILE_LOW,
  996.         PM_PROFILE_MID,
  997.         PM_PROFILE_HIGH,
  998. };
  999.  
  1000. #define PM_PROFILE_DEFAULT_IDX 0
  1001. #define PM_PROFILE_LOW_SH_IDX  1
  1002. #define PM_PROFILE_MID_SH_IDX  2
  1003. #define PM_PROFILE_HIGH_SH_IDX 3
  1004. #define PM_PROFILE_LOW_MH_IDX  4
  1005. #define PM_PROFILE_MID_MH_IDX  5
  1006. #define PM_PROFILE_HIGH_MH_IDX 6
  1007. #define PM_PROFILE_MAX         7
  1008.  
  1009. struct radeon_pm_profile {
  1010.         int dpms_off_ps_idx;
  1011.         int dpms_on_ps_idx;
  1012.         int dpms_off_cm_idx;
  1013.         int dpms_on_cm_idx;
  1014. };
  1015.  
  1016. enum radeon_int_thermal_type {
  1017.         THERMAL_TYPE_NONE,
  1018.         THERMAL_TYPE_RV6XX,
  1019.         THERMAL_TYPE_RV770,
  1020.         THERMAL_TYPE_EVERGREEN,
  1021.         THERMAL_TYPE_SUMO,
  1022.         THERMAL_TYPE_NI,
  1023.         THERMAL_TYPE_SI,
  1024. };
  1025.  
  1026. struct radeon_voltage {
  1027.         enum radeon_voltage_type type;
  1028.         /* gpio voltage */
  1029.         struct radeon_gpio_rec gpio;
  1030.         u32 delay; /* delay in usec from voltage drop to sclk change */
  1031.         bool active_high; /* voltage drop is active when bit is high */
  1032.         /* VDDC voltage */
  1033.         u8 vddc_id; /* index into vddc voltage table */
  1034.         u8 vddci_id; /* index into vddci voltage table */
  1035.         bool vddci_enabled;
  1036.         /* r6xx+ sw */
  1037.         u16 voltage;
  1038.         /* evergreen+ vddci */
  1039.         u16 vddci;
  1040. };
  1041.  
  1042. /* clock mode flags */
  1043. #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
  1044.  
  1045. struct radeon_pm_clock_info {
  1046.         /* memory clock */
  1047.         u32 mclk;
  1048.         /* engine clock */
  1049.         u32 sclk;
  1050.         /* voltage info */
  1051.         struct radeon_voltage voltage;
  1052.         /* standardized clock flags */
  1053.         u32 flags;
  1054. };
  1055.  
  1056. /* state flags */
  1057. #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
  1058.  
  1059. struct radeon_power_state {
  1060.         enum radeon_pm_state_type type;
  1061.         struct radeon_pm_clock_info *clock_info;
  1062.         /* number of valid clock modes in this power state */
  1063.         int num_clock_modes;
  1064.         struct radeon_pm_clock_info *default_clock_mode;
  1065.         /* standardized state flags */
  1066.         u32 flags;
  1067.         u32 misc; /* vbios specific flags */
  1068.         u32 misc2; /* vbios specific flags */
  1069.         int pcie_lanes; /* pcie lanes */
  1070. };
  1071.  
  1072. /*
  1073.  * Some modes are overclocked by very low value, accept them
  1074.  */
  1075. #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
  1076.  
  1077. struct radeon_pm {
  1078.         struct mutex            mutex;
  1079.         /* write locked while reprogramming mclk */
  1080.         struct rw_semaphore     mclk_lock;
  1081.         u32                     active_crtcs;
  1082.         int                     active_crtc_count;
  1083.         int                     req_vblank;
  1084.         bool                    vblank_sync;
  1085.         fixed20_12              max_bandwidth;
  1086.         fixed20_12              igp_sideport_mclk;
  1087.         fixed20_12              igp_system_mclk;
  1088.         fixed20_12              igp_ht_link_clk;
  1089.         fixed20_12              igp_ht_link_width;
  1090.         fixed20_12              k8_bandwidth;
  1091.         fixed20_12              sideport_bandwidth;
  1092.         fixed20_12              ht_bandwidth;
  1093.         fixed20_12              core_bandwidth;
  1094.         fixed20_12              sclk;
  1095.         fixed20_12              mclk;
  1096.         fixed20_12              needed_bandwidth;
  1097.         struct radeon_power_state *power_state;
  1098.         /* number of valid power states */
  1099.         int                     num_power_states;
  1100.         int                     current_power_state_index;
  1101.         int                     current_clock_mode_index;
  1102.         int                     requested_power_state_index;
  1103.         int                     requested_clock_mode_index;
  1104.         int                     default_power_state_index;
  1105.         u32                     current_sclk;
  1106.         u32                     current_mclk;
  1107.         u16                     current_vddc;
  1108.         u16                     current_vddci;
  1109.         u32                     default_sclk;
  1110.         u32                     default_mclk;
  1111.         u16                     default_vddc;
  1112.         u16                     default_vddci;
  1113.         struct radeon_i2c_chan *i2c_bus;
  1114.         /* selected pm method */
  1115.         enum radeon_pm_method     pm_method;
  1116.         /* dynpm power management */
  1117. //   struct delayed_work dynpm_idle_work;
  1118.         enum radeon_dynpm_state dynpm_state;
  1119.         enum radeon_dynpm_action        dynpm_planned_action;
  1120.         unsigned long           dynpm_action_timeout;
  1121.         bool                    dynpm_can_upclock;
  1122.         bool                    dynpm_can_downclock;
  1123.         /* profile-based power management */
  1124.         enum radeon_pm_profile_type profile;
  1125.         int                     profile_index;
  1126.         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
  1127.         /* internal thermal controller on rv6xx+ */
  1128.         enum radeon_int_thermal_type int_thermal_type;
  1129.         struct device           *int_hwmon_dev;
  1130. };
  1131.  
  1132. int radeon_pm_get_type_index(struct radeon_device *rdev,
  1133.                              enum radeon_pm_state_type ps_type,
  1134.                              int instance);
  1135.  
  1136. struct r600_audio {
  1137.         int                     channels;
  1138.         int                     rate;
  1139.         int                     bits_per_sample;
  1140.         u8                      status_bits;
  1141.         u8                      category_code;
  1142. };
  1143. /*
  1144.  * ASIC specific functions.
  1145.  */
  1146. struct radeon_asic {
  1147.         int (*init)(struct radeon_device *rdev);
  1148.         void (*fini)(struct radeon_device *rdev);
  1149.         int (*resume)(struct radeon_device *rdev);
  1150.         int (*suspend)(struct radeon_device *rdev);
  1151.         void (*vga_set_state)(struct radeon_device *rdev, bool state);
  1152.         int (*asic_reset)(struct radeon_device *rdev);
  1153.         /* ioctl hw specific callback. Some hw might want to perform special
  1154.          * operation on specific ioctl. For instance on wait idle some hw
  1155.          * might want to perform and HDP flush through MMIO as it seems that
  1156.          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
  1157.          * through ring.
  1158.          */
  1159.         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
  1160.         /* check if 3D engine is idle */
  1161.         bool (*gui_idle)(struct radeon_device *rdev);
  1162.         /* wait for mc_idle */
  1163.         int (*mc_wait_for_idle)(struct radeon_device *rdev);
  1164.         /* gart */
  1165.         struct {
  1166.                 void (*tlb_flush)(struct radeon_device *rdev);
  1167.                 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  1168.         } gart;
  1169.         struct {
  1170.                 int (*init)(struct radeon_device *rdev);
  1171.                 void (*fini)(struct radeon_device *rdev);
  1172.  
  1173.                 u32 pt_ring_index;
  1174.                 void (*set_page)(struct radeon_device *rdev, uint64_t pe,
  1175.                                  uint64_t addr, unsigned count,
  1176.                                  uint32_t incr, uint32_t flags);
  1177.         } vm;
  1178.         /* ring specific callbacks */
  1179.         struct {
  1180.                 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  1181.                 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
  1182.                 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
  1183.                 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
  1184.                                        struct radeon_semaphore *semaphore, bool emit_wait);
  1185.                 int (*cs_parse)(struct radeon_cs_parser *p);
  1186.                 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
  1187.                 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
  1188.                 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
  1189.                 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
  1190.                 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
  1191.         } ring[RADEON_NUM_RINGS];
  1192.         /* irqs */
  1193.         struct {
  1194.                 int (*set)(struct radeon_device *rdev);
  1195.                 int (*process)(struct radeon_device *rdev);
  1196.         } irq;
  1197.         /* displays */
  1198.         struct {
  1199.                 /* display watermarks */
  1200.                 void (*bandwidth_update)(struct radeon_device *rdev);
  1201.                 /* get frame count */
  1202.         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  1203.                 /* wait for vblank */
  1204.                 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
  1205.                 /* set backlight level */
  1206.                 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
  1207.                 /* get backlight level */
  1208.                 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
  1209.         } display;
  1210.         /* copy functions for bo handling */
  1211.         struct {
  1212.                 int (*blit)(struct radeon_device *rdev,
  1213.                          uint64_t src_offset,
  1214.                          uint64_t dst_offset,
  1215.                          unsigned num_gpu_pages,
  1216.                             struct radeon_fence **fence);
  1217.                 u32 blit_ring_index;
  1218.                 int (*dma)(struct radeon_device *rdev,
  1219.                         uint64_t src_offset,
  1220.                         uint64_t dst_offset,
  1221.                         unsigned num_gpu_pages,
  1222.                            struct radeon_fence **fence);
  1223.                 u32 dma_ring_index;
  1224.                 /* method used for bo copy */
  1225.         int (*copy)(struct radeon_device *rdev,
  1226.                     uint64_t src_offset,
  1227.                     uint64_t dst_offset,
  1228.                     unsigned num_gpu_pages,
  1229.                             struct radeon_fence **fence);
  1230.                 /* ring used for bo copies */
  1231.                 u32 copy_ring_index;
  1232.         } copy;
  1233.         /* surfaces */
  1234.         struct {
  1235.                 int (*set_reg)(struct radeon_device *rdev, int reg,
  1236.                                        uint32_t tiling_flags, uint32_t pitch,
  1237.                                        uint32_t offset, uint32_t obj_size);
  1238.                 void (*clear_reg)(struct radeon_device *rdev, int reg);
  1239.         } surface;
  1240.         /* hotplug detect */
  1241.         struct {
  1242.                 void (*init)(struct radeon_device *rdev);
  1243.                 void (*fini)(struct radeon_device *rdev);
  1244.                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  1245.                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  1246.         } hpd;
  1247.         /* power management */
  1248.         struct {
  1249.                 void (*misc)(struct radeon_device *rdev);
  1250.                 void (*prepare)(struct radeon_device *rdev);
  1251.                 void (*finish)(struct radeon_device *rdev);
  1252.                 void (*init_profile)(struct radeon_device *rdev);
  1253.                 void (*get_dynpm_state)(struct radeon_device *rdev);
  1254.         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
  1255.         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  1256.         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
  1257.         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  1258.         int (*get_pcie_lanes)(struct radeon_device *rdev);
  1259.         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  1260.         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  1261.         } pm;
  1262.         /* pageflipping */
  1263.         struct {
  1264.         void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
  1265.         u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
  1266.         void (*post_page_flip)(struct radeon_device *rdev, int crtc);
  1267.         } pflip;
  1268. };
  1269.  
  1270. /*
  1271.  * Asic structures
  1272.  */
  1273. struct r100_asic {
  1274.         const unsigned  *reg_safe_bm;
  1275.         unsigned        reg_safe_bm_size;
  1276.         u32             hdp_cntl;
  1277. };
  1278.  
  1279. struct r300_asic {
  1280.         const unsigned  *reg_safe_bm;
  1281.         unsigned        reg_safe_bm_size;
  1282.         u32             resync_scratch;
  1283.         u32             hdp_cntl;
  1284. };
  1285.  
  1286. struct r600_asic {
  1287.         unsigned max_pipes;
  1288.         unsigned max_tile_pipes;
  1289.         unsigned max_simds;
  1290.         unsigned max_backends;
  1291.         unsigned max_gprs;
  1292.         unsigned max_threads;
  1293.         unsigned max_stack_entries;
  1294.         unsigned max_hw_contexts;
  1295.         unsigned max_gs_threads;
  1296.         unsigned sx_max_export_size;
  1297.         unsigned sx_max_export_pos_size;
  1298.         unsigned sx_max_export_smx_size;
  1299.         unsigned sq_num_cf_insts;
  1300.         unsigned tiling_nbanks;
  1301.         unsigned tiling_npipes;
  1302.         unsigned tiling_group_size;
  1303.         unsigned                tile_config;
  1304.         unsigned                backend_map;
  1305. };
  1306.  
  1307. struct rv770_asic {
  1308.         unsigned max_pipes;
  1309.         unsigned max_tile_pipes;
  1310.         unsigned max_simds;
  1311.         unsigned max_backends;
  1312.         unsigned max_gprs;
  1313.         unsigned max_threads;
  1314.         unsigned max_stack_entries;
  1315.         unsigned max_hw_contexts;
  1316.         unsigned max_gs_threads;
  1317.         unsigned sx_max_export_size;
  1318.         unsigned sx_max_export_pos_size;
  1319.         unsigned sx_max_export_smx_size;
  1320.         unsigned sq_num_cf_insts;
  1321.         unsigned sx_num_of_sets;
  1322.         unsigned sc_prim_fifo_size;
  1323.         unsigned sc_hiz_tile_fifo_size;
  1324.         unsigned sc_earlyz_tile_fifo_fize;
  1325.         unsigned tiling_nbanks;
  1326.         unsigned tiling_npipes;
  1327.         unsigned tiling_group_size;
  1328.         unsigned                tile_config;
  1329.         unsigned                backend_map;
  1330. };
  1331.  
  1332. struct evergreen_asic {
  1333.         unsigned num_ses;
  1334.         unsigned max_pipes;
  1335.         unsigned max_tile_pipes;
  1336.         unsigned max_simds;
  1337.         unsigned max_backends;
  1338.         unsigned max_gprs;
  1339.         unsigned max_threads;
  1340.         unsigned max_stack_entries;
  1341.         unsigned max_hw_contexts;
  1342.         unsigned max_gs_threads;
  1343.         unsigned sx_max_export_size;
  1344.         unsigned sx_max_export_pos_size;
  1345.         unsigned sx_max_export_smx_size;
  1346.         unsigned sq_num_cf_insts;
  1347.         unsigned sx_num_of_sets;
  1348.         unsigned sc_prim_fifo_size;
  1349.         unsigned sc_hiz_tile_fifo_size;
  1350.         unsigned sc_earlyz_tile_fifo_size;
  1351.         unsigned tiling_nbanks;
  1352.         unsigned tiling_npipes;
  1353.         unsigned tiling_group_size;
  1354.         unsigned tile_config;
  1355.         unsigned backend_map;
  1356. };
  1357.  
  1358. struct cayman_asic {
  1359.         unsigned max_shader_engines;
  1360.         unsigned max_pipes_per_simd;
  1361.         unsigned max_tile_pipes;
  1362.         unsigned max_simds_per_se;
  1363.         unsigned max_backends_per_se;
  1364.         unsigned max_texture_channel_caches;
  1365.         unsigned max_gprs;
  1366.         unsigned max_threads;
  1367.         unsigned max_gs_threads;
  1368.         unsigned max_stack_entries;
  1369.         unsigned sx_num_of_sets;
  1370.         unsigned sx_max_export_size;
  1371.         unsigned sx_max_export_pos_size;
  1372.         unsigned sx_max_export_smx_size;
  1373.         unsigned max_hw_contexts;
  1374.         unsigned sq_num_cf_insts;
  1375.         unsigned sc_prim_fifo_size;
  1376.         unsigned sc_hiz_tile_fifo_size;
  1377.         unsigned sc_earlyz_tile_fifo_size;
  1378.  
  1379.         unsigned num_shader_engines;
  1380.         unsigned num_shader_pipes_per_simd;
  1381.         unsigned num_tile_pipes;
  1382.         unsigned num_simds_per_se;
  1383.         unsigned num_backends_per_se;
  1384.         unsigned backend_disable_mask_per_asic;
  1385.         unsigned backend_map;
  1386.         unsigned num_texture_channel_caches;
  1387.         unsigned mem_max_burst_length_bytes;
  1388.         unsigned mem_row_size_in_kb;
  1389.         unsigned shader_engine_tile_size;
  1390.         unsigned num_gpus;
  1391.         unsigned multi_gpu_tile_size;
  1392.  
  1393.         unsigned tile_config;
  1394. };
  1395.  
  1396. struct si_asic {
  1397.         unsigned max_shader_engines;
  1398.         unsigned max_tile_pipes;
  1399.         unsigned max_cu_per_sh;
  1400.         unsigned max_sh_per_se;
  1401.         unsigned max_backends_per_se;
  1402.         unsigned max_texture_channel_caches;
  1403.         unsigned max_gprs;
  1404.         unsigned max_gs_threads;
  1405.         unsigned max_hw_contexts;
  1406.         unsigned sc_prim_fifo_size_frontend;
  1407.         unsigned sc_prim_fifo_size_backend;
  1408.         unsigned sc_hiz_tile_fifo_size;
  1409.         unsigned sc_earlyz_tile_fifo_size;
  1410.  
  1411.         unsigned num_tile_pipes;
  1412.         unsigned num_backends_per_se;
  1413.         unsigned backend_disable_mask_per_asic;
  1414.         unsigned backend_map;
  1415.         unsigned num_texture_channel_caches;
  1416.         unsigned mem_max_burst_length_bytes;
  1417.         unsigned mem_row_size_in_kb;
  1418.         unsigned shader_engine_tile_size;
  1419.         unsigned num_gpus;
  1420.         unsigned multi_gpu_tile_size;
  1421.  
  1422.         unsigned tile_config;
  1423. };
  1424.  
  1425. union radeon_asic_config {
  1426.         struct r300_asic        r300;
  1427.         struct r100_asic        r100;
  1428.         struct r600_asic        r600;
  1429.         struct rv770_asic       rv770;
  1430.         struct evergreen_asic   evergreen;
  1431.         struct cayman_asic      cayman;
  1432.         struct si_asic          si;
  1433. };
  1434.  
  1435. /*
  1436.  * asic initizalization from radeon_asic.c
  1437.  */
  1438. void radeon_agp_disable(struct radeon_device *rdev);
  1439. int radeon_asic_init(struct radeon_device *rdev);
  1440.  
  1441.  
  1442.  
  1443. /* VRAM scratch page for HDP bug, default vram page */
  1444. struct r600_vram_scratch {
  1445.         struct radeon_bo                *robj;
  1446.         volatile uint32_t               *ptr;
  1447.         u64                             gpu_addr;
  1448. };
  1449.  
  1450.  
  1451. /*
  1452.  * Core structure, functions and helpers.
  1453.  */
  1454. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  1455. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  1456.  
  1457. struct radeon_device {
  1458.     struct device              *dev;
  1459.     struct drm_device          *ddev;
  1460.     struct pci_dev             *pdev;
  1461.         struct rw_semaphore             exclusive_lock;
  1462.     /* ASIC */
  1463.     union radeon_asic_config    config;
  1464.     enum radeon_family          family;
  1465.     unsigned long               flags;
  1466.     int                         usec_timeout;
  1467.     enum radeon_pll_errata      pll_errata;
  1468.     int                         num_gb_pipes;
  1469.         int                                         num_z_pipes;
  1470.     int                         disp_priority;
  1471.     /* BIOS */
  1472.     uint8_t                     *bios;
  1473.     bool                        is_atom_bios;
  1474.     uint16_t                    bios_header_start;
  1475.         struct radeon_bo                    *stollen_vga_memory;
  1476.     /* Register mmio */
  1477.         resource_size_t                 rmmio_base;
  1478.         resource_size_t                 rmmio_size;
  1479.         /* protects concurrent MM_INDEX/DATA based register access */
  1480.         spinlock_t mmio_idx_lock;
  1481.         void __iomem                    *rmmio;
  1482.     radeon_rreg_t               mc_rreg;
  1483.     radeon_wreg_t               mc_wreg;
  1484.     radeon_rreg_t               pll_rreg;
  1485.     radeon_wreg_t               pll_wreg;
  1486.         uint32_t                        pcie_reg_mask;
  1487.     radeon_rreg_t               pciep_rreg;
  1488.     radeon_wreg_t               pciep_wreg;
  1489.         /* io port */
  1490.         void __iomem                    *rio_mem;
  1491.         resource_size_t                 rio_mem_size;
  1492.     struct radeon_clock         clock;
  1493.     struct radeon_mc            mc;
  1494.     struct radeon_gart          gart;
  1495.         struct radeon_mode_info         mode_info;
  1496.     struct radeon_scratch       scratch;
  1497.     struct radeon_mman          mman;
  1498.         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
  1499.         wait_queue_head_t               fence_queue;
  1500.         struct mutex                    ring_lock;
  1501.         struct radeon_ring              ring[RADEON_NUM_RINGS];
  1502.         bool                            ib_pool_ready;
  1503.         struct radeon_sa_manager        ring_tmp_bo;
  1504.     struct radeon_irq       irq;
  1505.     struct radeon_asic         *asic;
  1506.     struct radeon_gem       gem;
  1507.         struct radeon_pm                pm;
  1508.         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  1509.     struct radeon_wb        wb;
  1510.         struct radeon_dummy_page        dummy_page;
  1511.     bool                shutdown;
  1512.     bool                suspend;
  1513.         bool                            need_dma32;
  1514.         bool                            accel_working;
  1515.         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  1516.         const struct firmware *me_fw;   /* all family ME firmware */
  1517.         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
  1518.         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
  1519.         const struct firmware *mc_fw;   /* NI MC firmware */
  1520.         const struct firmware *ce_fw;   /* SI CE firmware */
  1521.         struct r600_blit r600_blit;
  1522.         struct r600_vram_scratch vram_scratch;
  1523.         int msi_enabled; /* msi enabled */
  1524.         struct r600_ih ih; /* r6/700 interrupt ring */
  1525.         struct si_rlc rlc;
  1526. //      struct work_struct hotplug_work;
  1527. //      struct work_struct audio_work;
  1528.         int num_crtc; /* number of crtcs */
  1529.         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
  1530.         bool                    audio_enabled;
  1531. //   struct r600_audio audio_status; /* audio stuff */
  1532. //   struct notifier_block acpi_nb;
  1533.         /* only one userspace can use Hyperz features or CMASK at a time */
  1534. //      struct drm_file *hyperz_filp;
  1535. //      struct drm_file *cmask_filp;
  1536.         /* i2c buses */
  1537.         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
  1538.         /* debugfs */
  1539. //      struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
  1540.         unsigned                debugfs_count;
  1541.         /* virtual memory */
  1542.         struct radeon_vm_manager        vm_manager;
  1543.         struct mutex                    gpu_clock_mutex;
  1544.         /* ACPI interface */
  1545. //      struct radeon_atif              atif;
  1546. //      struct radeon_atcs              atcs;
  1547. };
  1548.  
  1549. int radeon_device_init(struct radeon_device *rdev,
  1550.                        struct drm_device *ddev,
  1551.                        struct pci_dev *pdev,
  1552.                        uint32_t flags);
  1553. void radeon_device_fini(struct radeon_device *rdev);
  1554. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  1555.  
  1556. uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
  1557.                       bool always_indirect);
  1558. void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
  1559.                   bool always_indirect);
  1560. u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
  1561. void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  1562.  
  1563. /*
  1564.  * Cast helper
  1565.  */
  1566. #define to_radeon_fence(p) ((struct radeon_fence *)(p))
  1567.  
  1568. /*
  1569.  * Registers read & write functions.
  1570.  */
  1571. #define RREG8(reg) readb((rdev->rmmio) + (reg))
  1572. #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
  1573. #define RREG16(reg) readw((rdev->rmmio) + (reg))
  1574. #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
  1575. #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
  1576. #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
  1577. #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
  1578. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
  1579. #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
  1580. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  1581. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  1582. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  1583. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  1584. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  1585. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  1586. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  1587. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  1588. #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
  1589. #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
  1590. #define WREG32_P(reg, val, mask)                                \
  1591.         do {                                                    \
  1592.                 uint32_t tmp_ = RREG32(reg);                    \
  1593.                 tmp_ &= (mask);                                 \
  1594.                 tmp_ |= ((val) & ~(mask));                      \
  1595.                 WREG32(reg, tmp_);                              \
  1596.         } while (0)
  1597. #define WREG32_PLL_P(reg, val, mask)                            \
  1598.         do {                                                    \
  1599.                 uint32_t tmp_ = RREG32_PLL(reg);                \
  1600.                 tmp_ &= (mask);                                 \
  1601.                 tmp_ |= ((val) & ~(mask));                      \
  1602.                 WREG32_PLL(reg, tmp_);                          \
  1603.         } while (0)
  1604. #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
  1605. #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
  1606.  
  1607. /*
  1608.  * Indirect registers accessor
  1609.  */
  1610. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  1611. {
  1612.         uint32_t r;
  1613.  
  1614.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  1615.         r = RREG32(RADEON_PCIE_DATA);
  1616.         return r;
  1617. }
  1618.  
  1619. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  1620. {
  1621.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  1622.         WREG32(RADEON_PCIE_DATA, (v));
  1623. }
  1624.  
  1625. void r100_pll_errata_after_index(struct radeon_device *rdev);
  1626.  
  1627.  
  1628. /*
  1629.  * ASICs helpers.
  1630.  */
  1631. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  1632.                             (rdev->pdev->device == 0x5969))
  1633. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  1634.         (rdev->family == CHIP_RV200) || \
  1635.         (rdev->family == CHIP_RS100) || \
  1636.         (rdev->family == CHIP_RS200) || \
  1637.         (rdev->family == CHIP_RV250) || \
  1638.         (rdev->family == CHIP_RV280) || \
  1639.         (rdev->family == CHIP_RS300))
  1640. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
  1641.         (rdev->family == CHIP_RV350) ||         \
  1642.         (rdev->family == CHIP_R350)  ||         \
  1643.         (rdev->family == CHIP_RV380) ||         \
  1644.         (rdev->family == CHIP_R420)  ||         \
  1645.         (rdev->family == CHIP_R423)  ||         \
  1646.         (rdev->family == CHIP_RV410) ||         \
  1647.         (rdev->family == CHIP_RS400) ||         \
  1648.         (rdev->family == CHIP_RS480))
  1649. #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
  1650.                 (rdev->ddev->pdev->device == 0x9443) || \
  1651.                 (rdev->ddev->pdev->device == 0x944B) || \
  1652.                 (rdev->ddev->pdev->device == 0x9506) || \
  1653.                 (rdev->ddev->pdev->device == 0x9509) || \
  1654.                 (rdev->ddev->pdev->device == 0x950F) || \
  1655.                 (rdev->ddev->pdev->device == 0x689C) || \
  1656.                 (rdev->ddev->pdev->device == 0x689D))
  1657. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  1658. #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
  1659.                             (rdev->family == CHIP_RS690)  ||    \
  1660.                             (rdev->family == CHIP_RS740)  ||    \
  1661.                             (rdev->family >= CHIP_R600))
  1662. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  1663. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  1664. #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
  1665. #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
  1666.                              (rdev->flags & RADEON_IS_IGP))
  1667. #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
  1668. #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
  1669. #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
  1670.                              (rdev->flags & RADEON_IS_IGP))
  1671.  
  1672. /*
  1673.  * BIOS helpers.
  1674.  */
  1675. #define RBIOS8(i) (rdev->bios[i])
  1676. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  1677. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  1678.  
  1679. int radeon_combios_init(struct radeon_device *rdev);
  1680. void radeon_combios_fini(struct radeon_device *rdev);
  1681. int radeon_atombios_init(struct radeon_device *rdev);
  1682. void radeon_atombios_fini(struct radeon_device *rdev);
  1683.  
  1684.  
  1685. /*
  1686.  * RING helpers.
  1687.  */
  1688. #if DRM_DEBUG_CODE == 0
  1689. static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
  1690. {
  1691.         ring->ring[ring->wptr++] = v;
  1692.         ring->wptr &= ring->ptr_mask;
  1693.         ring->count_dw--;
  1694.         ring->ring_free_dw--;
  1695. }
  1696. #else
  1697. /* With debugging this is just too big to inline */
  1698. void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
  1699. #endif
  1700.  
  1701. /*
  1702.  * ASICs macro.
  1703.  */
  1704. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  1705. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  1706. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  1707. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  1708. #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
  1709. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  1710. #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
  1711. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
  1712. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
  1713. #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
  1714. #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
  1715. #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags)))
  1716. #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
  1717. #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
  1718. #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
  1719. #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
  1720. #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
  1721. #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
  1722. #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
  1723. #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
  1724. #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
  1725. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
  1726. #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
  1727. #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
  1728. #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
  1729. #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
  1730. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
  1731. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
  1732. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
  1733. #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
  1734. #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
  1735. #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
  1736. #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
  1737. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
  1738. #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
  1739. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
  1740. #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
  1741. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
  1742. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
  1743. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
  1744. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
  1745. #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
  1746. #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
  1747. #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
  1748. #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
  1749. #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
  1750. #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
  1751. #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
  1752. #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
  1753. #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
  1754. #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
  1755. #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
  1756. #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
  1757. #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
  1758. #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
  1759. #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
  1760. #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
  1761.  
  1762. /* Common functions */
  1763. /* AGP */
  1764. extern int radeon_gpu_reset(struct radeon_device *rdev);
  1765. extern void radeon_agp_disable(struct radeon_device *rdev);
  1766. extern int radeon_modeset_init(struct radeon_device *rdev);
  1767. extern void radeon_modeset_fini(struct radeon_device *rdev);
  1768. extern bool radeon_card_posted(struct radeon_device *rdev);
  1769. extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
  1770. extern void radeon_update_display_priority(struct radeon_device *rdev);
  1771. extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
  1772. extern void radeon_scratch_init(struct radeon_device *rdev);
  1773. extern void radeon_wb_fini(struct radeon_device *rdev);
  1774. extern int radeon_wb_init(struct radeon_device *rdev);
  1775. extern void radeon_wb_disable(struct radeon_device *rdev);
  1776. extern void radeon_surface_init(struct radeon_device *rdev);
  1777. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  1778. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  1779. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  1780. extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
  1781. extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
  1782. extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
  1783. extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
  1784. extern int radeon_resume_kms(struct drm_device *dev);
  1785. extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
  1786. extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
  1787.  
  1788. /*
  1789.  * vm
  1790.  */
  1791. int radeon_vm_manager_init(struct radeon_device *rdev);
  1792. void radeon_vm_manager_fini(struct radeon_device *rdev);
  1793. void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
  1794. void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
  1795. int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
  1796. void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
  1797. struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
  1798.                                        struct radeon_vm *vm, int ring);
  1799. void radeon_vm_fence(struct radeon_device *rdev,
  1800.                      struct radeon_vm *vm,
  1801.                      struct radeon_fence *fence);
  1802. uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
  1803. int radeon_vm_bo_update_pte(struct radeon_device *rdev,
  1804.                             struct radeon_vm *vm,
  1805.                             struct radeon_bo *bo,
  1806.                             struct ttm_mem_reg *mem);
  1807. void radeon_vm_bo_invalidate(struct radeon_device *rdev,
  1808.                              struct radeon_bo *bo);
  1809. struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
  1810.                                        struct radeon_bo *bo);
  1811. struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
  1812.                                       struct radeon_vm *vm,
  1813.                                       struct radeon_bo *bo);
  1814. int radeon_vm_bo_set_addr(struct radeon_device *rdev,
  1815.                           struct radeon_bo_va *bo_va,
  1816.                           uint64_t offset,
  1817.                           uint32_t flags);
  1818. int radeon_vm_bo_rmv(struct radeon_device *rdev,
  1819.                      struct radeon_bo_va *bo_va);
  1820.  
  1821. /* audio */
  1822. void r600_audio_update_hdmi(struct work_struct *work);
  1823.  
  1824. /*
  1825.  * R600 vram scratch functions
  1826.  */
  1827. int r600_vram_scratch_init(struct radeon_device *rdev);
  1828. void r600_vram_scratch_fini(struct radeon_device *rdev);
  1829.  
  1830. /*
  1831.  * r600 cs checking helper
  1832.  */
  1833. unsigned r600_mip_minify(unsigned size, unsigned level);
  1834. bool r600_fmt_is_valid_color(u32 format);
  1835. bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
  1836. int r600_fmt_get_blocksize(u32 format);
  1837. int r600_fmt_get_nblocksx(u32 format, u32 w);
  1838. int r600_fmt_get_nblocksy(u32 format, u32 h);
  1839.  
  1840. /*
  1841.  * r600 functions used by radeon_encoder.c
  1842.  */
  1843. struct radeon_hdmi_acr {
  1844.         u32 clock;
  1845.  
  1846.         int n_32khz;
  1847.         int cts_32khz;
  1848.  
  1849.         int n_44_1khz;
  1850.         int cts_44_1khz;
  1851.  
  1852.         int n_48khz;
  1853.         int cts_48khz;
  1854.  
  1855. };
  1856.  
  1857. extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
  1858.  
  1859. extern void r600_hdmi_enable(struct drm_encoder *encoder);
  1860. extern void r600_hdmi_disable(struct drm_encoder *encoder);
  1861. extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  1862. extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
  1863.                                      u32 tiling_pipe_num,
  1864.                                      u32 max_rb_num,
  1865.                                      u32 total_max_rb_num,
  1866.                                      u32 enabled_rb_mask);
  1867.  
  1868. /*
  1869.  * evergreen functions used by radeon_encoder.c
  1870.  */
  1871.  
  1872. extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  1873.  
  1874. extern int ni_init_microcode(struct radeon_device *rdev);
  1875. extern int ni_mc_load_microcode(struct radeon_device *rdev);
  1876.  
  1877. /* radeon_acpi.c */
  1878. #if defined(CONFIG_ACPI)
  1879. extern int radeon_acpi_init(struct radeon_device *rdev);
  1880. extern void radeon_acpi_fini(struct radeon_device *rdev);
  1881. #else
  1882. static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
  1883. static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
  1884. #endif
  1885.  
  1886. #include "radeon_object.h"
  1887.  
  1888. #define DRM_UDELAY(d)           udelay(d)
  1889.  
  1890. resource_size_t
  1891. drm_get_resource_start(struct drm_device *dev, unsigned int resource);
  1892. resource_size_t
  1893. drm_get_resource_len(struct drm_device *dev, unsigned int resource);
  1894.  
  1895. bool set_mode(struct drm_device *dev, struct drm_connector *connector,
  1896.               videomode_t *mode, bool strict);
  1897.  
  1898.  
  1899.  
  1900. #define radeon_ttm_set_active_vram_size(a, b)
  1901.  
  1902. #endif
  1903.