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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30.  
  31. /* TODO: Here are things that needs to be done :
  32.  *      - surface allocator & initializer : (bit like scratch reg) should
  33.  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34.  *        related to surface
  35.  *      - WB : write back stuff (do it bit like scratch reg things)
  36.  *      - Vblank : look at Jesse's rework and what we should do
  37.  *      - r600/r700: gart & cp
  38.  *      - cs : clean cs ioctl use bitmap & things like that.
  39.  *      - power management stuff
  40.  *      - Barrier in gart code
  41.  *      - Unmappabled vram ?
  42.  *      - TESTING, TESTING, TESTING
  43.  */
  44.  
  45. /* Initialization path:
  46.  *  We expect that acceleration initialization might fail for various
  47.  *  reasons even thought we work hard to make it works on most
  48.  *  configurations. In order to still have a working userspace in such
  49.  *  situation the init path must succeed up to the memory controller
  50.  *  initialization point. Failure before this point are considered as
  51.  *  fatal error. Here is the init callchain :
  52.  *      radeon_device_init  perform common structure, mutex initialization
  53.  *      asic_init           setup the GPU memory layout and perform all
  54.  *                          one time initialization (failure in this
  55.  *                          function are considered fatal)
  56.  *      asic_startup        setup the GPU acceleration, in order to
  57.  *                          follow guideline the first thing this
  58.  *                          function should do is setting the GPU
  59.  *                          memory controller (only MC setup failure
  60.  *                          are considered as fatal)
  61.  */
  62.  
  63. #include <asm/atomic.h>
  64.  
  65. #include <linux/list.h>
  66. #include <linux/kref.h>
  67.  
  68. #include <ttm/ttm_bo_api.h>
  69. #include <ttm/ttm_bo_driver.h>
  70. #include <ttm/ttm_placement.h>
  71. #include <ttm/ttm_module.h>
  72.  
  73. #include <linux/irqreturn.h>
  74. #include <pci.h>
  75.  
  76. #include <errno-base.h>
  77. #include "drm_edid.h"
  78.  
  79. #include "radeon_family.h"
  80. #include "radeon_mode.h"
  81. #include "radeon_reg.h"
  82.  
  83. #include <syscall.h>
  84.  
  85. extern unsigned long volatile jiffies;
  86.  
  87. /*
  88.  * Modules parameters.
  89.  */
  90. extern int radeon_no_wb;
  91. extern int radeon_modeset;
  92. extern int radeon_dynclks;
  93. extern int radeon_r4xx_atom;
  94. extern int radeon_agpmode;
  95. extern int radeon_vram_limit;
  96. extern int radeon_gart_size;
  97. extern int radeon_benchmarking;
  98. extern int radeon_testing;
  99. extern int radeon_connector_table;
  100. extern int radeon_tv;
  101. extern int radeon_audio;
  102. extern int radeon_disp_priority;
  103. extern int radeon_hw_i2c;
  104. extern int radeon_pcie_gen2;
  105. typedef struct pm_message {
  106.     int event;
  107. } pm_message_t;
  108.  
  109. typedef struct
  110. {
  111.   int width;
  112.   int height;
  113.   int bpp;
  114.   int freq;
  115. }videomode_t;
  116.  
  117. static inline uint8_t __raw_readb(const volatile void __iomem *addr)
  118. {
  119.     return *(const volatile uint8_t __force *) addr;
  120. }
  121.  
  122. static inline uint16_t __raw_readw(const volatile void __iomem *addr)
  123. {
  124.     return *(const volatile uint16_t __force *) addr;
  125. }
  126.  
  127. static inline uint32_t __raw_readl(const volatile void __iomem *addr)
  128. {
  129.     return *(const volatile uint32_t __force *) addr;
  130. }
  131.  
  132. #define readb __raw_readb
  133. #define readw __raw_readw
  134. #define readl __raw_readl
  135.  
  136.  
  137.  
  138. static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
  139. {
  140.     *(volatile uint8_t __force *) addr = b;
  141. }
  142.  
  143. static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
  144. {
  145.     *(volatile uint16_t __force *) addr = b;
  146. }
  147.  
  148. static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
  149. {
  150.     *(volatile uint32_t __force *) addr = b;
  151. }
  152.  
  153. static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
  154. {
  155.         *(volatile __u64 *)addr = b;
  156. }
  157.  
  158. #define writeb __raw_writeb
  159. #define writew __raw_writew
  160. #define writel __raw_writel
  161. #define writeq __raw_writeq
  162.  
  163.  
  164. static inline u32 ioread32(const volatile void __iomem *addr)
  165. {
  166.     return in32((u32)addr);
  167. }
  168.  
  169. static inline void iowrite32(uint32_t b, volatile void __iomem *addr)
  170. {
  171.     out32((u32)addr, b);
  172. }
  173.  
  174. struct __wait_queue_head {
  175.         spinlock_t lock;
  176.         struct list_head task_list;
  177. };
  178. typedef struct __wait_queue_head wait_queue_head_t;
  179.  
  180.  
  181. /*
  182.  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  183.  * symbol;
  184.  */
  185. #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  186. #define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
  187. /* RADEON_IB_POOL_SIZE must be a power of 2 */
  188. #define RADEON_IB_POOL_SIZE             16
  189. #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  190. #define RADEONFB_CONN_LIMIT             4
  191. #define RADEON_BIOS_NUM_SCRATCH         8
  192.  
  193. /*
  194.  * Errata workarounds.
  195.  */
  196. enum radeon_pll_errata {
  197.     CHIP_ERRATA_R300_CG             = 0x00000001,
  198.     CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  199.     CHIP_ERRATA_PLL_DELAY           = 0x00000004
  200. };
  201.  
  202.  
  203. struct radeon_device;
  204.  
  205.  
  206. /*
  207.  * BIOS.
  208.  */
  209. #define ATRM_BIOS_PAGE 4096
  210.  
  211. #if defined(CONFIG_VGA_SWITCHEROO)
  212. bool radeon_atrm_supported(struct pci_dev *pdev);
  213. int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
  214. #else
  215. static inline bool radeon_atrm_supported(struct pci_dev *pdev)
  216. {
  217.         return false;
  218. }
  219.  
  220. static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
  221.         return -EINVAL;
  222. }
  223. #endif
  224. bool radeon_get_bios(struct radeon_device *rdev);
  225.  
  226.  
  227. /*
  228.  * Dummy page
  229.  */
  230. struct radeon_dummy_page {
  231.         struct page     *page;
  232.         dma_addr_t      addr;
  233. };
  234. int radeon_dummy_page_init(struct radeon_device *rdev);
  235. void radeon_dummy_page_fini(struct radeon_device *rdev);
  236.  
  237.  
  238. /*
  239.  * Clocks
  240.  */
  241. struct radeon_clock {
  242.         struct radeon_pll p1pll;
  243.         struct radeon_pll p2pll;
  244.         struct radeon_pll dcpll;
  245.         struct radeon_pll spll;
  246.         struct radeon_pll mpll;
  247.         /* 10 Khz units */
  248.         uint32_t default_mclk;
  249.         uint32_t default_sclk;
  250.         uint32_t default_dispclk;
  251.         uint32_t dp_extclk;
  252.         uint32_t max_pixel_clock;
  253. };
  254.  
  255. /*
  256.  * Power management
  257.  */
  258. int radeon_pm_init(struct radeon_device *rdev);
  259. void radeon_pm_fini(struct radeon_device *rdev);
  260. void radeon_pm_compute_clocks(struct radeon_device *rdev);
  261. void radeon_pm_suspend(struct radeon_device *rdev);
  262. void radeon_pm_resume(struct radeon_device *rdev);
  263. void radeon_combios_get_power_modes(struct radeon_device *rdev);
  264. void radeon_atombios_get_power_modes(struct radeon_device *rdev);
  265. void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
  266. int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
  267. void rs690_pm_info(struct radeon_device *rdev);
  268. extern int rv6xx_get_temp(struct radeon_device *rdev);
  269. extern int rv770_get_temp(struct radeon_device *rdev);
  270. extern int evergreen_get_temp(struct radeon_device *rdev);
  271. extern int sumo_get_temp(struct radeon_device *rdev);
  272.  
  273. /*
  274.  * Fences.
  275.  */
  276. struct radeon_fence_driver {
  277.         uint32_t                        scratch_reg;
  278.         atomic_t                        seq;
  279.         uint32_t                        last_seq;
  280.         unsigned long                   last_jiffies;
  281.         unsigned long                   last_timeout;
  282.         wait_queue_head_t               queue;
  283.         rwlock_t                        lock;
  284.         struct list_head                created;
  285.         struct list_head                emited;
  286.         struct list_head                signaled;
  287.         bool                            initialized;
  288. };
  289.  
  290. struct radeon_fence {
  291.         struct radeon_device            *rdev;
  292.         struct kref                     kref;
  293.         struct list_head                list;
  294.         /* protected by radeon_fence.lock */
  295.         uint32_t                        seq;
  296.         bool                            emited;
  297.         bool                            signaled;
  298.     evhandle_t              evnt;
  299. };
  300.  
  301. int radeon_fence_driver_init(struct radeon_device *rdev);
  302. void radeon_fence_driver_fini(struct radeon_device *rdev);
  303. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
  304. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
  305. void radeon_fence_process(struct radeon_device *rdev);
  306. bool radeon_fence_signaled(struct radeon_fence *fence);
  307. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  308. int radeon_fence_wait_next(struct radeon_device *rdev);
  309. int radeon_fence_wait_last(struct radeon_device *rdev);
  310. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  311. void radeon_fence_unref(struct radeon_fence **fence);
  312.  
  313. /*
  314.  * Tiling registers
  315.  */
  316. struct radeon_surface_reg {
  317.         struct radeon_bo *bo;
  318. };
  319.  
  320. #define RADEON_GEM_MAX_SURFACES 8
  321.  
  322. /*
  323.  * TTM.
  324.  */
  325. struct radeon_mman {
  326.         struct ttm_bo_global_ref        bo_global_ref;
  327. //      struct drm_global_reference     mem_global_ref;
  328.         struct ttm_bo_device            bdev;
  329.         bool                            mem_global_referenced;
  330.         bool                            initialized;
  331. };
  332.  
  333. struct radeon_bo {
  334.         /* Protected by gem.mutex */
  335.         struct list_head                list;
  336.         /* Protected by tbo.reserved */
  337.         u32                             placements[3];
  338.         struct ttm_placement            placement;
  339.         struct ttm_buffer_object        tbo;
  340.         struct ttm_bo_kmap_obj          kmap;
  341.     unsigned                    pin_count;
  342.     void                       *kptr;
  343.     u32                         cpu_addr;
  344.     u32                         tiling_flags;
  345.     u32                         pitch;
  346.     int                         surface_reg;
  347.         /* Constant after initialization */
  348.         struct radeon_device            *rdev;
  349.         struct drm_gem_object           gem_base;
  350.     u32                          domain;
  351. };
  352. #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
  353.  
  354. struct radeon_bo_list {
  355.         struct radeon_bo        *bo;
  356.         uint64_t                gpu_offset;
  357.         unsigned                rdomain;
  358.         unsigned                wdomain;
  359.         u32                     tiling_flags;
  360. };
  361.  
  362. /*
  363.  * GEM objects.
  364.  */
  365. struct radeon_gem {
  366.         struct mutex            mutex;
  367.         struct list_head        objects;
  368. };
  369.  
  370. int radeon_gem_init(struct radeon_device *rdev);
  371. void radeon_gem_fini(struct radeon_device *rdev);
  372. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  373.                              int alignment, int initial_domain,
  374.                              bool discardable, bool kernel,
  375.                              struct drm_gem_object **obj);
  376. int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
  377.                           uint64_t *gpu_addr);
  378. void radeon_gem_object_unpin(struct drm_gem_object *obj);
  379.  
  380. int radeon_mode_dumb_create(struct drm_file *file_priv,
  381.                             struct drm_device *dev,
  382.                             struct drm_mode_create_dumb *args);
  383. int radeon_mode_dumb_mmap(struct drm_file *filp,
  384.                           struct drm_device *dev,
  385.                           uint32_t handle, uint64_t *offset_p);
  386. int radeon_mode_dumb_destroy(struct drm_file *file_priv,
  387.                              struct drm_device *dev,
  388.                              uint32_t handle);
  389.  
  390. /*
  391.  * GART structures, functions & helpers
  392.  */
  393. struct radeon_mc;
  394.  
  395. struct radeon_gart_table_ram {
  396.     volatile uint32_t       *ptr;
  397. };
  398.  
  399. struct radeon_gart_table_vram {
  400.         struct radeon_bo                *robj;
  401.     volatile uint32_t       *ptr;
  402. };
  403.  
  404. union radeon_gart_table {
  405.     struct radeon_gart_table_ram    ram;
  406.     struct radeon_gart_table_vram   vram;
  407. };
  408.  
  409. #define RADEON_GPU_PAGE_SIZE 4096
  410. #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
  411.  
  412. struct radeon_gart {
  413.     dma_addr_t          table_addr;
  414.     unsigned            num_gpu_pages;
  415.     unsigned            num_cpu_pages;
  416.     unsigned            table_size;
  417.     union radeon_gart_table     table;
  418.     struct page         **pages;
  419.     dma_addr_t          *pages_addr;
  420.         bool                            *ttm_alloced;
  421.     bool                ready;
  422. };
  423.  
  424. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  425. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  426. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  427. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  428. int radeon_gart_init(struct radeon_device *rdev);
  429. void radeon_gart_fini(struct radeon_device *rdev);
  430. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  431.                         int pages);
  432. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  433.             int pages, u32_t *pagelist);
  434.  
  435.  
  436. /*
  437.  * GPU MC structures, functions & helpers
  438.  */
  439. struct radeon_mc {
  440.     resource_size_t     aper_size;
  441.     resource_size_t     aper_base;
  442.     resource_size_t     agp_base;
  443.         /* for some chips with <= 32MB we need to lie
  444.          * about vram size near mc fb location */
  445.         u64                     mc_vram_size;
  446.         u64                     visible_vram_size;
  447.         u64                     gtt_size;
  448.         u64                     gtt_start;
  449.         u64                     gtt_end;
  450.         u64                     vram_start;
  451.         u64                     vram_end;
  452.     unsigned            vram_width;
  453.         u64                     real_vram_size;
  454.     int                 vram_mtrr;
  455.     bool                vram_is_ddr;
  456.         bool                    igp_sideport_enabled;
  457.         u64                     gtt_base_align;
  458. };
  459.  
  460. bool radeon_combios_sideport_present(struct radeon_device *rdev);
  461. bool radeon_atombios_sideport_present(struct radeon_device *rdev);
  462.  
  463. /*
  464.  * GPU scratch registers structures, functions & helpers
  465.  */
  466. struct radeon_scratch {
  467.     unsigned        num_reg;
  468.         uint32_t                reg_base;
  469.     bool            free[32];
  470.     uint32_t        reg[32];
  471. };
  472.  
  473. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  474. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  475.  
  476.  
  477. /*
  478.  * IRQS.
  479.  */
  480. struct r500_irq_stat_regs {
  481.         u32 disp_int;
  482. };
  483.  
  484. struct r600_irq_stat_regs {
  485.         u32 disp_int;
  486.         u32 disp_int_cont;
  487.         u32 disp_int_cont2;
  488.         u32 d1grph_int;
  489.         u32 d2grph_int;
  490. };
  491.  
  492. struct evergreen_irq_stat_regs {
  493.         u32 disp_int;
  494.         u32 disp_int_cont;
  495.         u32 disp_int_cont2;
  496.         u32 disp_int_cont3;
  497.         u32 disp_int_cont4;
  498.         u32 disp_int_cont5;
  499.         u32 d1grph_int;
  500.         u32 d2grph_int;
  501.         u32 d3grph_int;
  502.         u32 d4grph_int;
  503.         u32 d5grph_int;
  504.         u32 d6grph_int;
  505. };
  506.  
  507. union radeon_irq_stat_regs {
  508.         struct r500_irq_stat_regs r500;
  509.         struct r600_irq_stat_regs r600;
  510.         struct evergreen_irq_stat_regs evergreen;
  511. };
  512.  
  513. struct radeon_irq {
  514.         bool            installed;
  515.         bool            sw_int;
  516.         /* FIXME: use a define max crtc rather than hardcode it */
  517.         bool            crtc_vblank_int[6];
  518.         bool            pflip[6];
  519.     wait_queue_head_t   vblank_queue;
  520.         /* FIXME: use defines for max hpd/dacs */
  521.         bool            hpd[6];
  522.         bool            gui_idle;
  523.         bool            gui_idle_acked;
  524.    wait_queue_head_t   idle_queue;
  525.         /* FIXME: use defines for max HDMI blocks */
  526.         bool            hdmi[2];
  527.     spinlock_t  sw_lock;
  528.         int sw_refcount;
  529.         union radeon_irq_stat_regs stat_regs;
  530.         spinlock_t pflip_lock[6];
  531.         int pflip_refcount[6];
  532. };
  533.  
  534. int radeon_irq_kms_init(struct radeon_device *rdev);
  535. void radeon_irq_kms_fini(struct radeon_device *rdev);
  536. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
  537. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
  538. void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
  539. void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
  540.  
  541. /*
  542.  * CP & ring.
  543.  */
  544. struct radeon_ib {
  545.     struct list_head    list;
  546.         unsigned                idx;
  547.     uint64_t            gpu_addr;
  548.         struct radeon_fence     *fence;
  549.     uint32_t            *ptr;
  550.     uint32_t            length_dw;
  551.         bool                    free;
  552. };
  553.  
  554. /*
  555.  * locking -
  556.  * mutex protects scheduled_ibs, ready, alloc_bm
  557.  */
  558. struct radeon_ib_pool {
  559.         struct mutex            mutex;
  560.         struct radeon_bo        *robj;
  561.         struct list_head        bogus_ib;
  562.         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
  563.     bool                ready;
  564.         unsigned                head_id;
  565. };
  566.  
  567. struct radeon_cp {
  568.         struct radeon_bo        *ring_obj;
  569.         volatile uint32_t       *ring;
  570.     unsigned            rptr;
  571.     unsigned            wptr;
  572.     unsigned            wptr_old;
  573.     unsigned            ring_size;
  574.     unsigned            ring_free_dw;
  575.     int                 count_dw;
  576.     uint64_t            gpu_addr;
  577.     uint32_t            align_mask;
  578.     uint32_t            ptr_mask;
  579.         struct mutex            mutex;
  580.     bool                ready;
  581. };
  582.  
  583. /*
  584.  * R6xx+ IH ring
  585.  */
  586. struct r600_ih {
  587.         struct radeon_bo        *ring_obj;
  588.         volatile uint32_t       *ring;
  589.     unsigned            rptr;
  590.     unsigned            wptr;
  591.     unsigned            wptr_old;
  592.     unsigned            ring_size;
  593.     uint64_t            gpu_addr;
  594.     uint32_t            ptr_mask;
  595.     spinlock_t              lock;
  596.     bool                enabled;
  597. };
  598.  
  599. struct r600_blit {
  600.         struct mutex            mutex;
  601.         struct radeon_bo        *shader_obj;
  602.         u64 shader_gpu_addr;
  603.         u32 vs_offset, ps_offset;
  604.         u32 state_offset;
  605.         u32 state_len;
  606.         u32 vb_used, vb_total;
  607.         struct radeon_ib *vb_ib;
  608. };
  609.  
  610. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
  611. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
  612. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
  613. int radeon_ib_pool_init(struct radeon_device *rdev);
  614. void radeon_ib_pool_fini(struct radeon_device *rdev);
  615. int radeon_ib_test(struct radeon_device *rdev);
  616. extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
  617. /* Ring access between begin & end cannot sleep */
  618. void radeon_ring_free_size(struct radeon_device *rdev);
  619. int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
  620. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
  621. void radeon_ring_commit(struct radeon_device *rdev);
  622. void radeon_ring_unlock_commit(struct radeon_device *rdev);
  623. void radeon_ring_unlock_undo(struct radeon_device *rdev);
  624. int radeon_ring_test(struct radeon_device *rdev);
  625. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
  626. void radeon_ring_fini(struct radeon_device *rdev);
  627.  
  628.  
  629. /*
  630.  * CS.
  631.  */
  632. struct radeon_cs_reloc {
  633. //      struct drm_gem_object           *gobj;
  634.         struct radeon_bo                *robj;
  635.         struct radeon_bo_list           lobj;
  636.     uint32_t                handle;
  637.     uint32_t                flags;
  638. };
  639.  
  640. struct radeon_cs_chunk {
  641.         uint32_t                chunk_id;
  642.         uint32_t                length_dw;
  643.         int kpage_idx[2];
  644.         uint32_t                *kpage[2];
  645.         uint32_t                *kdata;
  646.         void __user *user_ptr;
  647.         int last_copied_page;
  648.         int last_page_index;
  649. };
  650.  
  651. struct radeon_cs_parser {
  652.         struct device           *dev;
  653.         struct radeon_device    *rdev;
  654.         struct drm_file         *filp;
  655.         /* chunks */
  656.         unsigned                nchunks;
  657.         struct radeon_cs_chunk  *chunks;
  658.         uint64_t                *chunks_array;
  659.         /* IB */
  660.         unsigned                idx;
  661.         /* relocations */
  662.         unsigned                nrelocs;
  663.         struct radeon_cs_reloc  *relocs;
  664.         struct radeon_cs_reloc  **relocs_ptr;
  665.         struct list_head        validated;
  666.         /* indices of various chunks */
  667.         int                     chunk_ib_idx;
  668.         int                     chunk_relocs_idx;
  669.         struct radeon_ib        *ib;
  670.         void                    *track;
  671.         unsigned                family;
  672.         int parser_error;
  673. };
  674.  
  675. extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
  676. extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
  677.  
  678.  
  679. static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  680. {
  681.         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  682.         u32 pg_idx, pg_offset;
  683.         u32 idx_value = 0;
  684.         int new_page;
  685.  
  686.         pg_idx = (idx * 4) / PAGE_SIZE;
  687.         pg_offset = (idx * 4) % PAGE_SIZE;
  688.  
  689.         if (ibc->kpage_idx[0] == pg_idx)
  690.                 return ibc->kpage[0][pg_offset/4];
  691.         if (ibc->kpage_idx[1] == pg_idx)
  692.                 return ibc->kpage[1][pg_offset/4];
  693.  
  694.         new_page = radeon_cs_update_pages(p, pg_idx);
  695.         if (new_page < 0) {
  696.                 p->parser_error = new_page;
  697.                 return 0;
  698.         }
  699.  
  700.         idx_value = ibc->kpage[new_page][pg_offset/4];
  701.         return idx_value;
  702. }
  703.  
  704. struct radeon_cs_packet {
  705.         unsigned        idx;
  706.         unsigned        type;
  707.         unsigned        reg;
  708.         unsigned        opcode;
  709.         int             count;
  710.         unsigned        one_reg_wr;
  711. };
  712.  
  713. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  714.                                       struct radeon_cs_packet *pkt,
  715.                                       unsigned idx, unsigned reg);
  716. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  717.                                       struct radeon_cs_packet *pkt);
  718.  
  719.  
  720. /*
  721.  * AGP
  722.  */
  723. int radeon_agp_init(struct radeon_device *rdev);
  724. void radeon_agp_resume(struct radeon_device *rdev);
  725. void radeon_agp_suspend(struct radeon_device *rdev);
  726. void radeon_agp_fini(struct radeon_device *rdev);
  727.  
  728.  
  729. /*
  730.  * Writeback
  731.  */
  732. struct radeon_wb {
  733.         struct radeon_bo        *wb_obj;
  734.         volatile uint32_t       *wb;
  735.         uint64_t                gpu_addr;
  736.         bool                    enabled;
  737.         bool                    use_event;
  738. };
  739.  
  740. #define RADEON_WB_SCRATCH_OFFSET 0
  741. #define RADEON_WB_CP_RPTR_OFFSET 1024
  742. #define RADEON_WB_CP1_RPTR_OFFSET 1280
  743. #define RADEON_WB_CP2_RPTR_OFFSET 1536
  744. #define R600_WB_IH_WPTR_OFFSET   2048
  745. #define R600_WB_EVENT_OFFSET     3072
  746.  
  747. /**
  748.  * struct radeon_pm - power management datas
  749.  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
  750.  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  751.  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
  752.  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
  753.  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
  754.  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
  755.  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  756.  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
  757.  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
  758.  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
  759.  * @needed_bandwidth:   current bandwidth needs
  760.  *
  761.  * It keeps track of various data needed to take powermanagement decision.
  762.  * Bandwidth need is used to determine minimun clock of the GPU and memory.
  763.  * Equation between gpu/memory clock and available bandwidth is hw dependent
  764.  * (type of memory, bus size, efficiency, ...)
  765.  */
  766.  
  767. enum radeon_pm_method {
  768.         PM_METHOD_PROFILE,
  769.         PM_METHOD_DYNPM,
  770. };
  771.  
  772. enum radeon_dynpm_state {
  773.         DYNPM_STATE_DISABLED,
  774.         DYNPM_STATE_MINIMUM,
  775.         DYNPM_STATE_PAUSED,
  776.         DYNPM_STATE_ACTIVE,
  777.         DYNPM_STATE_SUSPENDED,
  778. };
  779. enum radeon_dynpm_action {
  780.         DYNPM_ACTION_NONE,
  781.         DYNPM_ACTION_MINIMUM,
  782.         DYNPM_ACTION_DOWNCLOCK,
  783.         DYNPM_ACTION_UPCLOCK,
  784.         DYNPM_ACTION_DEFAULT
  785. };
  786.  
  787. enum radeon_voltage_type {
  788.         VOLTAGE_NONE = 0,
  789.         VOLTAGE_GPIO,
  790.         VOLTAGE_VDDC,
  791.         VOLTAGE_SW
  792. };
  793.  
  794. enum radeon_pm_state_type {
  795.         POWER_STATE_TYPE_DEFAULT,
  796.         POWER_STATE_TYPE_POWERSAVE,
  797.         POWER_STATE_TYPE_BATTERY,
  798.         POWER_STATE_TYPE_BALANCED,
  799.         POWER_STATE_TYPE_PERFORMANCE,
  800. };
  801.  
  802. enum radeon_pm_profile_type {
  803.         PM_PROFILE_DEFAULT,
  804.         PM_PROFILE_AUTO,
  805.         PM_PROFILE_LOW,
  806.         PM_PROFILE_MID,
  807.         PM_PROFILE_HIGH,
  808. };
  809.  
  810. #define PM_PROFILE_DEFAULT_IDX 0
  811. #define PM_PROFILE_LOW_SH_IDX  1
  812. #define PM_PROFILE_MID_SH_IDX  2
  813. #define PM_PROFILE_HIGH_SH_IDX 3
  814. #define PM_PROFILE_LOW_MH_IDX  4
  815. #define PM_PROFILE_MID_MH_IDX  5
  816. #define PM_PROFILE_HIGH_MH_IDX 6
  817. #define PM_PROFILE_MAX         7
  818.  
  819. struct radeon_pm_profile {
  820.         int dpms_off_ps_idx;
  821.         int dpms_on_ps_idx;
  822.         int dpms_off_cm_idx;
  823.         int dpms_on_cm_idx;
  824. };
  825.  
  826. enum radeon_int_thermal_type {
  827.         THERMAL_TYPE_NONE,
  828.         THERMAL_TYPE_RV6XX,
  829.         THERMAL_TYPE_RV770,
  830.         THERMAL_TYPE_EVERGREEN,
  831.         THERMAL_TYPE_SUMO,
  832.         THERMAL_TYPE_NI,
  833. };
  834.  
  835. struct radeon_voltage {
  836.         enum radeon_voltage_type type;
  837.         /* gpio voltage */
  838.         struct radeon_gpio_rec gpio;
  839.         u32 delay; /* delay in usec from voltage drop to sclk change */
  840.         bool active_high; /* voltage drop is active when bit is high */
  841.         /* VDDC voltage */
  842.         u8 vddc_id; /* index into vddc voltage table */
  843.         u8 vddci_id; /* index into vddci voltage table */
  844.         bool vddci_enabled;
  845.         /* r6xx+ sw */
  846.         u16 voltage;
  847.         /* evergreen+ vddci */
  848.         u16 vddci;
  849. };
  850.  
  851. /* clock mode flags */
  852. #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
  853.  
  854. struct radeon_pm_clock_info {
  855.         /* memory clock */
  856.         u32 mclk;
  857.         /* engine clock */
  858.         u32 sclk;
  859.         /* voltage info */
  860.         struct radeon_voltage voltage;
  861.         /* standardized clock flags */
  862.         u32 flags;
  863. };
  864.  
  865. /* state flags */
  866. #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
  867.  
  868. struct radeon_power_state {
  869.         enum radeon_pm_state_type type;
  870.         /* XXX: use a define for num clock modes */
  871.         struct radeon_pm_clock_info clock_info[8];
  872.         /* number of valid clock modes in this power state */
  873.         int num_clock_modes;
  874.         struct radeon_pm_clock_info *default_clock_mode;
  875.         /* standardized state flags */
  876.         u32 flags;
  877.         u32 misc; /* vbios specific flags */
  878.         u32 misc2; /* vbios specific flags */
  879.         int pcie_lanes; /* pcie lanes */
  880. };
  881.  
  882. /*
  883.  * Some modes are overclocked by very low value, accept them
  884.  */
  885. #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
  886.  
  887. struct radeon_pm {
  888.         struct mutex            mutex;
  889.         u32                     active_crtcs;
  890.         int                     active_crtc_count;
  891.         int                     req_vblank;
  892.         bool                    vblank_sync;
  893.         bool                    gui_idle;
  894.         fixed20_12              max_bandwidth;
  895.         fixed20_12              igp_sideport_mclk;
  896.         fixed20_12              igp_system_mclk;
  897.         fixed20_12              igp_ht_link_clk;
  898.         fixed20_12              igp_ht_link_width;
  899.         fixed20_12              k8_bandwidth;
  900.         fixed20_12              sideport_bandwidth;
  901.         fixed20_12              ht_bandwidth;
  902.         fixed20_12              core_bandwidth;
  903.         fixed20_12              sclk;
  904.         fixed20_12              mclk;
  905.         fixed20_12              needed_bandwidth;
  906.         struct radeon_power_state *power_state;
  907.         /* number of valid power states */
  908.         int                     num_power_states;
  909.         int                     current_power_state_index;
  910.         int                     current_clock_mode_index;
  911.         int                     requested_power_state_index;
  912.         int                     requested_clock_mode_index;
  913.         int                     default_power_state_index;
  914.         u32                     current_sclk;
  915.         u32                     current_mclk;
  916.         u16                     current_vddc;
  917.         u16                     current_vddci;
  918.         u32                     default_sclk;
  919.         u32                     default_mclk;
  920.         u16                     default_vddc;
  921.         u16                     default_vddci;
  922.         struct radeon_i2c_chan *i2c_bus;
  923.         /* selected pm method */
  924.         enum radeon_pm_method     pm_method;
  925.         /* dynpm power management */
  926. //   struct delayed_work dynpm_idle_work;
  927.         enum radeon_dynpm_state dynpm_state;
  928.         enum radeon_dynpm_action        dynpm_planned_action;
  929.         unsigned long           dynpm_action_timeout;
  930.         bool                    dynpm_can_upclock;
  931.         bool                    dynpm_can_downclock;
  932.         /* profile-based power management */
  933.         enum radeon_pm_profile_type profile;
  934.         int                     profile_index;
  935.         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
  936.         /* internal thermal controller on rv6xx+ */
  937.         enum radeon_int_thermal_type int_thermal_type;
  938.         struct device           *int_hwmon_dev;
  939. };
  940.  
  941. /*
  942.  * ASIC specific functions.
  943.  */
  944. struct radeon_asic {
  945.         int (*init)(struct radeon_device *rdev);
  946.         void (*fini)(struct radeon_device *rdev);
  947.         int (*resume)(struct radeon_device *rdev);
  948.         int (*suspend)(struct radeon_device *rdev);
  949.         void (*vga_set_state)(struct radeon_device *rdev, bool state);
  950.         bool (*gpu_is_lockup)(struct radeon_device *rdev);
  951.         int (*asic_reset)(struct radeon_device *rdev);
  952.         void (*gart_tlb_flush)(struct radeon_device *rdev);
  953.         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  954.         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
  955.         void (*cp_fini)(struct radeon_device *rdev);
  956.         void (*cp_disable)(struct radeon_device *rdev);
  957.         void (*cp_commit)(struct radeon_device *rdev);
  958.         void (*ring_start)(struct radeon_device *rdev);
  959.         int (*ring_test)(struct radeon_device *rdev);
  960.         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  961.         int (*irq_set)(struct radeon_device *rdev);
  962.         int (*irq_process)(struct radeon_device *rdev);
  963.         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  964.         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
  965.         int (*cs_parse)(struct radeon_cs_parser *p);
  966.         int (*copy_blit)(struct radeon_device *rdev,
  967.                          uint64_t src_offset,
  968.                          uint64_t dst_offset,
  969.                          unsigned num_pages,
  970.                          struct radeon_fence *fence);
  971.         int (*copy_dma)(struct radeon_device *rdev,
  972.                         uint64_t src_offset,
  973.                         uint64_t dst_offset,
  974.                         unsigned num_pages,
  975.                         struct radeon_fence *fence);
  976.         int (*copy)(struct radeon_device *rdev,
  977.                     uint64_t src_offset,
  978.                     uint64_t dst_offset,
  979.                     unsigned num_pages,
  980.                     struct radeon_fence *fence);
  981.         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
  982.         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  983.         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
  984.         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  985.         int (*get_pcie_lanes)(struct radeon_device *rdev);
  986.         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  987.         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  988.         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
  989.                                uint32_t tiling_flags, uint32_t pitch,
  990.                                uint32_t offset, uint32_t obj_size);
  991.         void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
  992.         void (*bandwidth_update)(struct radeon_device *rdev);
  993.         void (*hpd_init)(struct radeon_device *rdev);
  994.         void (*hpd_fini)(struct radeon_device *rdev);
  995.         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  996.         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  997.         /* ioctl hw specific callback. Some hw might want to perform special
  998.          * operation on specific ioctl. For instance on wait idle some hw
  999.          * might want to perform and HDP flush through MMIO as it seems that
  1000.          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
  1001.          * through ring.
  1002.          */
  1003.         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
  1004.         bool (*gui_idle)(struct radeon_device *rdev);
  1005.         /* power management */
  1006.         void (*pm_misc)(struct radeon_device *rdev);
  1007.         void (*pm_prepare)(struct radeon_device *rdev);
  1008.         void (*pm_finish)(struct radeon_device *rdev);
  1009.         void (*pm_init_profile)(struct radeon_device *rdev);
  1010.         void (*pm_get_dynpm_state)(struct radeon_device *rdev);
  1011.         /* pageflipping */
  1012.         void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
  1013.         u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
  1014.         void (*post_page_flip)(struct radeon_device *rdev, int crtc);
  1015. };
  1016.  
  1017. /*
  1018.  * Asic structures
  1019.  */
  1020. struct r100_gpu_lockup {
  1021.         unsigned long   last_jiffies;
  1022.         u32             last_cp_rptr;
  1023. };
  1024.  
  1025. struct r100_asic {
  1026.         const unsigned  *reg_safe_bm;
  1027.         unsigned        reg_safe_bm_size;
  1028.         u32             hdp_cntl;
  1029.         struct r100_gpu_lockup  lockup;
  1030. };
  1031.  
  1032. struct r300_asic {
  1033.         const unsigned  *reg_safe_bm;
  1034.         unsigned        reg_safe_bm_size;
  1035.         u32             resync_scratch;
  1036.         u32             hdp_cntl;
  1037.         struct r100_gpu_lockup  lockup;
  1038. };
  1039.  
  1040. struct r600_asic {
  1041.         unsigned max_pipes;
  1042.         unsigned max_tile_pipes;
  1043.         unsigned max_simds;
  1044.         unsigned max_backends;
  1045.         unsigned max_gprs;
  1046.         unsigned max_threads;
  1047.         unsigned max_stack_entries;
  1048.         unsigned max_hw_contexts;
  1049.         unsigned max_gs_threads;
  1050.         unsigned sx_max_export_size;
  1051.         unsigned sx_max_export_pos_size;
  1052.         unsigned sx_max_export_smx_size;
  1053.         unsigned sq_num_cf_insts;
  1054.         unsigned tiling_nbanks;
  1055.         unsigned tiling_npipes;
  1056.         unsigned tiling_group_size;
  1057.         unsigned                tile_config;
  1058.         struct r100_gpu_lockup  lockup;
  1059. };
  1060.  
  1061. struct rv770_asic {
  1062.         unsigned max_pipes;
  1063.         unsigned max_tile_pipes;
  1064.         unsigned max_simds;
  1065.         unsigned max_backends;
  1066.         unsigned max_gprs;
  1067.         unsigned max_threads;
  1068.         unsigned max_stack_entries;
  1069.         unsigned max_hw_contexts;
  1070.         unsigned max_gs_threads;
  1071.         unsigned sx_max_export_size;
  1072.         unsigned sx_max_export_pos_size;
  1073.         unsigned sx_max_export_smx_size;
  1074.         unsigned sq_num_cf_insts;
  1075.         unsigned sx_num_of_sets;
  1076.         unsigned sc_prim_fifo_size;
  1077.         unsigned sc_hiz_tile_fifo_size;
  1078.         unsigned sc_earlyz_tile_fifo_fize;
  1079.         unsigned tiling_nbanks;
  1080.         unsigned tiling_npipes;
  1081.         unsigned tiling_group_size;
  1082.         unsigned                tile_config;
  1083.         struct r100_gpu_lockup  lockup;
  1084. };
  1085.  
  1086. struct evergreen_asic {
  1087.         unsigned num_ses;
  1088.         unsigned max_pipes;
  1089.         unsigned max_tile_pipes;
  1090.         unsigned max_simds;
  1091.         unsigned max_backends;
  1092.         unsigned max_gprs;
  1093.         unsigned max_threads;
  1094.         unsigned max_stack_entries;
  1095.         unsigned max_hw_contexts;
  1096.         unsigned max_gs_threads;
  1097.         unsigned sx_max_export_size;
  1098.         unsigned sx_max_export_pos_size;
  1099.         unsigned sx_max_export_smx_size;
  1100.         unsigned sq_num_cf_insts;
  1101.         unsigned sx_num_of_sets;
  1102.         unsigned sc_prim_fifo_size;
  1103.         unsigned sc_hiz_tile_fifo_size;
  1104.         unsigned sc_earlyz_tile_fifo_size;
  1105.         unsigned tiling_nbanks;
  1106.         unsigned tiling_npipes;
  1107.         unsigned tiling_group_size;
  1108.         unsigned tile_config;
  1109.         struct r100_gpu_lockup  lockup;
  1110. };
  1111.  
  1112. struct cayman_asic {
  1113.         unsigned max_shader_engines;
  1114.         unsigned max_pipes_per_simd;
  1115.         unsigned max_tile_pipes;
  1116.         unsigned max_simds_per_se;
  1117.         unsigned max_backends_per_se;
  1118.         unsigned max_texture_channel_caches;
  1119.         unsigned max_gprs;
  1120.         unsigned max_threads;
  1121.         unsigned max_gs_threads;
  1122.         unsigned max_stack_entries;
  1123.         unsigned sx_num_of_sets;
  1124.         unsigned sx_max_export_size;
  1125.         unsigned sx_max_export_pos_size;
  1126.         unsigned sx_max_export_smx_size;
  1127.         unsigned max_hw_contexts;
  1128.         unsigned sq_num_cf_insts;
  1129.         unsigned sc_prim_fifo_size;
  1130.         unsigned sc_hiz_tile_fifo_size;
  1131.         unsigned sc_earlyz_tile_fifo_size;
  1132.  
  1133.         unsigned num_shader_engines;
  1134.         unsigned num_shader_pipes_per_simd;
  1135.         unsigned num_tile_pipes;
  1136.         unsigned num_simds_per_se;
  1137.         unsigned num_backends_per_se;
  1138.         unsigned backend_disable_mask_per_asic;
  1139.         unsigned backend_map;
  1140.         unsigned num_texture_channel_caches;
  1141.         unsigned mem_max_burst_length_bytes;
  1142.         unsigned mem_row_size_in_kb;
  1143.         unsigned shader_engine_tile_size;
  1144.         unsigned num_gpus;
  1145.         unsigned multi_gpu_tile_size;
  1146.  
  1147.         unsigned tile_config;
  1148.         struct r100_gpu_lockup  lockup;
  1149. };
  1150.  
  1151. union radeon_asic_config {
  1152.         struct r300_asic        r300;
  1153.         struct r100_asic        r100;
  1154.         struct r600_asic        r600;
  1155.         struct rv770_asic       rv770;
  1156.         struct evergreen_asic   evergreen;
  1157.         struct cayman_asic      cayman;
  1158. };
  1159.  
  1160. /*
  1161.  * asic initizalization from radeon_asic.c
  1162.  */
  1163. void radeon_agp_disable(struct radeon_device *rdev);
  1164. int radeon_asic_init(struct radeon_device *rdev);
  1165.  
  1166.  
  1167.  
  1168. /* VRAM scratch page for HDP bug */
  1169. struct r700_vram_scratch {
  1170.         struct radeon_bo                *robj;
  1171.         volatile uint32_t               *ptr;
  1172. };
  1173.  
  1174. /*
  1175.  * Core structure, functions and helpers.
  1176.  */
  1177. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  1178. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  1179.  
  1180. struct radeon_device {
  1181.         struct device                   *dev;
  1182.     struct drm_device          *ddev;
  1183.     struct pci_dev             *pdev;
  1184.     /* ASIC */
  1185.     union radeon_asic_config    config;
  1186.     enum radeon_family          family;
  1187.     unsigned long               flags;
  1188.     int                         usec_timeout;
  1189.     enum radeon_pll_errata      pll_errata;
  1190.     int                         num_gb_pipes;
  1191.         int                                         num_z_pipes;
  1192.     int                         disp_priority;
  1193.     /* BIOS */
  1194.     uint8_t                     *bios;
  1195.     bool                        is_atom_bios;
  1196.     uint16_t                    bios_header_start;
  1197.         struct radeon_bo                    *stollen_vga_memory;
  1198.     /* Register mmio */
  1199.         resource_size_t                 rmmio_base;
  1200.         resource_size_t                 rmmio_size;
  1201.     void                       *rmmio;
  1202.     radeon_rreg_t               mc_rreg;
  1203.     radeon_wreg_t               mc_wreg;
  1204.     radeon_rreg_t               pll_rreg;
  1205.     radeon_wreg_t               pll_wreg;
  1206.         uint32_t                        pcie_reg_mask;
  1207.     radeon_rreg_t               pciep_rreg;
  1208.     radeon_wreg_t               pciep_wreg;
  1209.         /* io port */
  1210.         void __iomem                    *rio_mem;
  1211.         resource_size_t                 rio_mem_size;
  1212.     struct radeon_clock         clock;
  1213.     struct radeon_mc            mc;
  1214.     struct radeon_gart          gart;
  1215.         struct radeon_mode_info         mode_info;
  1216.     struct radeon_scratch       scratch;
  1217.     struct radeon_mman          mman;
  1218.         struct radeon_fence_driver      fence_drv;
  1219.     struct radeon_cp            cp;
  1220.         /* cayman compute rings */
  1221.         struct radeon_cp                cp1;
  1222.         struct radeon_cp                cp2;
  1223.     struct radeon_ib_pool       ib_pool;
  1224.     struct radeon_irq       irq;
  1225.     struct radeon_asic         *asic;
  1226.     struct radeon_gem       gem;
  1227.         struct radeon_pm                pm;
  1228.         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  1229.         struct mutex                    cs_mutex;
  1230.     struct radeon_wb        wb;
  1231.         struct radeon_dummy_page        dummy_page;
  1232.     bool                gpu_lockup;
  1233.     bool                shutdown;
  1234.     bool                suspend;
  1235.         bool                            need_dma32;
  1236.         bool                            accel_working;
  1237.         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  1238.         const struct firmware *me_fw;   /* all family ME firmware */
  1239.         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
  1240.         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
  1241.         const struct firmware *mc_fw;   /* NI MC firmware */
  1242.         struct r600_blit r600_blit;
  1243.         struct r700_vram_scratch vram_scratch;
  1244.         int msi_enabled; /* msi enabled */
  1245.         struct r600_ih ih; /* r6/700 interrupt ring */
  1246. //      struct work_struct hotplug_work;
  1247.         int num_crtc; /* number of crtcs */
  1248.         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
  1249.         struct mutex vram_mutex;
  1250.  
  1251.         /* audio stuff */
  1252.         bool                    audio_enabled;
  1253. //      struct timer_list       audio_timer;
  1254.         int                     audio_channels;
  1255.         int                     audio_rate;
  1256.         int                     audio_bits_per_sample;
  1257.         uint8_t                 audio_status_bits;
  1258.         uint8_t                 audio_category_code;
  1259.  
  1260.  
  1261.         /* i2c buses */
  1262.         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
  1263. };
  1264.  
  1265. int radeon_device_init(struct radeon_device *rdev,
  1266.                        struct drm_device *ddev,
  1267.                        struct pci_dev *pdev,
  1268.                        uint32_t flags);
  1269. void radeon_device_fini(struct radeon_device *rdev);
  1270. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  1271.  
  1272. static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
  1273. {
  1274.         if (reg < rdev->rmmio_size)
  1275.                 return readl(((void __iomem *)rdev->rmmio) + reg);
  1276.         else {
  1277.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  1278.                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  1279.         }
  1280. }
  1281.  
  1282. static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  1283. {
  1284.         if (reg < rdev->rmmio_size)
  1285.                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
  1286.         else {
  1287.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  1288.                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  1289.         }
  1290. }
  1291.  
  1292. static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
  1293. {
  1294.         if (reg < rdev->rio_mem_size)
  1295.                 return ioread32(rdev->rio_mem + reg);
  1296.         else {
  1297.                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
  1298.                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
  1299.         }
  1300. }
  1301.  
  1302. static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  1303. {
  1304.         if (reg < rdev->rio_mem_size)
  1305.                 iowrite32(v, rdev->rio_mem + reg);
  1306.         else {
  1307.                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
  1308.                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
  1309.         }
  1310. }
  1311.  
  1312. /*
  1313.  * Cast helper
  1314.  */
  1315. #define to_radeon_fence(p) ((struct radeon_fence *)(p))
  1316.  
  1317. /*
  1318.  * Registers read & write functions.
  1319.  */
  1320. #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
  1321. #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
  1322. #define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))
  1323. #define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))
  1324. #define RREG32(reg) r100_mm_rreg(rdev, (reg))
  1325. #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
  1326. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
  1327. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  1328. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  1329. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  1330. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  1331. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  1332. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  1333. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  1334. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  1335. #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
  1336. #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
  1337. #define WREG32_P(reg, val, mask)                                \
  1338.         do {                                                    \
  1339.                 uint32_t tmp_ = RREG32(reg);                    \
  1340.                 tmp_ &= (mask);                                 \
  1341.                 tmp_ |= ((val) & ~(mask));                      \
  1342.                 WREG32(reg, tmp_);                              \
  1343.         } while (0)
  1344. #define WREG32_PLL_P(reg, val, mask)                            \
  1345.         do {                                                    \
  1346.                 uint32_t tmp_ = RREG32_PLL(reg);                \
  1347.                 tmp_ &= (mask);                                 \
  1348.                 tmp_ |= ((val) & ~(mask));                      \
  1349.                 WREG32_PLL(reg, tmp_);                          \
  1350.         } while (0)
  1351. #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
  1352. #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
  1353.  
  1354. /*
  1355.  * Indirect registers accessor
  1356.  */
  1357. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  1358. {
  1359.         uint32_t r;
  1360.  
  1361.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  1362.         r = RREG32(RADEON_PCIE_DATA);
  1363.         return r;
  1364. }
  1365.  
  1366. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  1367. {
  1368.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  1369.         WREG32(RADEON_PCIE_DATA, (v));
  1370. }
  1371.  
  1372. void r100_pll_errata_after_index(struct radeon_device *rdev);
  1373.  
  1374.  
  1375. /*
  1376.  * ASICs helpers.
  1377.  */
  1378. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  1379.                             (rdev->pdev->device == 0x5969))
  1380. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  1381.         (rdev->family == CHIP_RV200) || \
  1382.         (rdev->family == CHIP_RS100) || \
  1383.         (rdev->family == CHIP_RS200) || \
  1384.         (rdev->family == CHIP_RV250) || \
  1385.         (rdev->family == CHIP_RV280) || \
  1386.         (rdev->family == CHIP_RS300))
  1387. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
  1388.         (rdev->family == CHIP_RV350) ||         \
  1389.         (rdev->family == CHIP_R350)  ||         \
  1390.         (rdev->family == CHIP_RV380) ||         \
  1391.         (rdev->family == CHIP_R420)  ||         \
  1392.         (rdev->family == CHIP_R423)  ||         \
  1393.         (rdev->family == CHIP_RV410) ||         \
  1394.         (rdev->family == CHIP_RS400) ||         \
  1395.         (rdev->family == CHIP_RS480))
  1396. #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
  1397.                 (rdev->ddev->pdev->device == 0x9443) || \
  1398.                 (rdev->ddev->pdev->device == 0x944B) || \
  1399.                 (rdev->ddev->pdev->device == 0x9506) || \
  1400.                 (rdev->ddev->pdev->device == 0x9509) || \
  1401.                 (rdev->ddev->pdev->device == 0x950F) || \
  1402.                 (rdev->ddev->pdev->device == 0x689C) || \
  1403.                 (rdev->ddev->pdev->device == 0x689D))
  1404. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  1405. #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
  1406.                             (rdev->family == CHIP_RS690)  ||    \
  1407.                             (rdev->family == CHIP_RS740)  ||    \
  1408.                             (rdev->family >= CHIP_R600))
  1409. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  1410. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  1411. #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
  1412. #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
  1413.                              (rdev->flags & RADEON_IS_IGP))
  1414. #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
  1415.  
  1416. /*
  1417.  * BIOS helpers.
  1418.  */
  1419. #define RBIOS8(i) (rdev->bios[i])
  1420. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  1421. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  1422.  
  1423. int radeon_combios_init(struct radeon_device *rdev);
  1424. void radeon_combios_fini(struct radeon_device *rdev);
  1425. int radeon_atombios_init(struct radeon_device *rdev);
  1426. void radeon_atombios_fini(struct radeon_device *rdev);
  1427.  
  1428.  
  1429. /*
  1430.  * RING helpers.
  1431.  */
  1432. static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  1433. {
  1434. #if DRM_DEBUG_CODE
  1435.         if (rdev->cp.count_dw <= 0) {
  1436.                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  1437.         }
  1438. #endif
  1439.         rdev->cp.ring[rdev->cp.wptr++] = v;
  1440.         rdev->cp.wptr &= rdev->cp.ptr_mask;
  1441.         rdev->cp.count_dw--;
  1442.         rdev->cp.ring_free_dw--;
  1443. }
  1444.  
  1445.  
  1446. /*
  1447.  * ASICs macro.
  1448.  */
  1449. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  1450. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  1451. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  1452. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  1453. #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
  1454. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  1455. #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
  1456. #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
  1457. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
  1458. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
  1459. #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
  1460. #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
  1461. #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
  1462. #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
  1463. #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
  1464. #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
  1465. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
  1466. #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
  1467. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
  1468. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
  1469. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
  1470. #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
  1471. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  1472. #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
  1473. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
  1474. #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
  1475. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
  1476. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
  1477. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
  1478. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
  1479. #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
  1480. #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
  1481. #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
  1482. #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
  1483. #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
  1484. #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
  1485. #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
  1486. #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
  1487. #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
  1488. #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
  1489. #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
  1490. #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
  1491. #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
  1492. #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
  1493.  
  1494. /* Common functions */
  1495. /* AGP */
  1496. extern int radeon_gpu_reset(struct radeon_device *rdev);
  1497. extern void radeon_agp_disable(struct radeon_device *rdev);
  1498. extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  1499. extern void radeon_gart_restore(struct radeon_device *rdev);
  1500. extern int radeon_modeset_init(struct radeon_device *rdev);
  1501. extern void radeon_modeset_fini(struct radeon_device *rdev);
  1502. extern bool radeon_card_posted(struct radeon_device *rdev);
  1503. extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
  1504. extern void radeon_update_display_priority(struct radeon_device *rdev);
  1505. extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
  1506. extern void radeon_scratch_init(struct radeon_device *rdev);
  1507. extern void radeon_wb_fini(struct radeon_device *rdev);
  1508. extern int radeon_wb_init(struct radeon_device *rdev);
  1509. extern void radeon_wb_disable(struct radeon_device *rdev);
  1510. extern void radeon_surface_init(struct radeon_device *rdev);
  1511. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  1512. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  1513. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  1514. extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
  1515. extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
  1516. extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
  1517. extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
  1518. extern int radeon_resume_kms(struct drm_device *dev);
  1519. extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
  1520. extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
  1521.  
  1522. /*
  1523.  * r600 functions used by radeon_encoder.c
  1524.  */
  1525. extern void r600_hdmi_enable(struct drm_encoder *encoder);
  1526. extern void r600_hdmi_disable(struct drm_encoder *encoder);
  1527. extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  1528.  
  1529. extern int ni_init_microcode(struct radeon_device *rdev);
  1530. extern int ni_mc_load_microcode(struct radeon_device *rdev);
  1531.  
  1532. /* radeon_acpi.c */
  1533. #if defined(CONFIG_ACPI)
  1534. extern int radeon_acpi_init(struct radeon_device *rdev);
  1535. #else
  1536. static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
  1537. #endif
  1538.  
  1539. #include "radeon_object.h"
  1540.  
  1541. #define DRM_UDELAY(d)           udelay(d)
  1542.  
  1543. resource_size_t
  1544. drm_get_resource_start(struct drm_device *dev, unsigned int resource);
  1545. resource_size_t
  1546. drm_get_resource_len(struct drm_device *dev, unsigned int resource);
  1547.  
  1548. bool set_mode(struct drm_device *dev, struct drm_connector *connector,
  1549.               videomode_t *mode, bool strict);
  1550.  
  1551.  
  1552.  
  1553. struct work_struct;
  1554. typedef void (*work_func_t)(struct work_struct *work);
  1555.  
  1556. /*
  1557.  * The first word is the work queue pointer and the flags rolled into
  1558.  * one
  1559.  */
  1560. #define work_data_bits(work) ((unsigned long *)(&(work)->data))
  1561.  
  1562. struct work_struct {
  1563.         atomic_long_t data;
  1564. #define WORK_STRUCT_PENDING 0           /* T if work item pending execution */
  1565. #define WORK_STRUCT_FLAG_MASK (3UL)
  1566. #define WORK_STRUCT_WQ_DATA_MASK (~WORK_STRUCT_FLAG_MASK)
  1567.         struct list_head entry;
  1568.         work_func_t func;
  1569. };
  1570.  
  1571. #endif
  1572.