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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30.  
  31. /* TODO: Here are things that needs to be done :
  32.  *      - surface allocator & initializer : (bit like scratch reg) should
  33.  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34.  *        related to surface
  35.  *      - WB : write back stuff (do it bit like scratch reg things)
  36.  *      - Vblank : look at Jesse's rework and what we should do
  37.  *      - r600/r700: gart & cp
  38.  *      - cs : clean cs ioctl use bitmap & things like that.
  39.  *      - power management stuff
  40.  *      - Barrier in gart code
  41.  *      - Unmappabled vram ?
  42.  *      - TESTING, TESTING, TESTING
  43.  */
  44.  
  45. /* Initialization path:
  46.  *  We expect that acceleration initialization might fail for various
  47.  *  reasons even thought we work hard to make it works on most
  48.  *  configurations. In order to still have a working userspace in such
  49.  *  situation the init path must succeed up to the memory controller
  50.  *  initialization point. Failure before this point are considered as
  51.  *  fatal error. Here is the init callchain :
  52.  *      radeon_device_init  perform common structure, mutex initialization
  53.  *      asic_init           setup the GPU memory layout and perform all
  54.  *                          one time initialization (failure in this
  55.  *                          function are considered fatal)
  56.  *      asic_startup        setup the GPU acceleration, in order to
  57.  *                          follow guideline the first thing this
  58.  *                          function should do is setting the GPU
  59.  *                          memory controller (only MC setup failure
  60.  *                          are considered as fatal)
  61.  */
  62.  
  63. #include <asm/atomic.h>
  64.  
  65. #include <linux/list.h>
  66. #include <linux/kref.h>
  67.  
  68. #include <ttm/ttm_bo_api.h>
  69. #include <ttm/ttm_bo_driver.h>
  70. #include <ttm/ttm_placement.h>
  71. #include <ttm/ttm_module.h>
  72.  
  73.  
  74. #include <pci.h>
  75.  
  76. #include <errno-base.h>
  77. #include "drm_edid.h"
  78.  
  79. #include "radeon_family.h"
  80. #include "radeon_mode.h"
  81. #include "radeon_reg.h"
  82.  
  83. #include <syscall.h>
  84.  
  85. /*
  86.  * Modules parameters.
  87.  */
  88. extern int radeon_no_wb;
  89. extern int radeon_modeset;
  90. extern int radeon_dynclks;
  91. extern int radeon_r4xx_atom;
  92. extern int radeon_agpmode;
  93. extern int radeon_vram_limit;
  94. extern int radeon_gart_size;
  95. extern int radeon_benchmarking;
  96. extern int radeon_testing;
  97. extern int radeon_connector_table;
  98. extern int radeon_tv;
  99. extern int radeon_new_pll;
  100. extern int radeon_audio;
  101.  
  102. typedef struct
  103. {
  104.   int width;
  105.   int height;
  106.   int bpp;
  107.   int freq;
  108. }videomode_t;
  109.  
  110. static inline uint8_t __raw_readb(const volatile void __iomem *addr)
  111. {
  112.     return *(const volatile uint8_t __force *) addr;
  113. }
  114.  
  115. static inline uint16_t __raw_readw(const volatile void __iomem *addr)
  116. {
  117.     return *(const volatile uint16_t __force *) addr;
  118. }
  119.  
  120. static inline uint32_t __raw_readl(const volatile void __iomem *addr)
  121. {
  122.     return *(const volatile uint32_t __force *) addr;
  123. }
  124.  
  125. #define readb __raw_readb
  126. #define readw __raw_readw
  127. #define readl __raw_readl
  128.  
  129.  
  130.  
  131. static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
  132. {
  133.     *(volatile uint8_t __force *) addr = b;
  134. }
  135.  
  136. static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
  137. {
  138.     *(volatile uint16_t __force *) addr = b;
  139. }
  140.  
  141. static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
  142. {
  143.     *(volatile uint32_t __force *) addr = b;
  144. }
  145.  
  146. static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
  147. {
  148.         *(volatile __u64 *)addr = b;
  149. }
  150.  
  151. #define writeb __raw_writeb
  152. #define writew __raw_writew
  153. #define writel __raw_writel
  154. #define writeq __raw_writeq
  155.  
  156.  
  157. /*
  158.  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  159.  * symbol;
  160.  */
  161. #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  162. /* RADEON_IB_POOL_SIZE must be a power of 2 */
  163. #define RADEON_IB_POOL_SIZE             16
  164. #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  165. #define RADEONFB_CONN_LIMIT             4
  166. #define RADEON_BIOS_NUM_SCRATCH         8
  167.  
  168. /*
  169.  * Errata workarounds.
  170.  */
  171. enum radeon_pll_errata {
  172.     CHIP_ERRATA_R300_CG             = 0x00000001,
  173.     CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  174.     CHIP_ERRATA_PLL_DELAY           = 0x00000004
  175. };
  176.  
  177.  
  178. struct radeon_device;
  179.  
  180.  
  181. /*
  182.  * BIOS.
  183.  */
  184. bool radeon_get_bios(struct radeon_device *rdev);
  185.  
  186.  
  187. /*
  188.  * Dummy page
  189.  */
  190. struct radeon_dummy_page {
  191.         struct page     *page;
  192.         dma_addr_t      addr;
  193. };
  194. int radeon_dummy_page_init(struct radeon_device *rdev);
  195. void radeon_dummy_page_fini(struct radeon_device *rdev);
  196.  
  197.  
  198. /*
  199.  * Clocks
  200.  */
  201. struct radeon_clock {
  202.         struct radeon_pll p1pll;
  203.         struct radeon_pll p2pll;
  204.         struct radeon_pll spll;
  205.         struct radeon_pll mpll;
  206.         /* 10 Khz units */
  207.         uint32_t default_mclk;
  208.         uint32_t default_sclk;
  209. };
  210.  
  211. /*
  212.  * Power management
  213.  */
  214. int radeon_pm_init(struct radeon_device *rdev);
  215.  
  216. /*
  217.  * Fences.
  218.  */
  219. struct radeon_fence_driver {
  220.         uint32_t                        scratch_reg;
  221.         atomic_t                        seq;
  222.         uint32_t                        last_seq;
  223.         unsigned long                   count_timeout;
  224. //      wait_queue_head_t               queue;
  225.         rwlock_t                        lock;
  226.         struct list_head                created;
  227.         struct list_head                emited;
  228.         struct list_head                signaled;
  229.         bool                            initialized;
  230. };
  231.  
  232. struct radeon_fence {
  233.         struct radeon_device            *rdev;
  234.         struct kref                     kref;
  235.         struct list_head                list;
  236.         /* protected by radeon_fence.lock */
  237.         uint32_t                        seq;
  238.         unsigned long                   timeout;
  239.         bool                            emited;
  240.         bool                            signaled;
  241. };
  242.  
  243. int radeon_fence_driver_init(struct radeon_device *rdev);
  244. void radeon_fence_driver_fini(struct radeon_device *rdev);
  245. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
  246. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
  247. void radeon_fence_process(struct radeon_device *rdev);
  248. bool radeon_fence_signaled(struct radeon_fence *fence);
  249. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  250. int radeon_fence_wait_next(struct radeon_device *rdev);
  251. int radeon_fence_wait_last(struct radeon_device *rdev);
  252. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  253. void radeon_fence_unref(struct radeon_fence **fence);
  254.  
  255. /*
  256.  * Tiling registers
  257.  */
  258. struct radeon_surface_reg {
  259.         struct radeon_bo *bo;
  260. };
  261.  
  262. #define RADEON_GEM_MAX_SURFACES 8
  263.  
  264. /*
  265.  * TTM.
  266.  */
  267. struct radeon_mman {
  268.         struct ttm_bo_global_ref        bo_global_ref;
  269.         struct ttm_global_reference     mem_global_ref;
  270.         struct ttm_bo_device            bdev;
  271.         bool                            mem_global_referenced;
  272.         bool                            initialized;
  273. };
  274.  
  275. struct radeon_bo {
  276.         /* Protected by gem.mutex */
  277.         struct list_head                list;
  278.         /* Protected by tbo.reserved */
  279.         u32                             placements[3];
  280.         struct ttm_placement            placement;
  281.         struct ttm_buffer_object        tbo;
  282.         struct ttm_bo_kmap_obj          kmap;
  283.     unsigned                    pin_count;
  284.     void                       *kptr;
  285.     u32                         cpu_addr;
  286.     u32                         tiling_flags;
  287.     u32                         pitch;
  288.     int                         surface_reg;
  289.         /* Constant after initialization */
  290.         struct radeon_device            *rdev;
  291.         struct drm_gem_object           *gobj;
  292.     u32                          domain;
  293. };
  294.  
  295. struct radeon_bo_list {
  296.         struct list_head        list;
  297.         struct radeon_bo        *bo;
  298.         uint64_t                gpu_offset;
  299.         unsigned                rdomain;
  300.         unsigned                wdomain;
  301.         u32                     tiling_flags;
  302. };
  303.  
  304. /*
  305.  * GEM objects.
  306.  */
  307. struct radeon_gem {
  308.         struct list_head        objects;
  309. };
  310.  
  311. int radeon_gem_init(struct radeon_device *rdev);
  312. void radeon_gem_fini(struct radeon_device *rdev);
  313. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  314.                              int alignment, int initial_domain,
  315.                              bool discardable, bool kernel,
  316.                              struct drm_gem_object **obj);
  317. int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
  318.                           uint64_t *gpu_addr);
  319. void radeon_gem_object_unpin(struct drm_gem_object *obj);
  320.  
  321.  
  322. /*
  323.  * GART structures, functions & helpers
  324.  */
  325. struct radeon_mc;
  326.  
  327. struct radeon_gart_table_ram {
  328.     volatile uint32_t       *ptr;
  329. };
  330.  
  331. struct radeon_gart_table_vram {
  332.         struct radeon_bo                *robj;
  333.     volatile uint32_t       *ptr;
  334. };
  335.  
  336. union radeon_gart_table {
  337.     struct radeon_gart_table_ram    ram;
  338.     struct radeon_gart_table_vram   vram;
  339. };
  340.  
  341. #define RADEON_GPU_PAGE_SIZE 4096
  342.  
  343. struct radeon_gart {
  344.     dma_addr_t          table_addr;
  345.     unsigned            num_gpu_pages;
  346.     unsigned            num_cpu_pages;
  347.     unsigned            table_size;
  348.     union radeon_gart_table     table;
  349.     struct page         **pages;
  350.     dma_addr_t          *pages_addr;
  351.     bool                ready;
  352. };
  353.  
  354. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  355. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  356. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  357. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  358. int radeon_gart_init(struct radeon_device *rdev);
  359. void radeon_gart_fini(struct radeon_device *rdev);
  360. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  361.                         int pages);
  362. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  363.             int pages, u32_t *pagelist);
  364.  
  365.  
  366. /*
  367.  * GPU MC structures, functions & helpers
  368.  */
  369. struct radeon_mc {
  370.     resource_size_t     aper_size;
  371.     resource_size_t     aper_base;
  372.     resource_size_t     agp_base;
  373.         /* for some chips with <= 32MB we need to lie
  374.          * about vram size near mc fb location */
  375.         u64                     mc_vram_size;
  376.         u64                     gtt_location;
  377.         u64                     gtt_size;
  378.         u64                     gtt_start;
  379.         u64                     gtt_end;
  380.         u64                     vram_location;
  381.         u64                     vram_start;
  382.         u64                     vram_end;
  383.     unsigned            vram_width;
  384.         u64                     real_vram_size;
  385.     int                 vram_mtrr;
  386.     bool                vram_is_ddr;
  387.         bool                    igp_sideport_enabled;
  388. };
  389.  
  390. int radeon_mc_setup(struct radeon_device *rdev);
  391. bool radeon_combios_sideport_present(struct radeon_device *rdev);
  392. bool radeon_atombios_sideport_present(struct radeon_device *rdev);
  393.  
  394. /*
  395.  * GPU scratch registers structures, functions & helpers
  396.  */
  397. struct radeon_scratch {
  398.     unsigned        num_reg;
  399.     bool            free[32];
  400.     uint32_t        reg[32];
  401. };
  402.  
  403. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  404. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  405.  
  406.  
  407. /*
  408.  * IRQS.
  409.  */
  410. struct radeon_irq {
  411.         bool            installed;
  412.         bool            sw_int;
  413.         /* FIXME: use a define max crtc rather than hardcode it */
  414.         bool            crtc_vblank_int[2];
  415.         /* FIXME: use defines for max hpd/dacs */
  416.         bool            hpd[6];
  417.     spinlock_t  sw_lock;
  418.         int sw_refcount;
  419. };
  420.  
  421. int radeon_irq_kms_init(struct radeon_device *rdev);
  422. void radeon_irq_kms_fini(struct radeon_device *rdev);
  423. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
  424. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
  425.  
  426. /*
  427.  * CP & ring.
  428.  */
  429. struct radeon_ib {
  430.     struct list_head    list;
  431.         unsigned                idx;
  432.     uint64_t            gpu_addr;
  433.         struct radeon_fence     *fence;
  434.     uint32_t            *ptr;
  435.     uint32_t            length_dw;
  436.         bool                    free;
  437. };
  438.  
  439. /*
  440.  * locking -
  441.  * mutex protects scheduled_ibs, ready, alloc_bm
  442.  */
  443. struct radeon_ib_pool {
  444. //   struct mutex        mutex;
  445.         struct radeon_bo        *robj;
  446.         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
  447.     bool                ready;
  448.         unsigned                head_id;
  449. };
  450.  
  451. struct radeon_cp {
  452.         struct radeon_bo        *ring_obj;
  453.         volatile uint32_t       *ring;
  454.     unsigned            rptr;
  455.     unsigned            wptr;
  456.     unsigned            wptr_old;
  457.     unsigned            ring_size;
  458.     unsigned            ring_free_dw;
  459.     int                 count_dw;
  460.     uint64_t            gpu_addr;
  461.     uint32_t            align_mask;
  462.     uint32_t            ptr_mask;
  463. //      struct mutex            mutex;
  464.     bool                ready;
  465. };
  466.  
  467. /*
  468.  * R6xx+ IH ring
  469.  */
  470. struct r600_ih {
  471.         struct radeon_bo        *ring_obj;
  472.         volatile uint32_t       *ring;
  473.     unsigned            rptr;
  474.     unsigned            wptr;
  475.     unsigned            wptr_old;
  476.     unsigned            ring_size;
  477.     uint64_t            gpu_addr;
  478.     uint32_t            ptr_mask;
  479.     spinlock_t              lock;
  480.     bool                enabled;
  481. };
  482.  
  483. struct r600_blit {
  484.         struct radeon_bo        *shader_obj;
  485.         u64 shader_gpu_addr;
  486.         u32 vs_offset, ps_offset;
  487.         u32 state_offset;
  488.         u32 state_len;
  489.         u32 vb_used, vb_total;
  490.         struct radeon_ib *vb_ib;
  491. };
  492.  
  493. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
  494. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
  495. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
  496. int radeon_ib_pool_init(struct radeon_device *rdev);
  497. void radeon_ib_pool_fini(struct radeon_device *rdev);
  498. int radeon_ib_test(struct radeon_device *rdev);
  499. /* Ring access between begin & end cannot sleep */
  500. void radeon_ring_free_size(struct radeon_device *rdev);
  501. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
  502. void radeon_ring_unlock_commit(struct radeon_device *rdev);
  503. void radeon_ring_unlock_undo(struct radeon_device *rdev);
  504. int radeon_ring_test(struct radeon_device *rdev);
  505. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
  506. void radeon_ring_fini(struct radeon_device *rdev);
  507.  
  508.  
  509. /*
  510.  * CS.
  511.  */
  512. struct radeon_cs_reloc {
  513. //      struct drm_gem_object           *gobj;
  514.         struct radeon_bo                *robj;
  515. //    struct radeon_bo_list   lobj;
  516.     uint32_t                handle;
  517.     uint32_t                flags;
  518. };
  519.  
  520. struct radeon_cs_chunk {
  521.         uint32_t                chunk_id;
  522.         uint32_t                length_dw;
  523.         int kpage_idx[2];
  524.         uint32_t                *kpage[2];
  525.         uint32_t                *kdata;
  526.         void __user *user_ptr;
  527.         int last_copied_page;
  528.         int last_page_index;
  529. };
  530.  
  531. struct radeon_cs_parser {
  532.         struct radeon_device    *rdev;
  533. //      struct drm_file         *filp;
  534.         /* chunks */
  535.         unsigned                nchunks;
  536.         struct radeon_cs_chunk  *chunks;
  537.         uint64_t                *chunks_array;
  538.         /* IB */
  539.         unsigned                idx;
  540.         /* relocations */
  541.         unsigned                nrelocs;
  542.         struct radeon_cs_reloc  *relocs;
  543.         struct radeon_cs_reloc  **relocs_ptr;
  544.         struct list_head        validated;
  545.         /* indices of various chunks */
  546.         int                     chunk_ib_idx;
  547.         int                     chunk_relocs_idx;
  548.         struct radeon_ib        *ib;
  549.         void                    *track;
  550.         unsigned                family;
  551.         int parser_error;
  552. };
  553.  
  554. extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
  555. extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
  556.  
  557.  
  558. static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  559. {
  560.         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  561.         u32 pg_idx, pg_offset;
  562.         u32 idx_value = 0;
  563.         int new_page;
  564.  
  565.         pg_idx = (idx * 4) / PAGE_SIZE;
  566.         pg_offset = (idx * 4) % PAGE_SIZE;
  567.  
  568.         if (ibc->kpage_idx[0] == pg_idx)
  569.                 return ibc->kpage[0][pg_offset/4];
  570.         if (ibc->kpage_idx[1] == pg_idx)
  571.                 return ibc->kpage[1][pg_offset/4];
  572.  
  573.         new_page = radeon_cs_update_pages(p, pg_idx);
  574.         if (new_page < 0) {
  575.                 p->parser_error = new_page;
  576.                 return 0;
  577.         }
  578.  
  579.         idx_value = ibc->kpage[new_page][pg_offset/4];
  580.         return idx_value;
  581. }
  582.  
  583. struct radeon_cs_packet {
  584.         unsigned        idx;
  585.         unsigned        type;
  586.         unsigned        reg;
  587.         unsigned        opcode;
  588.         int             count;
  589.         unsigned        one_reg_wr;
  590. };
  591.  
  592. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  593.                                       struct radeon_cs_packet *pkt,
  594.                                       unsigned idx, unsigned reg);
  595. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  596.                                       struct radeon_cs_packet *pkt);
  597.  
  598.  
  599. /*
  600.  * AGP
  601.  */
  602. int radeon_agp_init(struct radeon_device *rdev);
  603. void radeon_agp_resume(struct radeon_device *rdev);
  604. void radeon_agp_fini(struct radeon_device *rdev);
  605.  
  606.  
  607. /*
  608.  * Writeback
  609.  */
  610. struct radeon_wb {
  611.         struct radeon_bo        *wb_obj;
  612.         volatile uint32_t       *wb;
  613.         uint64_t                gpu_addr;
  614. };
  615.  
  616. /**
  617.  * struct radeon_pm - power management datas
  618.  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
  619.  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  620.  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
  621.  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
  622.  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
  623.  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
  624.  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  625.  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
  626.  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
  627.  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
  628.  * @needed_bandwidth:   current bandwidth needs
  629.  *
  630.  * It keeps track of various data needed to take powermanagement decision.
  631.  * Bandwith need is used to determine minimun clock of the GPU and memory.
  632.  * Equation between gpu/memory clock and available bandwidth is hw dependent
  633.  * (type of memory, bus size, efficiency, ...)
  634.  */
  635. struct radeon_pm {
  636.         fixed20_12              max_bandwidth;
  637.         fixed20_12              igp_sideport_mclk;
  638.         fixed20_12              igp_system_mclk;
  639.         fixed20_12              igp_ht_link_clk;
  640.         fixed20_12              igp_ht_link_width;
  641.         fixed20_12              k8_bandwidth;
  642.         fixed20_12              sideport_bandwidth;
  643.         fixed20_12              ht_bandwidth;
  644.         fixed20_12              core_bandwidth;
  645.         fixed20_12              sclk;
  646.         fixed20_12              needed_bandwidth;
  647. };
  648.  
  649. /*
  650.  * ASIC specific functions.
  651.  */
  652. struct radeon_asic {
  653.         int (*init)(struct radeon_device *rdev);
  654.         void (*fini)(struct radeon_device *rdev);
  655.         int (*resume)(struct radeon_device *rdev);
  656.         int (*suspend)(struct radeon_device *rdev);
  657.         void (*vga_set_state)(struct radeon_device *rdev, bool state);
  658.         int (*gpu_reset)(struct radeon_device *rdev);
  659.         void (*gart_tlb_flush)(struct radeon_device *rdev);
  660.         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  661.         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
  662.         void (*cp_fini)(struct radeon_device *rdev);
  663.         void (*cp_disable)(struct radeon_device *rdev);
  664.         void (*cp_commit)(struct radeon_device *rdev);
  665.         void (*ring_start)(struct radeon_device *rdev);
  666.         int (*ring_test)(struct radeon_device *rdev);
  667.         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  668.         int (*irq_set)(struct radeon_device *rdev);
  669.         int (*irq_process)(struct radeon_device *rdev);
  670.         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  671.         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
  672.         int (*cs_parse)(struct radeon_cs_parser *p);
  673.         int (*copy_blit)(struct radeon_device *rdev,
  674.                          uint64_t src_offset,
  675.                          uint64_t dst_offset,
  676.                          unsigned num_pages,
  677.                          struct radeon_fence *fence);
  678.         int (*copy_dma)(struct radeon_device *rdev,
  679.                         uint64_t src_offset,
  680.                         uint64_t dst_offset,
  681.                         unsigned num_pages,
  682.                         struct radeon_fence *fence);
  683.         int (*copy)(struct radeon_device *rdev,
  684.                     uint64_t src_offset,
  685.                     uint64_t dst_offset,
  686.                     unsigned num_pages,
  687.                     struct radeon_fence *fence);
  688.         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
  689.         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  690.         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
  691.         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  692.         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  693.         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  694.         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
  695.                                uint32_t tiling_flags, uint32_t pitch,
  696.                                uint32_t offset, uint32_t obj_size);
  697.         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
  698.         void (*bandwidth_update)(struct radeon_device *rdev);
  699.         void (*hpd_init)(struct radeon_device *rdev);
  700.         void (*hpd_fini)(struct radeon_device *rdev);
  701.         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  702.         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  703.         /* ioctl hw specific callback. Some hw might want to perform special
  704.          * operation on specific ioctl. For instance on wait idle some hw
  705.          * might want to perform and HDP flush through MMIO as it seems that
  706.          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
  707.          * through ring.
  708.          */
  709.         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
  710. };
  711.  
  712. /*
  713.  * Asic structures
  714.  */
  715. struct r100_asic {
  716.         const unsigned  *reg_safe_bm;
  717.         unsigned        reg_safe_bm_size;
  718.         u32             hdp_cntl;
  719. };
  720.  
  721. struct r300_asic {
  722.         const unsigned  *reg_safe_bm;
  723.         unsigned        reg_safe_bm_size;
  724.         u32             resync_scratch;
  725.         u32             hdp_cntl;
  726. };
  727.  
  728. struct r600_asic {
  729.         unsigned max_pipes;
  730.         unsigned max_tile_pipes;
  731.         unsigned max_simds;
  732.         unsigned max_backends;
  733.         unsigned max_gprs;
  734.         unsigned max_threads;
  735.         unsigned max_stack_entries;
  736.         unsigned max_hw_contexts;
  737.         unsigned max_gs_threads;
  738.         unsigned sx_max_export_size;
  739.         unsigned sx_max_export_pos_size;
  740.         unsigned sx_max_export_smx_size;
  741.         unsigned sq_num_cf_insts;
  742. };
  743.  
  744. struct rv770_asic {
  745.         unsigned max_pipes;
  746.         unsigned max_tile_pipes;
  747.         unsigned max_simds;
  748.         unsigned max_backends;
  749.         unsigned max_gprs;
  750.         unsigned max_threads;
  751.         unsigned max_stack_entries;
  752.         unsigned max_hw_contexts;
  753.         unsigned max_gs_threads;
  754.         unsigned sx_max_export_size;
  755.         unsigned sx_max_export_pos_size;
  756.         unsigned sx_max_export_smx_size;
  757.         unsigned sq_num_cf_insts;
  758.         unsigned sx_num_of_sets;
  759.         unsigned sc_prim_fifo_size;
  760.         unsigned sc_hiz_tile_fifo_size;
  761.         unsigned sc_earlyz_tile_fifo_fize;
  762. };
  763.  
  764. union radeon_asic_config {
  765.         struct r300_asic        r300;
  766.         struct r100_asic        r100;
  767.         struct r600_asic        r600;
  768.         struct rv770_asic       rv770;
  769. };
  770.  
  771.  
  772. /*
  773.  
  774.  
  775.  
  776.  
  777. /*
  778.  * Core structure, functions and helpers.
  779.  */
  780. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  781. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  782.  
  783. struct radeon_device {
  784.         struct device                   *dev;
  785.     struct drm_device          *ddev;
  786.     struct pci_dev             *pdev;
  787.     /* ASIC */
  788.     union radeon_asic_config    config;
  789.     enum radeon_family          family;
  790.     unsigned long               flags;
  791.     int                         usec_timeout;
  792.     enum radeon_pll_errata      pll_errata;
  793.     int                         num_gb_pipes;
  794.         int                                         num_z_pipes;
  795.     int                         disp_priority;
  796.     /* BIOS */
  797.     uint8_t                     *bios;
  798.     bool                        is_atom_bios;
  799.     uint16_t                    bios_header_start;
  800.         struct radeon_bo                    *stollen_vga_memory;
  801.     struct fb_info              *fbdev_info;
  802.         struct radeon_bo                    *fbdev_rbo;
  803.     struct radeon_framebuffer   *fbdev_rfb;
  804.     /* Register mmio */
  805.     unsigned long               rmmio_base;
  806.     unsigned long               rmmio_size;
  807.     void                       *rmmio;
  808.     radeon_rreg_t               mc_rreg;
  809.     radeon_wreg_t               mc_wreg;
  810.     radeon_rreg_t               pll_rreg;
  811.     radeon_wreg_t               pll_wreg;
  812.         uint32_t                        pcie_reg_mask;
  813.     radeon_rreg_t               pciep_rreg;
  814.     radeon_wreg_t               pciep_wreg;
  815.     struct radeon_clock         clock;
  816.     struct radeon_mc            mc;
  817.     struct radeon_gart          gart;
  818.         struct radeon_mode_info         mode_info;
  819.     struct radeon_scratch       scratch;
  820.     struct radeon_mman          mman;
  821.         struct radeon_fence_driver      fence_drv;
  822.     struct radeon_cp            cp;
  823.     struct radeon_ib_pool       ib_pool;
  824. //    struct radeon_irq       irq;
  825.     struct radeon_asic         *asic;
  826.     struct radeon_gem       gem;
  827.         struct radeon_pm                pm;
  828.         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  829. //    struct mutex            cs_mutex;
  830.     struct radeon_wb        wb;
  831.         struct radeon_dummy_page        dummy_page;
  832.     bool                gpu_lockup;
  833.     bool                shutdown;
  834.     bool                suspend;
  835.         bool                            need_dma32;
  836.         bool                            accel_working;
  837.         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  838.         const struct firmware *me_fw;   /* all family ME firmware */
  839.         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
  840.         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
  841.         struct r600_blit r600_blit;
  842.         int msi_enabled; /* msi enabled */
  843.  
  844.         /* audio stuff */
  845. //   struct timer_list   audio_timer;
  846.         int                     audio_channels;
  847.         int                     audio_rate;
  848.         int                     audio_bits_per_sample;
  849.         uint8_t                 audio_status_bits;
  850.         uint8_t                 audio_category_code;
  851. };
  852.  
  853. int radeon_device_init(struct radeon_device *rdev,
  854.                        struct drm_device *ddev,
  855.                        struct pci_dev *pdev,
  856.                        uint32_t flags);
  857. void radeon_device_fini(struct radeon_device *rdev);
  858. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  859.  
  860. /* r600 blit */
  861. int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
  862. void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
  863. void r600_kms_blit_copy(struct radeon_device *rdev,
  864.                         u64 src_gpu_addr, u64 dst_gpu_addr,
  865.                         int size_bytes);
  866.  
  867. static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
  868. {
  869.         if (reg < rdev->rmmio_size)
  870.                 return readl(((void __iomem *)rdev->rmmio) + reg);
  871.         else {
  872.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  873.                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  874.         }
  875. }
  876.  
  877. static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  878. {
  879.         if (reg < rdev->rmmio_size)
  880.                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
  881.         else {
  882.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  883.                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  884.         }
  885. }
  886.  
  887. /*
  888.  * Cast helper
  889.  */
  890. #define to_radeon_fence(p) ((struct radeon_fence *)(p))
  891.  
  892. /*
  893.  * Registers read & write functions.
  894.  */
  895. #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
  896. #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
  897. #define RREG32(reg) r100_mm_rreg(rdev, (reg))
  898. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
  899. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  900. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  901. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  902. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  903. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  904. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  905. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  906. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  907. #define WREG32_P(reg, val, mask)                                \
  908.         do {                                                    \
  909.                 uint32_t tmp_ = RREG32(reg);                    \
  910.                 tmp_ &= (mask);                                 \
  911.                 tmp_ |= ((val) & ~(mask));                      \
  912.                 WREG32(reg, tmp_);                              \
  913.         } while (0)
  914. #define WREG32_PLL_P(reg, val, mask)                            \
  915.         do {                                                    \
  916.                 uint32_t tmp_ = RREG32_PLL(reg);                \
  917.                 tmp_ &= (mask);                                 \
  918.                 tmp_ |= ((val) & ~(mask));                      \
  919.                 WREG32_PLL(reg, tmp_);                          \
  920.         } while (0)
  921.  
  922. /*
  923.  * Indirect registers accessor
  924.  */
  925. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  926. {
  927.         uint32_t r;
  928.  
  929.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  930.         r = RREG32(RADEON_PCIE_DATA);
  931.         return r;
  932. }
  933.  
  934. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  935. {
  936.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  937.         WREG32(RADEON_PCIE_DATA, (v));
  938. }
  939.  
  940. void r100_pll_errata_after_index(struct radeon_device *rdev);
  941.  
  942.  
  943. /*
  944.  * ASICs helpers.
  945.  */
  946. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  947.                             (rdev->pdev->device == 0x5969))
  948. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  949.         (rdev->family == CHIP_RV200) || \
  950.         (rdev->family == CHIP_RS100) || \
  951.         (rdev->family == CHIP_RS200) || \
  952.         (rdev->family == CHIP_RV250) || \
  953.         (rdev->family == CHIP_RV280) || \
  954.         (rdev->family == CHIP_RS300))
  955. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
  956.         (rdev->family == CHIP_RV350) ||         \
  957.         (rdev->family == CHIP_R350)  ||         \
  958.         (rdev->family == CHIP_RV380) ||         \
  959.         (rdev->family == CHIP_R420)  ||         \
  960.         (rdev->family == CHIP_R423)  ||         \
  961.         (rdev->family == CHIP_RV410) ||         \
  962.         (rdev->family == CHIP_RS400) ||         \
  963.         (rdev->family == CHIP_RS480))
  964. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  965. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  966. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  967.  
  968.  
  969. /*
  970.  * BIOS helpers.
  971.  */
  972. #define RBIOS8(i) (rdev->bios[i])
  973. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  974. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  975.  
  976. int radeon_combios_init(struct radeon_device *rdev);
  977. void radeon_combios_fini(struct radeon_device *rdev);
  978. int radeon_atombios_init(struct radeon_device *rdev);
  979. void radeon_atombios_fini(struct radeon_device *rdev);
  980.  
  981.  
  982. /*
  983.  * RING helpers.
  984.  */
  985. static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  986. {
  987. #if DRM_DEBUG_CODE
  988.         if (rdev->cp.count_dw <= 0) {
  989.                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  990.         }
  991. #endif
  992.         rdev->cp.ring[rdev->cp.wptr++] = v;
  993.         rdev->cp.wptr &= rdev->cp.ptr_mask;
  994.         rdev->cp.count_dw--;
  995.         rdev->cp.ring_free_dw--;
  996. }
  997.  
  998.  
  999. /*
  1000.  * ASICs macro.
  1001.  */
  1002. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  1003. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  1004. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  1005. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  1006. #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
  1007. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  1008. #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
  1009. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
  1010. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
  1011. #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
  1012. #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
  1013. #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
  1014. #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
  1015. #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
  1016. #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
  1017. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
  1018. #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
  1019. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
  1020. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
  1021. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
  1022. #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
  1023. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  1024. #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
  1025. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
  1026. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
  1027. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
  1028. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
  1029. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
  1030. #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
  1031. #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
  1032. #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
  1033. #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
  1034. #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
  1035.  
  1036. /* Common functions */
  1037. /* AGP */
  1038. extern void radeon_agp_disable(struct radeon_device *rdev);
  1039. extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  1040. extern int radeon_modeset_init(struct radeon_device *rdev);
  1041. extern void radeon_modeset_fini(struct radeon_device *rdev);
  1042. extern bool radeon_card_posted(struct radeon_device *rdev);
  1043. extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
  1044. extern int radeon_clocks_init(struct radeon_device *rdev);
  1045. extern void radeon_clocks_fini(struct radeon_device *rdev);
  1046. extern void radeon_scratch_init(struct radeon_device *rdev);
  1047. extern void radeon_surface_init(struct radeon_device *rdev);
  1048. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  1049. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  1050. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  1051. extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
  1052. extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
  1053.  
  1054. /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
  1055. struct r100_mc_save {
  1056.         u32     GENMO_WT;
  1057.         u32     CRTC_EXT_CNTL;
  1058.         u32     CRTC_GEN_CNTL;
  1059.         u32     CRTC2_GEN_CNTL;
  1060.         u32     CUR_OFFSET;
  1061.         u32     CUR2_OFFSET;
  1062. };
  1063. extern void r100_cp_disable(struct radeon_device *rdev);
  1064. extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  1065. extern void r100_cp_fini(struct radeon_device *rdev);
  1066. extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  1067. extern int r100_pci_gart_init(struct radeon_device *rdev);
  1068. extern void r100_pci_gart_fini(struct radeon_device *rdev);
  1069. extern int r100_pci_gart_enable(struct radeon_device *rdev);
  1070. extern void r100_pci_gart_disable(struct radeon_device *rdev);
  1071. extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  1072. extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  1073. extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
  1074. extern void r100_ib_fini(struct radeon_device *rdev);
  1075. extern int r100_ib_init(struct radeon_device *rdev);
  1076. extern void r100_irq_disable(struct radeon_device *rdev);
  1077. extern int r100_irq_set(struct radeon_device *rdev);
  1078. extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
  1079. extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
  1080. extern void r100_vram_init_sizes(struct radeon_device *rdev);
  1081. extern void r100_wb_disable(struct radeon_device *rdev);
  1082. extern void r100_wb_fini(struct radeon_device *rdev);
  1083. extern int r100_wb_init(struct radeon_device *rdev);
  1084. extern void r100_hdp_reset(struct radeon_device *rdev);
  1085. extern int r100_rb2d_reset(struct radeon_device *rdev);
  1086. extern int r100_cp_reset(struct radeon_device *rdev);
  1087. extern void r100_vga_render_disable(struct radeon_device *rdev);
  1088. extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  1089.                                                 struct radeon_cs_packet *pkt,
  1090.                                                 struct radeon_bo *robj);
  1091. extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  1092.                                 struct radeon_cs_packet *pkt,
  1093.                                 const unsigned *auth, unsigned n,
  1094.                                 radeon_packet0_check_t check);
  1095. extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
  1096.                                 struct radeon_cs_packet *pkt,
  1097.                                 unsigned idx);
  1098. extern void r100_enable_bm(struct radeon_device *rdev);
  1099. extern void r100_set_common_regs(struct radeon_device *rdev);
  1100.  
  1101. /* rv200,rv250,rv280 */
  1102. extern void r200_set_safe_registers(struct radeon_device *rdev);
  1103.  
  1104. /* r300,r350,rv350,rv370,rv380 */
  1105. extern void r300_set_reg_safe(struct radeon_device *rdev);
  1106. extern void r300_mc_program(struct radeon_device *rdev);
  1107. extern void r300_vram_info(struct radeon_device *rdev);
  1108. extern void r300_clock_startup(struct radeon_device *rdev);
  1109. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  1110. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
  1111. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
  1112. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
  1113. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
  1114.  
  1115. /* r420,r423,rv410 */
  1116. extern int r420_mc_init(struct radeon_device *rdev);
  1117. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
  1118. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  1119. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  1120. extern void r420_pipes_init(struct radeon_device *rdev);
  1121.  
  1122. /* rv515 */
  1123. struct rv515_mc_save {
  1124.         u32 d1vga_control;
  1125.         u32 d2vga_control;
  1126.         u32 vga_render_control;
  1127.         u32 vga_hdp_control;
  1128.         u32 d1crtc_control;
  1129.         u32 d2crtc_control;
  1130. };
  1131. extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  1132. extern void rv515_vga_render_disable(struct radeon_device *rdev);
  1133. extern void rv515_set_safe_registers(struct radeon_device *rdev);
  1134. extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
  1135. extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
  1136. extern void rv515_clock_startup(struct radeon_device *rdev);
  1137. extern void rv515_debugfs(struct radeon_device *rdev);
  1138. extern int rv515_suspend(struct radeon_device *rdev);
  1139.  
  1140. /* rs400 */
  1141. extern int rs400_gart_init(struct radeon_device *rdev);
  1142. extern int rs400_gart_enable(struct radeon_device *rdev);
  1143. extern void rs400_gart_adjust_size(struct radeon_device *rdev);
  1144. extern void rs400_gart_disable(struct radeon_device *rdev);
  1145. extern void rs400_gart_fini(struct radeon_device *rdev);
  1146.  
  1147. /* rs600 */
  1148. extern void rs600_set_safe_registers(struct radeon_device *rdev);
  1149. extern int rs600_irq_set(struct radeon_device *rdev);
  1150. extern void rs600_irq_disable(struct radeon_device *rdev);
  1151.  
  1152. /* rs690, rs740 */
  1153. extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
  1154.                                         struct drm_display_mode *mode1,
  1155.                                         struct drm_display_mode *mode2);
  1156.  
  1157. /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
  1158. extern bool r600_card_posted(struct radeon_device *rdev);
  1159. extern void r600_cp_stop(struct radeon_device *rdev);
  1160. extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1161. extern int r600_cp_resume(struct radeon_device *rdev);
  1162. extern void r600_cp_fini(struct radeon_device *rdev);
  1163. extern int r600_count_pipe_bits(uint32_t val);
  1164. extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
  1165. extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
  1166. extern int r600_pcie_gart_init(struct radeon_device *rdev);
  1167. extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  1168. extern int r600_ib_test(struct radeon_device *rdev);
  1169. extern int r600_ring_test(struct radeon_device *rdev);
  1170. extern void r600_wb_fini(struct radeon_device *rdev);
  1171. extern int r600_wb_enable(struct radeon_device *rdev);
  1172. extern void r600_wb_disable(struct radeon_device *rdev);
  1173. extern void r600_scratch_init(struct radeon_device *rdev);
  1174. extern int r600_blit_init(struct radeon_device *rdev);
  1175. extern void r600_blit_fini(struct radeon_device *rdev);
  1176. extern int r600_init_microcode(struct radeon_device *rdev);
  1177. extern int r600_gpu_reset(struct radeon_device *rdev);
  1178. /* r600 irq */
  1179. extern int r600_irq_init(struct radeon_device *rdev);
  1180. extern void r600_irq_fini(struct radeon_device *rdev);
  1181. extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1182. extern int r600_irq_set(struct radeon_device *rdev);
  1183. extern void r600_irq_suspend(struct radeon_device *rdev);
  1184. /* r600 audio */
  1185. extern int r600_audio_init(struct radeon_device *rdev);
  1186. extern int r600_audio_tmds_index(struct drm_encoder *encoder);
  1187. extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
  1188. extern void r600_audio_fini(struct radeon_device *rdev);
  1189. extern void r600_hdmi_init(struct drm_encoder *encoder);
  1190. extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
  1191. extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  1192. extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
  1193. extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
  1194.                                             int channels,
  1195.                                             int rate,
  1196.                                             int bps,
  1197.                                             uint8_t status_bits,
  1198.                                             uint8_t category_code);
  1199.  
  1200. #include "radeon_object.h"
  1201.  
  1202. #define DRM_UDELAY(d)           udelay(d)
  1203.  
  1204. resource_size_t
  1205. drm_get_resource_start(struct drm_device *dev, unsigned int resource);
  1206. resource_size_t
  1207. drm_get_resource_len(struct drm_device *dev, unsigned int resource);
  1208.  
  1209. bool set_mode(struct drm_device *dev, struct drm_connector *connector,
  1210.               videomode_t *mode, bool strict);
  1211.  
  1212.  
  1213. #endif
  1214.