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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30.  
  31. /* TODO: Here are things that needs to be done :
  32.  *      - surface allocator & initializer : (bit like scratch reg) should
  33.  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34.  *        related to surface
  35.  *      - WB : write back stuff (do it bit like scratch reg things)
  36.  *      - Vblank : look at Jesse's rework and what we should do
  37.  *      - r600/r700: gart & cp
  38.  *      - cs : clean cs ioctl use bitmap & things like that.
  39.  *      - power management stuff
  40.  *      - Barrier in gart code
  41.  *      - Unmappabled vram ?
  42.  *      - TESTING, TESTING, TESTING
  43.  */
  44.  
  45. /* Initialization path:
  46.  *  We expect that acceleration initialization might fail for various
  47.  *  reasons even thought we work hard to make it works on most
  48.  *  configurations. In order to still have a working userspace in such
  49.  *  situation the init path must succeed up to the memory controller
  50.  *  initialization point. Failure before this point are considered as
  51.  *  fatal error. Here is the init callchain :
  52.  *      radeon_device_init  perform common structure, mutex initialization
  53.  *      asic_init           setup the GPU memory layout and perform all
  54.  *                          one time initialization (failure in this
  55.  *                          function are considered fatal)
  56.  *      asic_startup        setup the GPU acceleration, in order to
  57.  *                          follow guideline the first thing this
  58.  *                          function should do is setting the GPU
  59.  *                          memory controller (only MC setup failure
  60.  *                          are considered as fatal)
  61.  */
  62.  
  63. #include <asm/atomic.h>
  64.  
  65. #include <linux/list.h>
  66. #include <linux/kref.h>
  67.  
  68. #include <ttm/ttm_bo_api.h>
  69. #include <ttm/ttm_bo_driver.h>
  70. #include <ttm/ttm_placement.h>
  71. #include <ttm/ttm_module.h>
  72.  
  73.  
  74. #include <pci.h>
  75.  
  76. #include <errno-base.h>
  77. #include "drm_edid.h"
  78.  
  79. #include "radeon_family.h"
  80. #include "radeon_mode.h"
  81. #include "radeon_reg.h"
  82.  
  83. #include <syscall.h>
  84.  
  85. /*
  86.  * Modules parameters.
  87.  */
  88. extern int radeon_no_wb;
  89. extern int radeon_modeset;
  90. extern int radeon_dynclks;
  91. extern int radeon_r4xx_atom;
  92. extern int radeon_agpmode;
  93. extern int radeon_vram_limit;
  94. extern int radeon_gart_size;
  95. extern int radeon_benchmarking;
  96. extern int radeon_testing;
  97. extern int radeon_connector_table;
  98. extern int radeon_tv;
  99. extern int radeon_new_pll;
  100.  
  101.  
  102. typedef struct
  103. {
  104.   int width;
  105.   int height;
  106.   int bpp;
  107.   int freq;
  108. }videomode_t;
  109.  
  110. static inline uint8_t __raw_readb(const volatile void __iomem *addr)
  111. {
  112.     return *(const volatile uint8_t __force *) addr;
  113. }
  114.  
  115. static inline uint16_t __raw_readw(const volatile void __iomem *addr)
  116. {
  117.     return *(const volatile uint16_t __force *) addr;
  118. }
  119.  
  120. static inline uint32_t __raw_readl(const volatile void __iomem *addr)
  121. {
  122.     return *(const volatile uint32_t __force *) addr;
  123. }
  124.  
  125. #define readb __raw_readb
  126. #define readw __raw_readw
  127. #define readl __raw_readl
  128.  
  129.  
  130.  
  131. static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
  132. {
  133.     *(volatile uint8_t __force *) addr = b;
  134. }
  135.  
  136. static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
  137. {
  138.     *(volatile uint16_t __force *) addr = b;
  139. }
  140.  
  141. static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
  142. {
  143.     *(volatile uint32_t __force *) addr = b;
  144. }
  145.  
  146. static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
  147. {
  148.         *(volatile __u64 *)addr = b;
  149. }
  150.  
  151. #define writeb __raw_writeb
  152. #define writew __raw_writew
  153. #define writel __raw_writel
  154. #define writeq __raw_writeq
  155.  
  156.  
  157. /*
  158.  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  159.  * symbol;
  160.  */
  161. #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  162. #define RADEON_IB_POOL_SIZE             16
  163. #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  164. #define RADEONFB_CONN_LIMIT             4
  165. #define RADEON_BIOS_NUM_SCRATCH         8
  166.  
  167. /*
  168.  * Errata workarounds.
  169.  */
  170. enum radeon_pll_errata {
  171.     CHIP_ERRATA_R300_CG             = 0x00000001,
  172.     CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  173.     CHIP_ERRATA_PLL_DELAY           = 0x00000004
  174. };
  175.  
  176.  
  177. struct radeon_device;
  178.  
  179.  
  180. /*
  181.  * BIOS.
  182.  */
  183. bool radeon_get_bios(struct radeon_device *rdev);
  184.  
  185.  
  186. /*
  187.  * Dummy page
  188.  */
  189. struct radeon_dummy_page {
  190.         struct page     *page;
  191.         dma_addr_t      addr;
  192. };
  193. int radeon_dummy_page_init(struct radeon_device *rdev);
  194. void radeon_dummy_page_fini(struct radeon_device *rdev);
  195.  
  196.  
  197. /*
  198.  * Clocks
  199.  */
  200. struct radeon_clock {
  201.         struct radeon_pll p1pll;
  202.         struct radeon_pll p2pll;
  203.         struct radeon_pll spll;
  204.         struct radeon_pll mpll;
  205.         /* 10 Khz units */
  206.         uint32_t default_mclk;
  207.         uint32_t default_sclk;
  208. };
  209.  
  210. /*
  211.  * Power management
  212.  */
  213. int radeon_pm_init(struct radeon_device *rdev);
  214.  
  215. /*
  216.  * Fences.
  217.  */
  218. struct radeon_fence_driver {
  219.         uint32_t                        scratch_reg;
  220.         atomic_t                        seq;
  221.         uint32_t                        last_seq;
  222.         unsigned long                   count_timeout;
  223. //      wait_queue_head_t               queue;
  224.         rwlock_t                        lock;
  225.         struct list_head                created;
  226.         struct list_head                emited;
  227.         struct list_head                signaled;
  228. };
  229.  
  230. struct radeon_fence {
  231.         struct radeon_device            *rdev;
  232.         struct kref                     kref;
  233.         struct list_head                list;
  234.         /* protected by radeon_fence.lock */
  235.         uint32_t                        seq;
  236.         unsigned long                   timeout;
  237.         bool                            emited;
  238.         bool                            signaled;
  239. };
  240.  
  241. int radeon_fence_driver_init(struct radeon_device *rdev);
  242. void radeon_fence_driver_fini(struct radeon_device *rdev);
  243. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
  244. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
  245. void radeon_fence_process(struct radeon_device *rdev);
  246. bool radeon_fence_signaled(struct radeon_fence *fence);
  247. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  248. int radeon_fence_wait_next(struct radeon_device *rdev);
  249. int radeon_fence_wait_last(struct radeon_device *rdev);
  250. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  251. void radeon_fence_unref(struct radeon_fence **fence);
  252.  
  253. /*
  254.  * Tiling registers
  255.  */
  256. struct radeon_surface_reg {
  257.         struct radeon_bo *bo;
  258. };
  259.  
  260. #define RADEON_GEM_MAX_SURFACES 8
  261.  
  262. /*
  263.  * TTM.
  264.  */
  265. struct radeon_mman {
  266.         struct ttm_bo_global_ref        bo_global_ref;
  267.         struct ttm_global_reference     mem_global_ref;
  268.         bool                            mem_global_referenced;
  269.         struct ttm_bo_device            bdev;
  270. };
  271.  
  272. struct radeon_bo {
  273.         /* Protected by gem.mutex */
  274.         struct list_head                list;
  275.         /* Protected by tbo.reserved */
  276.         u32                             placements[3];
  277.         struct ttm_placement            placement;
  278.         struct ttm_buffer_object        tbo;
  279.         struct ttm_bo_kmap_obj          kmap;
  280.         unsigned                        pin_count;
  281.         void                            *kptr;
  282.         u32                             tiling_flags;
  283.         u32                             pitch;
  284.         int                             surface_reg;
  285.         /* Constant after initialization */
  286.         struct radeon_device            *rdev;
  287.         struct drm_gem_object           *gobj;
  288. };
  289.  
  290. struct radeon_bo_list {
  291.         struct list_head        list;
  292.         struct radeon_bo        *bo;
  293.         uint64_t                gpu_offset;
  294.         unsigned                rdomain;
  295.         unsigned                wdomain;
  296.         u32                     tiling_flags;
  297. };
  298.  
  299. /*
  300.  * GEM objects.
  301.  */
  302. struct radeon_gem {
  303.         struct list_head        objects;
  304. };
  305.  
  306. int radeon_gem_init(struct radeon_device *rdev);
  307. void radeon_gem_fini(struct radeon_device *rdev);
  308. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  309.                              int alignment, int initial_domain,
  310.                              bool discardable, bool kernel,
  311.                              struct drm_gem_object **obj);
  312. int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
  313.                           uint64_t *gpu_addr);
  314. void radeon_gem_object_unpin(struct drm_gem_object *obj);
  315.  
  316.  
  317. /*
  318.  * GART structures, functions & helpers
  319.  */
  320. struct radeon_mc;
  321.  
  322. struct radeon_gart_table_ram {
  323.     volatile uint32_t       *ptr;
  324. };
  325.  
  326. struct radeon_gart_table_vram {
  327.         struct radeon_bo                *robj;
  328.     volatile uint32_t       *ptr;
  329. };
  330.  
  331. union radeon_gart_table {
  332.     struct radeon_gart_table_ram    ram;
  333.     struct radeon_gart_table_vram   vram;
  334. };
  335.  
  336. #define RADEON_GPU_PAGE_SIZE 4096
  337.  
  338. struct radeon_gart {
  339.     dma_addr_t          table_addr;
  340.     unsigned            num_gpu_pages;
  341.     unsigned            num_cpu_pages;
  342.     unsigned            table_size;
  343.     union radeon_gart_table     table;
  344.     struct page         **pages;
  345.     dma_addr_t          *pages_addr;
  346.     bool                ready;
  347. };
  348.  
  349. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  350. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  351. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  352. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  353. int radeon_gart_init(struct radeon_device *rdev);
  354. void radeon_gart_fini(struct radeon_device *rdev);
  355. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  356.                         int pages);
  357. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  358.             int pages, u32_t *pagelist);
  359.  
  360.  
  361. /*
  362.  * GPU MC structures, functions & helpers
  363.  */
  364. struct radeon_mc {
  365.     resource_size_t     aper_size;
  366.     resource_size_t     aper_base;
  367.     resource_size_t     agp_base;
  368.         /* for some chips with <= 32MB we need to lie
  369.          * about vram size near mc fb location */
  370.         u64                     mc_vram_size;
  371.         u64                     gtt_location;
  372.         u64                     gtt_size;
  373.         u64                     gtt_start;
  374.         u64                     gtt_end;
  375.         u64                     vram_location;
  376.         u64                     vram_start;
  377.         u64                     vram_end;
  378.     unsigned            vram_width;
  379.         u64                     real_vram_size;
  380.     int                 vram_mtrr;
  381.     bool                vram_is_ddr;
  382. };
  383.  
  384. int radeon_mc_setup(struct radeon_device *rdev);
  385.  
  386.  
  387. /*
  388.  * GPU scratch registers structures, functions & helpers
  389.  */
  390. struct radeon_scratch {
  391.     unsigned        num_reg;
  392.     bool            free[32];
  393.     uint32_t        reg[32];
  394. };
  395.  
  396. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  397. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  398.  
  399.  
  400. /*
  401.  * IRQS.
  402.  */
  403. struct radeon_irq {
  404.         bool            installed;
  405.         bool            sw_int;
  406.         /* FIXME: use a define max crtc rather than hardcode it */
  407.         bool            crtc_vblank_int[2];
  408.         /* FIXME: use defines for max hpd/dacs */
  409.         bool            hpd[6];
  410.     spinlock_t  sw_lock;
  411.         int sw_refcount;
  412. };
  413.  
  414. int radeon_irq_kms_init(struct radeon_device *rdev);
  415. void radeon_irq_kms_fini(struct radeon_device *rdev);
  416. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
  417. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
  418.  
  419. /*
  420.  * CP & ring.
  421.  */
  422. struct radeon_ib {
  423.         struct list_head        list;
  424.         unsigned long           idx;
  425.         uint64_t                gpu_addr;
  426.         struct radeon_fence     *fence;
  427.         uint32_t        *ptr;
  428.         uint32_t                length_dw;
  429. };
  430.  
  431. /*
  432.  * locking -
  433.  * mutex protects scheduled_ibs, ready, alloc_bm
  434.  */
  435. struct radeon_ib_pool {
  436. //      struct mutex            mutex;
  437.         struct radeon_bo        *robj;
  438.         struct list_head        scheduled_ibs;
  439.         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
  440.         bool                    ready;
  441.         DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
  442. };
  443.  
  444. struct radeon_cp {
  445.         struct radeon_bo        *ring_obj;
  446.         volatile uint32_t       *ring;
  447.         unsigned                rptr;
  448.         unsigned                wptr;
  449.         unsigned                wptr_old;
  450.         unsigned                ring_size;
  451.         unsigned                ring_free_dw;
  452.         int                     count_dw;
  453.         uint64_t                gpu_addr;
  454.         uint32_t                align_mask;
  455.         uint32_t                ptr_mask;
  456. //      struct mutex            mutex;
  457.         bool                    ready;
  458. };
  459.  
  460. /*
  461.  * R6xx+ IH ring
  462.  */
  463. struct r600_ih {
  464.         struct radeon_bo        *ring_obj;
  465.         volatile uint32_t       *ring;
  466.     unsigned            rptr;
  467.     unsigned            wptr;
  468.     unsigned            wptr_old;
  469.     unsigned            ring_size;
  470.     uint64_t            gpu_addr;
  471.     uint32_t            align_mask;
  472.     uint32_t            ptr_mask;
  473.     spinlock_t              lock;
  474.     bool                enabled;
  475. };
  476.  
  477. struct r600_blit {
  478.         struct radeon_bo        *shader_obj;
  479.         u64 shader_gpu_addr;
  480.         u32 vs_offset, ps_offset;
  481.         u32 state_offset;
  482.         u32 state_len;
  483.         u32 vb_used, vb_total;
  484.         struct radeon_ib *vb_ib;
  485. };
  486.  
  487. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
  488. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
  489. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
  490. int radeon_ib_pool_init(struct radeon_device *rdev);
  491. void radeon_ib_pool_fini(struct radeon_device *rdev);
  492. int radeon_ib_test(struct radeon_device *rdev);
  493. /* Ring access between begin & end cannot sleep */
  494. void radeon_ring_free_size(struct radeon_device *rdev);
  495. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
  496. void radeon_ring_unlock_commit(struct radeon_device *rdev);
  497. void radeon_ring_unlock_undo(struct radeon_device *rdev);
  498. int radeon_ring_test(struct radeon_device *rdev);
  499. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
  500. void radeon_ring_fini(struct radeon_device *rdev);
  501.  
  502.  
  503. /*
  504.  * CS.
  505.  */
  506. struct radeon_cs_reloc {
  507. //      struct drm_gem_object           *gobj;
  508.         struct radeon_bo                *robj;
  509. //    struct radeon_bo_list   lobj;
  510.         uint32_t                        handle;
  511.         uint32_t                        flags;
  512. };
  513.  
  514. struct radeon_cs_chunk {
  515.         uint32_t                chunk_id;
  516.         uint32_t                length_dw;
  517.         int kpage_idx[2];
  518.         uint32_t                *kpage[2];
  519.         uint32_t                *kdata;
  520.         void __user *user_ptr;
  521.         int last_copied_page;
  522.         int last_page_index;
  523. };
  524.  
  525. struct radeon_cs_parser {
  526.         struct radeon_device    *rdev;
  527. //      struct drm_file         *filp;
  528.         /* chunks */
  529.         unsigned                nchunks;
  530.         struct radeon_cs_chunk  *chunks;
  531.         uint64_t                *chunks_array;
  532.         /* IB */
  533.         unsigned                idx;
  534.         /* relocations */
  535.         unsigned                nrelocs;
  536.         struct radeon_cs_reloc  *relocs;
  537.         struct radeon_cs_reloc  **relocs_ptr;
  538.         struct list_head        validated;
  539.         /* indices of various chunks */
  540.         int                     chunk_ib_idx;
  541.         int                     chunk_relocs_idx;
  542.         struct radeon_ib        *ib;
  543.         void                    *track;
  544.         unsigned                family;
  545.         int parser_error;
  546. };
  547.  
  548. extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
  549. extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
  550.  
  551.  
  552. static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  553. {
  554.         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  555.         u32 pg_idx, pg_offset;
  556.         u32 idx_value = 0;
  557.         int new_page;
  558.  
  559.         pg_idx = (idx * 4) / PAGE_SIZE;
  560.         pg_offset = (idx * 4) % PAGE_SIZE;
  561.  
  562.         if (ibc->kpage_idx[0] == pg_idx)
  563.                 return ibc->kpage[0][pg_offset/4];
  564.         if (ibc->kpage_idx[1] == pg_idx)
  565.                 return ibc->kpage[1][pg_offset/4];
  566.  
  567.         new_page = radeon_cs_update_pages(p, pg_idx);
  568.         if (new_page < 0) {
  569.                 p->parser_error = new_page;
  570.                 return 0;
  571.         }
  572.  
  573.         idx_value = ibc->kpage[new_page][pg_offset/4];
  574.         return idx_value;
  575. }
  576.  
  577. struct radeon_cs_packet {
  578.         unsigned        idx;
  579.         unsigned        type;
  580.         unsigned        reg;
  581.         unsigned        opcode;
  582.         int             count;
  583.         unsigned        one_reg_wr;
  584. };
  585.  
  586. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  587.                                       struct radeon_cs_packet *pkt,
  588.                                       unsigned idx, unsigned reg);
  589. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  590.                                       struct radeon_cs_packet *pkt);
  591.  
  592.  
  593. /*
  594.  * AGP
  595.  */
  596. int radeon_agp_init(struct radeon_device *rdev);
  597. void radeon_agp_resume(struct radeon_device *rdev);
  598. void radeon_agp_fini(struct radeon_device *rdev);
  599.  
  600.  
  601. /*
  602.  * Writeback
  603.  */
  604. struct radeon_wb {
  605.         struct radeon_bo        *wb_obj;
  606.         volatile uint32_t       *wb;
  607.         uint64_t                gpu_addr;
  608. };
  609.  
  610. /**
  611.  * struct radeon_pm - power management datas
  612.  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
  613.  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  614.  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
  615.  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
  616.  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
  617.  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
  618.  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  619.  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
  620.  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
  621.  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
  622.  * @needed_bandwidth:   current bandwidth needs
  623.  *
  624.  * It keeps track of various data needed to take powermanagement decision.
  625.  * Bandwith need is used to determine minimun clock of the GPU and memory.
  626.  * Equation between gpu/memory clock and available bandwidth is hw dependent
  627.  * (type of memory, bus size, efficiency, ...)
  628.  */
  629. struct radeon_pm {
  630.         fixed20_12              max_bandwidth;
  631.         fixed20_12              igp_sideport_mclk;
  632.         fixed20_12              igp_system_mclk;
  633.         fixed20_12              igp_ht_link_clk;
  634.         fixed20_12              igp_ht_link_width;
  635.         fixed20_12              k8_bandwidth;
  636.         fixed20_12              sideport_bandwidth;
  637.         fixed20_12              ht_bandwidth;
  638.         fixed20_12              core_bandwidth;
  639.         fixed20_12              sclk;
  640.         fixed20_12              needed_bandwidth;
  641. };
  642.  
  643. /*
  644.  * ASIC specific functions.
  645.  */
  646. struct radeon_asic {
  647.         int (*init)(struct radeon_device *rdev);
  648.         void (*fini)(struct radeon_device *rdev);
  649.         int (*resume)(struct radeon_device *rdev);
  650.         int (*suspend)(struct radeon_device *rdev);
  651.         void (*vga_set_state)(struct radeon_device *rdev, bool state);
  652.         int (*gpu_reset)(struct radeon_device *rdev);
  653.         void (*gart_tlb_flush)(struct radeon_device *rdev);
  654.         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  655.         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
  656.         void (*cp_fini)(struct radeon_device *rdev);
  657.         void (*cp_disable)(struct radeon_device *rdev);
  658.         void (*cp_commit)(struct radeon_device *rdev);
  659.         void (*ring_start)(struct radeon_device *rdev);
  660.         int (*ring_test)(struct radeon_device *rdev);
  661.         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  662.         int (*irq_set)(struct radeon_device *rdev);
  663.         int (*irq_process)(struct radeon_device *rdev);
  664.         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  665.         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
  666.         int (*cs_parse)(struct radeon_cs_parser *p);
  667.         int (*copy_blit)(struct radeon_device *rdev,
  668.                          uint64_t src_offset,
  669.                          uint64_t dst_offset,
  670.                          unsigned num_pages,
  671.                          struct radeon_fence *fence);
  672.         int (*copy_dma)(struct radeon_device *rdev,
  673.                         uint64_t src_offset,
  674.                         uint64_t dst_offset,
  675.                         unsigned num_pages,
  676.                         struct radeon_fence *fence);
  677.         int (*copy)(struct radeon_device *rdev,
  678.                     uint64_t src_offset,
  679.                     uint64_t dst_offset,
  680.                     unsigned num_pages,
  681.                     struct radeon_fence *fence);
  682.         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
  683.         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  684.         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
  685.         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  686.         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  687.         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  688.         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
  689.                                uint32_t tiling_flags, uint32_t pitch,
  690.                                uint32_t offset, uint32_t obj_size);
  691.         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
  692.         void (*bandwidth_update)(struct radeon_device *rdev);
  693.         void (*hdp_flush)(struct radeon_device *rdev);
  694.         void (*hpd_init)(struct radeon_device *rdev);
  695.         void (*hpd_fini)(struct radeon_device *rdev);
  696.         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  697.         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  698. };
  699.  
  700. /*
  701.  * Asic structures
  702.  */
  703. struct r100_asic {
  704.         const unsigned  *reg_safe_bm;
  705.         unsigned        reg_safe_bm_size;
  706. };
  707.  
  708. struct r300_asic {
  709.         const unsigned  *reg_safe_bm;
  710.         unsigned        reg_safe_bm_size;
  711. };
  712.  
  713. struct r600_asic {
  714.         unsigned max_pipes;
  715.         unsigned max_tile_pipes;
  716.         unsigned max_simds;
  717.         unsigned max_backends;
  718.         unsigned max_gprs;
  719.         unsigned max_threads;
  720.         unsigned max_stack_entries;
  721.         unsigned max_hw_contexts;
  722.         unsigned max_gs_threads;
  723.         unsigned sx_max_export_size;
  724.         unsigned sx_max_export_pos_size;
  725.         unsigned sx_max_export_smx_size;
  726.         unsigned sq_num_cf_insts;
  727. };
  728.  
  729. struct rv770_asic {
  730.         unsigned max_pipes;
  731.         unsigned max_tile_pipes;
  732.         unsigned max_simds;
  733.         unsigned max_backends;
  734.         unsigned max_gprs;
  735.         unsigned max_threads;
  736.         unsigned max_stack_entries;
  737.         unsigned max_hw_contexts;
  738.         unsigned max_gs_threads;
  739.         unsigned sx_max_export_size;
  740.         unsigned sx_max_export_pos_size;
  741.         unsigned sx_max_export_smx_size;
  742.         unsigned sq_num_cf_insts;
  743.         unsigned sx_num_of_sets;
  744.         unsigned sc_prim_fifo_size;
  745.         unsigned sc_hiz_tile_fifo_size;
  746.         unsigned sc_earlyz_tile_fifo_fize;
  747. };
  748.  
  749. union radeon_asic_config {
  750.         struct r300_asic        r300;
  751.         struct r100_asic        r100;
  752.         struct r600_asic        r600;
  753.         struct rv770_asic       rv770;
  754. };
  755.  
  756.  
  757. /*
  758.  
  759.  
  760.  
  761.  
  762. /*
  763.  * Core structure, functions and helpers.
  764.  */
  765. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  766. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  767.  
  768. struct radeon_device {
  769.         void                               *dev;
  770.     struct drm_device          *ddev;
  771.     struct pci_dev             *pdev;
  772.     /* ASIC */
  773.     union radeon_asic_config    config;
  774.     enum radeon_family          family;
  775.     unsigned long               flags;
  776.     int                         usec_timeout;
  777.     enum radeon_pll_errata      pll_errata;
  778.     int                         num_gb_pipes;
  779.         int                             num_z_pipes;
  780.     int                         disp_priority;
  781.     /* BIOS */
  782.     uint8_t                     *bios;
  783.     bool                        is_atom_bios;
  784.     uint16_t                    bios_header_start;
  785.         struct radeon_bo                *stollen_vga_memory;
  786.     struct fb_info              *fbdev_info;
  787.         struct radeon_bo                *fbdev_rbo;
  788.     struct radeon_framebuffer   *fbdev_rfb;
  789.     /* Register mmio */
  790.     unsigned long               rmmio_base;
  791.     unsigned long               rmmio_size;
  792.     void                       *rmmio;
  793.     radeon_rreg_t               mc_rreg;
  794.     radeon_wreg_t               mc_wreg;
  795.     radeon_rreg_t               pll_rreg;
  796.     radeon_wreg_t               pll_wreg;
  797.         uint32_t                        pcie_reg_mask;
  798.     radeon_rreg_t               pciep_rreg;
  799.     radeon_wreg_t               pciep_wreg;
  800.     struct radeon_clock         clock;
  801.     struct radeon_mc            mc;
  802.     struct radeon_gart          gart;
  803.         struct radeon_mode_info         mode_info;
  804.     struct radeon_scratch       scratch;
  805.     struct radeon_mman          mman;
  806.         struct radeon_fence_driver      fence_drv;
  807.     struct radeon_cp            cp;
  808.     struct radeon_ib_pool       ib_pool;
  809. //    struct radeon_irq       irq;
  810.     struct radeon_asic         *asic;
  811.     struct radeon_gem       gem;
  812.         struct radeon_pm                pm;
  813.         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  814. //    struct mutex            cs_mutex;
  815.     struct radeon_wb        wb;
  816.         struct radeon_dummy_page        dummy_page;
  817.     bool                gpu_lockup;
  818.     bool                shutdown;
  819.     bool                suspend;
  820.         bool                            need_dma32;
  821.         bool                            accel_working;
  822.         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  823.         const struct firmware *me_fw;   /* all family ME firmware */
  824.         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
  825.         struct r600_blit r600_blit;
  826.         int msi_enabled; /* msi enabled */
  827. };
  828.  
  829. int radeon_device_init(struct radeon_device *rdev,
  830.                        struct drm_device *ddev,
  831.                        struct pci_dev *pdev,
  832.                        uint32_t flags);
  833. void radeon_device_fini(struct radeon_device *rdev);
  834. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  835.  
  836. /* r600 blit */
  837. int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
  838. void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
  839. void r600_kms_blit_copy(struct radeon_device *rdev,
  840.                         u64 src_gpu_addr, u64 dst_gpu_addr,
  841.                         int size_bytes);
  842.  
  843. static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
  844. {
  845.         if (reg < 0x10000)
  846.                 return readl(((void __iomem *)rdev->rmmio) + reg);
  847.         else {
  848.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  849.                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  850.         }
  851. }
  852.  
  853. static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  854. {
  855.         if (reg < 0x10000)
  856.                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
  857.         else {
  858.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  859.                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  860.         }
  861. }
  862.  
  863. /*
  864.  * Cast helper
  865.  */
  866. #define to_radeon_fence(p) ((struct radeon_fence *)(p))
  867.  
  868. /*
  869.  * Registers read & write functions.
  870.  */
  871. #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
  872. #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
  873. #define RREG32(reg) r100_mm_rreg(rdev, (reg))
  874. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
  875. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  876. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  877. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  878. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  879. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  880. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  881. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  882. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  883. #define WREG32_P(reg, val, mask)                                \
  884.         do {                                                    \
  885.                 uint32_t tmp_ = RREG32(reg);                    \
  886.                 tmp_ &= (mask);                                 \
  887.                 tmp_ |= ((val) & ~(mask));                      \
  888.                 WREG32(reg, tmp_);                              \
  889.         } while (0)
  890. #define WREG32_PLL_P(reg, val, mask)                            \
  891.         do {                                                    \
  892.                 uint32_t tmp_ = RREG32_PLL(reg);                \
  893.                 tmp_ &= (mask);                                 \
  894.                 tmp_ |= ((val) & ~(mask));                      \
  895.                 WREG32_PLL(reg, tmp_);                          \
  896.         } while (0)
  897.  
  898. /*
  899.  * Indirect registers accessor
  900.  */
  901. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  902. {
  903.         uint32_t r;
  904.  
  905.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  906.         r = RREG32(RADEON_PCIE_DATA);
  907.         return r;
  908. }
  909.  
  910. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  911. {
  912.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  913.         WREG32(RADEON_PCIE_DATA, (v));
  914. }
  915.  
  916. void r100_pll_errata_after_index(struct radeon_device *rdev);
  917.  
  918.  
  919. /*
  920.  * ASICs helpers.
  921.  */
  922. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  923.                             (rdev->pdev->device == 0x5969))
  924. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  925.         (rdev->family == CHIP_RV200) || \
  926.         (rdev->family == CHIP_RS100) || \
  927.         (rdev->family == CHIP_RS200) || \
  928.         (rdev->family == CHIP_RV250) || \
  929.         (rdev->family == CHIP_RV280) || \
  930.         (rdev->family == CHIP_RS300))
  931. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
  932.         (rdev->family == CHIP_RV350) ||         \
  933.         (rdev->family == CHIP_R350)  ||         \
  934.         (rdev->family == CHIP_RV380) ||         \
  935.         (rdev->family == CHIP_R420)  ||         \
  936.         (rdev->family == CHIP_R423)  ||         \
  937.         (rdev->family == CHIP_RV410) ||         \
  938.         (rdev->family == CHIP_RS400) ||         \
  939.         (rdev->family == CHIP_RS480))
  940. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  941. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  942. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  943.  
  944.  
  945. /*
  946.  * BIOS helpers.
  947.  */
  948. #define RBIOS8(i) (rdev->bios[i])
  949. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  950. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  951.  
  952. int radeon_combios_init(struct radeon_device *rdev);
  953. void radeon_combios_fini(struct radeon_device *rdev);
  954. int radeon_atombios_init(struct radeon_device *rdev);
  955. void radeon_atombios_fini(struct radeon_device *rdev);
  956.  
  957.  
  958. /*
  959.  * RING helpers.
  960.  */
  961. static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  962. {
  963. #if DRM_DEBUG_CODE
  964.         if (rdev->cp.count_dw <= 0) {
  965.                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  966.         }
  967. #endif
  968.         rdev->cp.ring[rdev->cp.wptr++] = v;
  969.         rdev->cp.wptr &= rdev->cp.ptr_mask;
  970.         rdev->cp.count_dw--;
  971.         rdev->cp.ring_free_dw--;
  972. }
  973.  
  974.  
  975. /*
  976.  * ASICs macro.
  977.  */
  978. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  979. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  980. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  981. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  982. #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
  983. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  984. #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
  985. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
  986. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
  987. #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
  988. #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
  989. #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
  990. #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
  991. #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
  992. #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
  993. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
  994. #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
  995. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
  996. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
  997. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
  998. #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
  999. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  1000. #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
  1001. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
  1002. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
  1003. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
  1004. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
  1005. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
  1006. #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
  1007. #define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
  1008. #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
  1009. #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
  1010. #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
  1011. #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
  1012.  
  1013. /* Common functions */
  1014. extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  1015. extern int radeon_modeset_init(struct radeon_device *rdev);
  1016. extern void radeon_modeset_fini(struct radeon_device *rdev);
  1017. extern bool radeon_card_posted(struct radeon_device *rdev);
  1018. extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
  1019. extern int radeon_clocks_init(struct radeon_device *rdev);
  1020. extern void radeon_clocks_fini(struct radeon_device *rdev);
  1021. extern void radeon_scratch_init(struct radeon_device *rdev);
  1022. extern void radeon_surface_init(struct radeon_device *rdev);
  1023. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  1024. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  1025. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  1026. extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
  1027.  
  1028. /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
  1029. struct r100_mc_save {
  1030.         u32     GENMO_WT;
  1031.         u32     CRTC_EXT_CNTL;
  1032.         u32     CRTC_GEN_CNTL;
  1033.         u32     CRTC2_GEN_CNTL;
  1034.         u32     CUR_OFFSET;
  1035.         u32     CUR2_OFFSET;
  1036. };
  1037. extern void r100_cp_disable(struct radeon_device *rdev);
  1038. extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  1039. extern void r100_cp_fini(struct radeon_device *rdev);
  1040. extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  1041. extern int r100_pci_gart_init(struct radeon_device *rdev);
  1042. extern void r100_pci_gart_fini(struct radeon_device *rdev);
  1043. extern int r100_pci_gart_enable(struct radeon_device *rdev);
  1044. extern void r100_pci_gart_disable(struct radeon_device *rdev);
  1045. extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  1046. extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  1047. extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
  1048. extern void r100_ib_fini(struct radeon_device *rdev);
  1049. extern int r100_ib_init(struct radeon_device *rdev);
  1050. extern void r100_irq_disable(struct radeon_device *rdev);
  1051. extern int r100_irq_set(struct radeon_device *rdev);
  1052. extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
  1053. extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
  1054. extern void r100_vram_init_sizes(struct radeon_device *rdev);
  1055. extern void r100_wb_disable(struct radeon_device *rdev);
  1056. extern void r100_wb_fini(struct radeon_device *rdev);
  1057. extern int r100_wb_init(struct radeon_device *rdev);
  1058. extern void r100_hdp_reset(struct radeon_device *rdev);
  1059. extern int r100_rb2d_reset(struct radeon_device *rdev);
  1060. extern int r100_cp_reset(struct radeon_device *rdev);
  1061. extern void r100_vga_render_disable(struct radeon_device *rdev);
  1062. extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  1063.                                                 struct radeon_cs_packet *pkt,
  1064.                                                 struct radeon_bo *robj);
  1065. extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  1066.                                 struct radeon_cs_packet *pkt,
  1067.                                 const unsigned *auth, unsigned n,
  1068.                                 radeon_packet0_check_t check);
  1069. extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
  1070.                                 struct radeon_cs_packet *pkt,
  1071.                                 unsigned idx);
  1072. extern void r100_enable_bm(struct radeon_device *rdev);
  1073. extern void r100_set_common_regs(struct radeon_device *rdev);
  1074.  
  1075. /* rv200,rv250,rv280 */
  1076. extern void r200_set_safe_registers(struct radeon_device *rdev);
  1077.  
  1078. /* r300,r350,rv350,rv370,rv380 */
  1079. extern void r300_set_reg_safe(struct radeon_device *rdev);
  1080. extern void r300_mc_program(struct radeon_device *rdev);
  1081. extern void r300_vram_info(struct radeon_device *rdev);
  1082. extern void r300_clock_startup(struct radeon_device *rdev);
  1083. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  1084. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
  1085. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
  1086. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
  1087. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
  1088.  
  1089. /* r420,r423,rv410 */
  1090. extern int r420_mc_init(struct radeon_device *rdev);
  1091. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
  1092. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  1093. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  1094. extern void r420_pipes_init(struct radeon_device *rdev);
  1095.  
  1096. /* rv515 */
  1097. struct rv515_mc_save {
  1098.         u32 d1vga_control;
  1099.         u32 d2vga_control;
  1100.         u32 vga_render_control;
  1101.         u32 vga_hdp_control;
  1102.         u32 d1crtc_control;
  1103.         u32 d2crtc_control;
  1104. };
  1105. extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  1106. extern void rv515_vga_render_disable(struct radeon_device *rdev);
  1107. extern void rv515_set_safe_registers(struct radeon_device *rdev);
  1108. extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
  1109. extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
  1110. extern void rv515_clock_startup(struct radeon_device *rdev);
  1111. extern void rv515_debugfs(struct radeon_device *rdev);
  1112. extern int rv515_suspend(struct radeon_device *rdev);
  1113.  
  1114. /* rs400 */
  1115. extern int rs400_gart_init(struct radeon_device *rdev);
  1116. extern int rs400_gart_enable(struct radeon_device *rdev);
  1117. extern void rs400_gart_adjust_size(struct radeon_device *rdev);
  1118. extern void rs400_gart_disable(struct radeon_device *rdev);
  1119. extern void rs400_gart_fini(struct radeon_device *rdev);
  1120.  
  1121. /* rs600 */
  1122. extern void rs600_set_safe_registers(struct radeon_device *rdev);
  1123. extern int rs600_irq_set(struct radeon_device *rdev);
  1124. extern void rs600_irq_disable(struct radeon_device *rdev);
  1125.  
  1126. /* rs690, rs740 */
  1127. extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
  1128.                                         struct drm_display_mode *mode1,
  1129.                                         struct drm_display_mode *mode2);
  1130.  
  1131. /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
  1132. extern bool r600_card_posted(struct radeon_device *rdev);
  1133. extern void r600_cp_stop(struct radeon_device *rdev);
  1134. extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1135. extern int r600_cp_resume(struct radeon_device *rdev);
  1136. extern int r600_count_pipe_bits(uint32_t val);
  1137. extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
  1138. extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
  1139. extern int r600_pcie_gart_init(struct radeon_device *rdev);
  1140. extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  1141. extern int r600_ib_test(struct radeon_device *rdev);
  1142. extern int r600_ring_test(struct radeon_device *rdev);
  1143. extern void r600_wb_fini(struct radeon_device *rdev);
  1144. extern int r600_wb_enable(struct radeon_device *rdev);
  1145. extern void r600_wb_disable(struct radeon_device *rdev);
  1146. extern void r600_scratch_init(struct radeon_device *rdev);
  1147. extern int r600_blit_init(struct radeon_device *rdev);
  1148. extern void r600_blit_fini(struct radeon_device *rdev);
  1149. extern int r600_init_microcode(struct radeon_device *rdev);
  1150. extern int r600_gpu_reset(struct radeon_device *rdev);
  1151. /* r600 irq */
  1152. extern int r600_irq_init(struct radeon_device *rdev);
  1153. extern void r600_irq_fini(struct radeon_device *rdev);
  1154. extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1155. extern int r600_irq_set(struct radeon_device *rdev);
  1156.  
  1157. #include "radeon_object.h"
  1158.  
  1159. #define DRM_UDELAY(d)           udelay(d)
  1160.  
  1161. resource_size_t
  1162. drm_get_resource_start(struct drm_device *dev, unsigned int resource);
  1163. resource_size_t
  1164. drm_get_resource_len(struct drm_device *dev, unsigned int resource);
  1165.  
  1166. bool set_mode(struct drm_device *dev, struct drm_connector *connector,
  1167.               mode_t *mode, bool strict);
  1168.  
  1169.  
  1170. #endif
  1171.