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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30.  
  31. //#include "radeon_object.h"
  32.  
  33. /* TODO: Here are things that needs to be done :
  34.  *      - surface allocator & initializer : (bit like scratch reg) should
  35.  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  36.  *        related to surface
  37.  *      - WB : write back stuff (do it bit like scratch reg things)
  38.  *      - Vblank : look at Jesse's rework and what we should do
  39.  *      - r600/r700: gart & cp
  40.  *      - cs : clean cs ioctl use bitmap & things like that.
  41.  *      - power management stuff
  42.  *      - Barrier in gart code
  43.  *      - Unmappabled vram ?
  44.  *      - TESTING, TESTING, TESTING
  45.  */
  46.  
  47. /* Initialization path:
  48.  *  We expect that acceleration initialization might fail for various
  49.  *  reasons even thought we work hard to make it works on most
  50.  *  configurations. In order to still have a working userspace in such
  51.  *  situation the init path must succeed up to the memory controller
  52.  *  initialization point. Failure before this point are considered as
  53.  *  fatal error. Here is the init callchain :
  54.  *      radeon_device_init  perform common structure, mutex initialization
  55.  *      asic_init           setup the GPU memory layout and perform all
  56.  *                          one time initialization (failure in this
  57.  *                          function are considered fatal)
  58.  *      asic_startup        setup the GPU acceleration, in order to
  59.  *                          follow guideline the first thing this
  60.  *                          function should do is setting the GPU
  61.  *                          memory controller (only MC setup failure
  62.  *                          are considered as fatal)
  63.  */
  64.  
  65.  
  66. #include <types.h>
  67.  
  68.  
  69. #include <linux/list.h>
  70.  
  71. #include <pci.h>
  72.  
  73. #include <errno-base.h>
  74. #include "drm_edid.h"
  75.  
  76. #include "radeon_family.h"
  77. #include "radeon_mode.h"
  78. #include "radeon_reg.h"
  79.  
  80. #include <syscall.h>
  81.  
  82. /*
  83.  * Modules parameters.
  84.  */
  85. extern int radeon_no_wb;
  86. extern int radeon_modeset;
  87. extern int radeon_dynclks;
  88. extern int radeon_r4xx_atom;
  89. extern int radeon_agpmode;
  90. extern int radeon_vram_limit;
  91. extern int radeon_gart_size;
  92. extern int radeon_benchmarking;
  93. extern int radeon_testing;
  94. extern int radeon_connector_table;
  95. extern int radeon_tv;
  96.  
  97. typedef struct
  98. {
  99.   int width;
  100.   int height;
  101.   int bpp;
  102.   int freq;
  103. }mode_t;
  104.  
  105. static inline uint8_t __raw_readb(const volatile void __iomem *addr)
  106. {
  107.     return *(const volatile uint8_t __force *) addr;
  108. }
  109.  
  110. static inline uint16_t __raw_readw(const volatile void __iomem *addr)
  111. {
  112.     return *(const volatile uint16_t __force *) addr;
  113. }
  114.  
  115. static inline uint32_t __raw_readl(const volatile void __iomem *addr)
  116. {
  117.     return *(const volatile uint32_t __force *) addr;
  118. }
  119.  
  120. #define readb __raw_readb
  121. #define readw __raw_readw
  122. #define readl __raw_readl
  123.  
  124.  
  125.  
  126. static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
  127. {
  128.     *(volatile uint8_t __force *) addr = b;
  129. }
  130.  
  131. static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
  132. {
  133.     *(volatile uint16_t __force *) addr = b;
  134. }
  135.  
  136. static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
  137. {
  138.     *(volatile uint32_t __force *) addr = b;
  139. }
  140.  
  141. static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
  142. {
  143.         *(volatile __u64 *)addr = b;
  144. }
  145.  
  146. #define writeb __raw_writeb
  147. #define writew __raw_writew
  148. #define writel __raw_writel
  149. #define writeq __raw_writeq
  150.  
  151.  
  152. /*
  153.  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  154.  * symbol;
  155.  */
  156. #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  157. #define RADEON_IB_POOL_SIZE             16
  158. #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  159. #define RADEONFB_CONN_LIMIT             4
  160. #define RADEON_BIOS_NUM_SCRATCH         8
  161.  
  162. /*
  163.  * Errata workarounds.
  164.  */
  165. enum radeon_pll_errata {
  166.     CHIP_ERRATA_R300_CG             = 0x00000001,
  167.     CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  168.     CHIP_ERRATA_PLL_DELAY           = 0x00000004
  169. };
  170.  
  171.  
  172. struct radeon_device;
  173.  
  174.  
  175. /*
  176.  * BIOS.
  177.  */
  178. bool radeon_get_bios(struct radeon_device *rdev);
  179.  
  180.  
  181. /*
  182.  * Dummy page
  183.  */
  184. struct radeon_dummy_page {
  185.         struct page     *page;
  186.         dma_addr_t      addr;
  187. };
  188. int radeon_dummy_page_init(struct radeon_device *rdev);
  189. void radeon_dummy_page_fini(struct radeon_device *rdev);
  190.  
  191.  
  192. /*
  193.  * Clocks
  194.  */
  195. struct radeon_clock {
  196.         struct radeon_pll p1pll;
  197.         struct radeon_pll p2pll;
  198.         struct radeon_pll spll;
  199.         struct radeon_pll mpll;
  200.         /* 10 Khz units */
  201.         uint32_t default_mclk;
  202.         uint32_t default_sclk;
  203. };
  204.  
  205.  
  206. /*
  207.  * Fences.
  208.  */
  209. struct radeon_fence_driver {
  210.         uint32_t                        scratch_reg;
  211. //      atomic_t                        seq;
  212.         uint32_t                        last_seq;
  213.         unsigned long                   count_timeout;
  214. //      wait_queue_head_t               queue;
  215. //      rwlock_t                        lock;
  216.         struct list_head                created;
  217.         struct list_head                emited;
  218.         struct list_head                signaled;
  219. };
  220.  
  221. struct radeon_fence {
  222.         struct radeon_device            *rdev;
  223. //      struct kref                     kref;
  224.         struct list_head                list;
  225.         /* protected by radeon_fence.lock */
  226.         uint32_t                        seq;
  227.         unsigned long                   timeout;
  228.         bool                            emited;
  229.         bool                            signaled;
  230. };
  231.  
  232. int radeon_fence_driver_init(struct radeon_device *rdev);
  233. void radeon_fence_driver_fini(struct radeon_device *rdev);
  234. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
  235. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
  236. void radeon_fence_process(struct radeon_device *rdev);
  237. bool radeon_fence_signaled(struct radeon_fence *fence);
  238. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  239. int radeon_fence_wait_next(struct radeon_device *rdev);
  240. int radeon_fence_wait_last(struct radeon_device *rdev);
  241. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  242. void radeon_fence_unref(struct radeon_fence **fence);
  243.  
  244. /*
  245.  * Tiling registers
  246.  */
  247. struct radeon_surface_reg {
  248.         struct radeon_object *robj;
  249. };
  250.  
  251. #define RADEON_GEM_MAX_SURFACES 8
  252.  
  253. /*
  254.  * Radeon buffer.
  255.  */
  256. struct radeon_object;
  257.  
  258. struct radeon_object_list {
  259.         struct list_head        list;
  260.         struct radeon_object    *robj;
  261.         uint64_t                gpu_offset;
  262.         unsigned                rdomain;
  263.         unsigned                wdomain;
  264.         uint32_t                tiling_flags;
  265. };
  266.  
  267. int radeon_object_init(struct radeon_device *rdev);
  268. void radeon_object_fini(struct radeon_device *rdev);
  269. int radeon_object_create(struct radeon_device *rdev,
  270.                          struct drm_gem_object *gobj,
  271.                          unsigned long size,
  272.                          bool kernel,
  273.                          uint32_t domain,
  274.                          bool interruptible,
  275.                          struct radeon_object **robj_ptr);
  276.  
  277.  
  278. /*
  279.  * GEM objects.
  280.  */
  281. struct radeon_gem {
  282.         struct list_head        objects;
  283. };
  284.  
  285. int radeon_gem_init(struct radeon_device *rdev);
  286. void radeon_gem_fini(struct radeon_device *rdev);
  287. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  288.                              int alignment, int initial_domain,
  289.                              bool discardable, bool kernel,
  290.                              bool interruptible,
  291.                              struct drm_gem_object **obj);
  292. int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
  293.                           uint64_t *gpu_addr);
  294. void radeon_gem_object_unpin(struct drm_gem_object *obj);
  295.  
  296.  
  297. /*
  298.  * GART structures, functions & helpers
  299.  */
  300. struct radeon_mc;
  301.  
  302. struct radeon_gart_table_ram {
  303.     volatile uint32_t       *ptr;
  304. };
  305.  
  306. struct radeon_gart_table_vram {
  307.     struct radeon_object        *robj;
  308.     volatile uint32_t       *ptr;
  309. };
  310.  
  311. union radeon_gart_table {
  312.     struct radeon_gart_table_ram    ram;
  313.     struct radeon_gart_table_vram   vram;
  314. };
  315.  
  316. struct radeon_gart {
  317.     dma_addr_t          table_addr;
  318.     unsigned            num_gpu_pages;
  319.     unsigned            num_cpu_pages;
  320.     unsigned            table_size;
  321.     union radeon_gart_table     table;
  322.     struct page         **pages;
  323.     dma_addr_t          *pages_addr;
  324.     bool                ready;
  325. };
  326.  
  327. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  328. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  329. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  330. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  331. int radeon_gart_init(struct radeon_device *rdev);
  332. void radeon_gart_fini(struct radeon_device *rdev);
  333. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  334.                         int pages);
  335. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  336.             int pages, u32_t *pagelist);
  337.  
  338.  
  339. /*
  340.  * GPU MC structures, functions & helpers
  341.  */
  342. struct radeon_mc {
  343.     resource_size_t     aper_size;
  344.     resource_size_t     aper_base;
  345.     resource_size_t     agp_base;
  346.         /* for some chips with <= 32MB we need to lie
  347.          * about vram size near mc fb location */
  348.         u64                     mc_vram_size;
  349.         u64                     gtt_location;
  350.         u64                     gtt_size;
  351.         u64                     gtt_start;
  352.         u64                     gtt_end;
  353.         u64                     vram_location;
  354.         u64                     vram_start;
  355.         u64                     vram_end;
  356.     unsigned            vram_width;
  357.         u64                     real_vram_size;
  358.     int                 vram_mtrr;
  359.     bool                vram_is_ddr;
  360. };
  361.  
  362. int radeon_mc_setup(struct radeon_device *rdev);
  363.  
  364.  
  365. /*
  366.  * GPU scratch registers structures, functions & helpers
  367.  */
  368. struct radeon_scratch {
  369.     unsigned        num_reg;
  370.     bool            free[32];
  371.     uint32_t        reg[32];
  372. };
  373.  
  374. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  375. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  376.  
  377.  
  378. /*
  379.  * IRQS.
  380.  */
  381. struct radeon_irq {
  382.         bool            installed;
  383.         bool            sw_int;
  384.         /* FIXME: use a define max crtc rather than hardcode it */
  385.         bool            crtc_vblank_int[2];
  386. };
  387.  
  388. int radeon_irq_kms_init(struct radeon_device *rdev);
  389. void radeon_irq_kms_fini(struct radeon_device *rdev);
  390.  
  391.  
  392. /*
  393.  * CP & ring.
  394.  */
  395. struct radeon_ib {
  396.         struct list_head        list;
  397.         unsigned long           idx;
  398.         uint64_t                gpu_addr;
  399.         struct radeon_fence     *fence;
  400.         uint32_t        *ptr;
  401.         uint32_t                length_dw;
  402. };
  403.  
  404. /*
  405.  * locking -
  406.  * mutex protects scheduled_ibs, ready, alloc_bm
  407.  */
  408. struct radeon_ib_pool {
  409. //      struct mutex            mutex;
  410.         struct radeon_object    *robj;
  411.         struct list_head        scheduled_ibs;
  412.         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
  413.         bool                    ready;
  414.         DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
  415. };
  416.  
  417. struct radeon_cp {
  418.         struct radeon_object    *ring_obj;
  419.         volatile uint32_t       *ring;
  420.         unsigned                rptr;
  421.         unsigned                wptr;
  422.         unsigned                wptr_old;
  423.         unsigned                ring_size;
  424.         unsigned                ring_free_dw;
  425.         int                     count_dw;
  426.         uint64_t                gpu_addr;
  427.         uint32_t                align_mask;
  428.         uint32_t                ptr_mask;
  429. //      struct mutex            mutex;
  430.         bool                    ready;
  431. };
  432.  
  433. struct r600_blit {
  434.         struct radeon_object    *shader_obj;
  435.         u64 shader_gpu_addr;
  436.         u32 vs_offset, ps_offset;
  437.         u32 state_offset;
  438.         u32 state_len;
  439.         u32 vb_used, vb_total;
  440.         struct radeon_ib *vb_ib;
  441. };
  442.  
  443. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
  444. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
  445. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
  446. int radeon_ib_pool_init(struct radeon_device *rdev);
  447. void radeon_ib_pool_fini(struct radeon_device *rdev);
  448. int radeon_ib_test(struct radeon_device *rdev);
  449. /* Ring access between begin & end cannot sleep */
  450. void radeon_ring_free_size(struct radeon_device *rdev);
  451. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
  452. void radeon_ring_unlock_commit(struct radeon_device *rdev);
  453. void radeon_ring_unlock_undo(struct radeon_device *rdev);
  454. int radeon_ring_test(struct radeon_device *rdev);
  455. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
  456. void radeon_ring_fini(struct radeon_device *rdev);
  457.  
  458.  
  459. /*
  460.  * CS.
  461.  */
  462. struct radeon_cs_reloc {
  463. //      struct drm_gem_object           *gobj;
  464.         struct radeon_object            *robj;
  465.         struct radeon_object_list       lobj;
  466.         uint32_t                        handle;
  467.         uint32_t                        flags;
  468. };
  469.  
  470. struct radeon_cs_chunk {
  471.         uint32_t                chunk_id;
  472.         uint32_t                length_dw;
  473.         int kpage_idx[2];
  474.         uint32_t                *kpage[2];
  475.         uint32_t                *kdata;
  476.         void __user *user_ptr;
  477.         int last_copied_page;
  478.         int last_page_index;
  479. };
  480.  
  481. struct radeon_cs_parser {
  482.         struct radeon_device    *rdev;
  483. //      struct drm_file         *filp;
  484.         /* chunks */
  485.         unsigned                nchunks;
  486.         struct radeon_cs_chunk  *chunks;
  487.         uint64_t                *chunks_array;
  488.         /* IB */
  489.         unsigned                idx;
  490.         /* relocations */
  491.         unsigned                nrelocs;
  492.         struct radeon_cs_reloc  *relocs;
  493.         struct radeon_cs_reloc  **relocs_ptr;
  494.         struct list_head        validated;
  495.         /* indices of various chunks */
  496.         int                     chunk_ib_idx;
  497.         int                     chunk_relocs_idx;
  498.         struct radeon_ib        *ib;
  499.         void                    *track;
  500.         unsigned                family;
  501.         int parser_error;
  502. };
  503.  
  504. extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
  505. extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
  506.  
  507.  
  508. static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  509. {
  510.         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  511.         u32 pg_idx, pg_offset;
  512.         u32 idx_value = 0;
  513.         int new_page;
  514.  
  515.         pg_idx = (idx * 4) / PAGE_SIZE;
  516.         pg_offset = (idx * 4) % PAGE_SIZE;
  517.  
  518.         if (ibc->kpage_idx[0] == pg_idx)
  519.                 return ibc->kpage[0][pg_offset/4];
  520.         if (ibc->kpage_idx[1] == pg_idx)
  521.                 return ibc->kpage[1][pg_offset/4];
  522.  
  523.         new_page = radeon_cs_update_pages(p, pg_idx);
  524.         if (new_page < 0) {
  525.                 p->parser_error = new_page;
  526.                 return 0;
  527.         }
  528.  
  529.         idx_value = ibc->kpage[new_page][pg_offset/4];
  530.         return idx_value;
  531. }
  532.  
  533. struct radeon_cs_packet {
  534.         unsigned        idx;
  535.         unsigned        type;
  536.         unsigned        reg;
  537.         unsigned        opcode;
  538.         int             count;
  539.         unsigned        one_reg_wr;
  540. };
  541.  
  542. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  543.                                       struct radeon_cs_packet *pkt,
  544.                                       unsigned idx, unsigned reg);
  545. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  546.                                       struct radeon_cs_packet *pkt);
  547.  
  548.  
  549. /*
  550.  * AGP
  551.  */
  552. int radeon_agp_init(struct radeon_device *rdev);
  553. void radeon_agp_fini(struct radeon_device *rdev);
  554.  
  555.  
  556. /*
  557.  * Writeback
  558.  */
  559. struct radeon_wb {
  560.         struct radeon_object    *wb_obj;
  561.         volatile uint32_t       *wb;
  562.         uint64_t                gpu_addr;
  563. };
  564.  
  565. /**
  566.  * struct radeon_pm - power management datas
  567.  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
  568.  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  569.  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
  570.  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
  571.  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
  572.  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
  573.  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  574.  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
  575.  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
  576.  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
  577.  * @needed_bandwidth:   current bandwidth needs
  578.  *
  579.  * It keeps track of various data needed to take powermanagement decision.
  580.  * Bandwith need is used to determine minimun clock of the GPU and memory.
  581.  * Equation between gpu/memory clock and available bandwidth is hw dependent
  582.  * (type of memory, bus size, efficiency, ...)
  583.  */
  584. struct radeon_pm {
  585.         fixed20_12              max_bandwidth;
  586.         fixed20_12              igp_sideport_mclk;
  587.         fixed20_12              igp_system_mclk;
  588.         fixed20_12              igp_ht_link_clk;
  589.         fixed20_12              igp_ht_link_width;
  590.         fixed20_12              k8_bandwidth;
  591.         fixed20_12              sideport_bandwidth;
  592.         fixed20_12              ht_bandwidth;
  593.         fixed20_12              core_bandwidth;
  594.         fixed20_12              sclk;
  595.         fixed20_12              needed_bandwidth;
  596. };
  597.  
  598. /*
  599.  * ASIC specific functions.
  600.  */
  601. struct radeon_asic {
  602.         int (*init)(struct radeon_device *rdev);
  603.         void (*fini)(struct radeon_device *rdev);
  604.         int (*resume)(struct radeon_device *rdev);
  605.         int (*suspend)(struct radeon_device *rdev);
  606.         void (*vga_set_state)(struct radeon_device *rdev, bool state);
  607.         int (*gpu_reset)(struct radeon_device *rdev);
  608.         void (*gart_tlb_flush)(struct radeon_device *rdev);
  609.         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  610.         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
  611.         void (*cp_fini)(struct radeon_device *rdev);
  612.         void (*cp_disable)(struct radeon_device *rdev);
  613.         void (*cp_commit)(struct radeon_device *rdev);
  614.         void (*ring_start)(struct radeon_device *rdev);
  615.         int (*ring_test)(struct radeon_device *rdev);
  616.         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  617.         int (*irq_set)(struct radeon_device *rdev);
  618.         int (*irq_process)(struct radeon_device *rdev);
  619.         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  620.         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
  621.         int (*cs_parse)(struct radeon_cs_parser *p);
  622.         int (*copy_blit)(struct radeon_device *rdev,
  623.                          uint64_t src_offset,
  624.                          uint64_t dst_offset,
  625.                          unsigned num_pages,
  626.                          struct radeon_fence *fence);
  627.         int (*copy_dma)(struct radeon_device *rdev,
  628.                         uint64_t src_offset,
  629.                         uint64_t dst_offset,
  630.                         unsigned num_pages,
  631.                         struct radeon_fence *fence);
  632.         int (*copy)(struct radeon_device *rdev,
  633.                     uint64_t src_offset,
  634.                     uint64_t dst_offset,
  635.                     unsigned num_pages,
  636.                     struct radeon_fence *fence);
  637.         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  638.         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  639.         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  640.         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  641.         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
  642.                                uint32_t tiling_flags, uint32_t pitch,
  643.                                uint32_t offset, uint32_t obj_size);
  644.         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
  645.         void (*bandwidth_update)(struct radeon_device *rdev);
  646. };
  647.  
  648. /*
  649.  * Asic structures
  650.  */
  651. struct r100_asic {
  652.         const unsigned  *reg_safe_bm;
  653.         unsigned        reg_safe_bm_size;
  654. };
  655.  
  656. struct r300_asic {
  657.         const unsigned  *reg_safe_bm;
  658.         unsigned        reg_safe_bm_size;
  659. };
  660.  
  661. struct r600_asic {
  662.         unsigned max_pipes;
  663.         unsigned max_tile_pipes;
  664.         unsigned max_simds;
  665.         unsigned max_backends;
  666.         unsigned max_gprs;
  667.         unsigned max_threads;
  668.         unsigned max_stack_entries;
  669.         unsigned max_hw_contexts;
  670.         unsigned max_gs_threads;
  671.         unsigned sx_max_export_size;
  672.         unsigned sx_max_export_pos_size;
  673.         unsigned sx_max_export_smx_size;
  674.         unsigned sq_num_cf_insts;
  675. };
  676.  
  677. struct rv770_asic {
  678.         unsigned max_pipes;
  679.         unsigned max_tile_pipes;
  680.         unsigned max_simds;
  681.         unsigned max_backends;
  682.         unsigned max_gprs;
  683.         unsigned max_threads;
  684.         unsigned max_stack_entries;
  685.         unsigned max_hw_contexts;
  686.         unsigned max_gs_threads;
  687.         unsigned sx_max_export_size;
  688.         unsigned sx_max_export_pos_size;
  689.         unsigned sx_max_export_smx_size;
  690.         unsigned sq_num_cf_insts;
  691.         unsigned sx_num_of_sets;
  692.         unsigned sc_prim_fifo_size;
  693.         unsigned sc_hiz_tile_fifo_size;
  694.         unsigned sc_earlyz_tile_fifo_fize;
  695. };
  696.  
  697. union radeon_asic_config {
  698.         struct r300_asic        r300;
  699.         struct r100_asic        r100;
  700.         struct r600_asic        r600;
  701.         struct rv770_asic       rv770;
  702. };
  703.  
  704.  
  705. /*
  706.  
  707.  
  708.  
  709.  
  710. /*
  711.  * Core structure, functions and helpers.
  712.  */
  713. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  714. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  715.  
  716. struct radeon_device {
  717.         void                               *dev;
  718.     struct drm_device          *ddev;
  719.     struct pci_dev             *pdev;
  720.     /* ASIC */
  721.     union radeon_asic_config    config;
  722.     enum radeon_family          family;
  723.     unsigned long               flags;
  724.     int                         usec_timeout;
  725.     enum radeon_pll_errata      pll_errata;
  726.     int                         num_gb_pipes;
  727.         int                             num_z_pipes;
  728.     int                         disp_priority;
  729.     /* BIOS */
  730.     uint8_t                     *bios;
  731.     bool                        is_atom_bios;
  732.     uint16_t                    bios_header_start;
  733.  
  734. //    struct radeon_object        *stollen_vga_memory;
  735.     struct fb_info              *fbdev_info;
  736.     struct radeon_object        *fbdev_robj;
  737.     struct radeon_framebuffer   *fbdev_rfb;
  738.     /* Register mmio */
  739.     unsigned long               rmmio_base;
  740.     unsigned long               rmmio_size;
  741.     void                       *rmmio;
  742.     radeon_rreg_t               mc_rreg;
  743.     radeon_wreg_t               mc_wreg;
  744.     radeon_rreg_t               pll_rreg;
  745.     radeon_wreg_t               pll_wreg;
  746.         uint32_t                        pcie_reg_mask;
  747.     radeon_rreg_t               pciep_rreg;
  748.     radeon_wreg_t               pciep_wreg;
  749.     struct radeon_clock         clock;
  750.     struct radeon_mc            mc;
  751.     struct radeon_gart          gart;
  752.         struct radeon_mode_info         mode_info;
  753.     struct radeon_scratch       scratch;
  754. //    struct radeon_mman          mman;
  755.         struct radeon_fence_driver      fence_drv;
  756.     struct radeon_cp            cp;
  757.     struct radeon_ib_pool       ib_pool;
  758. //    struct radeon_irq       irq;
  759.     struct radeon_asic         *asic;
  760.     struct radeon_gem       gem;
  761.         struct radeon_pm                pm;
  762.         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  763. //    struct mutex            cs_mutex;
  764.     struct radeon_wb        wb;
  765.         struct radeon_dummy_page        dummy_page;
  766.     bool                gpu_lockup;
  767.     bool                shutdown;
  768.     bool                suspend;
  769.         bool                            need_dma32;
  770.         bool                            accel_working;
  771.         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  772.         const struct firmware *me_fw;   /* all family ME firmware */
  773.         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
  774.         struct r600_blit r600_blit;
  775. };
  776.  
  777. int radeon_device_init(struct radeon_device *rdev,
  778.                        struct drm_device *ddev,
  779.                        struct pci_dev *pdev,
  780.                        uint32_t flags);
  781. void radeon_device_fini(struct radeon_device *rdev);
  782. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  783.  
  784. /* r600 blit */
  785. int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
  786. void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
  787. void r600_kms_blit_copy(struct radeon_device *rdev,
  788.                         u64 src_gpu_addr, u64 dst_gpu_addr,
  789.                         int size_bytes);
  790.  
  791. static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
  792. {
  793.         if (reg < 0x10000)
  794.                 return readl(((void __iomem *)rdev->rmmio) + reg);
  795.         else {
  796.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  797.                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  798.         }
  799. }
  800.  
  801. static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  802. {
  803.         if (reg < 0x10000)
  804.                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
  805.         else {
  806.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  807.                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  808.         }
  809. }
  810.  
  811.  
  812. /*
  813.  * Registers read & write functions.
  814.  */
  815. #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
  816. #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
  817. #define RREG32(reg) r100_mm_rreg(rdev, (reg))
  818. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
  819. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  820. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  821. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  822. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  823. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  824. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  825. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  826. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  827. #define WREG32_P(reg, val, mask)                                \
  828.         do {                                                    \
  829.                 uint32_t tmp_ = RREG32(reg);                    \
  830.                 tmp_ &= (mask);                                 \
  831.                 tmp_ |= ((val) & ~(mask));                      \
  832.                 WREG32(reg, tmp_);                              \
  833.         } while (0)
  834. #define WREG32_PLL_P(reg, val, mask)                            \
  835.         do {                                                    \
  836.                 uint32_t tmp_ = RREG32_PLL(reg);                \
  837.                 tmp_ &= (mask);                                 \
  838.                 tmp_ |= ((val) & ~(mask));                      \
  839.                 WREG32_PLL(reg, tmp_);                          \
  840.         } while (0)
  841.  
  842. /*
  843.  * Indirect registers accessor
  844.  */
  845. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  846. {
  847.         uint32_t r;
  848.  
  849.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  850.         r = RREG32(RADEON_PCIE_DATA);
  851.         return r;
  852. }
  853.  
  854. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  855. {
  856.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  857.         WREG32(RADEON_PCIE_DATA, (v));
  858. }
  859.  
  860. void r100_pll_errata_after_index(struct radeon_device *rdev);
  861.  
  862.  
  863.  
  864. enum chipset_type {
  865.     NOT_SUPPORTED,
  866.     SUPPORTED,
  867. };
  868.  
  869. struct agp_version {
  870.     u16_t major;
  871.     u16_t minor;
  872. };
  873.  
  874. struct agp_bridge_data;
  875.  
  876. struct agp_kern_info {
  877.     struct agp_version version;
  878.     struct pci_dev *device;
  879.     enum chipset_type chipset;
  880.     unsigned long mode;
  881.     unsigned long aper_base;
  882.     size_t aper_size;
  883.     int max_memory;     /* In pages */
  884.     int current_memory;
  885.     bool cant_use_aperture;
  886.     unsigned long page_mask;
  887. //    struct vm_operations_struct *vm_ops;
  888. };
  889.  
  890.  
  891. /**
  892.  * AGP data.
  893.  *
  894.  * \sa drm_agp_init() and drm_device::agp.
  895.  */
  896. struct drm_agp_head {
  897.     struct agp_kern_info agp_info;      /**< AGP device information */
  898. //    struct list_head memory;
  899.     unsigned long mode;     /**< AGP mode */
  900.     struct agp_bridge_data *bridge;
  901.     int enabled;            /**< whether the AGP bus as been enabled */
  902.     int acquired;           /**< whether the AGP device has been acquired */
  903.     unsigned long base;
  904.     int agp_mtrr;
  905.     int cant_use_aperture;
  906.     unsigned long page_mask;
  907. };
  908.  
  909.  
  910.  
  911. /*
  912.  * ASICs helpers.
  913.  */
  914. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  915.                             (rdev->pdev->device == 0x5969))
  916. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  917.         (rdev->family == CHIP_RV200) || \
  918.         (rdev->family == CHIP_RS100) || \
  919.         (rdev->family == CHIP_RS200) || \
  920.         (rdev->family == CHIP_RV250) || \
  921.         (rdev->family == CHIP_RV280) || \
  922.         (rdev->family == CHIP_RS300))
  923. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
  924.         (rdev->family == CHIP_RV350) ||         \
  925.         (rdev->family == CHIP_R350)  ||         \
  926.         (rdev->family == CHIP_RV380) ||         \
  927.         (rdev->family == CHIP_R420)  ||         \
  928.         (rdev->family == CHIP_R423)  ||         \
  929.         (rdev->family == CHIP_RV410) ||         \
  930.         (rdev->family == CHIP_RS400) ||         \
  931.         (rdev->family == CHIP_RS480))
  932. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  933. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  934. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  935.  
  936.  
  937. /*
  938.  * BIOS helpers.
  939.  */
  940. #define RBIOS8(i) (rdev->bios[i])
  941. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  942. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  943.  
  944. int radeon_combios_init(struct radeon_device *rdev);
  945. void radeon_combios_fini(struct radeon_device *rdev);
  946. int radeon_atombios_init(struct radeon_device *rdev);
  947. void radeon_atombios_fini(struct radeon_device *rdev);
  948.  
  949.  
  950. /*
  951.  * RING helpers.
  952.  */
  953. static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  954. {
  955. #if DRM_DEBUG_CODE
  956.         if (rdev->cp.count_dw <= 0) {
  957.                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  958.         }
  959. #endif
  960.         rdev->cp.ring[rdev->cp.wptr++] = v;
  961.         rdev->cp.wptr &= rdev->cp.ptr_mask;
  962.         rdev->cp.count_dw--;
  963.         rdev->cp.ring_free_dw--;
  964. }
  965.  
  966.  
  967. /*
  968.  * ASICs macro.
  969.  */
  970. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  971. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  972. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  973. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  974. #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
  975. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  976. #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
  977. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
  978. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
  979. #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
  980. #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
  981. #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
  982. #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
  983. #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
  984. #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
  985. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
  986. #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
  987. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
  988. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
  989. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
  990. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  991. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  992. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
  993. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
  994. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
  995. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
  996. #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
  997.  
  998. /* Common functions */
  999. extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  1000. extern int radeon_modeset_init(struct radeon_device *rdev);
  1001. extern void radeon_modeset_fini(struct radeon_device *rdev);
  1002. extern bool radeon_card_posted(struct radeon_device *rdev);
  1003. extern int radeon_clocks_init(struct radeon_device *rdev);
  1004. extern void radeon_clocks_fini(struct radeon_device *rdev);
  1005. extern void radeon_scratch_init(struct radeon_device *rdev);
  1006. extern void radeon_surface_init(struct radeon_device *rdev);
  1007. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  1008. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  1009. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  1010.  
  1011. /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
  1012. struct r100_mc_save {
  1013.         u32     GENMO_WT;
  1014.         u32     CRTC_EXT_CNTL;
  1015.         u32     CRTC_GEN_CNTL;
  1016.         u32     CRTC2_GEN_CNTL;
  1017.         u32     CUR_OFFSET;
  1018.         u32     CUR2_OFFSET;
  1019. };
  1020. extern void r100_cp_disable(struct radeon_device *rdev);
  1021. extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  1022. extern void r100_cp_fini(struct radeon_device *rdev);
  1023. extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  1024. extern int r100_pci_gart_init(struct radeon_device *rdev);
  1025. extern void r100_pci_gart_fini(struct radeon_device *rdev);
  1026. extern int r100_pci_gart_enable(struct radeon_device *rdev);
  1027. extern void r100_pci_gart_disable(struct radeon_device *rdev);
  1028. extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  1029. extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  1030. extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
  1031. extern void r100_ib_fini(struct radeon_device *rdev);
  1032. extern int r100_ib_init(struct radeon_device *rdev);
  1033. extern void r100_irq_disable(struct radeon_device *rdev);
  1034. extern int r100_irq_set(struct radeon_device *rdev);
  1035. extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
  1036. extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
  1037. extern void r100_vram_init_sizes(struct radeon_device *rdev);
  1038. extern void r100_wb_disable(struct radeon_device *rdev);
  1039. extern void r100_wb_fini(struct radeon_device *rdev);
  1040. extern int r100_wb_init(struct radeon_device *rdev);
  1041. extern void r100_hdp_reset(struct radeon_device *rdev);
  1042. extern int r100_rb2d_reset(struct radeon_device *rdev);
  1043. extern int r100_cp_reset(struct radeon_device *rdev);
  1044. extern void r100_vga_render_disable(struct radeon_device *rdev);
  1045. extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  1046.                                                 struct radeon_cs_packet *pkt,
  1047.                                                 struct radeon_object *robj);
  1048. extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  1049.                                 struct radeon_cs_packet *pkt,
  1050.                                 const unsigned *auth, unsigned n,
  1051.                                 radeon_packet0_check_t check);
  1052. extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
  1053.                                 struct radeon_cs_packet *pkt,
  1054.                                 unsigned idx);
  1055.  
  1056. /* rv200,rv250,rv280 */
  1057. extern void r200_set_safe_registers(struct radeon_device *rdev);
  1058.  
  1059. /* r300,r350,rv350,rv370,rv380 */
  1060. extern void r300_set_reg_safe(struct radeon_device *rdev);
  1061. extern void r300_mc_program(struct radeon_device *rdev);
  1062. extern void r300_vram_info(struct radeon_device *rdev);
  1063. extern void r300_clock_startup(struct radeon_device *rdev);
  1064. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  1065. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
  1066. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
  1067. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
  1068. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
  1069.  
  1070. /* r420,r423,rv410 */
  1071. extern int r420_mc_init(struct radeon_device *rdev);
  1072. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
  1073. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  1074. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  1075. extern void r420_pipes_init(struct radeon_device *rdev);
  1076.  
  1077. /* rv515 */
  1078. struct rv515_mc_save {
  1079.         u32 d1vga_control;
  1080.         u32 d2vga_control;
  1081.         u32 vga_render_control;
  1082.         u32 vga_hdp_control;
  1083.         u32 d1crtc_control;
  1084.         u32 d2crtc_control;
  1085. };
  1086. extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  1087. extern void rv515_vga_render_disable(struct radeon_device *rdev);
  1088. extern void rv515_set_safe_registers(struct radeon_device *rdev);
  1089. extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
  1090. extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
  1091. extern void rv515_clock_startup(struct radeon_device *rdev);
  1092. extern void rv515_debugfs(struct radeon_device *rdev);
  1093. extern int rv515_suspend(struct radeon_device *rdev);
  1094.  
  1095. /* rs400 */
  1096. extern int rs400_gart_init(struct radeon_device *rdev);
  1097. extern int rs400_gart_enable(struct radeon_device *rdev);
  1098. extern void rs400_gart_adjust_size(struct radeon_device *rdev);
  1099. extern void rs400_gart_disable(struct radeon_device *rdev);
  1100. extern void rs400_gart_fini(struct radeon_device *rdev);
  1101.  
  1102. /* rs600 */
  1103. extern void rs600_set_safe_registers(struct radeon_device *rdev);
  1104. extern int rs600_irq_set(struct radeon_device *rdev);
  1105. extern void rs600_irq_disable(struct radeon_device *rdev);
  1106.  
  1107. /* rs690, rs740 */
  1108. extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
  1109.                                         struct drm_display_mode *mode1,
  1110.                                         struct drm_display_mode *mode2);
  1111.  
  1112. /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
  1113. extern bool r600_card_posted(struct radeon_device *rdev);
  1114. extern void r600_cp_stop(struct radeon_device *rdev);
  1115. extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1116. extern int r600_cp_resume(struct radeon_device *rdev);
  1117. extern int r600_count_pipe_bits(uint32_t val);
  1118. extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
  1119. extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
  1120. extern int r600_pcie_gart_init(struct radeon_device *rdev);
  1121. extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  1122. extern int r600_ib_test(struct radeon_device *rdev);
  1123. extern int r600_ring_test(struct radeon_device *rdev);
  1124. extern void r600_wb_fini(struct radeon_device *rdev);
  1125. extern int r600_wb_enable(struct radeon_device *rdev);
  1126. extern void r600_wb_disable(struct radeon_device *rdev);
  1127. extern void r600_scratch_init(struct radeon_device *rdev);
  1128. extern int r600_blit_init(struct radeon_device *rdev);
  1129. extern void r600_blit_fini(struct radeon_device *rdev);
  1130. extern int r600_cp_init_microcode(struct radeon_device *rdev);
  1131. extern int r600_gpu_reset(struct radeon_device *rdev);
  1132.  
  1133.  
  1134.  
  1135. #define DRM_UDELAY(d)           udelay(d)
  1136.  
  1137. resource_size_t
  1138. drm_get_resource_start(struct drm_device *dev, unsigned int resource);
  1139. resource_size_t
  1140. drm_get_resource_len(struct drm_device *dev, unsigned int resource);
  1141.  
  1142. bool set_mode(struct drm_device *dev, int width, int height);
  1143.  
  1144.  
  1145.  
  1146. #endif
  1147.