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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30.  
  31. //#include "radeon_object.h"
  32.  
  33. /* TODO: Here are things that needs to be done :
  34.  *      - surface allocator & initializer : (bit like scratch reg) should
  35.  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  36.  *        related to surface
  37.  *      - WB : write back stuff (do it bit like scratch reg things)
  38.  *      - Vblank : look at Jesse's rework and what we should do
  39.  *      - r600/r700: gart & cp
  40.  *      - cs : clean cs ioctl use bitmap & things like that.
  41.  *      - power management stuff
  42.  *      - Barrier in gart code
  43.  *      - Unmappabled vram ?
  44.  *      - TESTING, TESTING, TESTING
  45.  */
  46.  
  47. /* Initialization path:
  48.  *  We expect that acceleration initialization might fail for various
  49.  *  reasons even thought we work hard to make it works on most
  50.  *  configurations. In order to still have a working userspace in such
  51.  *  situation the init path must succeed up to the memory controller
  52.  *  initialization point. Failure before this point are considered as
  53.  *  fatal error. Here is the init callchain :
  54.  *      radeon_device_init  perform common structure, mutex initialization
  55.  *      asic_init           setup the GPU memory layout and perform all
  56.  *                          one time initialization (failure in this
  57.  *                          function are considered fatal)
  58.  *      asic_startup        setup the GPU acceleration, in order to
  59.  *                          follow guideline the first thing this
  60.  *                          function should do is setting the GPU
  61.  *                          memory controller (only MC setup failure
  62.  *                          are considered as fatal)
  63.  */
  64.  
  65.  
  66. #include <types.h>
  67.  
  68.  
  69. #include <linux/list.h>
  70.  
  71. #include <pci.h>
  72.  
  73. #include <errno-base.h>
  74. #include "drm_edid.h"
  75.  
  76. #include "radeon_family.h"
  77. #include "radeon_mode.h"
  78. #include "radeon_reg.h"
  79.  
  80. #include <syscall.h>
  81.  
  82. /*
  83.  * Modules parameters.
  84.  */
  85. extern int radeon_no_wb;
  86. extern int radeon_modeset;
  87. extern int radeon_dynclks;
  88. extern int radeon_r4xx_atom;
  89. extern int radeon_agpmode;
  90. extern int radeon_vram_limit;
  91. extern int radeon_gart_size;
  92. extern int radeon_benchmarking;
  93. extern int radeon_testing;
  94. extern int radeon_connector_table;
  95. extern int radeon_tv;
  96.  
  97.  
  98. static inline uint8_t __raw_readb(const volatile void __iomem *addr)
  99. {
  100.     return *(const volatile uint8_t __force *) addr;
  101. }
  102.  
  103. static inline uint16_t __raw_readw(const volatile void __iomem *addr)
  104. {
  105.     return *(const volatile uint16_t __force *) addr;
  106. }
  107.  
  108. static inline uint32_t __raw_readl(const volatile void __iomem *addr)
  109. {
  110.     return *(const volatile uint32_t __force *) addr;
  111. }
  112.  
  113. #define readb __raw_readb
  114. #define readw __raw_readw
  115. #define readl __raw_readl
  116.  
  117.  
  118.  
  119. static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
  120. {
  121.     *(volatile uint8_t __force *) addr = b;
  122. }
  123.  
  124. static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
  125. {
  126.     *(volatile uint16_t __force *) addr = b;
  127. }
  128.  
  129. static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
  130. {
  131.     *(volatile uint32_t __force *) addr = b;
  132. }
  133.  
  134. static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
  135. {
  136.         *(volatile __u64 *)addr = b;
  137. }
  138.  
  139. #define writeb __raw_writeb
  140. #define writew __raw_writew
  141. #define writel __raw_writel
  142. #define writeq __raw_writeq
  143.  
  144.  
  145. /*
  146.  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  147.  * symbol;
  148.  */
  149. #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  150. #define RADEON_IB_POOL_SIZE             16
  151. #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  152. #define RADEONFB_CONN_LIMIT             4
  153. #define RADEON_BIOS_NUM_SCRATCH         8
  154.  
  155. /*
  156.  * Errata workarounds.
  157.  */
  158. enum radeon_pll_errata {
  159.     CHIP_ERRATA_R300_CG             = 0x00000001,
  160.     CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  161.     CHIP_ERRATA_PLL_DELAY           = 0x00000004
  162. };
  163.  
  164.  
  165. struct radeon_device;
  166.  
  167.  
  168. /*
  169.  * BIOS.
  170.  */
  171. bool radeon_get_bios(struct radeon_device *rdev);
  172.  
  173.  
  174. /*
  175.  * Dummy page
  176.  */
  177. struct radeon_dummy_page {
  178.         struct page     *page;
  179.         dma_addr_t      addr;
  180. };
  181. int radeon_dummy_page_init(struct radeon_device *rdev);
  182. void radeon_dummy_page_fini(struct radeon_device *rdev);
  183.  
  184.  
  185. /*
  186.  * Clocks
  187.  */
  188. struct radeon_clock {
  189.         struct radeon_pll p1pll;
  190.         struct radeon_pll p2pll;
  191.         struct radeon_pll spll;
  192.         struct radeon_pll mpll;
  193.         /* 10 Khz units */
  194.         uint32_t default_mclk;
  195.         uint32_t default_sclk;
  196. };
  197.  
  198.  
  199. /*
  200.  * Fences.
  201.  */
  202. struct radeon_fence_driver {
  203.         uint32_t                        scratch_reg;
  204. //      atomic_t                        seq;
  205.         uint32_t                        last_seq;
  206.         unsigned long                   count_timeout;
  207. //      wait_queue_head_t               queue;
  208. //      rwlock_t                        lock;
  209.         struct list_head                created;
  210.         struct list_head                emited;
  211.         struct list_head                signaled;
  212. };
  213.  
  214. struct radeon_fence {
  215.         struct radeon_device            *rdev;
  216. //      struct kref                     kref;
  217.         struct list_head                list;
  218.         /* protected by radeon_fence.lock */
  219.         uint32_t                        seq;
  220.         unsigned long                   timeout;
  221.         bool                            emited;
  222.         bool                            signaled;
  223. };
  224.  
  225. int radeon_fence_driver_init(struct radeon_device *rdev);
  226. void radeon_fence_driver_fini(struct radeon_device *rdev);
  227. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
  228. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
  229. void radeon_fence_process(struct radeon_device *rdev);
  230. bool radeon_fence_signaled(struct radeon_fence *fence);
  231. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  232. int radeon_fence_wait_next(struct radeon_device *rdev);
  233. int radeon_fence_wait_last(struct radeon_device *rdev);
  234. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  235. void radeon_fence_unref(struct radeon_fence **fence);
  236.  
  237. /*
  238.  * Tiling registers
  239.  */
  240. struct radeon_surface_reg {
  241.         struct radeon_object *robj;
  242. };
  243.  
  244. #define RADEON_GEM_MAX_SURFACES 8
  245.  
  246. /*
  247.  * Radeon buffer.
  248.  */
  249. struct radeon_object;
  250.  
  251. struct radeon_object_list {
  252.         struct list_head        list;
  253.         struct radeon_object    *robj;
  254.         uint64_t                gpu_offset;
  255.         unsigned                rdomain;
  256.         unsigned                wdomain;
  257.         uint32_t                tiling_flags;
  258. };
  259.  
  260. int radeon_object_init(struct radeon_device *rdev);
  261. void radeon_object_fini(struct radeon_device *rdev);
  262. int radeon_object_create(struct radeon_device *rdev,
  263.                          struct drm_gem_object *gobj,
  264.                          unsigned long size,
  265.                          bool kernel,
  266.                          uint32_t domain,
  267.                          bool interruptible,
  268.                          struct radeon_object **robj_ptr);
  269.  
  270.  
  271. /*
  272.  * GEM objects.
  273.  */
  274. struct radeon_gem {
  275.         struct list_head        objects;
  276. };
  277.  
  278. int radeon_gem_init(struct radeon_device *rdev);
  279. void radeon_gem_fini(struct radeon_device *rdev);
  280. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  281.                              int alignment, int initial_domain,
  282.                              bool discardable, bool kernel,
  283.                              bool interruptible,
  284.                              struct drm_gem_object **obj);
  285. int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
  286.                           uint64_t *gpu_addr);
  287. void radeon_gem_object_unpin(struct drm_gem_object *obj);
  288.  
  289.  
  290. /*
  291.  * GART structures, functions & helpers
  292.  */
  293. struct radeon_mc;
  294.  
  295. struct radeon_gart_table_ram {
  296.     volatile uint32_t       *ptr;
  297. };
  298.  
  299. struct radeon_gart_table_vram {
  300.     struct radeon_object        *robj;
  301.     volatile uint32_t       *ptr;
  302. };
  303.  
  304. union radeon_gart_table {
  305.     struct radeon_gart_table_ram    ram;
  306.     struct radeon_gart_table_vram   vram;
  307. };
  308.  
  309. struct radeon_gart {
  310.     dma_addr_t          table_addr;
  311.     unsigned            num_gpu_pages;
  312.     unsigned            num_cpu_pages;
  313.     unsigned            table_size;
  314.     union radeon_gart_table     table;
  315.     struct page         **pages;
  316.     dma_addr_t          *pages_addr;
  317.     bool                ready;
  318. };
  319.  
  320. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  321. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  322. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  323. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  324. int radeon_gart_init(struct radeon_device *rdev);
  325. void radeon_gart_fini(struct radeon_device *rdev);
  326. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  327.                         int pages);
  328. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  329.             int pages, u32_t *pagelist);
  330.  
  331.  
  332. /*
  333.  * GPU MC structures, functions & helpers
  334.  */
  335. struct radeon_mc {
  336.     resource_size_t     aper_size;
  337.     resource_size_t     aper_base;
  338.     resource_size_t     agp_base;
  339.         /* for some chips with <= 32MB we need to lie
  340.          * about vram size near mc fb location */
  341.         u64                     mc_vram_size;
  342.         u64                     gtt_location;
  343.         u64                     gtt_size;
  344.         u64                     gtt_start;
  345.         u64                     gtt_end;
  346.         u64                     vram_location;
  347.         u64                     vram_start;
  348.         u64                     vram_end;
  349.     unsigned            vram_width;
  350.         u64                     real_vram_size;
  351.     int                 vram_mtrr;
  352.     bool                vram_is_ddr;
  353. };
  354.  
  355. int radeon_mc_setup(struct radeon_device *rdev);
  356.  
  357.  
  358. /*
  359.  * GPU scratch registers structures, functions & helpers
  360.  */
  361. struct radeon_scratch {
  362.     unsigned        num_reg;
  363.     bool            free[32];
  364.     uint32_t        reg[32];
  365. };
  366.  
  367. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  368. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  369.  
  370.  
  371. /*
  372.  * IRQS.
  373.  */
  374. struct radeon_irq {
  375.         bool            installed;
  376.         bool            sw_int;
  377.         /* FIXME: use a define max crtc rather than hardcode it */
  378.         bool            crtc_vblank_int[2];
  379. };
  380.  
  381. int radeon_irq_kms_init(struct radeon_device *rdev);
  382. void radeon_irq_kms_fini(struct radeon_device *rdev);
  383.  
  384.  
  385. /*
  386.  * CP & ring.
  387.  */
  388. struct radeon_ib {
  389.         struct list_head        list;
  390.         unsigned long           idx;
  391.         uint64_t                gpu_addr;
  392.         struct radeon_fence     *fence;
  393.         uint32_t        *ptr;
  394.         uint32_t                length_dw;
  395. };
  396.  
  397. /*
  398.  * locking -
  399.  * mutex protects scheduled_ibs, ready, alloc_bm
  400.  */
  401. struct radeon_ib_pool {
  402. //      struct mutex            mutex;
  403.         struct radeon_object    *robj;
  404.         struct list_head        scheduled_ibs;
  405.         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
  406.         bool                    ready;
  407.         DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
  408. };
  409.  
  410. struct radeon_cp {
  411.         struct radeon_object    *ring_obj;
  412.         volatile uint32_t       *ring;
  413.         unsigned                rptr;
  414.         unsigned                wptr;
  415.         unsigned                wptr_old;
  416.         unsigned                ring_size;
  417.         unsigned                ring_free_dw;
  418.         int                     count_dw;
  419.         uint64_t                gpu_addr;
  420.         uint32_t                align_mask;
  421.         uint32_t                ptr_mask;
  422. //      struct mutex            mutex;
  423.         bool                    ready;
  424. };
  425.  
  426. struct r600_blit {
  427.         struct radeon_object    *shader_obj;
  428.         u64 shader_gpu_addr;
  429.         u32 vs_offset, ps_offset;
  430.         u32 state_offset;
  431.         u32 state_len;
  432.         u32 vb_used, vb_total;
  433.         struct radeon_ib *vb_ib;
  434. };
  435.  
  436. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
  437. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
  438. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
  439. int radeon_ib_pool_init(struct radeon_device *rdev);
  440. void radeon_ib_pool_fini(struct radeon_device *rdev);
  441. int radeon_ib_test(struct radeon_device *rdev);
  442. /* Ring access between begin & end cannot sleep */
  443. void radeon_ring_free_size(struct radeon_device *rdev);
  444. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
  445. void radeon_ring_unlock_commit(struct radeon_device *rdev);
  446. void radeon_ring_unlock_undo(struct radeon_device *rdev);
  447. int radeon_ring_test(struct radeon_device *rdev);
  448. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
  449. void radeon_ring_fini(struct radeon_device *rdev);
  450.  
  451.  
  452. /*
  453.  * CS.
  454.  */
  455. struct radeon_cs_reloc {
  456. //      struct drm_gem_object           *gobj;
  457.         struct radeon_object            *robj;
  458.         struct radeon_object_list       lobj;
  459.         uint32_t                        handle;
  460.         uint32_t                        flags;
  461. };
  462.  
  463. struct radeon_cs_chunk {
  464.         uint32_t                chunk_id;
  465.         uint32_t                length_dw;
  466.         int kpage_idx[2];
  467.         uint32_t                *kpage[2];
  468.         uint32_t                *kdata;
  469.         void __user *user_ptr;
  470.         int last_copied_page;
  471.         int last_page_index;
  472. };
  473.  
  474. struct radeon_cs_parser {
  475.         struct radeon_device    *rdev;
  476. //      struct drm_file         *filp;
  477.         /* chunks */
  478.         unsigned                nchunks;
  479.         struct radeon_cs_chunk  *chunks;
  480.         uint64_t                *chunks_array;
  481.         /* IB */
  482.         unsigned                idx;
  483.         /* relocations */
  484.         unsigned                nrelocs;
  485.         struct radeon_cs_reloc  *relocs;
  486.         struct radeon_cs_reloc  **relocs_ptr;
  487.         struct list_head        validated;
  488.         /* indices of various chunks */
  489.         int                     chunk_ib_idx;
  490.         int                     chunk_relocs_idx;
  491.         struct radeon_ib        *ib;
  492.         void                    *track;
  493.         unsigned                family;
  494.         int parser_error;
  495. };
  496.  
  497. extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
  498. extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
  499.  
  500.  
  501. static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  502. {
  503.         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  504.         u32 pg_idx, pg_offset;
  505.         u32 idx_value = 0;
  506.         int new_page;
  507.  
  508.         pg_idx = (idx * 4) / PAGE_SIZE;
  509.         pg_offset = (idx * 4) % PAGE_SIZE;
  510.  
  511.         if (ibc->kpage_idx[0] == pg_idx)
  512.                 return ibc->kpage[0][pg_offset/4];
  513.         if (ibc->kpage_idx[1] == pg_idx)
  514.                 return ibc->kpage[1][pg_offset/4];
  515.  
  516.         new_page = radeon_cs_update_pages(p, pg_idx);
  517.         if (new_page < 0) {
  518.                 p->parser_error = new_page;
  519.                 return 0;
  520.         }
  521.  
  522.         idx_value = ibc->kpage[new_page][pg_offset/4];
  523.         return idx_value;
  524. }
  525.  
  526. struct radeon_cs_packet {
  527.         unsigned        idx;
  528.         unsigned        type;
  529.         unsigned        reg;
  530.         unsigned        opcode;
  531.         int             count;
  532.         unsigned        one_reg_wr;
  533. };
  534.  
  535. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  536.                                       struct radeon_cs_packet *pkt,
  537.                                       unsigned idx, unsigned reg);
  538. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  539.                                       struct radeon_cs_packet *pkt);
  540.  
  541.  
  542. /*
  543.  * AGP
  544.  */
  545. int radeon_agp_init(struct radeon_device *rdev);
  546. void radeon_agp_fini(struct radeon_device *rdev);
  547.  
  548.  
  549. /*
  550.  * Writeback
  551.  */
  552. struct radeon_wb {
  553.         struct radeon_object    *wb_obj;
  554.         volatile uint32_t       *wb;
  555.         uint64_t                gpu_addr;
  556. };
  557.  
  558. /**
  559.  * struct radeon_pm - power management datas
  560.  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
  561.  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  562.  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
  563.  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
  564.  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
  565.  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
  566.  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  567.  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
  568.  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
  569.  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
  570.  * @needed_bandwidth:   current bandwidth needs
  571.  *
  572.  * It keeps track of various data needed to take powermanagement decision.
  573.  * Bandwith need is used to determine minimun clock of the GPU and memory.
  574.  * Equation between gpu/memory clock and available bandwidth is hw dependent
  575.  * (type of memory, bus size, efficiency, ...)
  576.  */
  577. struct radeon_pm {
  578.         fixed20_12              max_bandwidth;
  579.         fixed20_12              igp_sideport_mclk;
  580.         fixed20_12              igp_system_mclk;
  581.         fixed20_12              igp_ht_link_clk;
  582.         fixed20_12              igp_ht_link_width;
  583.         fixed20_12              k8_bandwidth;
  584.         fixed20_12              sideport_bandwidth;
  585.         fixed20_12              ht_bandwidth;
  586.         fixed20_12              core_bandwidth;
  587.         fixed20_12              sclk;
  588.         fixed20_12              needed_bandwidth;
  589. };
  590.  
  591. /*
  592.  * ASIC specific functions.
  593.  */
  594. struct radeon_asic {
  595.         int (*init)(struct radeon_device *rdev);
  596.         void (*fini)(struct radeon_device *rdev);
  597.         int (*resume)(struct radeon_device *rdev);
  598.         int (*suspend)(struct radeon_device *rdev);
  599.         void (*vga_set_state)(struct radeon_device *rdev, bool state);
  600.         int (*gpu_reset)(struct radeon_device *rdev);
  601.         void (*gart_tlb_flush)(struct radeon_device *rdev);
  602.         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  603.         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
  604.         void (*cp_fini)(struct radeon_device *rdev);
  605.         void (*cp_disable)(struct radeon_device *rdev);
  606.         void (*cp_commit)(struct radeon_device *rdev);
  607.         void (*ring_start)(struct radeon_device *rdev);
  608.         int (*ring_test)(struct radeon_device *rdev);
  609.         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  610.         int (*irq_set)(struct radeon_device *rdev);
  611.         int (*irq_process)(struct radeon_device *rdev);
  612.         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  613.         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
  614.         int (*cs_parse)(struct radeon_cs_parser *p);
  615.         int (*copy_blit)(struct radeon_device *rdev,
  616.                          uint64_t src_offset,
  617.                          uint64_t dst_offset,
  618.                          unsigned num_pages,
  619.                          struct radeon_fence *fence);
  620.         int (*copy_dma)(struct radeon_device *rdev,
  621.                         uint64_t src_offset,
  622.                         uint64_t dst_offset,
  623.                         unsigned num_pages,
  624.                         struct radeon_fence *fence);
  625.         int (*copy)(struct radeon_device *rdev,
  626.                     uint64_t src_offset,
  627.                     uint64_t dst_offset,
  628.                     unsigned num_pages,
  629.                     struct radeon_fence *fence);
  630.         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  631.         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  632.         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  633.         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  634.         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
  635.                                uint32_t tiling_flags, uint32_t pitch,
  636.                                uint32_t offset, uint32_t obj_size);
  637.         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
  638.         void (*bandwidth_update)(struct radeon_device *rdev);
  639. };
  640.  
  641. /*
  642.  * Asic structures
  643.  */
  644. struct r100_asic {
  645.         const unsigned  *reg_safe_bm;
  646.         unsigned        reg_safe_bm_size;
  647. };
  648.  
  649. struct r300_asic {
  650.         const unsigned  *reg_safe_bm;
  651.         unsigned        reg_safe_bm_size;
  652. };
  653.  
  654. struct r600_asic {
  655.         unsigned max_pipes;
  656.         unsigned max_tile_pipes;
  657.         unsigned max_simds;
  658.         unsigned max_backends;
  659.         unsigned max_gprs;
  660.         unsigned max_threads;
  661.         unsigned max_stack_entries;
  662.         unsigned max_hw_contexts;
  663.         unsigned max_gs_threads;
  664.         unsigned sx_max_export_size;
  665.         unsigned sx_max_export_pos_size;
  666.         unsigned sx_max_export_smx_size;
  667.         unsigned sq_num_cf_insts;
  668. };
  669.  
  670. struct rv770_asic {
  671.         unsigned max_pipes;
  672.         unsigned max_tile_pipes;
  673.         unsigned max_simds;
  674.         unsigned max_backends;
  675.         unsigned max_gprs;
  676.         unsigned max_threads;
  677.         unsigned max_stack_entries;
  678.         unsigned max_hw_contexts;
  679.         unsigned max_gs_threads;
  680.         unsigned sx_max_export_size;
  681.         unsigned sx_max_export_pos_size;
  682.         unsigned sx_max_export_smx_size;
  683.         unsigned sq_num_cf_insts;
  684.         unsigned sx_num_of_sets;
  685.         unsigned sc_prim_fifo_size;
  686.         unsigned sc_hiz_tile_fifo_size;
  687.         unsigned sc_earlyz_tile_fifo_fize;
  688. };
  689.  
  690. union radeon_asic_config {
  691.         struct r300_asic        r300;
  692.         struct r100_asic        r100;
  693.         struct r600_asic        r600;
  694.         struct rv770_asic       rv770;
  695. };
  696.  
  697.  
  698. /*
  699.  
  700.  
  701.  
  702.  
  703. /*
  704.  * Core structure, functions and helpers.
  705.  */
  706. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  707. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  708.  
  709. struct radeon_device {
  710.         void                               *dev;
  711.     struct drm_device          *ddev;
  712.     struct pci_dev             *pdev;
  713.     /* ASIC */
  714.     union radeon_asic_config    config;
  715.     enum radeon_family          family;
  716.     unsigned long               flags;
  717.     int                         usec_timeout;
  718.     enum radeon_pll_errata      pll_errata;
  719.     int                         num_gb_pipes;
  720.         int                             num_z_pipes;
  721.     int                         disp_priority;
  722.     /* BIOS */
  723.     uint8_t                     *bios;
  724.     bool                        is_atom_bios;
  725.     uint16_t                    bios_header_start;
  726.  
  727. //    struct radeon_object        *stollen_vga_memory;
  728.     struct fb_info              *fbdev_info;
  729.     struct radeon_object        *fbdev_robj;
  730.     struct radeon_framebuffer   *fbdev_rfb;
  731.     /* Register mmio */
  732.     unsigned long               rmmio_base;
  733.     unsigned long               rmmio_size;
  734.     void                       *rmmio;
  735.     radeon_rreg_t               mc_rreg;
  736.     radeon_wreg_t               mc_wreg;
  737.     radeon_rreg_t               pll_rreg;
  738.     radeon_wreg_t               pll_wreg;
  739.         uint32_t                        pcie_reg_mask;
  740.     radeon_rreg_t               pciep_rreg;
  741.     radeon_wreg_t               pciep_wreg;
  742.     struct radeon_clock         clock;
  743.     struct radeon_mc            mc;
  744.     struct radeon_gart          gart;
  745.         struct radeon_mode_info         mode_info;
  746.     struct radeon_scratch       scratch;
  747. //    struct radeon_mman          mman;
  748.         struct radeon_fence_driver      fence_drv;
  749.     struct radeon_cp            cp;
  750.     struct radeon_ib_pool       ib_pool;
  751. //    struct radeon_irq       irq;
  752.     struct radeon_asic         *asic;
  753.     struct radeon_gem       gem;
  754.         struct radeon_pm                pm;
  755.         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  756. //    struct mutex            cs_mutex;
  757.     struct radeon_wb        wb;
  758.         struct radeon_dummy_page        dummy_page;
  759.     bool                gpu_lockup;
  760.     bool                shutdown;
  761.     bool                suspend;
  762.         bool                            need_dma32;
  763.         bool                            accel_working;
  764.         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  765.         const struct firmware *me_fw;   /* all family ME firmware */
  766.         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
  767.         struct r600_blit r600_blit;
  768. };
  769.  
  770. int radeon_device_init(struct radeon_device *rdev,
  771.                        struct drm_device *ddev,
  772.                        struct pci_dev *pdev,
  773.                        uint32_t flags);
  774. void radeon_device_fini(struct radeon_device *rdev);
  775. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  776.  
  777. /* r600 blit */
  778. int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
  779. void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
  780. void r600_kms_blit_copy(struct radeon_device *rdev,
  781.                         u64 src_gpu_addr, u64 dst_gpu_addr,
  782.                         int size_bytes);
  783.  
  784. static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
  785. {
  786.         if (reg < 0x10000)
  787.                 return readl(((void __iomem *)rdev->rmmio) + reg);
  788.         else {
  789.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  790.                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  791.         }
  792. }
  793.  
  794. static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  795. {
  796.         if (reg < 0x10000)
  797.                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
  798.         else {
  799.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  800.                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  801.         }
  802. }
  803.  
  804.  
  805. /*
  806.  * Registers read & write functions.
  807.  */
  808. #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
  809. #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
  810. #define RREG32(reg) r100_mm_rreg(rdev, (reg))
  811. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
  812. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  813. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  814. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  815. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  816. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  817. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  818. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  819. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  820. #define WREG32_P(reg, val, mask)                                \
  821.         do {                                                    \
  822.                 uint32_t tmp_ = RREG32(reg);                    \
  823.                 tmp_ &= (mask);                                 \
  824.                 tmp_ |= ((val) & ~(mask));                      \
  825.                 WREG32(reg, tmp_);                              \
  826.         } while (0)
  827. #define WREG32_PLL_P(reg, val, mask)                            \
  828.         do {                                                    \
  829.                 uint32_t tmp_ = RREG32_PLL(reg);                \
  830.                 tmp_ &= (mask);                                 \
  831.                 tmp_ |= ((val) & ~(mask));                      \
  832.                 WREG32_PLL(reg, tmp_);                          \
  833.         } while (0)
  834.  
  835. /*
  836.  * Indirect registers accessor
  837.  */
  838. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  839. {
  840.         uint32_t r;
  841.  
  842.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  843.         r = RREG32(RADEON_PCIE_DATA);
  844.         return r;
  845. }
  846.  
  847. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  848. {
  849.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  850.         WREG32(RADEON_PCIE_DATA, (v));
  851. }
  852.  
  853. void r100_pll_errata_after_index(struct radeon_device *rdev);
  854.  
  855.  
  856.  
  857. enum chipset_type {
  858.     NOT_SUPPORTED,
  859.     SUPPORTED,
  860. };
  861.  
  862. struct agp_version {
  863.     u16_t major;
  864.     u16_t minor;
  865. };
  866.  
  867. struct agp_bridge_data;
  868.  
  869. struct agp_kern_info {
  870.     struct agp_version version;
  871.     struct pci_dev *device;
  872.     enum chipset_type chipset;
  873.     unsigned long mode;
  874.     unsigned long aper_base;
  875.     size_t aper_size;
  876.     int max_memory;     /* In pages */
  877.     int current_memory;
  878.     bool cant_use_aperture;
  879.     unsigned long page_mask;
  880. //    struct vm_operations_struct *vm_ops;
  881. };
  882.  
  883.  
  884. /**
  885.  * AGP data.
  886.  *
  887.  * \sa drm_agp_init() and drm_device::agp.
  888.  */
  889. struct drm_agp_head {
  890.     struct agp_kern_info agp_info;      /**< AGP device information */
  891. //    struct list_head memory;
  892.     unsigned long mode;     /**< AGP mode */
  893.     struct agp_bridge_data *bridge;
  894.     int enabled;            /**< whether the AGP bus as been enabled */
  895.     int acquired;           /**< whether the AGP device has been acquired */
  896.     unsigned long base;
  897.     int agp_mtrr;
  898.     int cant_use_aperture;
  899.     unsigned long page_mask;
  900. };
  901.  
  902.  
  903.  
  904. /*
  905.  * ASICs helpers.
  906.  */
  907. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  908.                             (rdev->pdev->device == 0x5969))
  909. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  910.         (rdev->family == CHIP_RV200) || \
  911.         (rdev->family == CHIP_RS100) || \
  912.         (rdev->family == CHIP_RS200) || \
  913.         (rdev->family == CHIP_RV250) || \
  914.         (rdev->family == CHIP_RV280) || \
  915.         (rdev->family == CHIP_RS300))
  916. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
  917.         (rdev->family == CHIP_RV350) ||         \
  918.         (rdev->family == CHIP_R350)  ||         \
  919.         (rdev->family == CHIP_RV380) ||         \
  920.         (rdev->family == CHIP_R420)  ||         \
  921.         (rdev->family == CHIP_R423)  ||         \
  922.         (rdev->family == CHIP_RV410) ||         \
  923.         (rdev->family == CHIP_RS400) ||         \
  924.         (rdev->family == CHIP_RS480))
  925. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  926. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  927. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  928.  
  929.  
  930. /*
  931.  * BIOS helpers.
  932.  */
  933. #define RBIOS8(i) (rdev->bios[i])
  934. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  935. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  936.  
  937. int radeon_combios_init(struct radeon_device *rdev);
  938. void radeon_combios_fini(struct radeon_device *rdev);
  939. int radeon_atombios_init(struct radeon_device *rdev);
  940. void radeon_atombios_fini(struct radeon_device *rdev);
  941.  
  942.  
  943. /*
  944.  * RING helpers.
  945.  */
  946. static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  947. {
  948. #if DRM_DEBUG_CODE
  949.         if (rdev->cp.count_dw <= 0) {
  950.                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  951.         }
  952. #endif
  953.         rdev->cp.ring[rdev->cp.wptr++] = v;
  954.         rdev->cp.wptr &= rdev->cp.ptr_mask;
  955.         rdev->cp.count_dw--;
  956.         rdev->cp.ring_free_dw--;
  957. }
  958.  
  959.  
  960. /*
  961.  * ASICs macro.
  962.  */
  963. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  964. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  965. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  966. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  967. #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
  968. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  969. #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
  970. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
  971. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
  972. #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
  973. #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
  974. #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
  975. #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
  976. #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
  977. #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
  978. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
  979. #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
  980. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
  981. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
  982. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
  983. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  984. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  985. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
  986. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
  987. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
  988. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
  989. #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
  990.  
  991. /* Common functions */
  992. extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  993. extern int radeon_modeset_init(struct radeon_device *rdev);
  994. extern void radeon_modeset_fini(struct radeon_device *rdev);
  995. extern bool radeon_card_posted(struct radeon_device *rdev);
  996. extern int radeon_clocks_init(struct radeon_device *rdev);
  997. extern void radeon_clocks_fini(struct radeon_device *rdev);
  998. extern void radeon_scratch_init(struct radeon_device *rdev);
  999. extern void radeon_surface_init(struct radeon_device *rdev);
  1000. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  1001. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  1002. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  1003.  
  1004. /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
  1005. struct r100_mc_save {
  1006.         u32     GENMO_WT;
  1007.         u32     CRTC_EXT_CNTL;
  1008.         u32     CRTC_GEN_CNTL;
  1009.         u32     CRTC2_GEN_CNTL;
  1010.         u32     CUR_OFFSET;
  1011.         u32     CUR2_OFFSET;
  1012. };
  1013. extern void r100_cp_disable(struct radeon_device *rdev);
  1014. extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  1015. extern void r100_cp_fini(struct radeon_device *rdev);
  1016. extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  1017. extern int r100_pci_gart_init(struct radeon_device *rdev);
  1018. extern void r100_pci_gart_fini(struct radeon_device *rdev);
  1019. extern int r100_pci_gart_enable(struct radeon_device *rdev);
  1020. extern void r100_pci_gart_disable(struct radeon_device *rdev);
  1021. extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  1022. extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  1023. extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
  1024. extern void r100_ib_fini(struct radeon_device *rdev);
  1025. extern int r100_ib_init(struct radeon_device *rdev);
  1026. extern void r100_irq_disable(struct radeon_device *rdev);
  1027. extern int r100_irq_set(struct radeon_device *rdev);
  1028. extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
  1029. extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
  1030. extern void r100_vram_init_sizes(struct radeon_device *rdev);
  1031. extern void r100_wb_disable(struct radeon_device *rdev);
  1032. extern void r100_wb_fini(struct radeon_device *rdev);
  1033. extern int r100_wb_init(struct radeon_device *rdev);
  1034. extern void r100_hdp_reset(struct radeon_device *rdev);
  1035. extern int r100_rb2d_reset(struct radeon_device *rdev);
  1036. extern int r100_cp_reset(struct radeon_device *rdev);
  1037. extern void r100_vga_render_disable(struct radeon_device *rdev);
  1038. extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  1039.                                                 struct radeon_cs_packet *pkt,
  1040.                                                 struct radeon_object *robj);
  1041. extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  1042.                                 struct radeon_cs_packet *pkt,
  1043.                                 const unsigned *auth, unsigned n,
  1044.                                 radeon_packet0_check_t check);
  1045. extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
  1046.                                 struct radeon_cs_packet *pkt,
  1047.                                 unsigned idx);
  1048.  
  1049. /* rv200,rv250,rv280 */
  1050. extern void r200_set_safe_registers(struct radeon_device *rdev);
  1051.  
  1052. /* r300,r350,rv350,rv370,rv380 */
  1053. extern void r300_set_reg_safe(struct radeon_device *rdev);
  1054. extern void r300_mc_program(struct radeon_device *rdev);
  1055. extern void r300_vram_info(struct radeon_device *rdev);
  1056. extern void r300_clock_startup(struct radeon_device *rdev);
  1057. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  1058. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
  1059. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
  1060. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
  1061. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
  1062.  
  1063. /* r420,r423,rv410 */
  1064. extern int r420_mc_init(struct radeon_device *rdev);
  1065. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
  1066. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  1067. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  1068. extern void r420_pipes_init(struct radeon_device *rdev);
  1069.  
  1070. /* rv515 */
  1071. struct rv515_mc_save {
  1072.         u32 d1vga_control;
  1073.         u32 d2vga_control;
  1074.         u32 vga_render_control;
  1075.         u32 vga_hdp_control;
  1076.         u32 d1crtc_control;
  1077.         u32 d2crtc_control;
  1078. };
  1079. extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  1080. extern void rv515_vga_render_disable(struct radeon_device *rdev);
  1081. extern void rv515_set_safe_registers(struct radeon_device *rdev);
  1082. extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
  1083. extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
  1084. extern void rv515_clock_startup(struct radeon_device *rdev);
  1085. extern void rv515_debugfs(struct radeon_device *rdev);
  1086. extern int rv515_suspend(struct radeon_device *rdev);
  1087.  
  1088. /* rs400 */
  1089. extern int rs400_gart_init(struct radeon_device *rdev);
  1090. extern int rs400_gart_enable(struct radeon_device *rdev);
  1091. extern void rs400_gart_adjust_size(struct radeon_device *rdev);
  1092. extern void rs400_gart_disable(struct radeon_device *rdev);
  1093. extern void rs400_gart_fini(struct radeon_device *rdev);
  1094.  
  1095. /* rs600 */
  1096. extern void rs600_set_safe_registers(struct radeon_device *rdev);
  1097. extern int rs600_irq_set(struct radeon_device *rdev);
  1098. extern void rs600_irq_disable(struct radeon_device *rdev);
  1099.  
  1100. /* rs690, rs740 */
  1101. extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
  1102.                                         struct drm_display_mode *mode1,
  1103.                                         struct drm_display_mode *mode2);
  1104.  
  1105. /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
  1106. extern bool r600_card_posted(struct radeon_device *rdev);
  1107. extern void r600_cp_stop(struct radeon_device *rdev);
  1108. extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1109. extern int r600_cp_resume(struct radeon_device *rdev);
  1110. extern int r600_count_pipe_bits(uint32_t val);
  1111. extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
  1112. extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
  1113. extern int r600_pcie_gart_init(struct radeon_device *rdev);
  1114. extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  1115. extern int r600_ib_test(struct radeon_device *rdev);
  1116. extern int r600_ring_test(struct radeon_device *rdev);
  1117. extern void r600_wb_fini(struct radeon_device *rdev);
  1118. extern int r600_wb_enable(struct radeon_device *rdev);
  1119. extern void r600_wb_disable(struct radeon_device *rdev);
  1120. extern void r600_scratch_init(struct radeon_device *rdev);
  1121. extern int r600_blit_init(struct radeon_device *rdev);
  1122. extern void r600_blit_fini(struct radeon_device *rdev);
  1123. extern int r600_cp_init_microcode(struct radeon_device *rdev);
  1124. extern int r600_gpu_reset(struct radeon_device *rdev);
  1125.  
  1126.  
  1127.  
  1128.  
  1129.  
  1130.  
  1131.  
  1132.  
  1133.  
  1134. #define DRM_UDELAY(d)           udelay(d)
  1135.  
  1136. resource_size_t
  1137. drm_get_resource_start(struct drm_device *dev, unsigned int resource);
  1138. resource_size_t
  1139. drm_get_resource_len(struct drm_device *dev, unsigned int resource);
  1140.  
  1141. bool set_mode(struct drm_device *dev, int width, int height);
  1142.  
  1143.  
  1144.  
  1145. #endif
  1146.