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  1. #include "drmP.h"
  2. #include "drm.h"
  3. #include "radeon_drm.h"
  4. #include "radeon.h"
  5.  
  6. #include "r600d.h"
  7.  
  8. #define DI_PT_RECTLIST        0x11
  9. #define DI_INDEX_SIZE_16_BIT  0x0
  10. #define DI_SRC_SEL_AUTO_INDEX 0x2
  11.  
  12. #define FMT_8                 0x1
  13. #define FMT_5_6_5             0x8
  14. #define FMT_8_8_8_8           0x1a
  15. #define COLOR_8               0x1
  16. #define COLOR_5_6_5           0x8
  17. #define COLOR_8_8_8_8         0x1a
  18.  
  19. //#define  CP_PACKET2              0x80000000
  20. //#define  PACKET2_PAD_SHIFT       0
  21. //#define  PACKET2_PAD_MASK        (0x3fffffff << 0)
  22.  
  23. //#define PACKET2(v)  (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
  24.  
  25. extern const u32 r7xx_default_state[];
  26. extern const u32 r6xx_default_state[];
  27. extern const u32 r6xx_default_size, r7xx_default_size;
  28.  
  29. extern const u32 R600_video_ps[];
  30. extern const u32 R600_video_vs[];
  31.  
  32. extern const u32 r600_video_ps_size;
  33. extern const u32 r600_video_vs_size;
  34.  
  35. extern struct radeon_device *main_device;
  36.  
  37. int r600_video_init(struct radeon_device *rdev)
  38. {
  39.     u32 obj_size;
  40.     int i, r, dwords;
  41.     void *ptr;
  42.     u32 packet2s[16];
  43.     int num_packet2s = 0;
  44.  
  45.     /* pin copy shader into vram if already initialized */
  46.     if (rdev->r600_video.shader_obj)
  47.         goto done;
  48.  
  49.     mutex_init(&rdev->r600_video.mutex);
  50.     rdev->r600_video.state_offset = 0;
  51.  
  52.     if (rdev->family >= CHIP_RV770)
  53.         rdev->r600_video.state_len = r7xx_default_size;
  54.     else
  55.         rdev->r600_video.state_len = r6xx_default_size;
  56.  
  57.     dwords = rdev->r600_video.state_len;
  58.     while (dwords & 0xf) {
  59.         packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
  60.         dwords++;
  61.     }
  62.  
  63.     obj_size = dwords * 4;
  64.     obj_size = ALIGN(obj_size, 256);
  65.  
  66.     rdev->r600_video.vs_offset = obj_size;
  67.     obj_size += r600_video_vs_size * 4;
  68.     obj_size = ALIGN(obj_size, 256);
  69.  
  70.     rdev->r600_video.ps_offset = obj_size;
  71.     obj_size += r600_video_ps_size * 4;
  72.     obj_size = ALIGN(obj_size, 256);
  73.  
  74.     r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
  75.                 &rdev->r600_video.shader_obj);
  76.     if (r) {
  77.         DRM_ERROR("r600 failed to allocate video shader\n");
  78.         return r;
  79.     }
  80.  
  81.     DRM_DEBUG("r6xx video blit allocated bo %08x vs %08x ps %08x\n",
  82.           obj_size,
  83.           rdev->r600_video.vs_offset, rdev->r600_video.ps_offset);
  84.  
  85.     r = radeon_bo_reserve(rdev->r600_video.shader_obj, false);
  86.     if (unlikely(r != 0))
  87.         return r;
  88.     r = radeon_bo_kmap(rdev->r600_video.shader_obj, &ptr);
  89.     if (r) {
  90.         DRM_ERROR("failed to map blit object %d\n", r);
  91.         return r;
  92.     }
  93.     if (rdev->family >= CHIP_RV770)
  94.         memcpy(ptr + rdev->r600_video.state_offset,
  95.                 r7xx_default_state, rdev->r600_video.state_len * 4);
  96.     else
  97.         memcpy(ptr + rdev->r600_video.state_offset,
  98.                 r6xx_default_state, rdev->r600_video.state_len * 4);
  99.     if (num_packet2s)
  100.         memcpy(ptr + rdev->r600_video.state_offset + (rdev->r600_video.state_len * 4),
  101.                 packet2s, num_packet2s * 4);
  102.     for (i = 0; i < r600_video_vs_size; i++)
  103.         *(u32 *)((unsigned long)ptr + rdev->r600_video.vs_offset + i * 4) = cpu_to_le32(R600_video_vs[i]);
  104.     for (i = 0; i < r600_video_ps_size; i++)
  105.         *(u32 *)((unsigned long)ptr + rdev->r600_video.ps_offset + i * 4) = cpu_to_le32(R600_video_ps[i]);
  106.     radeon_bo_kunmap(rdev->r600_video.shader_obj);
  107.     radeon_bo_unreserve(rdev->r600_video.shader_obj);
  108.  
  109. done:
  110.     r = radeon_bo_reserve(rdev->r600_video.shader_obj, false);
  111.     if (unlikely(r != 0))
  112.         return r;
  113.     r = radeon_bo_pin(rdev->r600_video.shader_obj, RADEON_GEM_DOMAIN_VRAM,
  114.               &rdev->r600_video.shader_gpu_addr);
  115.     radeon_bo_unreserve(rdev->r600_video.shader_obj);
  116.     if (r) {
  117.         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
  118.         return r;
  119.     }
  120.  
  121.     return 0;
  122. }
  123.  
  124. /* emits 21 on rv770+, 23 on r600 */
  125. static void
  126. set_render_target(struct radeon_device *rdev, int format,
  127.           int w, int h, u64 gpu_addr)
  128. {
  129.     u32 cb_color_info;
  130.     int pitch, slice;
  131.  
  132.     h = ALIGN(h, 8);
  133.     if (h < 8)
  134.         h = 8;
  135.  
  136.     cb_color_info = ((format << 2) | (1 << 27) | (1 << 8));
  137.     pitch = (w / 8) - 1;
  138.     slice = ((w * h) / 64) - 1;
  139.  
  140.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  141.     radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  142.     radeon_ring_write(rdev, gpu_addr >> 8);
  143.  
  144.     if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
  145.         radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
  146.         radeon_ring_write(rdev, 2 << 0);
  147.     }
  148.  
  149.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  150.     radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  151.     radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
  152.  
  153.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  154.     radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  155.     radeon_ring_write(rdev, 0);
  156.  
  157.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  158.     radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  159.     radeon_ring_write(rdev, cb_color_info);
  160.  
  161.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  162.     radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  163.     radeon_ring_write(rdev, 0);
  164.  
  165.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  166.     radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  167.     radeon_ring_write(rdev, 0);
  168.  
  169.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  170.     radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  171.     radeon_ring_write(rdev, 0);
  172. }
  173.  
  174. /* emits 5dw */
  175. static void
  176. cp_set_surface_sync(struct radeon_device *rdev,
  177.             u32 sync_type, u32 size,
  178.             u64 mc_addr)
  179. {
  180.     u32 cp_coher_size;
  181.  
  182.     if (size == 0xffffffff)
  183.         cp_coher_size = 0xffffffff;
  184.     else
  185.         cp_coher_size = ((size + 255) >> 8);
  186.  
  187.     radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
  188.     radeon_ring_write(rdev, sync_type);
  189.     radeon_ring_write(rdev, cp_coher_size);
  190.     radeon_ring_write(rdev, mc_addr >> 8);
  191.     radeon_ring_write(rdev, 10); /* poll interval */
  192. }
  193.  
  194. /* emits 21dw + 1 surface sync = 26dw */
  195. static void
  196. set_shaders(struct radeon_device *rdev)
  197. {
  198.     u64 gpu_addr;
  199.     u32 sq_pgm_resources;
  200.  
  201.     /* setup shader regs */
  202.     sq_pgm_resources = (1 << 0);
  203.  
  204.     /* VS */
  205.     gpu_addr = rdev->r600_video.shader_gpu_addr + rdev->r600_video.vs_offset;
  206.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  207.     radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  208.     radeon_ring_write(rdev, gpu_addr >> 8);
  209.  
  210.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  211.     radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  212.     radeon_ring_write(rdev, sq_pgm_resources);
  213.  
  214.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  215.     radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  216.     radeon_ring_write(rdev, 0);
  217.  
  218.     /* PS */
  219.     gpu_addr = rdev->r600_video.shader_gpu_addr + rdev->r600_video.ps_offset;
  220.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  221.     radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  222.     radeon_ring_write(rdev, gpu_addr >> 8);
  223.  
  224.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  225.     radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  226.     radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
  227.  
  228.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  229.     radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  230.     radeon_ring_write(rdev, 2);
  231.  
  232.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  233.     radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  234.     radeon_ring_write(rdev, 0);
  235.  
  236.     gpu_addr = rdev->r600_video.shader_gpu_addr + rdev->r600_video.vs_offset;
  237.     cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
  238. }
  239.  
  240. /* emits 9 + 1 sync (5) = 14*/
  241. static void
  242. set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
  243. {
  244.     u32 sq_vtx_constant_word2;
  245.  
  246.     sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
  247. #ifdef __BIG_ENDIAN
  248.     sq_vtx_constant_word2 |= (2 << 30);
  249. #endif
  250.  
  251.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
  252.     radeon_ring_write(rdev, 0x460);
  253.     radeon_ring_write(rdev, gpu_addr & 0xffffffff);
  254.     radeon_ring_write(rdev, 48 - 1);
  255.     radeon_ring_write(rdev, sq_vtx_constant_word2);
  256.     radeon_ring_write(rdev, 1 << 0);
  257.     radeon_ring_write(rdev, 0);
  258.     radeon_ring_write(rdev, 0);
  259.     radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
  260.  
  261.     if ((rdev->family == CHIP_RV610) ||
  262.         (rdev->family == CHIP_RV620) ||
  263.         (rdev->family == CHIP_RS780) ||
  264.         (rdev->family == CHIP_RS880) ||
  265.         (rdev->family == CHIP_RV710))
  266.         cp_set_surface_sync(rdev,
  267.                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
  268.     else
  269.         cp_set_surface_sync(rdev,
  270.                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
  271. }
  272.  
  273. /* emits 9 */
  274. static void
  275. set_tex_resource(struct radeon_device *rdev,
  276.          int format, int w, int h, int pitch,
  277.          u64 gpu_addr)
  278. {
  279.     uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
  280.  
  281.     if (h < 1)
  282.         h = 1;
  283.  
  284.     sq_tex_resource_word0 = (1 << 0) | (1 << 3);
  285.     sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
  286.                   ((w - 1) << 19));
  287.  
  288.     sq_tex_resource_word1 = (format << 26);
  289.     sq_tex_resource_word1 |= ((h - 1) << 0);
  290.  
  291.     sq_tex_resource_word4 = ((1 << 14) |
  292.                  (0 << 16) |
  293.                  (1 << 19) |
  294.                  (2 << 22) |
  295.                  (3 << 25));
  296.  
  297.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
  298.     radeon_ring_write(rdev, 0);
  299.     radeon_ring_write(rdev, sq_tex_resource_word0);
  300.     radeon_ring_write(rdev, sq_tex_resource_word1);
  301.     radeon_ring_write(rdev, gpu_addr >> 8);
  302.     radeon_ring_write(rdev, gpu_addr >> 8);
  303.     radeon_ring_write(rdev, sq_tex_resource_word4);
  304.     radeon_ring_write(rdev, 0);
  305.     radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
  306. }
  307.  
  308. /* emits 12 */
  309. static void
  310. set_scissors(struct radeon_device *rdev, int x1, int y1,
  311.          int x2, int y2)
  312. {
  313.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
  314.     radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  315.     radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
  316.     radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
  317.  
  318.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
  319.     radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  320.     radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
  321.     radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
  322.  
  323.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
  324.     radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  325.     radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
  326.     radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
  327. }
  328.  
  329. /* emits 10 */
  330. static void
  331. draw_auto(struct radeon_device *rdev)
  332. {
  333.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  334.     radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
  335.     radeon_ring_write(rdev, DI_PT_RECTLIST);
  336.  
  337.     radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
  338.     radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
  339.  
  340.     radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
  341.     radeon_ring_write(rdev, 1);
  342.  
  343.     radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
  344.     radeon_ring_write(rdev, 3);
  345.     radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
  346.  
  347. }
  348.  
  349.  
  350. /* emits 14 */
  351. static void
  352. set_default_state(struct radeon_device *rdev)
  353. {
  354.     u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
  355.     u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
  356.     int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
  357.     int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
  358.     int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
  359.     u64 gpu_addr;
  360.     int dwords;
  361.  
  362.     switch (rdev->family) {
  363.     case CHIP_R600:
  364.         num_ps_gprs = 192;
  365.         num_vs_gprs = 56;
  366.         num_temp_gprs = 4;
  367.         num_gs_gprs = 0;
  368.         num_es_gprs = 0;
  369.         num_ps_threads = 136;
  370.         num_vs_threads = 48;
  371.         num_gs_threads = 4;
  372.         num_es_threads = 4;
  373.         num_ps_stack_entries = 128;
  374.         num_vs_stack_entries = 128;
  375.         num_gs_stack_entries = 0;
  376.         num_es_stack_entries = 0;
  377.         break;
  378.     case CHIP_RV630:
  379.     case CHIP_RV635:
  380.         num_ps_gprs = 84;
  381.         num_vs_gprs = 36;
  382.         num_temp_gprs = 4;
  383.         num_gs_gprs = 0;
  384.         num_es_gprs = 0;
  385.         num_ps_threads = 144;
  386.         num_vs_threads = 40;
  387.         num_gs_threads = 4;
  388.         num_es_threads = 4;
  389.         num_ps_stack_entries = 40;
  390.         num_vs_stack_entries = 40;
  391.         num_gs_stack_entries = 32;
  392.         num_es_stack_entries = 16;
  393.         break;
  394.     case CHIP_RV610:
  395.     case CHIP_RV620:
  396.     case CHIP_RS780:
  397.     case CHIP_RS880:
  398.     default:
  399.         num_ps_gprs = 84;
  400.         num_vs_gprs = 36;
  401.         num_temp_gprs = 4;
  402.         num_gs_gprs = 0;
  403.         num_es_gprs = 0;
  404.         num_ps_threads = 136;
  405.         num_vs_threads = 48;
  406.         num_gs_threads = 4;
  407.         num_es_threads = 4;
  408.         num_ps_stack_entries = 40;
  409.         num_vs_stack_entries = 40;
  410.         num_gs_stack_entries = 32;
  411.         num_es_stack_entries = 16;
  412.         break;
  413.     case CHIP_RV670:
  414.         num_ps_gprs = 144;
  415.         num_vs_gprs = 40;
  416.         num_temp_gprs = 4;
  417.         num_gs_gprs = 0;
  418.         num_es_gprs = 0;
  419.         num_ps_threads = 136;
  420.         num_vs_threads = 48;
  421.         num_gs_threads = 4;
  422.         num_es_threads = 4;
  423.         num_ps_stack_entries = 40;
  424.         num_vs_stack_entries = 40;
  425.         num_gs_stack_entries = 32;
  426.         num_es_stack_entries = 16;
  427.         break;
  428.     case CHIP_RV770:
  429.         num_ps_gprs = 192;
  430.         num_vs_gprs = 56;
  431.         num_temp_gprs = 4;
  432.         num_gs_gprs = 0;
  433.         num_es_gprs = 0;
  434.         num_ps_threads = 188;
  435.         num_vs_threads = 60;
  436.         num_gs_threads = 0;
  437.         num_es_threads = 0;
  438.         num_ps_stack_entries = 256;
  439.         num_vs_stack_entries = 256;
  440.         num_gs_stack_entries = 0;
  441.         num_es_stack_entries = 0;
  442.         break;
  443.     case CHIP_RV730:
  444.     case CHIP_RV740:
  445.         num_ps_gprs = 84;
  446.         num_vs_gprs = 36;
  447.         num_temp_gprs = 4;
  448.         num_gs_gprs = 0;
  449.         num_es_gprs = 0;
  450.         num_ps_threads = 188;
  451.         num_vs_threads = 60;
  452.         num_gs_threads = 0;
  453.         num_es_threads = 0;
  454.         num_ps_stack_entries = 128;
  455.         num_vs_stack_entries = 128;
  456.         num_gs_stack_entries = 0;
  457.         num_es_stack_entries = 0;
  458.         break;
  459.     case CHIP_RV710:
  460.         num_ps_gprs = 192;
  461.         num_vs_gprs = 56;
  462.         num_temp_gprs = 4;
  463.         num_gs_gprs = 0;
  464.         num_es_gprs = 0;
  465.         num_ps_threads = 144;
  466.         num_vs_threads = 48;
  467.         num_gs_threads = 0;
  468.         num_es_threads = 0;
  469.         num_ps_stack_entries = 128;
  470.         num_vs_stack_entries = 128;
  471.         num_gs_stack_entries = 0;
  472.         num_es_stack_entries = 0;
  473.         break;
  474.     }
  475.  
  476.     if ((rdev->family == CHIP_RV610) ||
  477.         (rdev->family == CHIP_RV620) ||
  478.         (rdev->family == CHIP_RS780) ||
  479.         (rdev->family == CHIP_RS880) ||
  480.         (rdev->family == CHIP_RV710))
  481.         sq_config = 0;
  482.     else
  483.         sq_config = VC_ENABLE;
  484.  
  485.     sq_config |= (DX9_CONSTS |
  486.               ALU_INST_PREFER_VECTOR |
  487.               PS_PRIO(0) |
  488.               VS_PRIO(1) |
  489.               GS_PRIO(2) |
  490.               ES_PRIO(3));
  491.  
  492.     sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
  493.                   NUM_VS_GPRS(num_vs_gprs) |
  494.                   NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
  495.     sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
  496.                   NUM_ES_GPRS(num_es_gprs));
  497.     sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
  498.                    NUM_VS_THREADS(num_vs_threads) |
  499.                    NUM_GS_THREADS(num_gs_threads) |
  500.                    NUM_ES_THREADS(num_es_threads));
  501.     sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
  502.                     NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
  503.     sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
  504.                     NUM_ES_STACK_ENTRIES(num_es_stack_entries));
  505.  
  506.     /* emit an IB pointing at default state */
  507.     dwords = ALIGN(rdev->r600_video.state_len, 0x10);
  508.     gpu_addr = rdev->r600_video.shader_gpu_addr + rdev->r600_video.state_offset;
  509.     radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
  510.     radeon_ring_write(rdev, (gpu_addr & 0xFFFFFFFC));
  511.     radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
  512.     radeon_ring_write(rdev, dwords);
  513.  
  514.     /* SQ config */
  515.     radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
  516.     radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
  517.     radeon_ring_write(rdev, sq_config);
  518.     radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
  519.     radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
  520.     radeon_ring_write(rdev, sq_thread_resource_mgmt);
  521.     radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
  522.     radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
  523. }
  524.  
  525. static inline uint32_t i2f(uint32_t input)
  526. {
  527.     u32 result, i, exponent, fraction;
  528.  
  529.     if ((input & 0x3fff) == 0)
  530.         result = 0; /* 0 is a special case */
  531.     else {
  532.         exponent = 140; /* exponent biased by 127; */
  533.         fraction = (input & 0x3fff) << 10; /* cheat and only
  534.                               handle numbers below 2^^15 */
  535.         for (i = 0; i < 14; i++) {
  536.             if (fraction & 0x800000)
  537.                 break;
  538.             else {
  539.                 fraction = fraction << 1; /* keep
  540.                                  shifting left until top bit = 1 */
  541.                 exponent = exponent - 1;
  542.             }
  543.         }
  544.         result = exponent << 23 | (fraction & 0x7fffff); /* mask
  545.                                     off top bit; assumed 1 */
  546.     }
  547.     return result;
  548. }
  549.  
  550. static int r600_vb_ib_get(struct radeon_device *rdev)
  551. {
  552.     int r;
  553.     r = radeon_ib_get(rdev, &rdev->r600_video.vb_ib);
  554.     if (r) {
  555.         DRM_ERROR("failed to get IB for vertex buffer\n");
  556.         return r;
  557.     }
  558.  
  559.     rdev->r600_video.vb_total = 64*1024;
  560.     rdev->r600_video.vb_used = 0;
  561.     return 0;
  562. }
  563.  
  564. static void r600_vb_ib_put(struct radeon_device *rdev)
  565. {
  566.     radeon_fence_emit(rdev, rdev->r600_video.vb_ib->fence);
  567.     radeon_ib_free(rdev, &rdev->r600_video.vb_ib);
  568. }
  569.  
  570.  
  571. int r600_video_prepare_copy(struct radeon_device *rdev, int size_bytes)
  572. {
  573.     int r;
  574.     int ring_size, line_size;
  575.     int max_size;
  576.     /* loops of emits 64 + fence emit possible */
  577.     int dwords_per_loop = 76, num_loops;
  578.  
  579.     r = r600_vb_ib_get(rdev);
  580.     if (r)
  581.         return r;
  582.  
  583.     /* set_render_target emits 2 extra dwords on rv6xx */
  584.     if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
  585.         dwords_per_loop += 2;
  586.  
  587.     /* 8 bpp vs 32 bpp for xfer unit */
  588.     if (size_bytes & 3)
  589.         line_size = 8192;
  590.     else
  591.         line_size = 8192*4;
  592.  
  593.     max_size = 8192 * line_size;
  594.  
  595.     /* major loops cover the max size transfer */
  596.     num_loops = ((size_bytes + max_size) / max_size);
  597.     /* minor loops cover the extra non aligned bits */
  598.     num_loops += ((size_bytes % line_size) ? 1 : 0);
  599.     /* calculate number of loops correctly */
  600.     ring_size = num_loops * dwords_per_loop;
  601.     /* set default  + shaders */
  602.     ring_size += 40; /* shaders + def state */
  603.     ring_size += 10; /* fence emit for VB IB */
  604.     ring_size += 5; /* done copy */
  605.     ring_size += 10; /* fence emit for done copy */
  606.     r = radeon_ring_lock(rdev, ring_size);
  607.     if (r)
  608.         return r;
  609.  
  610.     set_default_state(rdev); /* 14 */
  611.     set_shaders(rdev); /* 26 */
  612.     return 0;
  613. }
  614.  
  615. void r600_video_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
  616. {
  617.     int r;
  618.  
  619.     if (rdev->r600_video.vb_ib)
  620.         r600_vb_ib_put(rdev);
  621.  
  622.     if (fence)
  623.         r = radeon_fence_emit(rdev, fence);
  624.  
  625.     radeon_ring_unlock_commit(rdev);
  626. }
  627.  
  628. void r600_kms_video_blit(struct radeon_device *rdev,
  629.             u64 src_gpu_addr, int dstx, int dsty, int w, int h, int pitch)
  630. {
  631.     u64 vb_gpu_addr;
  632.     u32 *vb;
  633.  
  634. //    DRM_DEBUG("emitting video copy\n");
  635.     vb = (u32 *)(rdev->r600_video.vb_ib->ptr + rdev->r600_video.vb_used);
  636.  
  637.     if ((rdev->r600_video.vb_used + 48) > rdev->r600_video.vb_total) {
  638.               // WARN_ON(1);
  639.     }
  640.  
  641.     vb[0] = i2f(dstx);
  642.     vb[1] = i2f(dsty);
  643.     vb[2] = 0;
  644.     vb[3] = 0;
  645.  
  646.     vb[4] = i2f(dstx);
  647.     vb[5] = i2f(dsty+h);
  648.     vb[6] = 0;
  649.     vb[7] = i2f(h);
  650.  
  651.     vb[8] = i2f(dstx + w);
  652.     vb[9] = i2f(dsty + h);
  653.     vb[10] = i2f(w);
  654.     vb[11] = i2f(h);
  655.  
  656.     /* src 9 */
  657.     set_tex_resource(rdev, FMT_8_8_8_8,
  658.                      w, h, pitch/4, src_gpu_addr);
  659.     /* 5 */
  660.     cp_set_surface_sync(rdev,
  661.                         PACKET3_TC_ACTION_ENA, pitch * h, src_gpu_addr);
  662.  
  663.     /* dst 23 */
  664.     set_render_target(rdev, COLOR_8_8_8_8,
  665.                      1024, 768, rdev->mc.vram_start);
  666.  
  667.             /* scissors 12  */
  668.     set_scissors(rdev, 0, 0, 1024, 768);
  669.  
  670.     /* Vertex buffer setup 14 */
  671.     vb_gpu_addr = rdev->r600_video.vb_ib->gpu_addr + rdev->r600_video.vb_used;
  672.     set_vtx_resource(rdev, vb_gpu_addr);
  673.  
  674.     /* draw 10 */
  675.     draw_auto(rdev);
  676.  
  677.     /* 5 */
  678.     cp_set_surface_sync(rdev,
  679.                 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
  680.                 1024*4*768, rdev->mc.vram_start);
  681.  
  682.     /* 78 ring dwords per loop */
  683.     vb += 12;
  684.     rdev->r600_video.vb_used += 12 * 4;
  685.  
  686. }
  687.  
  688.  
  689.  
  690. int r600_video_blit(uint64_t src_offset, int  x, int y,
  691.                     int w, int h, int pitch)
  692. {
  693.     struct radeon_device *rdev = main_device;
  694.     static struct radeon_fence *fence;
  695.     unsigned long irq_flags;
  696.  
  697.     int r;
  698.  
  699.     if(fence == NULL)
  700.     {
  701.         r = radeon_fence_create(rdev, &fence);
  702.         if (r) {
  703.             printf("%s epic fail", __FUNCTION__);
  704.             return r;
  705.         }
  706.     };
  707.  
  708.     fence->evnt = CreateEvent(NULL, 0);
  709.  
  710.     mutex_lock(&rdev->r600_video.mutex);
  711.     rdev->r600_video.vb_ib = NULL;
  712.     r = r600_video_prepare_copy(rdev, w*4);
  713.     if (r) {
  714. //       if (rdev->r600_blit.vb_ib)
  715. //           radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
  716.         mutex_unlock(&rdev->r600_video.mutex);
  717.         return r;
  718.     }
  719.  
  720.     r600_kms_video_blit(rdev, src_offset,x,y,w,h,pitch);
  721.     r600_video_done_copy(rdev, fence);
  722.     mutex_unlock(&rdev->r600_video.mutex);
  723.  
  724.     r = radeon_fence_wait(fence, false);
  725.  
  726.     write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  727.     list_del(&fence->list);
  728.     fence->emited = false;
  729.     fence->signaled = false;
  730.     write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  731.  
  732.     return r;
  733. };
  734.  
  735.  
  736. int r600_create_video(int w, int h, u32_t *outp)
  737. {
  738.     int r;
  739.     struct radeon_device *rdev = main_device;
  740.     struct radeon_bo *sobj = NULL;
  741.     uint64_t saddr;
  742.     void   *uaddr;
  743.  
  744.     size_t size;
  745.     size_t pitch;
  746.  
  747.     pitch = radeon_align_pitch(rdev, w, 32, false) * 4;
  748.  
  749.     size = pitch * h;
  750.     r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
  751.                          RADEON_GEM_DOMAIN_GTT, &sobj);
  752.     if (r) {
  753.         goto fail;
  754.     }
  755.     r = radeon_bo_reserve(sobj, false);
  756.     if (unlikely(r != 0))
  757.         goto fail;
  758.     r = radeon_bo_pin(sobj, RADEON_GEM_DOMAIN_GTT, &saddr);
  759. //   radeon_bo_unreserve(sobj);
  760.     if (r) {
  761.         goto fail;
  762.     }
  763.  
  764.     r = radeon_bo_user_map(sobj, &uaddr);
  765.     if (r) {
  766.         goto fail;
  767.     }
  768.  
  769.     ((uint64_t*)outp)[0] = saddr;
  770.     outp[2] = uaddr;
  771.     outp[3] = pitch;
  772.  
  773. //    dbgprintf("Create video surface %x, mapped at %x pitch %d\n",
  774. //              (uint32_t)saddr, uaddr, pitch);
  775.     return 0;
  776.  
  777. fail:
  778.     return -1;
  779. };
  780.  
  781.  
  782.  
  783.  
  784.  
  785.