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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Christian König.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Christian König
  25.  */
  26. #include <linux/hdmi.h>
  27. #include <drm/drmP.h>
  28. #include <drm/radeon_drm.h>
  29. #include "radeon.h"
  30. #include "radeon_asic.h"
  31. #include "r600d.h"
  32. #include "atom.h"
  33.  
  34. /*
  35.  * HDMI color format
  36.  */
  37. enum r600_hdmi_color_format {
  38.         RGB = 0,
  39.         YCC_422 = 1,
  40.         YCC_444 = 2
  41. };
  42.  
  43. /*
  44.  * IEC60958 status bits
  45.  */
  46. enum r600_hdmi_iec_status_bits {
  47.         AUDIO_STATUS_DIG_ENABLE   = 0x01,
  48.         AUDIO_STATUS_V      = 0x02,
  49.         AUDIO_STATUS_VCFG        = 0x04,
  50.         AUDIO_STATUS_EMPHASIS     = 0x08,
  51.         AUDIO_STATUS_COPYRIGHT    = 0x10,
  52.         AUDIO_STATUS_NONAUDIO     = 0x20,
  53.         AUDIO_STATUS_PROFESSIONAL = 0x40,
  54.         AUDIO_STATUS_LEVEL      = 0x80
  55. };
  56.  
  57. static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
  58.     /*       32kHz        44.1kHz       48kHz    */
  59.     /* Clock      N     CTS      N     CTS      N     CTS */
  60.     {  25175,  4096,  25175, 28224, 125875,  6144,  25175 }, /*  25,20/1.001 MHz */
  61.     {  25200,  4096,  25200,  6272,  28000,  6144,  25200 }, /*  25.20       MHz */
  62.     {  27000,  4096,  27000,  6272,  30000,  6144,  27000 }, /*  27.00       MHz */
  63.     {  27027,  4096,  27027,  6272,  30030,  6144,  27027 }, /*  27.00*1.001 MHz */
  64.     {  54000,  4096,  54000,  6272,  60000,  6144,  54000 }, /*  54.00       MHz */
  65.     {  54054,  4096,  54054,  6272,  60060,  6144,  54054 }, /*  54.00*1.001 MHz */
  66.     {  74176,  4096,  74176,  5733,  75335,  6144,  74176 }, /*  74.25/1.001 MHz */
  67.     {  74250,  4096,  74250,  6272,  82500,  6144,  74250 }, /*  74.25       MHz */
  68.     { 148352,  4096, 148352,  5733, 150670,  6144, 148352 }, /* 148.50/1.001 MHz */
  69.     { 148500,  4096, 148500,  6272, 165000,  6144, 148500 }, /* 148.50       MHz */
  70. };
  71.  
  72.  
  73. /*
  74.  * check if the chipset is supported
  75.  */
  76. static int r600_audio_chipset_supported(struct radeon_device *rdev)
  77. {
  78.         return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev);
  79. }
  80.  
  81. static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
  82. {
  83.         struct r600_audio_pin status;
  84.         uint32_t value;
  85.  
  86.         value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
  87.  
  88.         /* number of channels */
  89.         status.channels = (value & 0x7) + 1;
  90.  
  91.         /* bits per sample */
  92.         switch ((value & 0xF0) >> 4) {
  93.         case 0x0:
  94.                 status.bits_per_sample = 8;
  95.                 break;
  96.         case 0x1:
  97.                 status.bits_per_sample = 16;
  98.                 break;
  99.         case 0x2:
  100.                 status.bits_per_sample = 20;
  101.                 break;
  102.         case 0x3:
  103.                 status.bits_per_sample = 24;
  104.                 break;
  105.         case 0x4:
  106.                 status.bits_per_sample = 32;
  107.                 break;
  108.         default:
  109.                 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
  110.                         (int)value);
  111.                 status.bits_per_sample = 16;
  112.         }
  113.  
  114.         /* current sampling rate in HZ */
  115.         if (value & 0x4000)
  116.                 status.rate = 44100;
  117.         else
  118.                 status.rate = 48000;
  119.         status.rate *= ((value >> 11) & 0x7) + 1;
  120.         status.rate /= ((value >> 8) & 0x7) + 1;
  121.  
  122.         value = RREG32(R600_AUDIO_STATUS_BITS);
  123.  
  124.         /* iec 60958 status bits */
  125.         status.status_bits = value & 0xff;
  126.  
  127.         /* iec 60958 category code */
  128.         status.category_code = (value >> 8) & 0xff;
  129.  
  130.         return status;
  131. }
  132.  
  133. /*
  134.  * update all hdmi interfaces with current audio parameters
  135.  */
  136. void r600_audio_update_hdmi(struct work_struct *work)
  137. {
  138.         struct radeon_device *rdev = container_of(work, struct radeon_device,
  139.                                                   audio_work);
  140.         struct drm_device *dev = rdev->ddev;
  141.         struct r600_audio_pin audio_status = r600_audio_status(rdev);
  142.         struct drm_encoder *encoder;
  143.         bool changed = false;
  144.  
  145.         if (rdev->audio.pin[0].channels != audio_status.channels ||
  146.             rdev->audio.pin[0].rate != audio_status.rate ||
  147.             rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
  148.             rdev->audio.pin[0].status_bits != audio_status.status_bits ||
  149.             rdev->audio.pin[0].category_code != audio_status.category_code) {
  150.                 rdev->audio.pin[0] = audio_status;
  151.                 changed = true;
  152.         }
  153.  
  154.         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  155.                 if (!radeon_encoder_is_digital(encoder))
  156.                         continue;
  157.                 if (changed || r600_hdmi_buffer_status_changed(encoder))
  158.                         r600_hdmi_update_audio_settings(encoder);
  159.         }
  160. }
  161.  
  162. /* enable the audio stream */
  163. void r600_audio_enable(struct radeon_device *rdev,
  164.                        struct r600_audio_pin *pin,
  165.                        u8 enable_mask)
  166. {
  167.         u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
  168.  
  169.         if (!pin)
  170.                 return;
  171.  
  172.         if (enable_mask) {
  173.                 tmp |= AUDIO_ENABLED;
  174.                 if (enable_mask & 1)
  175.                         tmp |= PIN0_AUDIO_ENABLED;
  176.                 if (enable_mask & 2)
  177.                         tmp |= PIN1_AUDIO_ENABLED;
  178.                 if (enable_mask & 4)
  179.                         tmp |= PIN2_AUDIO_ENABLED;
  180.                 if (enable_mask & 8)
  181.                         tmp |= PIN3_AUDIO_ENABLED;
  182.         } else {
  183.                 tmp &= ~(AUDIO_ENABLED |
  184.                          PIN0_AUDIO_ENABLED |
  185.                          PIN1_AUDIO_ENABLED |
  186.                          PIN2_AUDIO_ENABLED |
  187.                          PIN3_AUDIO_ENABLED);
  188.         }
  189.  
  190.         WREG32(AZ_HOT_PLUG_CONTROL, tmp);
  191. }
  192.  
  193. /*
  194.  * initialize the audio vars
  195.  */
  196. int r600_audio_init(struct radeon_device *rdev)
  197. {
  198.         if (!radeon_audio || !r600_audio_chipset_supported(rdev))
  199.                 return 0;
  200.  
  201.         rdev->audio.enabled = true;
  202.  
  203.         rdev->audio.num_pins = 1;
  204.         rdev->audio.pin[0].channels = -1;
  205.         rdev->audio.pin[0].rate = -1;
  206.         rdev->audio.pin[0].bits_per_sample = -1;
  207.         rdev->audio.pin[0].status_bits = 0;
  208.         rdev->audio.pin[0].category_code = 0;
  209.         rdev->audio.pin[0].id = 0;
  210.         /* disable audio.  it will be set up later */
  211.         r600_audio_enable(rdev, &rdev->audio.pin[0], 0);
  212.  
  213.         return 0;
  214. }
  215.  
  216. /*
  217.  * release the audio timer
  218.  * TODO: How to do this correctly on SMP systems?
  219.  */
  220. void r600_audio_fini(struct radeon_device *rdev)
  221. {
  222.         if (!rdev->audio.enabled)
  223.                 return;
  224.  
  225.         r600_audio_enable(rdev, &rdev->audio.pin[0], 0);
  226.  
  227.         rdev->audio.enabled = false;
  228. }
  229.  
  230. struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
  231. {
  232.         /* only one pin on 6xx-NI */
  233.         return &rdev->audio.pin[0];
  234. }
  235.  
  236. /*
  237.  * calculate CTS and N values if they are not found in the table
  238.  */
  239. static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
  240. {
  241.         int n, cts;
  242.         unsigned long div, mul;
  243.  
  244.         /* Safe, but overly large values */
  245.         n = 128 * freq;
  246.         cts = clock * 1000;
  247.  
  248.         /* Smallest valid fraction */
  249.         div = gcd(n, cts);
  250.  
  251.         n /= div;
  252.         cts /= div;
  253.  
  254.         /*
  255.          * The optimal N is 128*freq/1000. Calculate the closest larger
  256.          * value that doesn't truncate any bits.
  257.          */
  258.         mul = ((128*freq/1000) + (n-1))/n;
  259.  
  260.         n *= mul;
  261.         cts *= mul;
  262.  
  263.         /* Check that we are in spec (not always possible) */
  264.         if (n < (128*freq/1500))
  265.                 printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
  266.         if (n > (128*freq/300))
  267.                 printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");
  268.  
  269.         *N = n;
  270.         *CTS = cts;
  271.  
  272.         DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
  273.                   *N, *CTS, freq);
  274. }
  275.  
  276. struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
  277. {
  278.         struct radeon_hdmi_acr res;
  279.         u8 i;
  280.  
  281.         /* Precalculated values for common clocks */
  282.         for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) {
  283.                 if (r600_hdmi_predefined_acr[i].clock == clock)
  284.                         return r600_hdmi_predefined_acr[i];
  285.         }
  286.  
  287.         /* And odd clocks get manually calculated */
  288.         r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
  289.         r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
  290.         r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
  291.  
  292.         return res;
  293. }
  294.  
  295. /*
  296.  * update the N and CTS parameters for a given pixel clock rate
  297.  */
  298. void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  299. {
  300.         struct drm_device *dev = encoder->dev;
  301.         struct radeon_device *rdev = dev->dev_private;
  302.         struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
  303.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  304.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  305.         uint32_t offset = dig->afmt->offset;
  306.  
  307.         WREG32_P(HDMI0_ACR_32_0 + offset,
  308.                  HDMI0_ACR_CTS_32(acr.cts_32khz),
  309.                  ~HDMI0_ACR_CTS_32_MASK);
  310.         WREG32_P(HDMI0_ACR_32_1 + offset,
  311.                  HDMI0_ACR_N_32(acr.n_32khz),
  312.                  ~HDMI0_ACR_N_32_MASK);
  313.  
  314.         WREG32_P(HDMI0_ACR_44_0 + offset,
  315.                  HDMI0_ACR_CTS_44(acr.cts_44_1khz),
  316.                  ~HDMI0_ACR_CTS_44_MASK);
  317.         WREG32_P(HDMI0_ACR_44_1 + offset,
  318.                  HDMI0_ACR_N_44(acr.n_44_1khz),
  319.                  ~HDMI0_ACR_N_44_MASK);
  320.  
  321.         WREG32_P(HDMI0_ACR_48_0 + offset,
  322.                  HDMI0_ACR_CTS_48(acr.cts_48khz),
  323.                  ~HDMI0_ACR_CTS_48_MASK);
  324.         WREG32_P(HDMI0_ACR_48_1 + offset,
  325.                  HDMI0_ACR_N_48(acr.n_48khz),
  326.                  ~HDMI0_ACR_N_48_MASK);
  327. }
  328.  
  329. /*
  330.  * build a HDMI Video Info Frame
  331.  */
  332. void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
  333.                                     size_t size)
  334. {
  335.         struct drm_device *dev = encoder->dev;
  336.         struct radeon_device *rdev = dev->dev_private;
  337.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  338.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  339.         uint32_t offset = dig->afmt->offset;
  340.         uint8_t *frame = buffer + 3;
  341.         uint8_t *header = buffer;
  342.  
  343.         WREG32(HDMI0_AVI_INFO0 + offset,
  344.                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
  345.         WREG32(HDMI0_AVI_INFO1 + offset,
  346.                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
  347.         WREG32(HDMI0_AVI_INFO2 + offset,
  348.                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
  349.         WREG32(HDMI0_AVI_INFO3 + offset,
  350.                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
  351. }
  352.  
  353. /*
  354.  * build a Audio Info Frame
  355.  */
  356. static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
  357.                                              const void *buffer, size_t size)
  358. {
  359.         struct drm_device *dev = encoder->dev;
  360.         struct radeon_device *rdev = dev->dev_private;
  361.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  362.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  363.         uint32_t offset = dig->afmt->offset;
  364.         const u8 *frame = buffer + 3;
  365.  
  366.         WREG32(HDMI0_AUDIO_INFO0 + offset,
  367.                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
  368.         WREG32(HDMI0_AUDIO_INFO1 + offset,
  369.                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
  370. }
  371.  
  372. /*
  373.  * test if audio buffer is filled enough to start playing
  374.  */
  375. static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
  376. {
  377.         struct drm_device *dev = encoder->dev;
  378.         struct radeon_device *rdev = dev->dev_private;
  379.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  380.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  381.         uint32_t offset = dig->afmt->offset;
  382.  
  383.         return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
  384. }
  385.  
  386. /*
  387.  * have buffer status changed since last call?
  388.  */
  389. int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
  390. {
  391.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  392.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  393.         int status, result;
  394.  
  395.         if (!dig->afmt || !dig->afmt->enabled)
  396.                 return 0;
  397.  
  398.         status = r600_hdmi_is_audio_buffer_filled(encoder);
  399.         result = dig->afmt->last_buffer_filled_status != status;
  400.         dig->afmt->last_buffer_filled_status = status;
  401.  
  402.         return result;
  403. }
  404.  
  405. /*
  406.  * write the audio workaround status to the hardware
  407.  */
  408. void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
  409. {
  410.         struct drm_device *dev = encoder->dev;
  411.         struct radeon_device *rdev = dev->dev_private;
  412.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  413.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  414.         uint32_t offset = dig->afmt->offset;
  415.         bool hdmi_audio_workaround = false; /* FIXME */
  416.         u32 value;
  417.  
  418.         if (!hdmi_audio_workaround ||
  419.             r600_hdmi_is_audio_buffer_filled(encoder))
  420.                 value = 0; /* disable workaround */
  421.         else
  422.                 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
  423.         WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
  424.                  value, ~HDMI0_AUDIO_TEST_EN);
  425. }
  426.  
  427. void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
  428. {
  429.         struct drm_device *dev = encoder->dev;
  430.         struct radeon_device *rdev = dev->dev_private;
  431.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  432.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  433.         u32 base_rate = 24000;
  434.         u32 max_ratio = clock / base_rate;
  435.         u32 dto_phase;
  436.         u32 dto_modulo = clock;
  437.         u32 wallclock_ratio;
  438.         u32 dto_cntl;
  439.  
  440.         if (!dig || !dig->afmt)
  441.                 return;
  442.  
  443.         if (max_ratio >= 8) {
  444.                 dto_phase = 192 * 1000;
  445.                 wallclock_ratio = 3;
  446.         } else if (max_ratio >= 4) {
  447.                 dto_phase = 96 * 1000;
  448.                 wallclock_ratio = 2;
  449.         } else if (max_ratio >= 2) {
  450.                 dto_phase = 48 * 1000;
  451.                 wallclock_ratio = 1;
  452.         } else {
  453.                 dto_phase = 24 * 1000;
  454.                 wallclock_ratio = 0;
  455.         }
  456.  
  457.         /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
  458.          * doesn't matter which one you use.  Just use the first one.
  459.          */
  460.         /* XXX two dtos; generally use dto0 for hdmi */
  461.         /* Express [24MHz / target pixel clock] as an exact rational
  462.          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
  463.          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
  464.          */
  465.         if (ASIC_IS_DCE32(rdev)) {
  466.                 if (dig->dig_encoder == 0) {
  467.                         dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
  468.                         dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
  469.                         WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
  470.                         WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
  471.                         WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
  472.                         WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
  473.                 } else {
  474.                         dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
  475.                         dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
  476.                         WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
  477.                         WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
  478.                         WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
  479.                         WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
  480.                 }
  481.         } else {
  482.                 /* according to the reg specs, this should DCE3.2 only, but in
  483.                  * practice it seems to cover DCE2.0/3.0/3.1 as well.
  484.                  */
  485.                 if (dig->dig_encoder == 0) {
  486.                 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
  487.                 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
  488.                 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
  489.         } else {
  490.                         WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);
  491.                         WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
  492.                         WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
  493.                 }
  494.         }
  495. }
  496.  
  497. /*
  498.  * update the info frames with the data from the current display mode
  499.  */
  500. void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
  501. {
  502.         struct drm_device *dev = encoder->dev;
  503.         struct radeon_device *rdev = dev->dev_private;
  504.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  505.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  506.         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
  507.         struct hdmi_avi_infoframe frame;
  508.         uint32_t offset;
  509.         uint32_t acr_ctl;
  510.         ssize_t err;
  511.  
  512.         if (!dig || !dig->afmt)
  513.                 return;
  514.  
  515.         /* Silent, r600_hdmi_enable will raise WARN for us */
  516.         if (!dig->afmt->enabled)
  517.                 return;
  518.         offset = dig->afmt->offset;
  519.  
  520.         /* disable audio prior to setting up hw */
  521.         dig->afmt->pin = r600_audio_get_pin(rdev);
  522.         r600_audio_enable(rdev, dig->afmt->pin, 0xf);
  523.  
  524.         r600_audio_set_dto(encoder, mode->clock);
  525.  
  526.         WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
  527.                        HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
  528.                        HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
  529.                        HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
  530.                  HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */
  531.                  ~(HDMI0_AUDIO_SAMPLE_SEND |
  532.                    HDMI0_AUDIO_DELAY_EN_MASK |
  533.                    HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
  534.                    HDMI0_60958_CS_UPDATE));
  535.  
  536.         /* DCE 3.0 uses register that's normally for CRC_CONTROL */
  537.         acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
  538.                                        HDMI0_ACR_PACKET_CONTROL;
  539.         WREG32_P(acr_ctl + offset,
  540.                HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
  541.                  HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
  542.                  ~(HDMI0_ACR_SOURCE |
  543.                    HDMI0_ACR_AUTO_SEND));
  544.  
  545.         WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
  546.                HDMI0_NULL_SEND | /* send null packets when required */
  547.                HDMI0_GC_SEND | /* send general control packets */
  548.                HDMI0_GC_CONT); /* send general control packets every frame */
  549.  
  550.         WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
  551.                HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
  552.                HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
  553.                HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
  554.                   HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
  555.  
  556.         WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
  557.                HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
  558.                  HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */
  559.                  ~(HDMI0_AVI_INFO_LINE_MASK |
  560.                    HDMI0_AUDIO_INFO_LINE_MASK));
  561.  
  562.         WREG32_AND(HDMI0_GC + offset,
  563.                    ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */
  564.  
  565.         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
  566.         if (err < 0) {
  567.                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
  568.                 return;
  569.         }
  570.  
  571.         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
  572.         if (err < 0) {
  573.                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
  574.                 return;
  575.         }
  576.  
  577.         r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
  578.  
  579.         /* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */
  580.  
  581.         WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
  582.                    ~(HDMI0_GENERIC0_SEND |
  583.                      HDMI0_GENERIC0_CONT |
  584.                      HDMI0_GENERIC0_UPDATE |
  585.                      HDMI0_GENERIC1_SEND |
  586.                      HDMI0_GENERIC1_CONT |
  587.                      HDMI0_GENERIC0_LINE_MASK |
  588.                      HDMI0_GENERIC1_LINE_MASK));
  589.  
  590.         r600_hdmi_update_ACR(encoder, mode->clock);
  591.  
  592.         WREG32_P(HDMI0_60958_0 + offset,
  593.                  HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
  594.                  ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
  595.                    HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
  596.  
  597.         WREG32_P(HDMI0_60958_1 + offset,
  598.                  HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
  599.                  ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
  600.  
  601.         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
  602.         WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
  603.         WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
  604.         WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
  605.         WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
  606.  
  607.         /* enable audio after to setting up hw */
  608.         r600_audio_enable(rdev, dig->afmt->pin, 0xf);
  609. }
  610.  
  611. /**
  612.  * r600_hdmi_update_audio_settings - Update audio infoframe
  613.  *
  614.  * @encoder: drm encoder
  615.  *
  616.  * Gets info about current audio stream and updates audio infoframe.
  617.  */
  618. void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
  619. {
  620.         struct drm_device *dev = encoder->dev;
  621.         struct radeon_device *rdev = dev->dev_private;
  622.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  623.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  624.         struct r600_audio_pin audio = r600_audio_status(rdev);
  625.         uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
  626.         struct hdmi_audio_infoframe frame;
  627.         uint32_t offset;
  628.         uint32_t value;
  629.         ssize_t err;
  630.  
  631.         if (!dig->afmt || !dig->afmt->enabled)
  632.                 return;
  633.         offset = dig->afmt->offset;
  634.  
  635.         DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
  636.                  r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
  637.                   audio.channels, audio.rate, audio.bits_per_sample);
  638.         DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
  639.                   (int)audio.status_bits, (int)audio.category_code);
  640.  
  641.         err = hdmi_audio_infoframe_init(&frame);
  642.         if (err < 0) {
  643.                 DRM_ERROR("failed to setup audio infoframe\n");
  644.                 return;
  645.         }
  646.  
  647.         frame.channels = audio.channels;
  648.  
  649.         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
  650.         if (err < 0) {
  651.                 DRM_ERROR("failed to pack audio infoframe\n");
  652.                 return;
  653.         }
  654.  
  655.         value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
  656.         if (value & HDMI0_AUDIO_TEST_EN)
  657.                 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
  658.                        value & ~HDMI0_AUDIO_TEST_EN);
  659.  
  660.         WREG32_OR(HDMI0_CONTROL + offset,
  661.                   HDMI0_ERROR_ACK);
  662.  
  663.         WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
  664.                    ~HDMI0_AUDIO_INFO_SOURCE);
  665.  
  666.         r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
  667.  
  668.         WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
  669.                   HDMI0_AUDIO_INFO_CONT |
  670.                   HDMI0_AUDIO_INFO_UPDATE);
  671. }
  672.  
  673. /*
  674.  * enable the HDMI engine
  675.  */
  676. void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
  677. {
  678.         struct drm_device *dev = encoder->dev;
  679.         struct radeon_device *rdev = dev->dev_private;
  680.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  681.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  682.         u32 hdmi = HDMI0_ERROR_ACK;
  683.  
  684.         if (!dig || !dig->afmt)
  685.                 return;
  686.  
  687.         /* Silent, r600_hdmi_enable will raise WARN for us */
  688.         if (enable && dig->afmt->enabled)
  689.                 return;
  690.         if (!enable && !dig->afmt->enabled)
  691.                 return;
  692.  
  693.         if (!enable && dig->afmt->pin) {
  694.                 r600_audio_enable(rdev, dig->afmt->pin, 0);
  695.                 dig->afmt->pin = NULL;
  696.         }
  697.  
  698.         /* Older chipsets require setting HDMI and routing manually */
  699.         if (!ASIC_IS_DCE3(rdev)) {
  700.                 if (enable)
  701.                         hdmi |= HDMI0_ENABLE;
  702.         switch (radeon_encoder->encoder_id) {
  703.         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  704.                         if (enable) {
  705.                                 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
  706.                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
  707.                         } else {
  708.                                 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
  709.                         }
  710.                 break;
  711.         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  712.                         if (enable) {
  713.                                 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
  714.                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
  715.                         } else {
  716.                                 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
  717.                         }
  718.                         break;
  719.                 case ENCODER_OBJECT_ID_INTERNAL_DDI:
  720.                         if (enable) {
  721.                                 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
  722.                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
  723.                         } else {
  724.                                 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
  725.                         }
  726.                         break;
  727.                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  728.                         if (enable)
  729.                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
  730.                 break;
  731.         default:
  732.                         dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
  733.                                 radeon_encoder->encoder_id);
  734.                 break;
  735.         }
  736.                 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
  737.         }
  738.  
  739.         if (rdev->irq.installed) {
  740.                 /* if irq is available use it */
  741.                 /* XXX: shouldn't need this on any asics.  Double check DCE2/3 */
  742. //       if (enable)
  743. //           radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
  744. //       else
  745. //           radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
  746.         }
  747.  
  748.         dig->afmt->enabled = enable;
  749.  
  750.         DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
  751.                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
  752. }
  753.  
  754.