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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Christian König.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Christian König
  25.  *          Rafał Miłecki
  26.  */
  27. #include <linux/hdmi.h>
  28. #include <drm/drmP.h>
  29. #include <drm/radeon_drm.h>
  30. #include "radeon.h"
  31. #include "radeon_asic.h"
  32. #include "evergreend.h"
  33. #include "atom.h"
  34.  
  35. /*
  36.  * update the N and CTS parameters for a given pixel clock rate
  37.  */
  38. static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  39. {
  40.         struct drm_device *dev = encoder->dev;
  41.         struct radeon_device *rdev = dev->dev_private;
  42.         struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
  43.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  44.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  45.         uint32_t offset = dig->afmt->offset;
  46.  
  47.         WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
  48.         WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
  49.  
  50.         WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
  51.         WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
  52.  
  53.         WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
  54.         WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
  55. }
  56.  
  57. static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
  58. {
  59.         struct radeon_device *rdev = encoder->dev->dev_private;
  60.         struct drm_connector *connector;
  61.         struct radeon_connector *radeon_connector = NULL;
  62.         struct cea_sad *sads;
  63.         int i, sad_count;
  64.  
  65.         static const u16 eld_reg_to_type[][2] = {
  66.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
  67.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
  68.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
  69.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
  70.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
  71.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
  72.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
  73.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
  74.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
  75.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
  76.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
  77.                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
  78.         };
  79.  
  80.         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  81.                 if (connector->encoder == encoder)
  82.                         radeon_connector = to_radeon_connector(connector);
  83.         }
  84.  
  85.         if (!radeon_connector) {
  86.                 DRM_ERROR("Couldn't find encoder's connector\n");
  87.                 return;
  88.         }
  89.  
  90.         sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
  91.         if (sad_count < 0) {
  92.                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
  93.                 return;
  94.         }
  95.         BUG_ON(!sads);
  96.  
  97.         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
  98.                 u32 value = 0;
  99.                 int j;
  100.  
  101.                 for (j = 0; j < sad_count; j++) {
  102.                         struct cea_sad *sad = &sads[j];
  103.  
  104.                         if (sad->format == eld_reg_to_type[i][1]) {
  105.                                 value = MAX_CHANNELS(sad->channels) |
  106.                                         DESCRIPTOR_BYTE_2(sad->byte2) |
  107.                                         SUPPORTED_FREQUENCIES(sad->freq);
  108.                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
  109.                                         value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
  110.                                 break;
  111.                         }
  112.                 }
  113.                 WREG32(eld_reg_to_type[i][0], value);
  114.         }
  115.  
  116.         kfree(sads);
  117. }
  118.  
  119. /*
  120.  * build a HDMI Video Info Frame
  121.  */
  122. static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
  123.                                                 void *buffer, size_t size)
  124. {
  125.         struct drm_device *dev = encoder->dev;
  126.         struct radeon_device *rdev = dev->dev_private;
  127.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  128.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  129.         uint32_t offset = dig->afmt->offset;
  130.         uint8_t *frame = buffer + 3;
  131.  
  132.         /* Our header values (type, version, length) should be alright, Intel
  133.          * is using the same. Checksum function also seems to be OK, it works
  134.          * fine for audio infoframe. However calculated value is always lower
  135.          * by 2 in comparison to fglrx. It breaks displaying anything in case
  136.          * of TVs that strictly check the checksum. Hack it manually here to
  137.          * workaround this issue. */
  138.         frame[0x0] += 2;
  139.  
  140.         WREG32(AFMT_AVI_INFO0 + offset,
  141.                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
  142.         WREG32(AFMT_AVI_INFO1 + offset,
  143.                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
  144.         WREG32(AFMT_AVI_INFO2 + offset,
  145.                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
  146.         WREG32(AFMT_AVI_INFO3 + offset,
  147.                 frame[0xC] | (frame[0xD] << 8));
  148. }
  149.  
  150. /*
  151.  * update the info frames with the data from the current display mode
  152.  */
  153. void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
  154. {
  155.         struct drm_device *dev = encoder->dev;
  156.         struct radeon_device *rdev = dev->dev_private;
  157.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  158.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  159.         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
  160.         struct hdmi_avi_infoframe frame;
  161.         uint32_t offset;
  162.         ssize_t err;
  163.  
  164.         /* Silent, r600_hdmi_enable will raise WARN for us */
  165.         if (!dig->afmt->enabled)
  166.                 return;
  167.         offset = dig->afmt->offset;
  168.  
  169. //   r600_audio_set_clock(encoder, mode->clock);
  170.  
  171.         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
  172.                HDMI_NULL_SEND); /* send null packets when required */
  173.  
  174.         WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
  175.  
  176.         WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
  177.                HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
  178.                HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
  179.  
  180.         WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
  181.                AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
  182.                AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
  183.  
  184.         WREG32(HDMI_ACR_PACKET_CONTROL + offset,
  185.                HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
  186.                HDMI_ACR_SOURCE); /* select SW CTS value */
  187.  
  188.         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
  189.                HDMI_NULL_SEND | /* send null packets when required */
  190.                HDMI_GC_SEND | /* send general control packets */
  191.                HDMI_GC_CONT); /* send general control packets every frame */
  192.  
  193.         WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
  194.                HDMI_AVI_INFO_SEND | /* enable AVI info frames */
  195.                HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */
  196.                HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
  197.                HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
  198.  
  199.         WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
  200.                AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
  201.  
  202.         WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
  203.                HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */
  204.                HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
  205.  
  206.         WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
  207.  
  208.         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
  209.         if (err < 0) {
  210.                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
  211.                 return;
  212.         }
  213.  
  214.         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
  215.         if (err < 0) {
  216.                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
  217.                 return;
  218.         }
  219.  
  220.         evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
  221.         evergreen_hdmi_update_ACR(encoder, mode->clock);
  222.  
  223.         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
  224.         WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
  225.         WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
  226.         WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
  227.         WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
  228. }
  229.