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  1. /*
  2.  * Copyright 2007-8 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the "Software"),
  7.  * to deal in the Software without restriction, including without limitation
  8.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9.  * and/or sell copies of the Software, and to permit persons to whom the
  10.  * Software is furnished to do so, subject to the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice shall be included in
  13.  * all copies or substantial portions of the Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21.  * OTHER DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors: Dave Airlie
  24.  *          Alex Deucher
  25.  *          Jerome Glisse
  26.  */
  27. #include <drm/drmP.h>
  28. #include <drm/radeon_drm.h>
  29. #include "radeon.h"
  30.  
  31. #include "atom.h"
  32. #include "atom-bits.h"
  33. #include <drm/drm_dp_helper.h>
  34.  
  35. /* move these to drm_dp_helper.c/h */
  36. #define DP_LINK_CONFIGURATION_SIZE 9
  37. #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  38.  
  39. static char *voltage_names[] = {
  40.         "0.4V", "0.6V", "0.8V", "1.2V"
  41. };
  42. static char *pre_emph_names[] = {
  43.         "0dB", "3.5dB", "6dB", "9.5dB"
  44. };
  45.  
  46. /***** radeon AUX functions *****/
  47. union aux_channel_transaction {
  48.         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  49.         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  50. };
  51.  
  52. static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  53.                                  u8 *send, int send_bytes,
  54.                                  u8 *recv, int recv_size,
  55.                                  u8 delay, u8 *ack)
  56. {
  57.         struct drm_device *dev = chan->dev;
  58.         struct radeon_device *rdev = dev->dev_private;
  59.         union aux_channel_transaction args;
  60.         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  61.         unsigned char *base;
  62.         int recv_bytes;
  63.  
  64.         memset(&args, 0, sizeof(args));
  65.  
  66.         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
  67.  
  68.         memcpy(base, send, send_bytes);
  69.  
  70.         args.v1.lpAuxRequest = 0 + 4;
  71.         args.v1.lpDataOut = 16 + 4;
  72.         args.v1.ucDataOutLen = 0;
  73.         args.v1.ucChannelID = chan->rec.i2c_id;
  74.         args.v1.ucDelay = delay / 10;
  75.         if (ASIC_IS_DCE4(rdev))
  76.                 args.v2.ucHPD_ID = chan->rec.hpd;
  77.  
  78.         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  79.  
  80.         *ack = args.v1.ucReplyStatus;
  81.  
  82.         /* timeout */
  83.         if (args.v1.ucReplyStatus == 1) {
  84.                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
  85.                 return -ETIMEDOUT;
  86.                         }
  87.  
  88.         /* flags not zero */
  89.         if (args.v1.ucReplyStatus == 2) {
  90.                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
  91.                 return -EBUSY;
  92.                         }
  93.  
  94.         /* error */
  95.         if (args.v1.ucReplyStatus == 3) {
  96.                 DRM_DEBUG_KMS("dp_aux_ch error\n");
  97.                 return -EIO;
  98.                 }
  99.  
  100.         recv_bytes = args.v1.ucDataOutLen;
  101.         if (recv_bytes > recv_size)
  102.                 recv_bytes = recv_size;
  103.  
  104.         if (recv && recv_size)
  105.                 memcpy(recv, base + 16, recv_bytes);
  106.  
  107.         return recv_bytes;
  108. }
  109.  
  110. static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
  111.                                       u16 address, u8 *send, u8 send_bytes, u8 delay)
  112. {
  113.         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
  114.         int ret;
  115.         u8 msg[20];
  116.         int msg_bytes = send_bytes + 4;
  117.         u8 ack;
  118.         unsigned retry;
  119.  
  120.         if (send_bytes > 16)
  121.                 return -1;
  122.  
  123.         msg[0] = address;
  124.         msg[1] = address >> 8;
  125.         msg[2] = AUX_NATIVE_WRITE << 4;
  126.         msg[3] = (msg_bytes << 4) | (send_bytes - 1);
  127.         memcpy(&msg[4], send, send_bytes);
  128.  
  129.         for (retry = 0; retry < 4; retry++) {
  130.                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
  131.                                             msg, msg_bytes, NULL, 0, delay, &ack);
  132.                 if (ret == -EBUSY)
  133.                         continue;
  134.                 else if (ret < 0)
  135.                         return ret;
  136.                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
  137.                         return send_bytes;
  138.                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  139.                         udelay(400);
  140.                 else
  141.                         return -EIO;
  142.                         }
  143.  
  144.         return -EIO;
  145. }
  146.  
  147. static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
  148.                                      u16 address, u8 *recv, int recv_bytes, u8 delay)
  149. {
  150.         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
  151.         u8 msg[4];
  152.         int msg_bytes = 4;
  153.         u8 ack;
  154.         int ret;
  155.         unsigned retry;
  156.  
  157.         msg[0] = address;
  158.         msg[1] = address >> 8;
  159.         msg[2] = AUX_NATIVE_READ << 4;
  160.         msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
  161.  
  162.         for (retry = 0; retry < 4; retry++) {
  163.                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
  164.                                             msg, msg_bytes, recv, recv_bytes, delay, &ack);
  165.                 if (ret == -EBUSY)
  166.                         continue;
  167.                 else if (ret < 0)
  168.                         return ret;
  169.                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
  170.                         return ret;
  171.                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  172.                         udelay(400);
  173.                 else if (ret == 0)
  174.                         return -EPROTO;
  175.                                 else
  176.                         return -EIO;
  177.                         }
  178.  
  179.         return -EIO;
  180. }
  181.  
  182. static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
  183.                                  u16 reg, u8 val)
  184. {
  185.         radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
  186. }
  187.  
  188. static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
  189.                                u16 reg)
  190. {
  191.         u8 val = 0;
  192.  
  193.         radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
  194.  
  195.         return val;
  196. }
  197.  
  198. int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
  199.                          u8 write_byte, u8 *read_byte)
  200. {
  201.         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  202.         struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
  203.         u16 address = algo_data->address;
  204.         u8 msg[5];
  205.         u8 reply[2];
  206.         unsigned retry;
  207.         int msg_bytes;
  208.         int reply_bytes = 1;
  209.         int ret;
  210.         u8 ack;
  211.  
  212.         /* Set up the command byte */
  213.         if (mode & MODE_I2C_READ)
  214.                 msg[2] = AUX_I2C_READ << 4;
  215.         else
  216.                 msg[2] = AUX_I2C_WRITE << 4;
  217.  
  218.         if (!(mode & MODE_I2C_STOP))
  219.                 msg[2] |= AUX_I2C_MOT << 4;
  220.  
  221.         msg[0] = address;
  222.         msg[1] = address >> 8;
  223.  
  224.         switch (mode) {
  225.         case MODE_I2C_WRITE:
  226.                 msg_bytes = 5;
  227.                 msg[3] = msg_bytes << 4;
  228.                 msg[4] = write_byte;
  229.                                 break;
  230.         case MODE_I2C_READ:
  231.                 msg_bytes = 4;
  232.                 msg[3] = msg_bytes << 4;
  233.                                 break;
  234.                         default:
  235.                 msg_bytes = 4;
  236.                 msg[3] = 3 << 4;
  237.                                 break;
  238.                         }
  239.  
  240.         for (retry = 0; retry < 4; retry++) {
  241.                 ret = radeon_process_aux_ch(auxch,
  242.                                             msg, msg_bytes, reply, reply_bytes, 0, &ack);
  243.                 if (ret == -EBUSY)
  244.                         continue;
  245.                 else if (ret < 0) {
  246.                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
  247.                         return ret;
  248.                 }
  249.  
  250.                 switch (ack & AUX_NATIVE_REPLY_MASK) {
  251.                 case AUX_NATIVE_REPLY_ACK:
  252.                         /* I2C-over-AUX Reply field is only valid
  253.                          * when paired with AUX ACK.
  254.                          */
  255.                 break;
  256.                 case AUX_NATIVE_REPLY_NACK:
  257.                         DRM_DEBUG_KMS("aux_ch native nack\n");
  258.                         return -EREMOTEIO;
  259.                 case AUX_NATIVE_REPLY_DEFER:
  260.                         DRM_DEBUG_KMS("aux_ch native defer\n");
  261.                         udelay(400);
  262.                         continue;
  263.                 default:
  264.                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
  265.                         return -EREMOTEIO;
  266.                 }
  267.  
  268.                 switch (ack & AUX_I2C_REPLY_MASK) {
  269.                 case AUX_I2C_REPLY_ACK:
  270.                         if (mode == MODE_I2C_READ)
  271.                                 *read_byte = reply[0];
  272.                         return ret;
  273.                 case AUX_I2C_REPLY_NACK:
  274.                         DRM_DEBUG_KMS("aux_i2c nack\n");
  275.                         return -EREMOTEIO;
  276.                 case AUX_I2C_REPLY_DEFER:
  277.                         DRM_DEBUG_KMS("aux_i2c defer\n");
  278.                         udelay(400);
  279.                                 break;
  280.                         default:
  281.                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
  282.                         return -EREMOTEIO;
  283.                 }
  284.         }
  285.  
  286.         DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
  287.         return -EREMOTEIO;
  288. }
  289.  
  290. /***** general DP utility functions *****/
  291.  
  292. #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
  293. #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
  294.  
  295. static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
  296.                                 int lane_count,
  297.                                 u8 train_set[4])
  298. {
  299.         u8 v = 0;
  300.         u8 p = 0;
  301.         int lane;
  302.  
  303.         for (lane = 0; lane < lane_count; lane++) {
  304.                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
  305.                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
  306.  
  307.                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
  308.                           lane,
  309.                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
  310.                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
  311.  
  312.                 if (this_v > v)
  313.                         v = this_v;
  314.                 if (this_p > p)
  315.                         p = this_p;
  316.         }
  317.  
  318.         if (v >= DP_VOLTAGE_MAX)
  319.                 v |= DP_TRAIN_MAX_SWING_REACHED;
  320.  
  321.         if (p >= DP_PRE_EMPHASIS_MAX)
  322.                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  323.  
  324.         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
  325.                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
  326.                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
  327.  
  328.         for (lane = 0; lane < 4; lane++)
  329.                 train_set[lane] = v | p;
  330. }
  331.  
  332. /* convert bits per color to bits per pixel */
  333. /* get bpc from the EDID */
  334. static int convert_bpc_to_bpp(int bpc)
  335. {
  336.         if (bpc == 0)
  337.                 return 24;
  338.         else
  339.                 return bpc * 3;
  340. }
  341.  
  342. /* get the max pix clock supported by the link rate and lane num */
  343. static int dp_get_max_dp_pix_clock(int link_rate,
  344.                                    int lane_num,
  345.                                    int bpp)
  346. {
  347.         return (link_rate * lane_num * 8) / bpp;
  348. }
  349.  
  350. /***** radeon specific DP functions *****/
  351.  
  352. /* First get the min lane# when low rate is used according to pixel clock
  353.  * (prefer low rate), second check max lane# supported by DP panel,
  354.  * if the max lane# < low rate lane# then use max lane# instead.
  355.  */
  356. static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
  357.                                         u8 dpcd[DP_DPCD_SIZE],
  358.                                         int pix_clock)
  359. {
  360.         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
  361.         int max_link_rate = drm_dp_max_link_rate(dpcd);
  362.         int max_lane_num = drm_dp_max_lane_count(dpcd);
  363.         int lane_num;
  364.         int max_dp_pix_clock;
  365.  
  366.         for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
  367.                 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
  368.                 if (pix_clock <= max_dp_pix_clock)
  369.                         break;
  370.         }
  371.  
  372.         return lane_num;
  373. }
  374.  
  375. static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
  376.                                        u8 dpcd[DP_DPCD_SIZE],
  377.                                        int pix_clock)
  378. {
  379.         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
  380.         int lane_num, max_pix_clock;
  381.  
  382.         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
  383.             ENCODER_OBJECT_ID_NUTMEG)
  384.                 return 270000;
  385.  
  386.         lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
  387.         max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
  388.         if (pix_clock <= max_pix_clock)
  389.                 return 162000;
  390.         max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
  391.         if (pix_clock <= max_pix_clock)
  392.                 return 270000;
  393.         if (radeon_connector_is_dp12_capable(connector)) {
  394.                 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
  395.                 if (pix_clock <= max_pix_clock)
  396.                         return 540000;
  397.         }
  398.  
  399.         return drm_dp_max_link_rate(dpcd);
  400. }
  401.  
  402. static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
  403.                                     int action, int dp_clock,
  404.                                     u8 ucconfig, u8 lane_num)
  405. {
  406.         DP_ENCODER_SERVICE_PARAMETERS args;
  407.         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
  408.  
  409.         memset(&args, 0, sizeof(args));
  410.         args.ucLinkClock = dp_clock / 10;
  411.         args.ucConfig = ucconfig;
  412.         args.ucAction = action;
  413.         args.ucLaneNum = lane_num;
  414.         args.ucStatus = 0;
  415.  
  416.         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  417.         return args.ucStatus;
  418. }
  419.  
  420. u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
  421. {
  422.         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
  423.         struct drm_device *dev = radeon_connector->base.dev;
  424.         struct radeon_device *rdev = dev->dev_private;
  425.  
  426.         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
  427.                                          dig_connector->dp_i2c_bus->rec.i2c_id, 0);
  428. }
  429.  
  430. static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
  431. {
  432.         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
  433.         u8 buf[3];
  434.  
  435.         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
  436.                 return;
  437.  
  438.         if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
  439.                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
  440.                               buf[0], buf[1], buf[2]);
  441.  
  442.         if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
  443.                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
  444.                               buf[0], buf[1], buf[2]);
  445. }
  446.  
  447. bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
  448. {
  449.         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
  450.         u8 msg[DP_DPCD_SIZE];
  451.         int ret, i;
  452.  
  453.     ENTER();
  454.  
  455.         ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
  456.                                         DP_DPCD_SIZE, 0);
  457.         if (ret > 0) {
  458.                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
  459.                         DRM_DEBUG_KMS("DPCD: ");
  460.                 for (i = 0; i < DP_DPCD_SIZE; i++)
  461.                                 DRM_DEBUG_KMS("%02x ", msg[i]);
  462.                         DRM_DEBUG_KMS("\n");
  463.  
  464.                 radeon_dp_probe_oui(radeon_connector);
  465.         LEAVE();
  466.                 return true;
  467.         }
  468.     FAIL();
  469.         dig_connector->dpcd[0] = 0;
  470.         return false;
  471. }
  472.  
  473. int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
  474.                                      struct drm_connector *connector)
  475. {
  476.         struct drm_device *dev = encoder->dev;
  477.         struct radeon_device *rdev = dev->dev_private;
  478.         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  479.         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
  480.         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
  481.         u8 tmp;
  482.  
  483.         if (!ASIC_IS_DCE4(rdev))
  484.                 return panel_mode;
  485.  
  486.         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
  487.                 /* DP bridge chips */
  488.                 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
  489.                 if (tmp & 1)
  490.                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
  491.                 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
  492.                          (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
  493.                 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
  494.                 else
  495.                         panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
  496.         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
  497.                 /* eDP */
  498.                 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
  499.                 if (tmp & 1)
  500.                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
  501.         }
  502.  
  503.         return panel_mode;
  504. }
  505.  
  506. void radeon_dp_set_link_config(struct drm_connector *connector,
  507.                                const struct drm_display_mode *mode)
  508. {
  509.         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  510.         struct radeon_connector_atom_dig *dig_connector;
  511.  
  512.         if (!radeon_connector->con_priv)
  513.                 return;
  514.         dig_connector = radeon_connector->con_priv;
  515.  
  516.         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
  517.             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
  518.         dig_connector->dp_clock =
  519.                         radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
  520.         dig_connector->dp_lane_count =
  521.                         radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
  522.         }
  523. }
  524.  
  525. int radeon_dp_mode_valid_helper(struct drm_connector *connector,
  526.                                 struct drm_display_mode *mode)
  527. {
  528.         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  529.         struct radeon_connector_atom_dig *dig_connector;
  530.         int dp_clock;
  531.  
  532.         if (!radeon_connector->con_priv)
  533.                 return MODE_CLOCK_HIGH;
  534.         dig_connector = radeon_connector->con_priv;
  535.  
  536.         dp_clock =
  537.                 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
  538.  
  539.         if ((dp_clock == 540000) &&
  540.             (!radeon_connector_is_dp12_capable(connector)))
  541.                 return MODE_CLOCK_HIGH;
  542.  
  543.         return MODE_OK;
  544. }
  545.  
  546. static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
  547.                                     u8 link_status[DP_LINK_STATUS_SIZE])
  548. {
  549.         int ret;
  550.         ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
  551.                                         link_status, DP_LINK_STATUS_SIZE, 100);
  552.         if (ret <= 0) {
  553.                 return false;
  554.         }
  555.  
  556.         DRM_DEBUG_KMS("link status %*ph\n", 6, link_status);
  557.         return true;
  558. }
  559.  
  560. bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
  561. {
  562.         u8 link_status[DP_LINK_STATUS_SIZE];
  563.         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
  564.  
  565.         if (!radeon_dp_get_link_status(radeon_connector, link_status))
  566.                 return false;
  567.         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
  568.                 return false;
  569.         return true;
  570. }
  571.  
  572. struct radeon_dp_link_train_info {
  573.         struct radeon_device *rdev;
  574.         struct drm_encoder *encoder;
  575.         struct drm_connector *connector;
  576.         struct radeon_connector *radeon_connector;
  577.         int enc_id;
  578.         int dp_clock;
  579.         int dp_lane_count;
  580.         bool tp3_supported;
  581.         u8 dpcd[DP_RECEIVER_CAP_SIZE];
  582.         u8 train_set[4];
  583.         u8 link_status[DP_LINK_STATUS_SIZE];
  584.         u8 tries;
  585.         bool use_dpencoder;
  586. };
  587.  
  588. static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
  589. {
  590.         /* set the initial vs/emph on the source */
  591.         atombios_dig_transmitter_setup(dp_info->encoder,
  592.                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
  593.                                        0, dp_info->train_set[0]); /* sets all lanes at once */
  594.  
  595.         /* set the vs/emph on the sink */
  596.         radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
  597.                                    dp_info->train_set, dp_info->dp_lane_count, 0);
  598. }
  599.  
  600. static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
  601. {
  602.         int rtp = 0;
  603.  
  604.         /* set training pattern on the source */
  605.         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
  606.                 switch (tp) {
  607.                 case DP_TRAINING_PATTERN_1:
  608.                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
  609.                         break;
  610.                 case DP_TRAINING_PATTERN_2:
  611.                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
  612.                         break;
  613.                 case DP_TRAINING_PATTERN_3:
  614.                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
  615.                         break;
  616.                 }
  617.                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
  618.         } else {
  619.                 switch (tp) {
  620.                 case DP_TRAINING_PATTERN_1:
  621.                         rtp = 0;
  622.                         break;
  623.                 case DP_TRAINING_PATTERN_2:
  624.                         rtp = 1;
  625.                         break;
  626.                 }
  627.                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
  628.                                           dp_info->dp_clock, dp_info->enc_id, rtp);
  629.         }
  630.  
  631.         /* enable training pattern on the sink */
  632.         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
  633. }
  634.  
  635. static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
  636. {
  637.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
  638.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  639.         u8 tmp;
  640.  
  641.         /* power up the sink */
  642.         if (dp_info->dpcd[0] >= 0x11)
  643.                 radeon_write_dpcd_reg(dp_info->radeon_connector,
  644.                                       DP_SET_POWER, DP_SET_POWER_D0);
  645.  
  646.         /* possibly enable downspread on the sink */
  647.         if (dp_info->dpcd[3] & 0x1)
  648.                 radeon_write_dpcd_reg(dp_info->radeon_connector,
  649.                                       DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
  650.         else
  651.                 radeon_write_dpcd_reg(dp_info->radeon_connector,
  652.                                       DP_DOWNSPREAD_CTRL, 0);
  653.  
  654.         if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
  655.             (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
  656.                 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
  657.         }
  658.  
  659.         /* set the lane count on the sink */
  660.         tmp = dp_info->dp_lane_count;
  661.         if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
  662.             dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
  663.                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  664.         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
  665.  
  666.         /* set the link rate on the sink */
  667.         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
  668.         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
  669.  
  670.         /* start training on the source */
  671.         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
  672.                 atombios_dig_encoder_setup(dp_info->encoder,
  673.                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
  674.         else
  675.                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
  676.                                           dp_info->dp_clock, dp_info->enc_id, 0);
  677.  
  678.         /* disable the training pattern on the sink */
  679.         radeon_write_dpcd_reg(dp_info->radeon_connector,
  680.                               DP_TRAINING_PATTERN_SET,
  681.                               DP_TRAINING_PATTERN_DISABLE);
  682.  
  683.         return 0;
  684. }
  685.  
  686. static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
  687. {
  688.         udelay(400);
  689.  
  690.         /* disable the training pattern on the sink */
  691.         radeon_write_dpcd_reg(dp_info->radeon_connector,
  692.                               DP_TRAINING_PATTERN_SET,
  693.                               DP_TRAINING_PATTERN_DISABLE);
  694.  
  695.         /* disable the training pattern on the source */
  696.         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
  697.                 atombios_dig_encoder_setup(dp_info->encoder,
  698.                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
  699.         else
  700.                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
  701.                                           dp_info->dp_clock, dp_info->enc_id, 0);
  702.  
  703.         return 0;
  704. }
  705.  
  706. static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
  707. {
  708.         bool clock_recovery;
  709.         u8 voltage;
  710.         int i;
  711.  
  712.         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
  713.         memset(dp_info->train_set, 0, 4);
  714.         radeon_dp_update_vs_emph(dp_info);
  715.  
  716.         udelay(400);
  717.  
  718.         /* clock recovery loop */
  719.         clock_recovery = false;
  720.         dp_info->tries = 0;
  721.         voltage = 0xff;
  722.         while (1) {
  723.                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
  724.  
  725.                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
  726.                         DRM_ERROR("displayport link status failed\n");
  727.                         break;
  728.                 }
  729.  
  730.                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
  731.                         clock_recovery = true;
  732.                         break;
  733.                 }
  734.  
  735.                 for (i = 0; i < dp_info->dp_lane_count; i++) {
  736.                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
  737.                                 break;
  738.                 }
  739.                 if (i == dp_info->dp_lane_count) {
  740.                         DRM_ERROR("clock recovery reached max voltage\n");
  741.                         break;
  742.                 }
  743.  
  744.                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
  745.                         ++dp_info->tries;
  746.                         if (dp_info->tries == 5) {
  747.                                 DRM_ERROR("clock recovery tried 5 times\n");
  748.                                 break;
  749.                         }
  750.                 } else
  751.                         dp_info->tries = 0;
  752.  
  753.                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  754.  
  755.                 /* Compute new train_set as requested by sink */
  756.                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
  757.  
  758.                 radeon_dp_update_vs_emph(dp_info);
  759.         }
  760.         if (!clock_recovery) {
  761.                 DRM_ERROR("clock recovery failed\n");
  762.                 return -1;
  763.         } else {
  764.                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
  765.                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
  766.                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
  767.                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
  768.                 return 0;
  769.         }
  770. }
  771.  
  772. static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
  773. {
  774.         bool channel_eq;
  775.  
  776.         if (dp_info->tp3_supported)
  777.                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
  778.         else
  779.                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
  780.  
  781.         /* channel equalization loop */
  782.         dp_info->tries = 0;
  783.         channel_eq = false;
  784.         while (1) {
  785.                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
  786.  
  787.                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
  788.                         DRM_ERROR("displayport link status failed\n");
  789.                         break;
  790.                 }
  791.  
  792.                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
  793.                         channel_eq = true;
  794.                         break;
  795.                 }
  796.  
  797.                 /* Try 5 times */
  798.                 if (dp_info->tries > 5) {
  799.                         DRM_ERROR("channel eq failed: 5 tries\n");
  800.                         break;
  801.                 }
  802.  
  803.                 /* Compute new train_set as requested by sink */
  804.                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
  805.  
  806.                 radeon_dp_update_vs_emph(dp_info);
  807.                 dp_info->tries++;
  808.         }
  809.  
  810.         if (!channel_eq) {
  811.                 DRM_ERROR("channel eq failed\n");
  812.                 return -1;
  813.         } else {
  814.                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
  815.                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
  816.                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
  817.                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
  818.                 return 0;
  819.         }
  820. }
  821.  
  822. void radeon_dp_link_train(struct drm_encoder *encoder,
  823.                           struct drm_connector *connector)
  824. {
  825.         struct drm_device *dev = encoder->dev;
  826.         struct radeon_device *rdev = dev->dev_private;
  827.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  828.         struct radeon_encoder_atom_dig *dig;
  829.         struct radeon_connector *radeon_connector;
  830.         struct radeon_connector_atom_dig *dig_connector;
  831.         struct radeon_dp_link_train_info dp_info;
  832.         int index;
  833.         u8 tmp, frev, crev;
  834.  
  835.         if (!radeon_encoder->enc_priv)
  836.                 return;
  837.         dig = radeon_encoder->enc_priv;
  838.  
  839.         radeon_connector = to_radeon_connector(connector);
  840.         if (!radeon_connector->con_priv)
  841.                 return;
  842.         dig_connector = radeon_connector->con_priv;
  843.  
  844.         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
  845.             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
  846.                 return;
  847.  
  848.         /* DPEncoderService newer than 1.1 can't program properly the
  849.          * training pattern. When facing such version use the
  850.          * DIGXEncoderControl (X== 1 | 2)
  851.          */
  852.         dp_info.use_dpencoder = true;
  853.         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
  854.         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
  855.                 if (crev > 1) {
  856.                         dp_info.use_dpencoder = false;
  857.                 }
  858.         }
  859.  
  860.         dp_info.enc_id = 0;
  861.         if (dig->dig_encoder)
  862.                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
  863.         else
  864.                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
  865.         if (dig->linkb)
  866.                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
  867.         else
  868.                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
  869.  
  870.         tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
  871.         if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
  872.                 dp_info.tp3_supported = true;
  873.         else
  874.                 dp_info.tp3_supported = false;
  875.  
  876.         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
  877.         dp_info.rdev = rdev;
  878.         dp_info.encoder = encoder;
  879.         dp_info.connector = connector;
  880.         dp_info.radeon_connector = radeon_connector;
  881.         dp_info.dp_lane_count = dig_connector->dp_lane_count;
  882.         dp_info.dp_clock = dig_connector->dp_clock;
  883.  
  884.         if (radeon_dp_link_train_init(&dp_info))
  885.                 goto done;
  886.         if (radeon_dp_link_train_cr(&dp_info))
  887.                 goto done;
  888.         if (radeon_dp_link_train_ce(&dp_info))
  889.                 goto done;
  890. done:
  891.         if (radeon_dp_link_train_finish(&dp_info))
  892.                 return;
  893. }
  894.