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  1. /*
  2.  * Copyright © 2011 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20.  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21.  * SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25.  *
  26.  * New plane/sprite handling.
  27.  *
  28.  * The older chips had a separate interface for programming plane related
  29.  * registers; newer ones are much simpler and we can use the new DRM plane
  30.  * support.
  31.  */
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_fourcc.h>
  35. #include <drm/drm_rect.h>
  36. #include <drm/drm_atomic.h>
  37. #include <drm/drm_plane_helper.h>
  38. #include "intel_drv.h"
  39. #include <drm/i915_drm.h>
  40. #include "i915_drv.h"
  41.  
  42. static bool
  43. format_is_yuv(uint32_t format)
  44. {
  45.         switch (format) {
  46.         case DRM_FORMAT_YUYV:
  47.         case DRM_FORMAT_UYVY:
  48.         case DRM_FORMAT_VYUY:
  49.         case DRM_FORMAT_YVYU:
  50.                 return true;
  51.         default:
  52.                 return false;
  53.         }
  54. }
  55.  
  56. static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  57.                               int usecs)
  58. {
  59.         /* paranoia */
  60.         if (!adjusted_mode->crtc_htotal)
  61.                 return 1;
  62.  
  63.         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  64.                             1000 * adjusted_mode->crtc_htotal);
  65. }
  66.  
  67. /**
  68.  * intel_pipe_update_start() - start update of a set of display registers
  69.  * @crtc: the crtc of which the registers are going to be updated
  70.  * @start_vbl_count: vblank counter return pointer used for error checking
  71.  *
  72.  * Mark the start of an update to pipe registers that should be updated
  73.  * atomically regarding vblank. If the next vblank will happens within
  74.  * the next 100 us, this function waits until the vblank passes.
  75.  *
  76.  * After a successful call to this function, interrupts will be disabled
  77.  * until a subsequent call to intel_pipe_update_end(). That is done to
  78.  * avoid random delays. The value written to @start_vbl_count should be
  79.  * supplied to intel_pipe_update_end() for error checking.
  80.  */
  81. void intel_pipe_update_start(struct intel_crtc *crtc)
  82. {
  83.         struct drm_device *dev = crtc->base.dev;
  84.         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  85.         enum pipe pipe = crtc->pipe;
  86.         long timeout = msecs_to_jiffies_timeout(1);
  87.         int scanline, min, max, vblank_start;
  88.         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  89.         DEFINE_WAIT(wait);
  90.  
  91.         vblank_start = adjusted_mode->crtc_vblank_start;
  92.         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  93.                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  94.  
  95.         /* FIXME needs to be calibrated sensibly */
  96.         min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
  97.         max = vblank_start - 1;
  98.  
  99.         local_irq_disable();
  100.  
  101.         if (min <= 0 || max <= 0)
  102.                 return;
  103.  
  104.         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
  105.                 return;
  106.  
  107.         crtc->debug.min_vbl = min;
  108.         crtc->debug.max_vbl = max;
  109.         trace_i915_pipe_update_start(crtc);
  110.  
  111.         for (;;) {
  112.                 /*
  113.                  * prepare_to_wait() has a memory barrier, which guarantees
  114.                  * other CPUs can see the task state update by the time we
  115.                  * read the scanline.
  116.                  */
  117.                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
  118.  
  119.                 scanline = intel_get_crtc_scanline(crtc);
  120.                 if (scanline < min || scanline > max)
  121.                         break;
  122.  
  123.                 if (timeout <= 0) {
  124.                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
  125.                                   pipe_name(crtc->pipe));
  126.                         break;
  127.                 }
  128.  
  129.                 local_irq_enable();
  130.                
  131.                 {
  132.                         unsigned long expire;
  133.                         expire = timeout + jiffies;
  134.                         WaitEventTimeout(wait.evnt, timeout);;
  135.                         timeout = expire - jiffies;
  136.                         timeout = timeout < 0 ? 0 : timeout;
  137.                 }
  138.                 local_irq_disable();
  139.         }
  140.  
  141.         finish_wait(wq, &wait);
  142.  
  143.         drm_crtc_vblank_put(&crtc->base);
  144.  
  145.         crtc->debug.scanline_start = scanline;
  146.         crtc->debug.start_vbl_time = ktime_get();
  147.         crtc->debug.start_vbl_count =
  148.                 dev->driver->get_vblank_counter(dev, pipe);
  149.  
  150.         trace_i915_pipe_update_vblank_evaded(crtc);
  151. }
  152.  
  153. /**
  154.  * intel_pipe_update_end() - end update of a set of display registers
  155.  * @crtc: the crtc of which the registers were updated
  156.  * @start_vbl_count: start vblank counter (used for error checking)
  157.  *
  158.  * Mark the end of an update started with intel_pipe_update_start(). This
  159.  * re-enables interrupts and verifies the update was actually completed
  160.  * before a vblank using the value of @start_vbl_count.
  161.  */
  162. void intel_pipe_update_end(struct intel_crtc *crtc)
  163. {
  164.         struct drm_device *dev = crtc->base.dev;
  165.         enum pipe pipe = crtc->pipe;
  166.         int scanline_end = intel_get_crtc_scanline(crtc);
  167.         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
  168.         ktime_t end_vbl_time = ktime_get();
  169.  
  170.         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
  171.  
  172.         local_irq_enable();
  173.  
  174.         if (crtc->debug.start_vbl_count &&
  175.             crtc->debug.start_vbl_count != end_vbl_count) {
  176.                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
  177.                           pipe_name(pipe), crtc->debug.start_vbl_count,
  178.                           end_vbl_count,
  179.                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
  180.                           crtc->debug.min_vbl, crtc->debug.max_vbl,
  181.                           crtc->debug.scanline_start, scanline_end);
  182.         }
  183. }
  184.  
  185. static void
  186. skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
  187.                  struct drm_framebuffer *fb,
  188.                  int crtc_x, int crtc_y,
  189.                  unsigned int crtc_w, unsigned int crtc_h,
  190.                  uint32_t x, uint32_t y,
  191.                  uint32_t src_w, uint32_t src_h)
  192. {
  193.         struct drm_device *dev = drm_plane->dev;
  194.         struct drm_i915_private *dev_priv = dev->dev_private;
  195.         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
  196.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  197.         const int pipe = intel_plane->pipe;
  198.         const int plane = intel_plane->plane + 1;
  199.         u32 plane_ctl, stride_div, stride;
  200.         const struct drm_intel_sprite_colorkey *key =
  201.                 &to_intel_plane_state(drm_plane->state)->ckey;
  202.         u32 surf_addr;
  203.         u32 tile_height, plane_offset, plane_size;
  204.         unsigned int rotation;
  205.         int x_offset, y_offset;
  206.         struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
  207.         int scaler_id;
  208.  
  209.         plane_ctl = PLANE_CTL_ENABLE |
  210.                 PLANE_CTL_PIPE_GAMMA_ENABLE |
  211.                 PLANE_CTL_PIPE_CSC_ENABLE;
  212.  
  213.         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
  214.         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
  215.  
  216.         rotation = drm_plane->state->rotation;
  217.         plane_ctl |= skl_plane_ctl_rotation(rotation);
  218.  
  219.         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
  220.                                                fb->pixel_format);
  221.  
  222.         scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;
  223.  
  224.         /* Sizes are 0 based */
  225.         src_w--;
  226.         src_h--;
  227.         crtc_w--;
  228.         crtc_h--;
  229.  
  230.         if (key->flags) {
  231.                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
  232.                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
  233.                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
  234.         }
  235.  
  236.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  237.                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
  238.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  239.                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
  240.  
  241.         surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
  242.  
  243.         if (intel_rotation_90_or_270(rotation)) {
  244.                 /* stride: Surface height in tiles */
  245.                 tile_height = intel_tile_height(dev, fb->pixel_format,
  246.                                                 fb->modifier[0], 0);
  247.                 stride = DIV_ROUND_UP(fb->height, tile_height);
  248.                 plane_size = (src_w << 16) | src_h;
  249.                 x_offset = stride * tile_height - y - (src_h + 1);
  250.                 y_offset = x;
  251.         } else {
  252.                 stride = fb->pitches[0] / stride_div;
  253.                 plane_size = (src_h << 16) | src_w;
  254.                 x_offset = x;
  255.                 y_offset = y;
  256.         }
  257.         plane_offset = y_offset << 16 | x_offset;
  258.  
  259.         I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
  260.         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
  261.         I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
  262.  
  263.         /* program plane scaler */
  264.         if (scaler_id >= 0) {
  265.                 uint32_t ps_ctrl = 0;
  266.  
  267.                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
  268.                         PS_PLANE_SEL(plane));
  269.                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
  270.                         crtc_state->scaler_state.scalers[scaler_id].mode;
  271.                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
  272.                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
  273.                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
  274.                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
  275.                         ((crtc_w + 1) << 16)|(crtc_h + 1));
  276.  
  277.                 I915_WRITE(PLANE_POS(pipe, plane), 0);
  278.         } else {
  279.                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
  280.         }
  281.  
  282.         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
  283.         I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
  284.         POSTING_READ(PLANE_SURF(pipe, plane));
  285. }
  286.  
  287. static void
  288. skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
  289. {
  290.         struct drm_device *dev = dplane->dev;
  291.         struct drm_i915_private *dev_priv = dev->dev_private;
  292.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  293.         const int pipe = intel_plane->pipe;
  294.         const int plane = intel_plane->plane + 1;
  295.  
  296.         I915_WRITE(PLANE_CTL(pipe, plane), 0);
  297.  
  298.         I915_WRITE(PLANE_SURF(pipe, plane), 0);
  299.         POSTING_READ(PLANE_SURF(pipe, plane));
  300. }
  301.  
  302. static void
  303. chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
  304. {
  305.         struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
  306.         int plane = intel_plane->plane;
  307.  
  308.         /* Seems RGB data bypasses the CSC always */
  309.         if (!format_is_yuv(format))
  310.                 return;
  311.  
  312.         /*
  313.          * BT.601 limited range YCbCr -> full range RGB
  314.          *
  315.          * |r|   | 6537 4769     0|   |cr  |
  316.          * |g| = |-3330 4769 -1605| x |y-64|
  317.          * |b|   |    0 4769  8263|   |cb  |
  318.          *
  319.          * Cb and Cr apparently come in as signed already, so no
  320.          * need for any offset. For Y we need to remove the offset.
  321.          */
  322.         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
  323.         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
  324.         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
  325.  
  326.         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
  327.         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
  328.         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
  329.         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
  330.         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
  331.  
  332.         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
  333.         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
  334.         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
  335.  
  336.         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  337.         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  338.         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  339. }
  340.  
  341. static void
  342. vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
  343.                  struct drm_framebuffer *fb,
  344.                  int crtc_x, int crtc_y,
  345.                  unsigned int crtc_w, unsigned int crtc_h,
  346.                  uint32_t x, uint32_t y,
  347.                  uint32_t src_w, uint32_t src_h)
  348. {
  349.         struct drm_device *dev = dplane->dev;
  350.         struct drm_i915_private *dev_priv = dev->dev_private;
  351.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  352.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  353.         int pipe = intel_plane->pipe;
  354.         int plane = intel_plane->plane;
  355.         u32 sprctl;
  356.         unsigned long sprsurf_offset, linear_offset;
  357.         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  358.         const struct drm_intel_sprite_colorkey *key =
  359.                 &to_intel_plane_state(dplane->state)->ckey;
  360.  
  361.         sprctl = SP_ENABLE;
  362.  
  363.         switch (fb->pixel_format) {
  364.         case DRM_FORMAT_YUYV:
  365.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
  366.                 break;
  367.         case DRM_FORMAT_YVYU:
  368.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
  369.                 break;
  370.         case DRM_FORMAT_UYVY:
  371.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
  372.                 break;
  373.         case DRM_FORMAT_VYUY:
  374.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
  375.                 break;
  376.         case DRM_FORMAT_RGB565:
  377.                 sprctl |= SP_FORMAT_BGR565;
  378.                 break;
  379.         case DRM_FORMAT_XRGB8888:
  380.                 sprctl |= SP_FORMAT_BGRX8888;
  381.                 break;
  382.         case DRM_FORMAT_ARGB8888:
  383.                 sprctl |= SP_FORMAT_BGRA8888;
  384.                 break;
  385.         case DRM_FORMAT_XBGR2101010:
  386.                 sprctl |= SP_FORMAT_RGBX1010102;
  387.                 break;
  388.         case DRM_FORMAT_ABGR2101010:
  389.                 sprctl |= SP_FORMAT_RGBA1010102;
  390.                 break;
  391.         case DRM_FORMAT_XBGR8888:
  392.                 sprctl |= SP_FORMAT_RGBX8888;
  393.                 break;
  394.         case DRM_FORMAT_ABGR8888:
  395.                 sprctl |= SP_FORMAT_RGBA8888;
  396.                 break;
  397.         default:
  398.                 /*
  399.                  * If we get here one of the upper layers failed to filter
  400.                  * out the unsupported plane formats
  401.                  */
  402.                 BUG();
  403.                 break;
  404.         }
  405.  
  406.         /*
  407.          * Enable gamma to match primary/cursor plane behaviour.
  408.          * FIXME should be user controllable via propertiesa.
  409.          */
  410.         sprctl |= SP_GAMMA_ENABLE;
  411.  
  412.         if (obj->tiling_mode != I915_TILING_NONE)
  413.                 sprctl |= SP_TILED;
  414.  
  415.         /* Sizes are 0 based */
  416.         src_w--;
  417.         src_h--;
  418.         crtc_w--;
  419.         crtc_h--;
  420.  
  421.         linear_offset = y * fb->pitches[0] + x * pixel_size;
  422.         sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
  423.                                                         &x, &y,
  424.                                                         obj->tiling_mode,
  425.                                                         pixel_size,
  426.                                                         fb->pitches[0]);
  427.         linear_offset -= sprsurf_offset;
  428.  
  429.         if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
  430.                 sprctl |= SP_ROTATE_180;
  431.  
  432.                 x += src_w;
  433.                 y += src_h;
  434.                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
  435.         }
  436.  
  437.         if (key->flags) {
  438.                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
  439.                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
  440.                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
  441.         }
  442.  
  443.         if (key->flags & I915_SET_COLORKEY_SOURCE)
  444.                 sprctl |= SP_SOURCE_KEY;
  445.  
  446.         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
  447.                 chv_update_csc(intel_plane, fb->pixel_format);
  448.  
  449.         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
  450.         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
  451.  
  452.         if (obj->tiling_mode != I915_TILING_NONE)
  453.                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
  454.         else
  455.                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
  456.  
  457.         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
  458.  
  459.         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
  460.         I915_WRITE(SPCNTR(pipe, plane), sprctl);
  461.         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
  462.                    sprsurf_offset);
  463.         POSTING_READ(SPSURF(pipe, plane));
  464. }
  465.  
  466. static void
  467. vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
  468. {
  469.         struct drm_device *dev = dplane->dev;
  470.         struct drm_i915_private *dev_priv = dev->dev_private;
  471.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  472.         int pipe = intel_plane->pipe;
  473.         int plane = intel_plane->plane;
  474.  
  475.         I915_WRITE(SPCNTR(pipe, plane), 0);
  476.  
  477.         I915_WRITE(SPSURF(pipe, plane), 0);
  478.         POSTING_READ(SPSURF(pipe, plane));
  479. }
  480.  
  481. static void
  482. ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
  483.                  struct drm_framebuffer *fb,
  484.                  int crtc_x, int crtc_y,
  485.                  unsigned int crtc_w, unsigned int crtc_h,
  486.                  uint32_t x, uint32_t y,
  487.                  uint32_t src_w, uint32_t src_h)
  488. {
  489.         struct drm_device *dev = plane->dev;
  490.         struct drm_i915_private *dev_priv = dev->dev_private;
  491.         struct intel_plane *intel_plane = to_intel_plane(plane);
  492.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  493.         enum pipe pipe = intel_plane->pipe;
  494.         u32 sprctl, sprscale = 0;
  495.         unsigned long sprsurf_offset, linear_offset;
  496.         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  497.         const struct drm_intel_sprite_colorkey *key =
  498.                 &to_intel_plane_state(plane->state)->ckey;
  499.  
  500.         sprctl = SPRITE_ENABLE;
  501.  
  502.         switch (fb->pixel_format) {
  503.         case DRM_FORMAT_XBGR8888:
  504.                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
  505.                 break;
  506.         case DRM_FORMAT_XRGB8888:
  507.                 sprctl |= SPRITE_FORMAT_RGBX888;
  508.                 break;
  509.         case DRM_FORMAT_YUYV:
  510.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
  511.                 break;
  512.         case DRM_FORMAT_YVYU:
  513.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
  514.                 break;
  515.         case DRM_FORMAT_UYVY:
  516.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
  517.                 break;
  518.         case DRM_FORMAT_VYUY:
  519.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
  520.                 break;
  521.         default:
  522.                 BUG();
  523.         }
  524.  
  525.         /*
  526.          * Enable gamma to match primary/cursor plane behaviour.
  527.          * FIXME should be user controllable via propertiesa.
  528.          */
  529.         sprctl |= SPRITE_GAMMA_ENABLE;
  530.  
  531.         if (obj->tiling_mode != I915_TILING_NONE)
  532.                 sprctl |= SPRITE_TILED;
  533.  
  534.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  535.                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
  536.         else
  537.                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
  538.  
  539.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  540.                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
  541.  
  542.         /* Sizes are 0 based */
  543.         src_w--;
  544.         src_h--;
  545.         crtc_w--;
  546.         crtc_h--;
  547.  
  548.         if (crtc_w != src_w || crtc_h != src_h)
  549.                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
  550.  
  551.         linear_offset = y * fb->pitches[0] + x * pixel_size;
  552.         sprsurf_offset =
  553.                 intel_gen4_compute_page_offset(dev_priv,
  554.                                                &x, &y, obj->tiling_mode,
  555.                                                pixel_size, fb->pitches[0]);
  556.         linear_offset -= sprsurf_offset;
  557.  
  558.         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
  559.                 sprctl |= SPRITE_ROTATE_180;
  560.  
  561.                 /* HSW and BDW does this automagically in hardware */
  562.                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
  563.                         x += src_w;
  564.                         y += src_h;
  565.                         linear_offset += src_h * fb->pitches[0] +
  566.                                 src_w * pixel_size;
  567.                 }
  568.         }
  569.  
  570.         if (key->flags) {
  571.                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
  572.                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
  573.                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
  574.         }
  575.  
  576.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  577.                 sprctl |= SPRITE_DEST_KEY;
  578.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  579.                 sprctl |= SPRITE_SOURCE_KEY;
  580.  
  581.         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
  582.         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
  583.  
  584.         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
  585.          * register */
  586.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  587.                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
  588.         else if (obj->tiling_mode != I915_TILING_NONE)
  589.                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
  590.         else
  591.                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
  592.  
  593.         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
  594.         if (intel_plane->can_scale)
  595.                 I915_WRITE(SPRSCALE(pipe), sprscale);
  596.         I915_WRITE(SPRCTL(pipe), sprctl);
  597.         I915_WRITE(SPRSURF(pipe),
  598.                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
  599.         POSTING_READ(SPRSURF(pipe));
  600. }
  601.  
  602. static void
  603. ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
  604. {
  605.         struct drm_device *dev = plane->dev;
  606.         struct drm_i915_private *dev_priv = dev->dev_private;
  607.         struct intel_plane *intel_plane = to_intel_plane(plane);
  608.         int pipe = intel_plane->pipe;
  609.  
  610.         I915_WRITE(SPRCTL(pipe), 0);
  611.         /* Can't leave the scaler enabled... */
  612.         if (intel_plane->can_scale)
  613.                 I915_WRITE(SPRSCALE(pipe), 0);
  614.  
  615.         I915_WRITE(SPRSURF(pipe), 0);
  616.         POSTING_READ(SPRSURF(pipe));
  617. }
  618.  
  619. static void
  620. ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
  621.                  struct drm_framebuffer *fb,
  622.                  int crtc_x, int crtc_y,
  623.                  unsigned int crtc_w, unsigned int crtc_h,
  624.                  uint32_t x, uint32_t y,
  625.                  uint32_t src_w, uint32_t src_h)
  626. {
  627.         struct drm_device *dev = plane->dev;
  628.         struct drm_i915_private *dev_priv = dev->dev_private;
  629.         struct intel_plane *intel_plane = to_intel_plane(plane);
  630.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  631.         int pipe = intel_plane->pipe;
  632.         unsigned long dvssurf_offset, linear_offset;
  633.         u32 dvscntr, dvsscale;
  634.         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  635.         const struct drm_intel_sprite_colorkey *key =
  636.                 &to_intel_plane_state(plane->state)->ckey;
  637.  
  638.         dvscntr = DVS_ENABLE;
  639.  
  640.         switch (fb->pixel_format) {
  641.         case DRM_FORMAT_XBGR8888:
  642.                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
  643.                 break;
  644.         case DRM_FORMAT_XRGB8888:
  645.                 dvscntr |= DVS_FORMAT_RGBX888;
  646.                 break;
  647.         case DRM_FORMAT_YUYV:
  648.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
  649.                 break;
  650.         case DRM_FORMAT_YVYU:
  651.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
  652.                 break;
  653.         case DRM_FORMAT_UYVY:
  654.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
  655.                 break;
  656.         case DRM_FORMAT_VYUY:
  657.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
  658.                 break;
  659.         default:
  660.                 BUG();
  661.         }
  662.  
  663.         /*
  664.          * Enable gamma to match primary/cursor plane behaviour.
  665.          * FIXME should be user controllable via propertiesa.
  666.          */
  667.         dvscntr |= DVS_GAMMA_ENABLE;
  668.  
  669.         if (obj->tiling_mode != I915_TILING_NONE)
  670.                 dvscntr |= DVS_TILED;
  671.  
  672.         if (IS_GEN6(dev))
  673.                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
  674.  
  675.         /* Sizes are 0 based */
  676.         src_w--;
  677.         src_h--;
  678.         crtc_w--;
  679.         crtc_h--;
  680.  
  681.         dvsscale = 0;
  682.         if (crtc_w != src_w || crtc_h != src_h)
  683.                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
  684.  
  685.         linear_offset = y * fb->pitches[0] + x * pixel_size;
  686.         dvssurf_offset =
  687.                 intel_gen4_compute_page_offset(dev_priv,
  688.                                                &x, &y, obj->tiling_mode,
  689.                                                pixel_size, fb->pitches[0]);
  690.         linear_offset -= dvssurf_offset;
  691.  
  692.         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
  693.                 dvscntr |= DVS_ROTATE_180;
  694.  
  695.                 x += src_w;
  696.                 y += src_h;
  697.                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
  698.         }
  699.  
  700.         if (key->flags) {
  701.                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
  702.                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
  703.                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
  704.         }
  705.  
  706.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  707.                 dvscntr |= DVS_DEST_KEY;
  708.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  709.                 dvscntr |= DVS_SOURCE_KEY;
  710.  
  711.         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
  712.         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
  713.  
  714.         if (obj->tiling_mode != I915_TILING_NONE)
  715.                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
  716.         else
  717.                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
  718.  
  719.         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
  720.         I915_WRITE(DVSSCALE(pipe), dvsscale);
  721.         I915_WRITE(DVSCNTR(pipe), dvscntr);
  722.         I915_WRITE(DVSSURF(pipe),
  723.                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
  724.         POSTING_READ(DVSSURF(pipe));
  725. }
  726.  
  727. static void
  728. ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
  729. {
  730.         struct drm_device *dev = plane->dev;
  731.         struct drm_i915_private *dev_priv = dev->dev_private;
  732.         struct intel_plane *intel_plane = to_intel_plane(plane);
  733.         int pipe = intel_plane->pipe;
  734.  
  735.         I915_WRITE(DVSCNTR(pipe), 0);
  736.         /* Disable the scaler */
  737.         I915_WRITE(DVSSCALE(pipe), 0);
  738.  
  739.         I915_WRITE(DVSSURF(pipe), 0);
  740.         POSTING_READ(DVSSURF(pipe));
  741. }
  742.  
  743. static int
  744. intel_check_sprite_plane(struct drm_plane *plane,
  745.                          struct intel_crtc_state *crtc_state,
  746.                          struct intel_plane_state *state)
  747. {
  748.         struct drm_device *dev = plane->dev;
  749.         struct drm_crtc *crtc = state->base.crtc;
  750.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  751.         struct intel_plane *intel_plane = to_intel_plane(plane);
  752.         struct drm_framebuffer *fb = state->base.fb;
  753.         int crtc_x, crtc_y;
  754.         unsigned int crtc_w, crtc_h;
  755.         uint32_t src_x, src_y, src_w, src_h;
  756.         struct drm_rect *src = &state->src;
  757.         struct drm_rect *dst = &state->dst;
  758.         const struct drm_rect *clip = &state->clip;
  759.         int hscale, vscale;
  760.         int max_scale, min_scale;
  761.         bool can_scale;
  762.         int pixel_size;
  763.  
  764.         if (!fb) {
  765.                 state->visible = false;
  766.                 return 0;
  767.         }
  768.  
  769.         /* Don't modify another pipe's plane */
  770.         if (intel_plane->pipe != intel_crtc->pipe) {
  771.                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
  772.                 return -EINVAL;
  773.         }
  774.  
  775.         /* FIXME check all gen limits */
  776.         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
  777.                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
  778.                 return -EINVAL;
  779.         }
  780.  
  781.         /* setup can_scale, min_scale, max_scale */
  782.         if (INTEL_INFO(dev)->gen >= 9) {
  783.                 /* use scaler when colorkey is not required */
  784.                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
  785.                         can_scale = 1;
  786.                         min_scale = 1;
  787.                         max_scale = skl_max_scale(intel_crtc, crtc_state);
  788.                 } else {
  789.                         can_scale = 0;
  790.                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
  791.                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
  792.                 }
  793.         } else {
  794.                 can_scale = intel_plane->can_scale;
  795.                 max_scale = intel_plane->max_downscale << 16;
  796.                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
  797.         }
  798.  
  799.         /*
  800.          * FIXME the following code does a bunch of fuzzy adjustments to the
  801.          * coordinates and sizes. We probably need some way to decide whether
  802.          * more strict checking should be done instead.
  803.          */
  804.         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
  805.                         state->base.rotation);
  806.  
  807.         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
  808.         BUG_ON(hscale < 0);
  809.  
  810.         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
  811.         BUG_ON(vscale < 0);
  812.  
  813.         state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
  814.  
  815.         crtc_x = dst->x1;
  816.         crtc_y = dst->y1;
  817.         crtc_w = drm_rect_width(dst);
  818.         crtc_h = drm_rect_height(dst);
  819.  
  820.         if (state->visible) {
  821.                 /* check again in case clipping clamped the results */
  822.                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
  823.                 if (hscale < 0) {
  824.                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
  825.                         drm_rect_debug_print("src: ", src, true);
  826.                         drm_rect_debug_print("dst: ", dst, false);
  827.  
  828.                         return hscale;
  829.                 }
  830.  
  831.                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
  832.                 if (vscale < 0) {
  833.                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
  834.                         drm_rect_debug_print("src: ", src, true);
  835.                         drm_rect_debug_print("dst: ", dst, false);
  836.  
  837.                         return vscale;
  838.                 }
  839.  
  840.                 /* Make the source viewport size an exact multiple of the scaling factors. */
  841.                 drm_rect_adjust_size(src,
  842.                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
  843.                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
  844.  
  845.                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
  846.                                     state->base.rotation);
  847.  
  848.                 /* sanity check to make sure the src viewport wasn't enlarged */
  849.                 WARN_ON(src->x1 < (int) state->base.src_x ||
  850.                         src->y1 < (int) state->base.src_y ||
  851.                         src->x2 > (int) state->base.src_x + state->base.src_w ||
  852.                         src->y2 > (int) state->base.src_y + state->base.src_h);
  853.  
  854.                 /*
  855.                  * Hardware doesn't handle subpixel coordinates.
  856.                  * Adjust to (macro)pixel boundary, but be careful not to
  857.                  * increase the source viewport size, because that could
  858.                  * push the downscaling factor out of bounds.
  859.                  */
  860.                 src_x = src->x1 >> 16;
  861.                 src_w = drm_rect_width(src) >> 16;
  862.                 src_y = src->y1 >> 16;
  863.                 src_h = drm_rect_height(src) >> 16;
  864.  
  865.                 if (format_is_yuv(fb->pixel_format)) {
  866.                         src_x &= ~1;
  867.                         src_w &= ~1;
  868.  
  869.                         /*
  870.                          * Must keep src and dst the
  871.                          * same if we can't scale.
  872.                          */
  873.                         if (!can_scale)
  874.                                 crtc_w &= ~1;
  875.  
  876.                         if (crtc_w == 0)
  877.                                 state->visible = false;
  878.                 }
  879.         }
  880.  
  881.         /* Check size restrictions when scaling */
  882.         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
  883.                 unsigned int width_bytes;
  884.  
  885.                 WARN_ON(!can_scale);
  886.  
  887.                 /* FIXME interlacing min height is 6 */
  888.  
  889.                 if (crtc_w < 3 || crtc_h < 3)
  890.                         state->visible = false;
  891.  
  892.                 if (src_w < 3 || src_h < 3)
  893.                         state->visible = false;
  894.  
  895.                 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  896.                 width_bytes = ((src_x * pixel_size) & 63) +
  897.                                         src_w * pixel_size;
  898.  
  899.                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
  900.                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
  901.                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
  902.                         return -EINVAL;
  903.                 }
  904.         }
  905.  
  906.         if (state->visible) {
  907.                 src->x1 = src_x << 16;
  908.                 src->x2 = (src_x + src_w) << 16;
  909.                 src->y1 = src_y << 16;
  910.                 src->y2 = (src_y + src_h) << 16;
  911.         }
  912.  
  913.         dst->x1 = crtc_x;
  914.         dst->x2 = crtc_x + crtc_w;
  915.         dst->y1 = crtc_y;
  916.         dst->y2 = crtc_y + crtc_h;
  917.  
  918.         return 0;
  919. }
  920.  
  921. static void
  922. intel_commit_sprite_plane(struct drm_plane *plane,
  923.                           struct intel_plane_state *state)
  924. {
  925.         struct drm_crtc *crtc = state->base.crtc;
  926.         struct intel_plane *intel_plane = to_intel_plane(plane);
  927.         struct drm_framebuffer *fb = state->base.fb;
  928.  
  929.         crtc = crtc ? crtc : plane->crtc;
  930.  
  931.         if (state->visible) {
  932.                 intel_plane->update_plane(plane, crtc, fb,
  933.                                           state->dst.x1, state->dst.y1,
  934.                                           drm_rect_width(&state->dst),
  935.                                           drm_rect_height(&state->dst),
  936.                                           state->src.x1 >> 16,
  937.                                           state->src.y1 >> 16,
  938.                                           drm_rect_width(&state->src) >> 16,
  939.                                           drm_rect_height(&state->src) >> 16);
  940.         } else {
  941.                 intel_plane->disable_plane(plane, crtc);
  942.         }
  943. }
  944.  
  945. int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  946.                               struct drm_file *file_priv)
  947. {
  948.         struct drm_intel_sprite_colorkey *set = data;
  949.         struct drm_plane *plane;
  950.         struct drm_plane_state *plane_state;
  951.         struct drm_atomic_state *state;
  952.         struct drm_modeset_acquire_ctx ctx;
  953.         int ret = 0;
  954.  
  955.         /* Make sure we don't try to enable both src & dest simultaneously */
  956.         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
  957.                 return -EINVAL;
  958.  
  959.         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
  960.             set->flags & I915_SET_COLORKEY_DESTINATION)
  961.                 return -EINVAL;
  962.  
  963.         plane = drm_plane_find(dev, set->plane_id);
  964.         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
  965.                 return -ENOENT;
  966.  
  967.         drm_modeset_acquire_init(&ctx, 0);
  968.  
  969.         state = drm_atomic_state_alloc(plane->dev);
  970.         if (!state) {
  971.                 ret = -ENOMEM;
  972.                 goto out;
  973.         }
  974.         state->acquire_ctx = &ctx;
  975.  
  976.         while (1) {
  977.                 plane_state = drm_atomic_get_plane_state(state, plane);
  978.                 ret = PTR_ERR_OR_ZERO(plane_state);
  979.                 if (!ret) {
  980.                         to_intel_plane_state(plane_state)->ckey = *set;
  981.                         ret = drm_atomic_commit(state);
  982.                 }
  983.  
  984.                 if (ret != -EDEADLK)
  985.                         break;
  986.  
  987.                 drm_atomic_state_clear(state);
  988.                 drm_modeset_backoff(&ctx);
  989.         }
  990.  
  991.         if (ret)
  992.                 drm_atomic_state_free(state);
  993.  
  994. out:
  995.         drm_modeset_drop_locks(&ctx);
  996.         drm_modeset_acquire_fini(&ctx);
  997.         return ret;
  998. }
  999.  
  1000. static const uint32_t ilk_plane_formats[] = {
  1001.         DRM_FORMAT_XRGB8888,
  1002.         DRM_FORMAT_YUYV,
  1003.         DRM_FORMAT_YVYU,
  1004.         DRM_FORMAT_UYVY,
  1005.         DRM_FORMAT_VYUY,
  1006. };
  1007.  
  1008. static const uint32_t snb_plane_formats[] = {
  1009.         DRM_FORMAT_XBGR8888,
  1010.         DRM_FORMAT_XRGB8888,
  1011.         DRM_FORMAT_YUYV,
  1012.         DRM_FORMAT_YVYU,
  1013.         DRM_FORMAT_UYVY,
  1014.         DRM_FORMAT_VYUY,
  1015. };
  1016.  
  1017. static const uint32_t vlv_plane_formats[] = {
  1018.         DRM_FORMAT_RGB565,
  1019.         DRM_FORMAT_ABGR8888,
  1020.         DRM_FORMAT_ARGB8888,
  1021.         DRM_FORMAT_XBGR8888,
  1022.         DRM_FORMAT_XRGB8888,
  1023.         DRM_FORMAT_XBGR2101010,
  1024.         DRM_FORMAT_ABGR2101010,
  1025.         DRM_FORMAT_YUYV,
  1026.         DRM_FORMAT_YVYU,
  1027.         DRM_FORMAT_UYVY,
  1028.         DRM_FORMAT_VYUY,
  1029. };
  1030.  
  1031. static uint32_t skl_plane_formats[] = {
  1032.         DRM_FORMAT_RGB565,
  1033.         DRM_FORMAT_ABGR8888,
  1034.         DRM_FORMAT_ARGB8888,
  1035.         DRM_FORMAT_XBGR8888,
  1036.         DRM_FORMAT_XRGB8888,
  1037.         DRM_FORMAT_YUYV,
  1038.         DRM_FORMAT_YVYU,
  1039.         DRM_FORMAT_UYVY,
  1040.         DRM_FORMAT_VYUY,
  1041. };
  1042.  
  1043. int
  1044. intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
  1045. {
  1046.         struct intel_plane *intel_plane;
  1047.         struct intel_plane_state *state;
  1048.         unsigned long possible_crtcs;
  1049.         const uint32_t *plane_formats;
  1050.         int num_plane_formats;
  1051.         int ret;
  1052.  
  1053.         if (INTEL_INFO(dev)->gen < 5)
  1054.                 return -ENODEV;
  1055.  
  1056.         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
  1057.         if (!intel_plane)
  1058.                 return -ENOMEM;
  1059.  
  1060.         state = intel_create_plane_state(&intel_plane->base);
  1061.         if (!state) {
  1062.                 kfree(intel_plane);
  1063.                 return -ENOMEM;
  1064.         }
  1065.         intel_plane->base.state = &state->base;
  1066.  
  1067.         switch (INTEL_INFO(dev)->gen) {
  1068.         case 5:
  1069.         case 6:
  1070.                 intel_plane->can_scale = true;
  1071.                 intel_plane->max_downscale = 16;
  1072.                 intel_plane->update_plane = ilk_update_plane;
  1073.                 intel_plane->disable_plane = ilk_disable_plane;
  1074.  
  1075.                 if (IS_GEN6(dev)) {
  1076.                         plane_formats = snb_plane_formats;
  1077.                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
  1078.                 } else {
  1079.                         plane_formats = ilk_plane_formats;
  1080.                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
  1081.                 }
  1082.                 break;
  1083.  
  1084.         case 7:
  1085.         case 8:
  1086.                 if (IS_IVYBRIDGE(dev)) {
  1087.                         intel_plane->can_scale = true;
  1088.                         intel_plane->max_downscale = 2;
  1089.                 } else {
  1090.                         intel_plane->can_scale = false;
  1091.                         intel_plane->max_downscale = 1;
  1092.                 }
  1093.  
  1094.                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
  1095.                         intel_plane->update_plane = vlv_update_plane;
  1096.                         intel_plane->disable_plane = vlv_disable_plane;
  1097.  
  1098.                         plane_formats = vlv_plane_formats;
  1099.                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
  1100.                 } else {
  1101.                         intel_plane->update_plane = ivb_update_plane;
  1102.                         intel_plane->disable_plane = ivb_disable_plane;
  1103.  
  1104.                         plane_formats = snb_plane_formats;
  1105.                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
  1106.                 }
  1107.                 break;
  1108.         case 9:
  1109.                 intel_plane->can_scale = true;
  1110.                 intel_plane->update_plane = skl_update_plane;
  1111.                 intel_plane->disable_plane = skl_disable_plane;
  1112.                 state->scaler_id = -1;
  1113.  
  1114.                 plane_formats = skl_plane_formats;
  1115.                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
  1116.                 break;
  1117.         default:
  1118.                 kfree(intel_plane);
  1119.                 return -ENODEV;
  1120.         }
  1121.  
  1122.         intel_plane->pipe = pipe;
  1123.         intel_plane->plane = plane;
  1124.         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
  1125.         intel_plane->check_plane = intel_check_sprite_plane;
  1126.         intel_plane->commit_plane = intel_commit_sprite_plane;
  1127.         possible_crtcs = (1 << pipe);
  1128.         ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
  1129.                                        &intel_plane_funcs,
  1130.                                        plane_formats, num_plane_formats,
  1131.                                        DRM_PLANE_TYPE_OVERLAY, NULL);
  1132.         if (ret) {
  1133.                 kfree(intel_plane);
  1134.                 goto out;
  1135.         }
  1136.  
  1137.         intel_create_rotation_property(dev, intel_plane);
  1138.  
  1139.         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
  1140.  
  1141. out:
  1142.         return ret;
  1143. }
  1144.