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  1. /*
  2.  * Copyright © 2011 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20.  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21.  * SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25.  *
  26.  * New plane/sprite handling.
  27.  *
  28.  * The older chips had a separate interface for programming plane related
  29.  * registers; newer ones are much simpler and we can use the new DRM plane
  30.  * support.
  31.  */
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_fourcc.h>
  35. #include <drm/drm_rect.h>
  36. #include <drm/drm_atomic.h>
  37. #include <drm/drm_plane_helper.h>
  38. #include "intel_drv.h"
  39. #include <drm/i915_drm.h>
  40. #include "i915_drv.h"
  41.  
  42. static bool
  43. format_is_yuv(uint32_t format)
  44. {
  45.         switch (format) {
  46.         case DRM_FORMAT_YUYV:
  47.         case DRM_FORMAT_UYVY:
  48.         case DRM_FORMAT_VYUY:
  49.         case DRM_FORMAT_YVYU:
  50.                 return true;
  51.         default:
  52.                 return false;
  53.         }
  54. }
  55.  
  56. static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  57.                               int usecs)
  58. {
  59.         /* paranoia */
  60.         if (!adjusted_mode->crtc_htotal)
  61.                 return 1;
  62.  
  63.         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  64.                             1000 * adjusted_mode->crtc_htotal);
  65. }
  66.  
  67. /**
  68.  * intel_pipe_update_start() - start update of a set of display registers
  69.  * @crtc: the crtc of which the registers are going to be updated
  70.  * @start_vbl_count: vblank counter return pointer used for error checking
  71.  *
  72.  * Mark the start of an update to pipe registers that should be updated
  73.  * atomically regarding vblank. If the next vblank will happens within
  74.  * the next 100 us, this function waits until the vblank passes.
  75.  *
  76.  * After a successful call to this function, interrupts will be disabled
  77.  * until a subsequent call to intel_pipe_update_end(). That is done to
  78.  * avoid random delays. The value written to @start_vbl_count should be
  79.  * supplied to intel_pipe_update_end() for error checking.
  80.  */
  81. void intel_pipe_update_start(struct intel_crtc *crtc)
  82. {
  83. ENTER();
  84.         struct drm_device *dev = crtc->base.dev;
  85.         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  86.         enum pipe pipe = crtc->pipe;
  87.         long timeout = msecs_to_jiffies_timeout(1);
  88.         int scanline, min, max, vblank_start;
  89. #if 0
  90. //   wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  91. //   DEFINE_WAIT(wait);
  92.  
  93.         vblank_start = adjusted_mode->crtc_vblank_start;
  94.         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  95.                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  96.  
  97.         /* FIXME needs to be calibrated sensibly */
  98.         min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
  99.         max = vblank_start - 1;
  100.  
  101.         if (min <= 0 || max <= 0)
  102.                 return;
  103.  
  104. //   if (WARN_ON(drm_vblank_get(dev, pipe)))
  105. //       return false;
  106.  
  107.         crtc->debug.min_vbl = min;
  108.         crtc->debug.max_vbl = max;
  109.         trace_i915_pipe_update_start(crtc);
  110.  
  111.         for (;;) {
  112.                 /*
  113.                  * prepare_to_wait() has a memory barrier, which guarantees
  114.                  * other CPUs can see the task state update by the time we
  115.                  * read the scanline.
  116.                  */
  117.                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
  118.  
  119.                 scanline = intel_get_crtc_scanline(crtc);
  120.                 if (scanline < min || scanline > max)
  121.                         break;
  122.  
  123.                 if (timeout <= 0) {
  124.                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
  125.                                   pipe_name(crtc->pipe));
  126.                         break;
  127.                 }
  128.  
  129. //       local_irq_enable();
  130.  
  131.         schedule_timeout(timeout);
  132.         timeout = 0;
  133. //       local_irq_disable();
  134.         }
  135.  
  136.         finish_wait(wq, &wait);
  137. #endif
  138.  
  139.         crtc->debug.scanline_start = scanline;
  140.         crtc->debug.start_vbl_time = ktime_get();
  141.         crtc->debug.start_vbl_count =
  142.                 dev->driver->get_vblank_counter(dev, pipe);
  143.  
  144.         trace_i915_pipe_update_vblank_evaded(crtc);
  145. }
  146.  
  147. /**
  148.  * intel_pipe_update_end() - end update of a set of display registers
  149.  * @crtc: the crtc of which the registers were updated
  150.  * @start_vbl_count: start vblank counter (used for error checking)
  151.  *
  152.  * Mark the end of an update started with intel_pipe_update_start(). This
  153.  * re-enables interrupts and verifies the update was actually completed
  154.  * before a vblank using the value of @start_vbl_count.
  155.  */
  156. void intel_pipe_update_end(struct intel_crtc *crtc)
  157. {
  158.         struct drm_device *dev = crtc->base.dev;
  159.         enum pipe pipe = crtc->pipe;
  160.         int scanline_end = intel_get_crtc_scanline(crtc);
  161.         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
  162.         ktime_t end_vbl_time = ktime_get();
  163.  
  164.         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
  165.  
  166. //   local_irq_enable();
  167.  
  168.         if (crtc->debug.start_vbl_count &&
  169.             crtc->debug.start_vbl_count != end_vbl_count) {
  170.                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
  171.                           pipe_name(pipe), crtc->debug.start_vbl_count,
  172.                           end_vbl_count,
  173.                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
  174.                           crtc->debug.min_vbl, crtc->debug.max_vbl,
  175.                           crtc->debug.scanline_start, scanline_end);
  176.         }
  177. }
  178.  
  179. static void
  180. skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
  181.                  struct drm_framebuffer *fb,
  182.                  int crtc_x, int crtc_y,
  183.                  unsigned int crtc_w, unsigned int crtc_h,
  184.                  uint32_t x, uint32_t y,
  185.                  uint32_t src_w, uint32_t src_h)
  186. {
  187.         struct drm_device *dev = drm_plane->dev;
  188.         struct drm_i915_private *dev_priv = dev->dev_private;
  189.         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
  190.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  191.         const int pipe = intel_plane->pipe;
  192.         const int plane = intel_plane->plane + 1;
  193.         u32 plane_ctl, stride_div, stride;
  194.         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  195.         const struct drm_intel_sprite_colorkey *key =
  196.                 &to_intel_plane_state(drm_plane->state)->ckey;
  197.         unsigned long surf_addr;
  198.         u32 tile_height, plane_offset, plane_size;
  199.         unsigned int rotation;
  200.         int x_offset, y_offset;
  201.         struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
  202.         int scaler_id;
  203.  
  204.         plane_ctl = PLANE_CTL_ENABLE |
  205.                 PLANE_CTL_PIPE_GAMMA_ENABLE |
  206.                 PLANE_CTL_PIPE_CSC_ENABLE;
  207.  
  208.         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
  209.         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
  210.  
  211.         rotation = drm_plane->state->rotation;
  212.         plane_ctl |= skl_plane_ctl_rotation(rotation);
  213.  
  214.         intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
  215.                                        pixel_size, true,
  216.                                        src_w != crtc_w || src_h != crtc_h);
  217.  
  218.         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
  219.                                                fb->pixel_format);
  220.  
  221.         scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;
  222.  
  223.         /* Sizes are 0 based */
  224.         src_w--;
  225.         src_h--;
  226.         crtc_w--;
  227.         crtc_h--;
  228.  
  229.         if (key->flags) {
  230.                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
  231.                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
  232.                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
  233.         }
  234.  
  235.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  236.                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
  237.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  238.                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
  239.  
  240.         surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
  241.  
  242.         if (intel_rotation_90_or_270(rotation)) {
  243.                 /* stride: Surface height in tiles */
  244.                 tile_height = intel_tile_height(dev, fb->pixel_format,
  245.                                                 fb->modifier[0], 0);
  246.                 stride = DIV_ROUND_UP(fb->height, tile_height);
  247.                 plane_size = (src_w << 16) | src_h;
  248.                 x_offset = stride * tile_height - y - (src_h + 1);
  249.                 y_offset = x;
  250.         } else {
  251.                 stride = fb->pitches[0] / stride_div;
  252.                 plane_size = (src_h << 16) | src_w;
  253.                 x_offset = x;
  254.                 y_offset = y;
  255.         }
  256.         plane_offset = y_offset << 16 | x_offset;
  257.  
  258.         I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
  259.         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
  260.         I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
  261.  
  262.         /* program plane scaler */
  263.         if (scaler_id >= 0) {
  264.                 uint32_t ps_ctrl = 0;
  265.  
  266.                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
  267.                         PS_PLANE_SEL(plane));
  268.                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
  269.                         crtc_state->scaler_state.scalers[scaler_id].mode;
  270.                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
  271.                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
  272.                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
  273.                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
  274.                         ((crtc_w + 1) << 16)|(crtc_h + 1));
  275.  
  276.                 I915_WRITE(PLANE_POS(pipe, plane), 0);
  277.         } else {
  278.                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
  279.         }
  280.  
  281.         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
  282.         I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
  283.         POSTING_READ(PLANE_SURF(pipe, plane));
  284. }
  285.  
  286. static void
  287. skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
  288. {
  289.         struct drm_device *dev = dplane->dev;
  290.         struct drm_i915_private *dev_priv = dev->dev_private;
  291.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  292.         const int pipe = intel_plane->pipe;
  293.         const int plane = intel_plane->plane + 1;
  294.  
  295.         I915_WRITE(PLANE_CTL(pipe, plane), 0);
  296.  
  297.         I915_WRITE(PLANE_SURF(pipe, plane), 0);
  298.         POSTING_READ(PLANE_SURF(pipe, plane));
  299.  
  300.         intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
  301. }
  302.  
  303. static void
  304. chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
  305. {
  306.         struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
  307.         int plane = intel_plane->plane;
  308.  
  309.         /* Seems RGB data bypasses the CSC always */
  310.         if (!format_is_yuv(format))
  311.                 return;
  312.  
  313.         /*
  314.          * BT.601 limited range YCbCr -> full range RGB
  315.          *
  316.          * |r|   | 6537 4769     0|   |cr  |
  317.          * |g| = |-3330 4769 -1605| x |y-64|
  318.          * |b|   |    0 4769  8263|   |cb  |
  319.          *
  320.          * Cb and Cr apparently come in as signed already, so no
  321.          * need for any offset. For Y we need to remove the offset.
  322.          */
  323.         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
  324.         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
  325.         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
  326.  
  327.         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
  328.         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
  329.         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
  330.         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
  331.         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
  332.  
  333.         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
  334.         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
  335.         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
  336.  
  337.         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  338.         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  339.         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  340. }
  341.  
  342. static void
  343. vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
  344.                  struct drm_framebuffer *fb,
  345.                  int crtc_x, int crtc_y,
  346.                  unsigned int crtc_w, unsigned int crtc_h,
  347.                  uint32_t x, uint32_t y,
  348.                  uint32_t src_w, uint32_t src_h)
  349. {
  350.         struct drm_device *dev = dplane->dev;
  351.         struct drm_i915_private *dev_priv = dev->dev_private;
  352.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  353.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  354.         int pipe = intel_plane->pipe;
  355.         int plane = intel_plane->plane;
  356.         u32 sprctl;
  357.         unsigned long sprsurf_offset, linear_offset;
  358.         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  359.         const struct drm_intel_sprite_colorkey *key =
  360.                 &to_intel_plane_state(dplane->state)->ckey;
  361.  
  362.         sprctl = SP_ENABLE;
  363.  
  364.         switch (fb->pixel_format) {
  365.         case DRM_FORMAT_YUYV:
  366.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
  367.                 break;
  368.         case DRM_FORMAT_YVYU:
  369.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
  370.                 break;
  371.         case DRM_FORMAT_UYVY:
  372.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
  373.                 break;
  374.         case DRM_FORMAT_VYUY:
  375.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
  376.                 break;
  377.         case DRM_FORMAT_RGB565:
  378.                 sprctl |= SP_FORMAT_BGR565;
  379.                 break;
  380.         case DRM_FORMAT_XRGB8888:
  381.                 sprctl |= SP_FORMAT_BGRX8888;
  382.                 break;
  383.         case DRM_FORMAT_ARGB8888:
  384.                 sprctl |= SP_FORMAT_BGRA8888;
  385.                 break;
  386.         case DRM_FORMAT_XBGR2101010:
  387.                 sprctl |= SP_FORMAT_RGBX1010102;
  388.                 break;
  389.         case DRM_FORMAT_ABGR2101010:
  390.                 sprctl |= SP_FORMAT_RGBA1010102;
  391.                 break;
  392.         case DRM_FORMAT_XBGR8888:
  393.                 sprctl |= SP_FORMAT_RGBX8888;
  394.                 break;
  395.         case DRM_FORMAT_ABGR8888:
  396.                 sprctl |= SP_FORMAT_RGBA8888;
  397.                 break;
  398.         default:
  399.                 /*
  400.                  * If we get here one of the upper layers failed to filter
  401.                  * out the unsupported plane formats
  402.                  */
  403.                 BUG();
  404.                 break;
  405.         }
  406.  
  407.         /*
  408.          * Enable gamma to match primary/cursor plane behaviour.
  409.          * FIXME should be user controllable via propertiesa.
  410.          */
  411.         sprctl |= SP_GAMMA_ENABLE;
  412.  
  413.         if (obj->tiling_mode != I915_TILING_NONE)
  414.                 sprctl |= SP_TILED;
  415.  
  416.         /* Sizes are 0 based */
  417.         src_w--;
  418.         src_h--;
  419.         crtc_w--;
  420.         crtc_h--;
  421.  
  422.         linear_offset = y * fb->pitches[0] + x * pixel_size;
  423.         sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
  424.                                                         &x, &y,
  425.                                                         obj->tiling_mode,
  426.                                                         pixel_size,
  427.                                                         fb->pitches[0]);
  428.         linear_offset -= sprsurf_offset;
  429.  
  430.         if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
  431.                 sprctl |= SP_ROTATE_180;
  432.  
  433.                 x += src_w;
  434.                 y += src_h;
  435.                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
  436.         }
  437.  
  438.         if (key->flags) {
  439.                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
  440.                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
  441.                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
  442.         }
  443.  
  444.         if (key->flags & I915_SET_COLORKEY_SOURCE)
  445.                 sprctl |= SP_SOURCE_KEY;
  446.  
  447.         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
  448.                 chv_update_csc(intel_plane, fb->pixel_format);
  449.  
  450.         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
  451.         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
  452.  
  453.         if (obj->tiling_mode != I915_TILING_NONE)
  454.                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
  455.         else
  456.                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
  457.  
  458.         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
  459.  
  460.         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
  461.         I915_WRITE(SPCNTR(pipe, plane), sprctl);
  462.         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
  463.                    sprsurf_offset);
  464.         POSTING_READ(SPSURF(pipe, plane));
  465. }
  466.  
  467. static void
  468. vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
  469. {
  470.         struct drm_device *dev = dplane->dev;
  471.         struct drm_i915_private *dev_priv = dev->dev_private;
  472.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  473.         int pipe = intel_plane->pipe;
  474.         int plane = intel_plane->plane;
  475.  
  476.         I915_WRITE(SPCNTR(pipe, plane), 0);
  477.  
  478.         I915_WRITE(SPSURF(pipe, plane), 0);
  479.         POSTING_READ(SPSURF(pipe, plane));
  480. }
  481.  
  482. static void
  483. ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
  484.                  struct drm_framebuffer *fb,
  485.                  int crtc_x, int crtc_y,
  486.                  unsigned int crtc_w, unsigned int crtc_h,
  487.                  uint32_t x, uint32_t y,
  488.                  uint32_t src_w, uint32_t src_h)
  489. {
  490.         struct drm_device *dev = plane->dev;
  491.         struct drm_i915_private *dev_priv = dev->dev_private;
  492.         struct intel_plane *intel_plane = to_intel_plane(plane);
  493.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  494.         enum pipe pipe = intel_plane->pipe;
  495.         u32 sprctl, sprscale = 0;
  496.         unsigned long sprsurf_offset, linear_offset;
  497.         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  498.         const struct drm_intel_sprite_colorkey *key =
  499.                 &to_intel_plane_state(plane->state)->ckey;
  500.  
  501.         sprctl = SPRITE_ENABLE;
  502.  
  503.         switch (fb->pixel_format) {
  504.         case DRM_FORMAT_XBGR8888:
  505.                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
  506.                 break;
  507.         case DRM_FORMAT_XRGB8888:
  508.                 sprctl |= SPRITE_FORMAT_RGBX888;
  509.                 break;
  510.         case DRM_FORMAT_YUYV:
  511.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
  512.                 break;
  513.         case DRM_FORMAT_YVYU:
  514.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
  515.                 break;
  516.         case DRM_FORMAT_UYVY:
  517.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
  518.                 break;
  519.         case DRM_FORMAT_VYUY:
  520.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
  521.                 break;
  522.         default:
  523.                 BUG();
  524.         }
  525.  
  526.         /*
  527.          * Enable gamma to match primary/cursor plane behaviour.
  528.          * FIXME should be user controllable via propertiesa.
  529.          */
  530.         sprctl |= SPRITE_GAMMA_ENABLE;
  531.  
  532.         if (obj->tiling_mode != I915_TILING_NONE)
  533.                 sprctl |= SPRITE_TILED;
  534.  
  535.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  536.                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
  537.         else
  538.                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
  539.  
  540.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  541.                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
  542.  
  543.         intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
  544.                                        true,
  545.                                        src_w != crtc_w || src_h != crtc_h);
  546.  
  547.         /* Sizes are 0 based */
  548.         src_w--;
  549.         src_h--;
  550.         crtc_w--;
  551.         crtc_h--;
  552.  
  553.         if (crtc_w != src_w || crtc_h != src_h)
  554.                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
  555.  
  556.         linear_offset = y * fb->pitches[0] + x * pixel_size;
  557.         sprsurf_offset =
  558.                 intel_gen4_compute_page_offset(dev_priv,
  559.                                                &x, &y, obj->tiling_mode,
  560.                                                pixel_size, fb->pitches[0]);
  561.         linear_offset -= sprsurf_offset;
  562.  
  563.         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
  564.                 sprctl |= SPRITE_ROTATE_180;
  565.  
  566.                 /* HSW and BDW does this automagically in hardware */
  567.                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
  568.                         x += src_w;
  569.                         y += src_h;
  570.                         linear_offset += src_h * fb->pitches[0] +
  571.                                 src_w * pixel_size;
  572.                 }
  573.         }
  574.  
  575.         if (key->flags) {
  576.                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
  577.                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
  578.                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
  579.         }
  580.  
  581.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  582.                 sprctl |= SPRITE_DEST_KEY;
  583.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  584.                 sprctl |= SPRITE_SOURCE_KEY;
  585.  
  586.         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
  587.         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
  588.  
  589.         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
  590.          * register */
  591.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  592.                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
  593.         else if (obj->tiling_mode != I915_TILING_NONE)
  594.                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
  595.         else
  596.                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
  597.  
  598.         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
  599.         if (intel_plane->can_scale)
  600.                 I915_WRITE(SPRSCALE(pipe), sprscale);
  601.         I915_WRITE(SPRCTL(pipe), sprctl);
  602.         I915_WRITE(SPRSURF(pipe),
  603.                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
  604.         POSTING_READ(SPRSURF(pipe));
  605. }
  606.  
  607. static void
  608. ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
  609. {
  610.         struct drm_device *dev = plane->dev;
  611.         struct drm_i915_private *dev_priv = dev->dev_private;
  612.         struct intel_plane *intel_plane = to_intel_plane(plane);
  613.         int pipe = intel_plane->pipe;
  614.  
  615.         I915_WRITE(SPRCTL(pipe), 0);
  616.         /* Can't leave the scaler enabled... */
  617.         if (intel_plane->can_scale)
  618.                 I915_WRITE(SPRSCALE(pipe), 0);
  619.  
  620.         I915_WRITE(SPRSURF(pipe), 0);
  621.         POSTING_READ(SPRSURF(pipe));
  622. }
  623.  
  624. static void
  625. ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
  626.                  struct drm_framebuffer *fb,
  627.                  int crtc_x, int crtc_y,
  628.                  unsigned int crtc_w, unsigned int crtc_h,
  629.                  uint32_t x, uint32_t y,
  630.                  uint32_t src_w, uint32_t src_h)
  631. {
  632.         struct drm_device *dev = plane->dev;
  633.         struct drm_i915_private *dev_priv = dev->dev_private;
  634.         struct intel_plane *intel_plane = to_intel_plane(plane);
  635.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  636.         int pipe = intel_plane->pipe;
  637.         unsigned long dvssurf_offset, linear_offset;
  638.         u32 dvscntr, dvsscale;
  639.         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  640.         const struct drm_intel_sprite_colorkey *key =
  641.                 &to_intel_plane_state(plane->state)->ckey;
  642.  
  643.         dvscntr = DVS_ENABLE;
  644.  
  645.         switch (fb->pixel_format) {
  646.         case DRM_FORMAT_XBGR8888:
  647.                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
  648.                 break;
  649.         case DRM_FORMAT_XRGB8888:
  650.                 dvscntr |= DVS_FORMAT_RGBX888;
  651.                 break;
  652.         case DRM_FORMAT_YUYV:
  653.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
  654.                 break;
  655.         case DRM_FORMAT_YVYU:
  656.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
  657.                 break;
  658.         case DRM_FORMAT_UYVY:
  659.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
  660.                 break;
  661.         case DRM_FORMAT_VYUY:
  662.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
  663.                 break;
  664.         default:
  665.                 BUG();
  666.         }
  667.  
  668.         /*
  669.          * Enable gamma to match primary/cursor plane behaviour.
  670.          * FIXME should be user controllable via propertiesa.
  671.          */
  672.         dvscntr |= DVS_GAMMA_ENABLE;
  673.  
  674.         if (obj->tiling_mode != I915_TILING_NONE)
  675.                 dvscntr |= DVS_TILED;
  676.  
  677.         if (IS_GEN6(dev))
  678.                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
  679.  
  680.         intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
  681.                                        pixel_size, true,
  682.                                        src_w != crtc_w || src_h != crtc_h);
  683.  
  684.         /* Sizes are 0 based */
  685.         src_w--;
  686.         src_h--;
  687.         crtc_w--;
  688.         crtc_h--;
  689.  
  690.         dvsscale = 0;
  691.         if (crtc_w != src_w || crtc_h != src_h)
  692.                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
  693.  
  694.         linear_offset = y * fb->pitches[0] + x * pixel_size;
  695.         dvssurf_offset =
  696.                 intel_gen4_compute_page_offset(dev_priv,
  697.                                                &x, &y, obj->tiling_mode,
  698.                                                pixel_size, fb->pitches[0]);
  699.         linear_offset -= dvssurf_offset;
  700.  
  701.         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
  702.                 dvscntr |= DVS_ROTATE_180;
  703.  
  704.                 x += src_w;
  705.                 y += src_h;
  706.                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
  707.         }
  708.  
  709.         if (key->flags) {
  710.                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
  711.                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
  712.                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
  713.         }
  714.  
  715.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  716.                 dvscntr |= DVS_DEST_KEY;
  717.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  718.                 dvscntr |= DVS_SOURCE_KEY;
  719.  
  720.         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
  721.         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
  722.  
  723.         if (obj->tiling_mode != I915_TILING_NONE)
  724.                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
  725.         else
  726.                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
  727.  
  728.         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
  729.         I915_WRITE(DVSSCALE(pipe), dvsscale);
  730.         I915_WRITE(DVSCNTR(pipe), dvscntr);
  731.         I915_WRITE(DVSSURF(pipe),
  732.                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
  733.         POSTING_READ(DVSSURF(pipe));
  734. }
  735.  
  736. static void
  737. ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
  738. {
  739.         struct drm_device *dev = plane->dev;
  740.         struct drm_i915_private *dev_priv = dev->dev_private;
  741.         struct intel_plane *intel_plane = to_intel_plane(plane);
  742.         int pipe = intel_plane->pipe;
  743.  
  744.         I915_WRITE(DVSCNTR(pipe), 0);
  745.         /* Disable the scaler */
  746.         I915_WRITE(DVSSCALE(pipe), 0);
  747.  
  748.         I915_WRITE(DVSSURF(pipe), 0);
  749.         POSTING_READ(DVSSURF(pipe));
  750. }
  751.  
  752. static int
  753. intel_check_sprite_plane(struct drm_plane *plane,
  754.                          struct intel_crtc_state *crtc_state,
  755.                          struct intel_plane_state *state)
  756. {
  757.         struct drm_device *dev = plane->dev;
  758.         struct drm_crtc *crtc = state->base.crtc;
  759.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  760.         struct intel_plane *intel_plane = to_intel_plane(plane);
  761.         struct drm_framebuffer *fb = state->base.fb;
  762.         int crtc_x, crtc_y;
  763.         unsigned int crtc_w, crtc_h;
  764.         uint32_t src_x, src_y, src_w, src_h;
  765.         struct drm_rect *src = &state->src;
  766.         struct drm_rect *dst = &state->dst;
  767.         const struct drm_rect *clip = &state->clip;
  768.         int hscale, vscale;
  769.         int max_scale, min_scale;
  770.         bool can_scale;
  771.         int pixel_size;
  772.  
  773.         if (!fb) {
  774.                 state->visible = false;
  775.                 return 0;
  776.         }
  777.  
  778.         /* Don't modify another pipe's plane */
  779.         if (intel_plane->pipe != intel_crtc->pipe) {
  780.                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
  781.                 return -EINVAL;
  782.         }
  783.  
  784.         /* FIXME check all gen limits */
  785.         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
  786.                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
  787.                 return -EINVAL;
  788.         }
  789.  
  790.         /* setup can_scale, min_scale, max_scale */
  791.         if (INTEL_INFO(dev)->gen >= 9) {
  792.                 /* use scaler when colorkey is not required */
  793.                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
  794.                         can_scale = 1;
  795.                         min_scale = 1;
  796.                         max_scale = skl_max_scale(intel_crtc, crtc_state);
  797.                 } else {
  798.                         can_scale = 0;
  799.                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
  800.                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
  801.                 }
  802.         } else {
  803.                 can_scale = intel_plane->can_scale;
  804.                 max_scale = intel_plane->max_downscale << 16;
  805.                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
  806.         }
  807.  
  808.         /*
  809.          * FIXME the following code does a bunch of fuzzy adjustments to the
  810.          * coordinates and sizes. We probably need some way to decide whether
  811.          * more strict checking should be done instead.
  812.          */
  813.         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
  814.                         state->base.rotation);
  815.  
  816.         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
  817.         BUG_ON(hscale < 0);
  818.  
  819.         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
  820.         BUG_ON(vscale < 0);
  821.  
  822.         state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
  823.  
  824.         crtc_x = dst->x1;
  825.         crtc_y = dst->y1;
  826.         crtc_w = drm_rect_width(dst);
  827.         crtc_h = drm_rect_height(dst);
  828.  
  829.         if (state->visible) {
  830.                 /* check again in case clipping clamped the results */
  831.                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
  832.                 if (hscale < 0) {
  833.                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
  834.                         drm_rect_debug_print(src, true);
  835.                         drm_rect_debug_print(dst, false);
  836.  
  837.                         return hscale;
  838.                 }
  839.  
  840.                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
  841.                 if (vscale < 0) {
  842.                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
  843.                         drm_rect_debug_print(src, true);
  844.                         drm_rect_debug_print(dst, false);
  845.  
  846.                         return vscale;
  847.                 }
  848.  
  849.                 /* Make the source viewport size an exact multiple of the scaling factors. */
  850.                 drm_rect_adjust_size(src,
  851.                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
  852.                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
  853.  
  854.                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
  855.                                     state->base.rotation);
  856.  
  857.                 /* sanity check to make sure the src viewport wasn't enlarged */
  858.                 WARN_ON(src->x1 < (int) state->base.src_x ||
  859.                         src->y1 < (int) state->base.src_y ||
  860.                         src->x2 > (int) state->base.src_x + state->base.src_w ||
  861.                         src->y2 > (int) state->base.src_y + state->base.src_h);
  862.  
  863.                 /*
  864.                  * Hardware doesn't handle subpixel coordinates.
  865.                  * Adjust to (macro)pixel boundary, but be careful not to
  866.                  * increase the source viewport size, because that could
  867.                  * push the downscaling factor out of bounds.
  868.                  */
  869.                 src_x = src->x1 >> 16;
  870.                 src_w = drm_rect_width(src) >> 16;
  871.                 src_y = src->y1 >> 16;
  872.                 src_h = drm_rect_height(src) >> 16;
  873.  
  874.                 if (format_is_yuv(fb->pixel_format)) {
  875.                         src_x &= ~1;
  876.                         src_w &= ~1;
  877.  
  878.                         /*
  879.                          * Must keep src and dst the
  880.                          * same if we can't scale.
  881.                          */
  882.                         if (!can_scale)
  883.                                 crtc_w &= ~1;
  884.  
  885.                         if (crtc_w == 0)
  886.                                 state->visible = false;
  887.                 }
  888.         }
  889.  
  890.         /* Check size restrictions when scaling */
  891.         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
  892.                 unsigned int width_bytes;
  893.  
  894.                 WARN_ON(!can_scale);
  895.  
  896.                 /* FIXME interlacing min height is 6 */
  897.  
  898.                 if (crtc_w < 3 || crtc_h < 3)
  899.                         state->visible = false;
  900.  
  901.                 if (src_w < 3 || src_h < 3)
  902.                         state->visible = false;
  903.  
  904.                 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  905.                 width_bytes = ((src_x * pixel_size) & 63) +
  906.                                         src_w * pixel_size;
  907.  
  908.                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
  909.                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
  910.                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
  911.                         return -EINVAL;
  912.                 }
  913.         }
  914.  
  915.         if (state->visible) {
  916.                 src->x1 = src_x << 16;
  917.                 src->x2 = (src_x + src_w) << 16;
  918.                 src->y1 = src_y << 16;
  919.                 src->y2 = (src_y + src_h) << 16;
  920.         }
  921.  
  922.         dst->x1 = crtc_x;
  923.         dst->x2 = crtc_x + crtc_w;
  924.         dst->y1 = crtc_y;
  925.         dst->y2 = crtc_y + crtc_h;
  926.  
  927.         return 0;
  928. }
  929.  
  930. static void
  931. intel_commit_sprite_plane(struct drm_plane *plane,
  932.                           struct intel_plane_state *state)
  933. {
  934.         struct drm_crtc *crtc = state->base.crtc;
  935.         struct intel_plane *intel_plane = to_intel_plane(plane);
  936.         struct drm_framebuffer *fb = state->base.fb;
  937.  
  938.         crtc = crtc ? crtc : plane->crtc;
  939.  
  940.         if (!crtc->state->active)
  941.                 return;
  942.  
  943.         if (state->visible) {
  944.                 intel_plane->update_plane(plane, crtc, fb,
  945.                                           state->dst.x1, state->dst.y1,
  946.                                           drm_rect_width(&state->dst),
  947.                                           drm_rect_height(&state->dst),
  948.                                           state->src.x1 >> 16,
  949.                                           state->src.y1 >> 16,
  950.                                           drm_rect_width(&state->src) >> 16,
  951.                                           drm_rect_height(&state->src) >> 16);
  952.         } else {
  953.                 intel_plane->disable_plane(plane, crtc);
  954.         }
  955. }
  956.  
  957. int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  958.                               struct drm_file *file_priv)
  959. {
  960.         struct drm_intel_sprite_colorkey *set = data;
  961.         struct drm_plane *plane;
  962.         struct drm_plane_state *plane_state;
  963.         struct drm_atomic_state *state;
  964.         struct drm_modeset_acquire_ctx ctx;
  965.         int ret = 0;
  966.  
  967.         /* Make sure we don't try to enable both src & dest simultaneously */
  968.         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
  969.                 return -EINVAL;
  970.  
  971.         if (IS_VALLEYVIEW(dev) &&
  972.             set->flags & I915_SET_COLORKEY_DESTINATION)
  973.                 return -EINVAL;
  974.  
  975.         plane = drm_plane_find(dev, set->plane_id);
  976.         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
  977.                 return -ENOENT;
  978.  
  979.         drm_modeset_acquire_init(&ctx, 0);
  980.  
  981.         state = drm_atomic_state_alloc(plane->dev);
  982.         if (!state) {
  983.                 ret = -ENOMEM;
  984.                 goto out;
  985.         }
  986.         state->acquire_ctx = &ctx;
  987.  
  988.         while (1) {
  989.                 plane_state = drm_atomic_get_plane_state(state, plane);
  990.                 ret = PTR_ERR_OR_ZERO(plane_state);
  991.                 if (!ret) {
  992.                         to_intel_plane_state(plane_state)->ckey = *set;
  993.                         ret = drm_atomic_commit(state);
  994.                 }
  995.  
  996.                 if (ret != -EDEADLK)
  997.                         break;
  998.  
  999.                 drm_atomic_state_clear(state);
  1000.                 drm_modeset_backoff(&ctx);
  1001.         }
  1002.  
  1003.         if (ret)
  1004.                 drm_atomic_state_free(state);
  1005.  
  1006. out:
  1007.         drm_modeset_drop_locks(&ctx);
  1008.         drm_modeset_acquire_fini(&ctx);
  1009.         return ret;
  1010. }
  1011.  
  1012. static const uint32_t ilk_plane_formats[] = {
  1013.         DRM_FORMAT_XRGB8888,
  1014.         DRM_FORMAT_YUYV,
  1015.         DRM_FORMAT_YVYU,
  1016.         DRM_FORMAT_UYVY,
  1017.         DRM_FORMAT_VYUY,
  1018. };
  1019.  
  1020. static const uint32_t snb_plane_formats[] = {
  1021.         DRM_FORMAT_XBGR8888,
  1022.         DRM_FORMAT_XRGB8888,
  1023.         DRM_FORMAT_YUYV,
  1024.         DRM_FORMAT_YVYU,
  1025.         DRM_FORMAT_UYVY,
  1026.         DRM_FORMAT_VYUY,
  1027. };
  1028.  
  1029. static const uint32_t vlv_plane_formats[] = {
  1030.         DRM_FORMAT_RGB565,
  1031.         DRM_FORMAT_ABGR8888,
  1032.         DRM_FORMAT_ARGB8888,
  1033.         DRM_FORMAT_XBGR8888,
  1034.         DRM_FORMAT_XRGB8888,
  1035.         DRM_FORMAT_XBGR2101010,
  1036.         DRM_FORMAT_ABGR2101010,
  1037.         DRM_FORMAT_YUYV,
  1038.         DRM_FORMAT_YVYU,
  1039.         DRM_FORMAT_UYVY,
  1040.         DRM_FORMAT_VYUY,
  1041. };
  1042.  
  1043. static uint32_t skl_plane_formats[] = {
  1044.         DRM_FORMAT_RGB565,
  1045.         DRM_FORMAT_ABGR8888,
  1046.         DRM_FORMAT_ARGB8888,
  1047.         DRM_FORMAT_XBGR8888,
  1048.         DRM_FORMAT_XRGB8888,
  1049.         DRM_FORMAT_YUYV,
  1050.         DRM_FORMAT_YVYU,
  1051.         DRM_FORMAT_UYVY,
  1052.         DRM_FORMAT_VYUY,
  1053. };
  1054.  
  1055. int
  1056. intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
  1057. {
  1058.         struct intel_plane *intel_plane;
  1059.         struct intel_plane_state *state;
  1060.         unsigned long possible_crtcs;
  1061.         const uint32_t *plane_formats;
  1062.         int num_plane_formats;
  1063.         int ret;
  1064.  
  1065.         if (INTEL_INFO(dev)->gen < 5)
  1066.                 return -ENODEV;
  1067.  
  1068.         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
  1069.         if (!intel_plane)
  1070.                 return -ENOMEM;
  1071.  
  1072.         state = intel_create_plane_state(&intel_plane->base);
  1073.         if (!state) {
  1074.                 kfree(intel_plane);
  1075.                 return -ENOMEM;
  1076.         }
  1077.         intel_plane->base.state = &state->base;
  1078.  
  1079.         switch (INTEL_INFO(dev)->gen) {
  1080.         case 5:
  1081.         case 6:
  1082.                 intel_plane->can_scale = true;
  1083.                 intel_plane->max_downscale = 16;
  1084.                 intel_plane->update_plane = ilk_update_plane;
  1085.                 intel_plane->disable_plane = ilk_disable_plane;
  1086.  
  1087.                 if (IS_GEN6(dev)) {
  1088.                         plane_formats = snb_plane_formats;
  1089.                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
  1090.                 } else {
  1091.                         plane_formats = ilk_plane_formats;
  1092.                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
  1093.                 }
  1094.                 break;
  1095.  
  1096.         case 7:
  1097.         case 8:
  1098.                 if (IS_IVYBRIDGE(dev)) {
  1099.                         intel_plane->can_scale = true;
  1100.                         intel_plane->max_downscale = 2;
  1101.                 } else {
  1102.                         intel_plane->can_scale = false;
  1103.                         intel_plane->max_downscale = 1;
  1104.                 }
  1105.  
  1106.                 if (IS_VALLEYVIEW(dev)) {
  1107.                         intel_plane->update_plane = vlv_update_plane;
  1108.                         intel_plane->disable_plane = vlv_disable_plane;
  1109.  
  1110.                         plane_formats = vlv_plane_formats;
  1111.                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
  1112.                 } else {
  1113.                         intel_plane->update_plane = ivb_update_plane;
  1114.                         intel_plane->disable_plane = ivb_disable_plane;
  1115.  
  1116.                         plane_formats = snb_plane_formats;
  1117.                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
  1118.                 }
  1119.                 break;
  1120.         case 9:
  1121.                 intel_plane->can_scale = true;
  1122.                 intel_plane->update_plane = skl_update_plane;
  1123.                 intel_plane->disable_plane = skl_disable_plane;
  1124.                 state->scaler_id = -1;
  1125.  
  1126.                 plane_formats = skl_plane_formats;
  1127.                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
  1128.                 break;
  1129.         default:
  1130.                 kfree(intel_plane);
  1131.                 return -ENODEV;
  1132.         }
  1133.  
  1134.         intel_plane->pipe = pipe;
  1135.         intel_plane->plane = plane;
  1136.         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
  1137.         intel_plane->check_plane = intel_check_sprite_plane;
  1138.         intel_plane->commit_plane = intel_commit_sprite_plane;
  1139.         possible_crtcs = (1 << pipe);
  1140.         ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
  1141.                                        &intel_plane_funcs,
  1142.                                        plane_formats, num_plane_formats,
  1143.                                        DRM_PLANE_TYPE_OVERLAY);
  1144.         if (ret) {
  1145.                 kfree(intel_plane);
  1146.                 goto out;
  1147.         }
  1148.  
  1149.         intel_create_rotation_property(dev, intel_plane);
  1150.  
  1151.         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
  1152.  
  1153. out:
  1154.         return ret;
  1155. }
  1156.