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  1. /*
  2.  * Copyright © 2012 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25.  *
  26.  */
  27.  
  28. #define iowrite32(v, addr)      writel((v), (addr))
  29. #define ioread32(addr)          readl(addr)
  30.  
  31. //#include <linux/cpufreq.h>
  32. #include "i915_drv.h"
  33. #include "intel_drv.h"
  34. #include <linux/math64.h>
  35. //#include "../../../platform/x86/intel_ips.h"
  36. #include <linux/module.h>
  37.  
  38. #define FORCEWAKE_ACK_TIMEOUT_MS 2
  39.  
  40. #define assert_spin_locked(x)
  41.  
  42. void getrawmonotonic(struct timespec *ts);
  43. void set_normalized_timespec(struct timespec *ts, time_t sec, long nsec);
  44.  
  45. static inline struct timespec timespec_sub(struct timespec lhs,
  46.                                                 struct timespec rhs)
  47. {
  48.     struct timespec ts_delta;
  49.     set_normalized_timespec(&ts_delta, lhs.tv_sec - rhs.tv_sec,
  50.                                 lhs.tv_nsec - rhs.tv_nsec);
  51.     return ts_delta;
  52. }
  53.  
  54.  
  55. /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  56.  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  57.  * during in-memory transfers and, therefore, reduce the power packet.
  58.  *
  59.  * The benefits of FBC are mostly visible with solid backgrounds and
  60.  * variation-less patterns.
  61.  *
  62.  * FBC-related functionality can be enabled by the means of the
  63.  * i915.i915_enable_fbc parameter
  64.  */
  65.  
  66. static void i8xx_disable_fbc(struct drm_device *dev)
  67. {
  68.         struct drm_i915_private *dev_priv = dev->dev_private;
  69.         u32 fbc_ctl;
  70.  
  71.         /* Disable compression */
  72.         fbc_ctl = I915_READ(FBC_CONTROL);
  73.         if ((fbc_ctl & FBC_CTL_EN) == 0)
  74.                 return;
  75.  
  76.         fbc_ctl &= ~FBC_CTL_EN;
  77.         I915_WRITE(FBC_CONTROL, fbc_ctl);
  78.  
  79.         /* Wait for compressing bit to clear */
  80.         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  81.                 DRM_DEBUG_KMS("FBC idle timed out\n");
  82.                 return;
  83.         }
  84.  
  85.         DRM_DEBUG_KMS("disabled FBC\n");
  86. }
  87.  
  88. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  89. {
  90.         struct drm_device *dev = crtc->dev;
  91.         struct drm_i915_private *dev_priv = dev->dev_private;
  92.         struct drm_framebuffer *fb = crtc->fb;
  93.         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  94.         struct drm_i915_gem_object *obj = intel_fb->obj;
  95.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  96.         int cfb_pitch;
  97.         int plane, i;
  98.         u32 fbc_ctl, fbc_ctl2;
  99.  
  100.         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  101.         if (fb->pitches[0] < cfb_pitch)
  102.                 cfb_pitch = fb->pitches[0];
  103.  
  104.         /* FBC_CTL wants 64B units */
  105.         cfb_pitch = (cfb_pitch / 64) - 1;
  106.         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  107.  
  108.         /* Clear old tags */
  109.         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  110.                 I915_WRITE(FBC_TAG + (i * 4), 0);
  111.  
  112.         /* Set it up... */
  113.         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  114.         fbc_ctl2 |= plane;
  115.         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  116.         I915_WRITE(FBC_FENCE_OFF, crtc->y);
  117.  
  118.         /* enable it... */
  119.         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  120.         if (IS_I945GM(dev))
  121.                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  122.         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  123.         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  124.         fbc_ctl |= obj->fence_reg;
  125.         I915_WRITE(FBC_CONTROL, fbc_ctl);
  126.  
  127.         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
  128.                       cfb_pitch, crtc->y, intel_crtc->plane);
  129. }
  130.  
  131. static bool i8xx_fbc_enabled(struct drm_device *dev)
  132. {
  133.         struct drm_i915_private *dev_priv = dev->dev_private;
  134.  
  135.         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  136. }
  137.  
  138. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  139. {
  140.         struct drm_device *dev = crtc->dev;
  141.         struct drm_i915_private *dev_priv = dev->dev_private;
  142.         struct drm_framebuffer *fb = crtc->fb;
  143.         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  144.         struct drm_i915_gem_object *obj = intel_fb->obj;
  145.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  146.         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  147.         unsigned long stall_watermark = 200;
  148.         u32 dpfc_ctl;
  149.  
  150.         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  151.         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
  152.         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  153.  
  154.         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  155.                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  156.                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  157.         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  158.  
  159.         /* enable it... */
  160.         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  161.  
  162.         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  163. }
  164.  
  165. static void g4x_disable_fbc(struct drm_device *dev)
  166. {
  167.         struct drm_i915_private *dev_priv = dev->dev_private;
  168.         u32 dpfc_ctl;
  169.  
  170.         /* Disable compression */
  171.         dpfc_ctl = I915_READ(DPFC_CONTROL);
  172.         if (dpfc_ctl & DPFC_CTL_EN) {
  173.                 dpfc_ctl &= ~DPFC_CTL_EN;
  174.                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  175.  
  176.                 DRM_DEBUG_KMS("disabled FBC\n");
  177.         }
  178. }
  179.  
  180. static bool g4x_fbc_enabled(struct drm_device *dev)
  181. {
  182.         struct drm_i915_private *dev_priv = dev->dev_private;
  183.  
  184.         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  185. }
  186.  
  187. static void sandybridge_blit_fbc_update(struct drm_device *dev)
  188. {
  189.         struct drm_i915_private *dev_priv = dev->dev_private;
  190.         u32 blt_ecoskpd;
  191.  
  192.         /* Make sure blitter notifies FBC of writes */
  193.         gen6_gt_force_wake_get(dev_priv);
  194.         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
  195.         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
  196.                 GEN6_BLITTER_LOCK_SHIFT;
  197.         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  198.         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
  199.         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  200.         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
  201.                          GEN6_BLITTER_LOCK_SHIFT);
  202.         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  203.         POSTING_READ(GEN6_BLITTER_ECOSKPD);
  204.         gen6_gt_force_wake_put(dev_priv);
  205. }
  206.  
  207. static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  208. {
  209.         struct drm_device *dev = crtc->dev;
  210.         struct drm_i915_private *dev_priv = dev->dev_private;
  211.         struct drm_framebuffer *fb = crtc->fb;
  212.         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  213.         struct drm_i915_gem_object *obj = intel_fb->obj;
  214.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  215.         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  216.         unsigned long stall_watermark = 200;
  217.         u32 dpfc_ctl;
  218.  
  219.         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  220.         dpfc_ctl &= DPFC_RESERVED;
  221.         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
  222.         /* Set persistent mode for front-buffer rendering, ala X. */
  223.         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
  224.         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
  225.         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
  226.  
  227.         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  228.                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  229.                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  230.         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
  231.         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
  232.         /* enable it... */
  233.         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
  234.  
  235.         if (IS_GEN6(dev)) {
  236.                 I915_WRITE(SNB_DPFC_CTL_SA,
  237.                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
  238.                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  239.                 sandybridge_blit_fbc_update(dev);
  240.         }
  241.  
  242.         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  243. }
  244.  
  245. static void ironlake_disable_fbc(struct drm_device *dev)
  246. {
  247.         struct drm_i915_private *dev_priv = dev->dev_private;
  248.         u32 dpfc_ctl;
  249.  
  250.         /* Disable compression */
  251.         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  252.         if (dpfc_ctl & DPFC_CTL_EN) {
  253.                 dpfc_ctl &= ~DPFC_CTL_EN;
  254.                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  255.  
  256.                 DRM_DEBUG_KMS("disabled FBC\n");
  257.         }
  258. }
  259.  
  260. static bool ironlake_fbc_enabled(struct drm_device *dev)
  261. {
  262.         struct drm_i915_private *dev_priv = dev->dev_private;
  263.  
  264.         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  265. }
  266.  
  267. bool intel_fbc_enabled(struct drm_device *dev)
  268. {
  269.         struct drm_i915_private *dev_priv = dev->dev_private;
  270.  
  271.         if (!dev_priv->display.fbc_enabled)
  272.                 return false;
  273.  
  274.         return dev_priv->display.fbc_enabled(dev);
  275. }
  276.  
  277. #if 0
  278. static void intel_fbc_work_fn(struct work_struct *__work)
  279. {
  280.         struct intel_fbc_work *work =
  281.                 container_of(to_delayed_work(__work),
  282.                              struct intel_fbc_work, work);
  283.         struct drm_device *dev = work->crtc->dev;
  284.         struct drm_i915_private *dev_priv = dev->dev_private;
  285.  
  286.         mutex_lock(&dev->struct_mutex);
  287.         if (work == dev_priv->fbc_work) {
  288.                 /* Double check that we haven't switched fb without cancelling
  289.                  * the prior work.
  290.                  */
  291.                 if (work->crtc->fb == work->fb) {
  292.                         dev_priv->display.enable_fbc(work->crtc,
  293.                                                      work->interval);
  294.  
  295.                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
  296.                         dev_priv->cfb_fb = work->crtc->fb->base.id;
  297.                         dev_priv->cfb_y = work->crtc->y;
  298.                 }
  299.  
  300.                 dev_priv->fbc_work = NULL;
  301.         }
  302.         mutex_unlock(&dev->struct_mutex);
  303.  
  304.         kfree(work);
  305. }
  306.  
  307. static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
  308. {
  309.         if (dev_priv->fbc_work == NULL)
  310.                 return;
  311.  
  312.         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
  313.  
  314.         /* Synchronisation is provided by struct_mutex and checking of
  315.          * dev_priv->fbc_work, so we can perform the cancellation
  316.          * entirely asynchronously.
  317.          */
  318.         if (cancel_delayed_work(&dev_priv->fbc_work->work))
  319.                 /* tasklet was killed before being run, clean up */
  320.                 kfree(dev_priv->fbc_work);
  321.  
  322.         /* Mark the work as no longer wanted so that if it does
  323.          * wake-up (because the work was already running and waiting
  324.          * for our mutex), it will discover that is no longer
  325.          * necessary to run.
  326.          */
  327.         dev_priv->fbc_work = NULL;
  328. }
  329. #endif
  330.  
  331. void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  332. {
  333.         struct intel_fbc_work *work;
  334.         struct drm_device *dev = crtc->dev;
  335.         struct drm_i915_private *dev_priv = dev->dev_private;
  336.  
  337. //   if (!dev_priv->display.enable_fbc)
  338.                 return;
  339. #if 0
  340.         intel_cancel_fbc_work(dev_priv);
  341.  
  342.         work = kzalloc(sizeof *work, GFP_KERNEL);
  343.         if (work == NULL) {
  344.                 dev_priv->display.enable_fbc(crtc, interval);
  345.                 return;
  346.         }
  347.  
  348.         work->crtc = crtc;
  349.         work->fb = crtc->fb;
  350.         work->interval = interval;
  351.         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
  352.  
  353.         dev_priv->fbc_work = work;
  354.  
  355.         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
  356.  
  357.         /* Delay the actual enabling to let pageflipping cease and the
  358.          * display to settle before starting the compression. Note that
  359.          * this delay also serves a second purpose: it allows for a
  360.          * vblank to pass after disabling the FBC before we attempt
  361.          * to modify the control registers.
  362.          *
  363.          * A more complicated solution would involve tracking vblanks
  364.          * following the termination of the page-flipping sequence
  365.          * and indeed performing the enable as a co-routine and not
  366.          * waiting synchronously upon the vblank.
  367.          */
  368.         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
  369. #endif
  370.  
  371. }
  372.  
  373. void intel_disable_fbc(struct drm_device *dev)
  374. {
  375.         struct drm_i915_private *dev_priv = dev->dev_private;
  376.  
  377. //   intel_cancel_fbc_work(dev_priv);
  378.  
  379. //   if (!dev_priv->display.disable_fbc)
  380. //       return;
  381.  
  382. //   dev_priv->display.disable_fbc(dev);
  383.         dev_priv->cfb_plane = -1;
  384. }
  385.  
  386. /**
  387.  * intel_update_fbc - enable/disable FBC as needed
  388.  * @dev: the drm_device
  389.  *
  390.  * Set up the framebuffer compression hardware at mode set time.  We
  391.  * enable it if possible:
  392.  *   - plane A only (on pre-965)
  393.  *   - no pixel mulitply/line duplication
  394.  *   - no alpha buffer discard
  395.  *   - no dual wide
  396.  *   - framebuffer <= 2048 in width, 1536 in height
  397.  *
  398.  * We can't assume that any compression will take place (worst case),
  399.  * so the compressed buffer has to be the same size as the uncompressed
  400.  * one.  It also must reside (along with the line length buffer) in
  401.  * stolen memory.
  402.  *
  403.  * We need to enable/disable FBC on a global basis.
  404.  */
  405. void intel_update_fbc(struct drm_device *dev)
  406. {
  407.         struct drm_i915_private *dev_priv = dev->dev_private;
  408.         struct drm_crtc *crtc = NULL, *tmp_crtc;
  409.         struct intel_crtc *intel_crtc;
  410.         struct drm_framebuffer *fb;
  411.         struct intel_framebuffer *intel_fb;
  412.         struct drm_i915_gem_object *obj;
  413.         int enable_fbc;
  414.  
  415.         if (!i915_powersave)
  416.                 return;
  417.  
  418.         if (!I915_HAS_FBC(dev))
  419.                 return;
  420.  
  421.         /*
  422.          * If FBC is already on, we just have to verify that we can
  423.          * keep it that way...
  424.          * Need to disable if:
  425.          *   - more than one pipe is active
  426.          *   - changing FBC params (stride, fence, mode)
  427.          *   - new fb is too large to fit in compressed buffer
  428.          *   - going to an unsupported config (interlace, pixel multiply, etc.)
  429.          */
  430.         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
  431.                 if (tmp_crtc->enabled &&
  432.                     !to_intel_crtc(tmp_crtc)->primary_disabled &&
  433.                     tmp_crtc->fb) {
  434.                         if (crtc) {
  435.                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
  436.                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
  437.                                 goto out_disable;
  438.                         }
  439.                         crtc = tmp_crtc;
  440.                 }
  441.         }
  442.  
  443.         if (!crtc || crtc->fb == NULL) {
  444.                 DRM_DEBUG_KMS("no output, disabling\n");
  445.                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
  446.                 goto out_disable;
  447.         }
  448.  
  449.         intel_crtc = to_intel_crtc(crtc);
  450.         fb = crtc->fb;
  451.         intel_fb = to_intel_framebuffer(fb);
  452.         obj = intel_fb->obj;
  453.  
  454.         enable_fbc = i915_enable_fbc;
  455.         if (enable_fbc < 0) {
  456.                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
  457.                 enable_fbc = 1;
  458.                 if (INTEL_INFO(dev)->gen <= 6)
  459.                         enable_fbc = 0;
  460.         }
  461.         if (!enable_fbc) {
  462.                 DRM_DEBUG_KMS("fbc disabled per module param\n");
  463.                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
  464.                 goto out_disable;
  465.         }
  466.         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
  467.                 DRM_DEBUG_KMS("framebuffer too large, disabling "
  468.                               "compression\n");
  469.                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  470.                 goto out_disable;
  471.         }
  472.         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
  473.             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
  474.                 DRM_DEBUG_KMS("mode incompatible with compression, "
  475.                               "disabling\n");
  476.                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  477.                 goto out_disable;
  478.         }
  479.         if ((crtc->mode.hdisplay > 2048) ||
  480.             (crtc->mode.vdisplay > 1536)) {
  481.                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  482.                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  483.                 goto out_disable;
  484.         }
  485.         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
  486.                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  487.                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  488.                 goto out_disable;
  489.         }
  490.  
  491.         /* The use of a CPU fence is mandatory in order to detect writes
  492.          * by the CPU to the scanout and trigger updates to the FBC.
  493.          */
  494.         if (obj->tiling_mode != I915_TILING_X ||
  495.             obj->fence_reg == I915_FENCE_REG_NONE) {
  496.                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
  497.                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
  498.                 goto out_disable;
  499.         }
  500.  
  501.         /* If the kernel debugger is active, always disable compression */
  502.         if (in_dbg_master())
  503.                 goto out_disable;
  504.  
  505.         /* If the scanout has not changed, don't modify the FBC settings.
  506.          * Note that we make the fundamental assumption that the fb->obj
  507.          * cannot be unpinned (and have its GTT offset and fence revoked)
  508.          * without first being decoupled from the scanout and FBC disabled.
  509.          */
  510.         if (dev_priv->cfb_plane == intel_crtc->plane &&
  511.             dev_priv->cfb_fb == fb->base.id &&
  512.             dev_priv->cfb_y == crtc->y)
  513.                 return;
  514.  
  515.         if (intel_fbc_enabled(dev)) {
  516.                 /* We update FBC along two paths, after changing fb/crtc
  517.                  * configuration (modeswitching) and after page-flipping
  518.                  * finishes. For the latter, we know that not only did
  519.                  * we disable the FBC at the start of the page-flip
  520.                  * sequence, but also more than one vblank has passed.
  521.                  *
  522.                  * For the former case of modeswitching, it is possible
  523.                  * to switch between two FBC valid configurations
  524.                  * instantaneously so we do need to disable the FBC
  525.                  * before we can modify its control registers. We also
  526.                  * have to wait for the next vblank for that to take
  527.                  * effect. However, since we delay enabling FBC we can
  528.                  * assume that a vblank has passed since disabling and
  529.                  * that we can safely alter the registers in the deferred
  530.                  * callback.
  531.                  *
  532.                  * In the scenario that we go from a valid to invalid
  533.                  * and then back to valid FBC configuration we have
  534.                  * no strict enforcement that a vblank occurred since
  535.                  * disabling the FBC. However, along all current pipe
  536.                  * disabling paths we do need to wait for a vblank at
  537.                  * some point. And we wait before enabling FBC anyway.
  538.                  */
  539.                 DRM_DEBUG_KMS("disabling active FBC for update\n");
  540.                 intel_disable_fbc(dev);
  541.         }
  542.  
  543.         intel_enable_fbc(crtc, 500);
  544.         return;
  545.  
  546. out_disable:
  547.         /* Multiple disables should be harmless */
  548.         if (intel_fbc_enabled(dev)) {
  549.                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  550.                 intel_disable_fbc(dev);
  551.         }
  552. }
  553.  
  554. static void i915_pineview_get_mem_freq(struct drm_device *dev)
  555. {
  556.         drm_i915_private_t *dev_priv = dev->dev_private;
  557.         u32 tmp;
  558.  
  559.         tmp = I915_READ(CLKCFG);
  560.  
  561.         switch (tmp & CLKCFG_FSB_MASK) {
  562.         case CLKCFG_FSB_533:
  563.                 dev_priv->fsb_freq = 533; /* 133*4 */
  564.                 break;
  565.         case CLKCFG_FSB_800:
  566.                 dev_priv->fsb_freq = 800; /* 200*4 */
  567.                 break;
  568.         case CLKCFG_FSB_667:
  569.                 dev_priv->fsb_freq =  667; /* 167*4 */
  570.                 break;
  571.         case CLKCFG_FSB_400:
  572.                 dev_priv->fsb_freq = 400; /* 100*4 */
  573.                 break;
  574.         }
  575.  
  576.         switch (tmp & CLKCFG_MEM_MASK) {
  577.         case CLKCFG_MEM_533:
  578.                 dev_priv->mem_freq = 533;
  579.                 break;
  580.         case CLKCFG_MEM_667:
  581.                 dev_priv->mem_freq = 667;
  582.                 break;
  583.         case CLKCFG_MEM_800:
  584.                 dev_priv->mem_freq = 800;
  585.                 break;
  586.         }
  587.  
  588.         /* detect pineview DDR3 setting */
  589.         tmp = I915_READ(CSHRDDR3CTL);
  590.         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
  591. }
  592.  
  593. static void i915_ironlake_get_mem_freq(struct drm_device *dev)
  594. {
  595.         drm_i915_private_t *dev_priv = dev->dev_private;
  596.         u16 ddrpll, csipll;
  597.  
  598.         ddrpll = I915_READ16(DDRMPLL1);
  599.         csipll = I915_READ16(CSIPLL0);
  600.  
  601.         switch (ddrpll & 0xff) {
  602.         case 0xc:
  603.                 dev_priv->mem_freq = 800;
  604.                 break;
  605.         case 0x10:
  606.                 dev_priv->mem_freq = 1066;
  607.                 break;
  608.         case 0x14:
  609.                 dev_priv->mem_freq = 1333;
  610.                 break;
  611.         case 0x18:
  612.                 dev_priv->mem_freq = 1600;
  613.                 break;
  614.         default:
  615.                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
  616.                                  ddrpll & 0xff);
  617.                 dev_priv->mem_freq = 0;
  618.                 break;
  619.         }
  620.  
  621.         dev_priv->ips.r_t = dev_priv->mem_freq;
  622.  
  623.         switch (csipll & 0x3ff) {
  624.         case 0x00c:
  625.                 dev_priv->fsb_freq = 3200;
  626.                 break;
  627.         case 0x00e:
  628.                 dev_priv->fsb_freq = 3733;
  629.                 break;
  630.         case 0x010:
  631.                 dev_priv->fsb_freq = 4266;
  632.                 break;
  633.         case 0x012:
  634.                 dev_priv->fsb_freq = 4800;
  635.                 break;
  636.         case 0x014:
  637.                 dev_priv->fsb_freq = 5333;
  638.                 break;
  639.         case 0x016:
  640.                 dev_priv->fsb_freq = 5866;
  641.                 break;
  642.         case 0x018:
  643.                 dev_priv->fsb_freq = 6400;
  644.                 break;
  645.         default:
  646.                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
  647.                                  csipll & 0x3ff);
  648.                 dev_priv->fsb_freq = 0;
  649.                 break;
  650.         }
  651.  
  652.         if (dev_priv->fsb_freq == 3200) {
  653.                 dev_priv->ips.c_m = 0;
  654.         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
  655.                 dev_priv->ips.c_m = 1;
  656.         } else {
  657.                 dev_priv->ips.c_m = 2;
  658.         }
  659. }
  660.  
  661. static const struct cxsr_latency cxsr_latency_table[] = {
  662.         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
  663.         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
  664.         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
  665.         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
  666.         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
  667.  
  668.         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
  669.         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
  670.         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
  671.         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
  672.         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
  673.  
  674.         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
  675.         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
  676.         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
  677.         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
  678.         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
  679.  
  680.         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
  681.         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
  682.         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
  683.         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
  684.         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
  685.  
  686.         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
  687.         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
  688.         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
  689.         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
  690.         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
  691.  
  692.         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
  693.         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
  694.         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
  695.         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
  696.         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
  697. };
  698.  
  699. static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
  700.                                                          int is_ddr3,
  701.                                                          int fsb,
  702.                                                          int mem)
  703. {
  704.         const struct cxsr_latency *latency;
  705.         int i;
  706.  
  707.         if (fsb == 0 || mem == 0)
  708.                 return NULL;
  709.  
  710.         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  711.                 latency = &cxsr_latency_table[i];
  712.                 if (is_desktop == latency->is_desktop &&
  713.                     is_ddr3 == latency->is_ddr3 &&
  714.                     fsb == latency->fsb_freq && mem == latency->mem_freq)
  715.                         return latency;
  716.         }
  717.  
  718.         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  719.  
  720.         return NULL;
  721. }
  722.  
  723. static void pineview_disable_cxsr(struct drm_device *dev)
  724. {
  725.         struct drm_i915_private *dev_priv = dev->dev_private;
  726.  
  727.         /* deactivate cxsr */
  728.         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
  729. }
  730.  
  731. /*
  732.  * Latency for FIFO fetches is dependent on several factors:
  733.  *   - memory configuration (speed, channels)
  734.  *   - chipset
  735.  *   - current MCH state
  736.  * It can be fairly high in some situations, so here we assume a fairly
  737.  * pessimal value.  It's a tradeoff between extra memory fetches (if we
  738.  * set this value too high, the FIFO will fetch frequently to stay full)
  739.  * and power consumption (set it too low to save power and we might see
  740.  * FIFO underruns and display "flicker").
  741.  *
  742.  * A value of 5us seems to be a good balance; safe for very low end
  743.  * platforms but not overly aggressive on lower latency configs.
  744.  */
  745. static const int latency_ns = 5000;
  746.  
  747. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  748. {
  749.         struct drm_i915_private *dev_priv = dev->dev_private;
  750.         uint32_t dsparb = I915_READ(DSPARB);
  751.         int size;
  752.  
  753.         size = dsparb & 0x7f;
  754.         if (plane)
  755.                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  756.  
  757.         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  758.                       plane ? "B" : "A", size);
  759.  
  760.         return size;
  761. }
  762.  
  763. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  764. {
  765.         struct drm_i915_private *dev_priv = dev->dev_private;
  766.         uint32_t dsparb = I915_READ(DSPARB);
  767.         int size;
  768.  
  769.         size = dsparb & 0x1ff;
  770.         if (plane)
  771.                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  772.         size >>= 1; /* Convert to cachelines */
  773.  
  774.         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  775.                       plane ? "B" : "A", size);
  776.  
  777.         return size;
  778. }
  779.  
  780. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  781. {
  782.         struct drm_i915_private *dev_priv = dev->dev_private;
  783.         uint32_t dsparb = I915_READ(DSPARB);
  784.         int size;
  785.  
  786.         size = dsparb & 0x7f;
  787.         size >>= 2; /* Convert to cachelines */
  788.  
  789.         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  790.                       plane ? "B" : "A",
  791.                       size);
  792.  
  793.         return size;
  794. }
  795.  
  796. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  797. {
  798.         struct drm_i915_private *dev_priv = dev->dev_private;
  799.         uint32_t dsparb = I915_READ(DSPARB);
  800.         int size;
  801.  
  802.         size = dsparb & 0x7f;
  803.         size >>= 1; /* Convert to cachelines */
  804.  
  805.         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  806.                       plane ? "B" : "A", size);
  807.  
  808.         return size;
  809. }
  810.  
  811. /* Pineview has different values for various configs */
  812. static const struct intel_watermark_params pineview_display_wm = {
  813.         PINEVIEW_DISPLAY_FIFO,
  814.         PINEVIEW_MAX_WM,
  815.         PINEVIEW_DFT_WM,
  816.         PINEVIEW_GUARD_WM,
  817.         PINEVIEW_FIFO_LINE_SIZE
  818. };
  819. static const struct intel_watermark_params pineview_display_hplloff_wm = {
  820.         PINEVIEW_DISPLAY_FIFO,
  821.         PINEVIEW_MAX_WM,
  822.         PINEVIEW_DFT_HPLLOFF_WM,
  823.         PINEVIEW_GUARD_WM,
  824.         PINEVIEW_FIFO_LINE_SIZE
  825. };
  826. static const struct intel_watermark_params pineview_cursor_wm = {
  827.         PINEVIEW_CURSOR_FIFO,
  828.         PINEVIEW_CURSOR_MAX_WM,
  829.         PINEVIEW_CURSOR_DFT_WM,
  830.         PINEVIEW_CURSOR_GUARD_WM,
  831.         PINEVIEW_FIFO_LINE_SIZE,
  832. };
  833. static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
  834.         PINEVIEW_CURSOR_FIFO,
  835.         PINEVIEW_CURSOR_MAX_WM,
  836.         PINEVIEW_CURSOR_DFT_WM,
  837.         PINEVIEW_CURSOR_GUARD_WM,
  838.         PINEVIEW_FIFO_LINE_SIZE
  839. };
  840. static const struct intel_watermark_params g4x_wm_info = {
  841.         G4X_FIFO_SIZE,
  842.         G4X_MAX_WM,
  843.         G4X_MAX_WM,
  844.         2,
  845.         G4X_FIFO_LINE_SIZE,
  846. };
  847. static const struct intel_watermark_params g4x_cursor_wm_info = {
  848.         I965_CURSOR_FIFO,
  849.         I965_CURSOR_MAX_WM,
  850.         I965_CURSOR_DFT_WM,
  851.         2,
  852.         G4X_FIFO_LINE_SIZE,
  853. };
  854. static const struct intel_watermark_params valleyview_wm_info = {
  855.         VALLEYVIEW_FIFO_SIZE,
  856.         VALLEYVIEW_MAX_WM,
  857.         VALLEYVIEW_MAX_WM,
  858.         2,
  859.         G4X_FIFO_LINE_SIZE,
  860. };
  861. static const struct intel_watermark_params valleyview_cursor_wm_info = {
  862.         I965_CURSOR_FIFO,
  863.         VALLEYVIEW_CURSOR_MAX_WM,
  864.         I965_CURSOR_DFT_WM,
  865.         2,
  866.         G4X_FIFO_LINE_SIZE,
  867. };
  868. static const struct intel_watermark_params i965_cursor_wm_info = {
  869.         I965_CURSOR_FIFO,
  870.         I965_CURSOR_MAX_WM,
  871.         I965_CURSOR_DFT_WM,
  872.         2,
  873.         I915_FIFO_LINE_SIZE,
  874. };
  875. static const struct intel_watermark_params i945_wm_info = {
  876.         I945_FIFO_SIZE,
  877.         I915_MAX_WM,
  878.         1,
  879.         2,
  880.         I915_FIFO_LINE_SIZE
  881. };
  882. static const struct intel_watermark_params i915_wm_info = {
  883.         I915_FIFO_SIZE,
  884.         I915_MAX_WM,
  885.         1,
  886.         2,
  887.         I915_FIFO_LINE_SIZE
  888. };
  889. static const struct intel_watermark_params i855_wm_info = {
  890.         I855GM_FIFO_SIZE,
  891.         I915_MAX_WM,
  892.         1,
  893.         2,
  894.         I830_FIFO_LINE_SIZE
  895. };
  896. static const struct intel_watermark_params i830_wm_info = {
  897.         I830_FIFO_SIZE,
  898.         I915_MAX_WM,
  899.         1,
  900.         2,
  901.         I830_FIFO_LINE_SIZE
  902. };
  903.  
  904. static const struct intel_watermark_params ironlake_display_wm_info = {
  905.         ILK_DISPLAY_FIFO,
  906.         ILK_DISPLAY_MAXWM,
  907.         ILK_DISPLAY_DFTWM,
  908.         2,
  909.         ILK_FIFO_LINE_SIZE
  910. };
  911. static const struct intel_watermark_params ironlake_cursor_wm_info = {
  912.         ILK_CURSOR_FIFO,
  913.         ILK_CURSOR_MAXWM,
  914.         ILK_CURSOR_DFTWM,
  915.         2,
  916.         ILK_FIFO_LINE_SIZE
  917. };
  918. static const struct intel_watermark_params ironlake_display_srwm_info = {
  919.         ILK_DISPLAY_SR_FIFO,
  920.         ILK_DISPLAY_MAX_SRWM,
  921.         ILK_DISPLAY_DFT_SRWM,
  922.         2,
  923.         ILK_FIFO_LINE_SIZE
  924. };
  925. static const struct intel_watermark_params ironlake_cursor_srwm_info = {
  926.         ILK_CURSOR_SR_FIFO,
  927.         ILK_CURSOR_MAX_SRWM,
  928.         ILK_CURSOR_DFT_SRWM,
  929.         2,
  930.         ILK_FIFO_LINE_SIZE
  931. };
  932.  
  933. static const struct intel_watermark_params sandybridge_display_wm_info = {
  934.         SNB_DISPLAY_FIFO,
  935.         SNB_DISPLAY_MAXWM,
  936.         SNB_DISPLAY_DFTWM,
  937.         2,
  938.         SNB_FIFO_LINE_SIZE
  939. };
  940. static const struct intel_watermark_params sandybridge_cursor_wm_info = {
  941.         SNB_CURSOR_FIFO,
  942.         SNB_CURSOR_MAXWM,
  943.         SNB_CURSOR_DFTWM,
  944.         2,
  945.         SNB_FIFO_LINE_SIZE
  946. };
  947. static const struct intel_watermark_params sandybridge_display_srwm_info = {
  948.         SNB_DISPLAY_SR_FIFO,
  949.         SNB_DISPLAY_MAX_SRWM,
  950.         SNB_DISPLAY_DFT_SRWM,
  951.         2,
  952.         SNB_FIFO_LINE_SIZE
  953. };
  954. static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
  955.         SNB_CURSOR_SR_FIFO,
  956.         SNB_CURSOR_MAX_SRWM,
  957.         SNB_CURSOR_DFT_SRWM,
  958.         2,
  959.         SNB_FIFO_LINE_SIZE
  960. };
  961.  
  962.  
  963. /**
  964.  * intel_calculate_wm - calculate watermark level
  965.  * @clock_in_khz: pixel clock
  966.  * @wm: chip FIFO params
  967.  * @pixel_size: display pixel size
  968.  * @latency_ns: memory latency for the platform
  969.  *
  970.  * Calculate the watermark level (the level at which the display plane will
  971.  * start fetching from memory again).  Each chip has a different display
  972.  * FIFO size and allocation, so the caller needs to figure that out and pass
  973.  * in the correct intel_watermark_params structure.
  974.  *
  975.  * As the pixel clock runs, the FIFO will be drained at a rate that depends
  976.  * on the pixel size.  When it reaches the watermark level, it'll start
  977.  * fetching FIFO line sized based chunks from memory until the FIFO fills
  978.  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
  979.  * will occur, and a display engine hang could result.
  980.  */
  981. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  982.                                         const struct intel_watermark_params *wm,
  983.                                         int fifo_size,
  984.                                         int pixel_size,
  985.                                         unsigned long latency_ns)
  986. {
  987.         long entries_required, wm_size;
  988.  
  989.         /*
  990.          * Note: we need to make sure we don't overflow for various clock &
  991.          * latency values.
  992.          * clocks go from a few thousand to several hundred thousand.
  993.          * latency is usually a few thousand
  994.          */
  995.         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  996.                 1000;
  997.         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  998.  
  999.         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
  1000.  
  1001.         wm_size = fifo_size - (entries_required + wm->guard_size);
  1002.  
  1003.         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
  1004.  
  1005.         /* Don't promote wm_size to unsigned... */
  1006.         if (wm_size > (long)wm->max_wm)
  1007.                 wm_size = wm->max_wm;
  1008.         if (wm_size <= 0)
  1009.                 wm_size = wm->default_wm;
  1010.         return wm_size;
  1011. }
  1012.  
  1013. static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
  1014. {
  1015.         struct drm_crtc *crtc, *enabled = NULL;
  1016.  
  1017.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1018.                 if (crtc->enabled && crtc->fb) {
  1019.                         if (enabled)
  1020.                                 return NULL;
  1021.                         enabled = crtc;
  1022.                 }
  1023.         }
  1024.  
  1025.         return enabled;
  1026. }
  1027.  
  1028. static void pineview_update_wm(struct drm_device *dev)
  1029. {
  1030.         struct drm_i915_private *dev_priv = dev->dev_private;
  1031.         struct drm_crtc *crtc;
  1032.         const struct cxsr_latency *latency;
  1033.         u32 reg;
  1034.         unsigned long wm;
  1035.  
  1036.         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  1037.                                          dev_priv->fsb_freq, dev_priv->mem_freq);
  1038.         if (!latency) {
  1039.                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  1040.                 pineview_disable_cxsr(dev);
  1041.                 return;
  1042.         }
  1043.  
  1044.         crtc = single_enabled_crtc(dev);
  1045.         if (crtc) {
  1046.                 int clock = crtc->mode.clock;
  1047.                 int pixel_size = crtc->fb->bits_per_pixel / 8;
  1048.  
  1049.                 /* Display SR */
  1050.                 wm = intel_calculate_wm(clock, &pineview_display_wm,
  1051.                                         pineview_display_wm.fifo_size,
  1052.                                         pixel_size, latency->display_sr);
  1053.                 reg = I915_READ(DSPFW1);
  1054.                 reg &= ~DSPFW_SR_MASK;
  1055.                 reg |= wm << DSPFW_SR_SHIFT;
  1056.                 I915_WRITE(DSPFW1, reg);
  1057.                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  1058.  
  1059.                 /* cursor SR */
  1060.                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
  1061.                                         pineview_display_wm.fifo_size,
  1062.                                         pixel_size, latency->cursor_sr);
  1063.                 reg = I915_READ(DSPFW3);
  1064.                 reg &= ~DSPFW_CURSOR_SR_MASK;
  1065.                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  1066.                 I915_WRITE(DSPFW3, reg);
  1067.  
  1068.                 /* Display HPLL off SR */
  1069.                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
  1070.                                         pineview_display_hplloff_wm.fifo_size,
  1071.                                         pixel_size, latency->display_hpll_disable);
  1072.                 reg = I915_READ(DSPFW3);
  1073.                 reg &= ~DSPFW_HPLL_SR_MASK;
  1074.                 reg |= wm & DSPFW_HPLL_SR_MASK;
  1075.                 I915_WRITE(DSPFW3, reg);
  1076.  
  1077.                 /* cursor HPLL off SR */
  1078.                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
  1079.                                         pineview_display_hplloff_wm.fifo_size,
  1080.                                         pixel_size, latency->cursor_hpll_disable);
  1081.                 reg = I915_READ(DSPFW3);
  1082.                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
  1083.                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  1084.                 I915_WRITE(DSPFW3, reg);
  1085.                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  1086.  
  1087.                 /* activate cxsr */
  1088.                 I915_WRITE(DSPFW3,
  1089.                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
  1090.                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
  1091.         } else {
  1092.                 pineview_disable_cxsr(dev);
  1093.                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
  1094.         }
  1095. }
  1096.  
  1097. static bool g4x_compute_wm0(struct drm_device *dev,
  1098.                             int plane,
  1099.                             const struct intel_watermark_params *display,
  1100.                             int display_latency_ns,
  1101.                             const struct intel_watermark_params *cursor,
  1102.                             int cursor_latency_ns,
  1103.                             int *plane_wm,
  1104.                             int *cursor_wm)
  1105. {
  1106.         struct drm_crtc *crtc;
  1107.         int htotal, hdisplay, clock, pixel_size;
  1108.         int line_time_us, line_count;
  1109.         int entries, tlb_miss;
  1110.  
  1111.         crtc = intel_get_crtc_for_plane(dev, plane);
  1112.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1113.  
  1114.     if (crtc->fb == NULL || !crtc->enabled || !intel_crtc->active) {
  1115.                 *cursor_wm = cursor->guard_size;
  1116.                 *plane_wm = display->guard_size;
  1117.         return false;
  1118.         }
  1119.  
  1120.         htotal = crtc->mode.htotal;
  1121.         hdisplay = crtc->mode.hdisplay;
  1122.         clock = crtc->mode.clock;
  1123.         pixel_size = crtc->fb->bits_per_pixel / 8;
  1124.  
  1125.         /* Use the small buffer method to calculate plane watermark */
  1126.         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  1127.         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
  1128.         if (tlb_miss > 0)
  1129.                 entries += tlb_miss;
  1130.         entries = DIV_ROUND_UP(entries, display->cacheline_size);
  1131.         *plane_wm = entries + display->guard_size;
  1132.         if (*plane_wm > (int)display->max_wm)
  1133.                 *plane_wm = display->max_wm;
  1134.  
  1135.         /* Use the large buffer method to calculate cursor watermark */
  1136.         line_time_us = ((htotal * 1000) / clock);
  1137.         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
  1138.         entries = line_count * 64 * pixel_size;
  1139.         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
  1140.         if (tlb_miss > 0)
  1141.                 entries += tlb_miss;
  1142.         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1143.         *cursor_wm = entries + cursor->guard_size;
  1144.         if (*cursor_wm > (int)cursor->max_wm)
  1145.                 *cursor_wm = (int)cursor->max_wm;
  1146.  
  1147.         return true;
  1148. }
  1149.  
  1150. /*
  1151.  * Check the wm result.
  1152.  *
  1153.  * If any calculated watermark values is larger than the maximum value that
  1154.  * can be programmed into the associated watermark register, that watermark
  1155.  * must be disabled.
  1156.  */
  1157. static bool g4x_check_srwm(struct drm_device *dev,
  1158.                            int display_wm, int cursor_wm,
  1159.                            const struct intel_watermark_params *display,
  1160.                            const struct intel_watermark_params *cursor)
  1161. {
  1162.         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
  1163.                       display_wm, cursor_wm);
  1164.  
  1165.         if (display_wm > display->max_wm) {
  1166.                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
  1167.                               display_wm, display->max_wm);
  1168.                 return false;
  1169.         }
  1170.  
  1171.         if (cursor_wm > cursor->max_wm) {
  1172.                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
  1173.                               cursor_wm, cursor->max_wm);
  1174.                 return false;
  1175.         }
  1176.  
  1177.         if (!(display_wm || cursor_wm)) {
  1178.                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
  1179.                 return false;
  1180.         }
  1181.  
  1182.         return true;
  1183. }
  1184.  
  1185. static bool g4x_compute_srwm(struct drm_device *dev,
  1186.                              int plane,
  1187.                              int latency_ns,
  1188.                              const struct intel_watermark_params *display,
  1189.                              const struct intel_watermark_params *cursor,
  1190.                              int *display_wm, int *cursor_wm)
  1191. {
  1192.         struct drm_crtc *crtc;
  1193.         int hdisplay, htotal, pixel_size, clock;
  1194.         unsigned long line_time_us;
  1195.         int line_count, line_size;
  1196.         int small, large;
  1197.         int entries;
  1198.  
  1199.         if (!latency_ns) {
  1200.                 *display_wm = *cursor_wm = 0;
  1201.                 return false;
  1202.         }
  1203.  
  1204.         crtc = intel_get_crtc_for_plane(dev, plane);
  1205.         hdisplay = crtc->mode.hdisplay;
  1206.         htotal = crtc->mode.htotal;
  1207.         clock = crtc->mode.clock;
  1208.         pixel_size = crtc->fb->bits_per_pixel / 8;
  1209.  
  1210.         line_time_us = (htotal * 1000) / clock;
  1211.         line_count = (latency_ns / line_time_us + 1000) / 1000;
  1212.         line_size = hdisplay * pixel_size;
  1213.  
  1214.         /* Use the minimum of the small and large buffer method for primary */
  1215.         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1216.         large = line_count * line_size;
  1217.  
  1218.         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1219.         *display_wm = entries + display->guard_size;
  1220.  
  1221.         /* calculate the self-refresh watermark for display cursor */
  1222.         entries = line_count * pixel_size * 64;
  1223.         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1224.         *cursor_wm = entries + cursor->guard_size;
  1225.  
  1226.         return g4x_check_srwm(dev,
  1227.                               *display_wm, *cursor_wm,
  1228.                               display, cursor);
  1229. }
  1230.  
  1231. static bool vlv_compute_drain_latency(struct drm_device *dev,
  1232.                                      int plane,
  1233.                                      int *plane_prec_mult,
  1234.                                      int *plane_dl,
  1235.                                      int *cursor_prec_mult,
  1236.                                      int *cursor_dl)
  1237. {
  1238.         struct drm_crtc *crtc;
  1239.         int clock, pixel_size;
  1240.         int entries;
  1241.  
  1242.         crtc = intel_get_crtc_for_plane(dev, plane);
  1243.         if (crtc->fb == NULL || !crtc->enabled)
  1244.                 return false;
  1245.  
  1246.         clock = crtc->mode.clock;       /* VESA DOT Clock */
  1247.         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
  1248.  
  1249.         entries = (clock / 1000) * pixel_size;
  1250.         *plane_prec_mult = (entries > 256) ?
  1251.                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
  1252.         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
  1253.                                                      pixel_size);
  1254.  
  1255.         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
  1256.         *cursor_prec_mult = (entries > 256) ?
  1257.                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
  1258.         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
  1259.  
  1260.         return true;
  1261. }
  1262.  
  1263. /*
  1264.  * Update drain latency registers of memory arbiter
  1265.  *
  1266.  * Valleyview SoC has a new memory arbiter and needs drain latency registers
  1267.  * to be programmed. Each plane has a drain latency multiplier and a drain
  1268.  * latency value.
  1269.  */
  1270.  
  1271. static void vlv_update_drain_latency(struct drm_device *dev)
  1272. {
  1273.         struct drm_i915_private *dev_priv = dev->dev_private;
  1274.         int planea_prec, planea_dl, planeb_prec, planeb_dl;
  1275.         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
  1276.         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
  1277.                                                         either 16 or 32 */
  1278.  
  1279.         /* For plane A, Cursor A */
  1280.         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
  1281.                                       &cursor_prec_mult, &cursora_dl)) {
  1282.                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1283.                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
  1284.                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1285.                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
  1286.  
  1287.                 I915_WRITE(VLV_DDL1, cursora_prec |
  1288.                                 (cursora_dl << DDL_CURSORA_SHIFT) |
  1289.                                 planea_prec | planea_dl);
  1290.         }
  1291.  
  1292.         /* For plane B, Cursor B */
  1293.         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
  1294.                                       &cursor_prec_mult, &cursorb_dl)) {
  1295.                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1296.                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
  1297.                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1298.                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
  1299.  
  1300.                 I915_WRITE(VLV_DDL2, cursorb_prec |
  1301.                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
  1302.                                 planeb_prec | planeb_dl);
  1303.         }
  1304. }
  1305.  
  1306. #define single_plane_enabled(mask) is_power_of_2(mask)
  1307.  
  1308. static void valleyview_update_wm(struct drm_device *dev)
  1309. {
  1310.         static const int sr_latency_ns = 12000;
  1311.         struct drm_i915_private *dev_priv = dev->dev_private;
  1312.         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  1313.         int plane_sr, cursor_sr;
  1314.         unsigned int enabled = 0;
  1315.  
  1316.         vlv_update_drain_latency(dev);
  1317.  
  1318.         if (g4x_compute_wm0(dev, 0,
  1319.                             &valleyview_wm_info, latency_ns,
  1320.                             &valleyview_cursor_wm_info, latency_ns,
  1321.                             &planea_wm, &cursora_wm))
  1322.                 enabled |= 1;
  1323.  
  1324.         if (g4x_compute_wm0(dev, 1,
  1325.                             &valleyview_wm_info, latency_ns,
  1326.                             &valleyview_cursor_wm_info, latency_ns,
  1327.                             &planeb_wm, &cursorb_wm))
  1328.                 enabled |= 2;
  1329.  
  1330.         plane_sr = cursor_sr = 0;
  1331.         if (single_plane_enabled(enabled) &&
  1332.             g4x_compute_srwm(dev, ffs(enabled) - 1,
  1333.                              sr_latency_ns,
  1334.                              &valleyview_wm_info,
  1335.                              &valleyview_cursor_wm_info,
  1336.                              &plane_sr, &cursor_sr))
  1337.                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
  1338.         else
  1339.                 I915_WRITE(FW_BLC_SELF_VLV,
  1340.                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
  1341.  
  1342.         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  1343.                       planea_wm, cursora_wm,
  1344.                       planeb_wm, cursorb_wm,
  1345.                       plane_sr, cursor_sr);
  1346.  
  1347.         I915_WRITE(DSPFW1,
  1348.                    (plane_sr << DSPFW_SR_SHIFT) |
  1349.                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  1350.                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
  1351.                    planea_wm);
  1352.         I915_WRITE(DSPFW2,
  1353.                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  1354.                    (cursora_wm << DSPFW_CURSORA_SHIFT));
  1355.         I915_WRITE(DSPFW3,
  1356.                    (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
  1357. }
  1358.  
  1359. static void g4x_update_wm(struct drm_device *dev)
  1360. {
  1361.         static const int sr_latency_ns = 12000;
  1362.         struct drm_i915_private *dev_priv = dev->dev_private;
  1363.         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  1364.         int plane_sr, cursor_sr;
  1365.         unsigned int enabled = 0;
  1366.  
  1367.         if (g4x_compute_wm0(dev, 0,
  1368.                             &g4x_wm_info, latency_ns,
  1369.                             &g4x_cursor_wm_info, latency_ns,
  1370.                             &planea_wm, &cursora_wm))
  1371.                 enabled |= 1;
  1372.  
  1373.         if (g4x_compute_wm0(dev, 1,
  1374.                             &g4x_wm_info, latency_ns,
  1375.                             &g4x_cursor_wm_info, latency_ns,
  1376.                             &planeb_wm, &cursorb_wm))
  1377.                 enabled |= 2;
  1378.  
  1379.         plane_sr = cursor_sr = 0;
  1380.         if (single_plane_enabled(enabled) &&
  1381.             g4x_compute_srwm(dev, ffs(enabled) - 1,
  1382.                              sr_latency_ns,
  1383.                              &g4x_wm_info,
  1384.                              &g4x_cursor_wm_info,
  1385.                              &plane_sr, &cursor_sr))
  1386.                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  1387.         else
  1388.                 I915_WRITE(FW_BLC_SELF,
  1389.                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
  1390.  
  1391.         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  1392.                       planea_wm, cursora_wm,
  1393.                       planeb_wm, cursorb_wm,
  1394.                       plane_sr, cursor_sr);
  1395.  
  1396.         I915_WRITE(DSPFW1,
  1397.                    (plane_sr << DSPFW_SR_SHIFT) |
  1398.                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  1399.                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
  1400.                    planea_wm);
  1401.         I915_WRITE(DSPFW2,
  1402.                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  1403.                    (cursora_wm << DSPFW_CURSORA_SHIFT));
  1404.         /* HPLL off in SR has some issues on G4x... disable it */
  1405.         I915_WRITE(DSPFW3,
  1406.                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  1407.                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1408. }
  1409.  
  1410. static void i965_update_wm(struct drm_device *dev)
  1411. {
  1412.         struct drm_i915_private *dev_priv = dev->dev_private;
  1413.         struct drm_crtc *crtc;
  1414.         int srwm = 1;
  1415.         int cursor_sr = 16;
  1416.  
  1417.         /* Calc sr entries for one plane configs */
  1418.         crtc = single_enabled_crtc(dev);
  1419.         if (crtc) {
  1420.                 /* self-refresh has much higher latency */
  1421.                 static const int sr_latency_ns = 12000;
  1422.                 int clock = crtc->mode.clock;
  1423.                 int htotal = crtc->mode.htotal;
  1424.                 int hdisplay = crtc->mode.hdisplay;
  1425.                 int pixel_size = crtc->fb->bits_per_pixel / 8;
  1426.                 unsigned long line_time_us;
  1427.                 int entries;
  1428.  
  1429.                 line_time_us = ((htotal * 1000) / clock);
  1430.  
  1431.                 /* Use ns/us then divide to preserve precision */
  1432.                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1433.                         pixel_size * hdisplay;
  1434.                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
  1435.                 srwm = I965_FIFO_SIZE - entries;
  1436.                 if (srwm < 0)
  1437.                         srwm = 1;
  1438.                 srwm &= 0x1ff;
  1439.                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
  1440.                               entries, srwm);
  1441.  
  1442.                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1443.                         pixel_size * 64;
  1444.                 entries = DIV_ROUND_UP(entries,
  1445.                                           i965_cursor_wm_info.cacheline_size);
  1446.                 cursor_sr = i965_cursor_wm_info.fifo_size -
  1447.                         (entries + i965_cursor_wm_info.guard_size);
  1448.  
  1449.                 if (cursor_sr > i965_cursor_wm_info.max_wm)
  1450.                         cursor_sr = i965_cursor_wm_info.max_wm;
  1451.  
  1452.                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  1453.                               "cursor %d\n", srwm, cursor_sr);
  1454.  
  1455.                 if (IS_CRESTLINE(dev))
  1456.                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  1457.         } else {
  1458.                 /* Turn off self refresh if both pipes are enabled */
  1459.                 if (IS_CRESTLINE(dev))
  1460.                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  1461.                                    & ~FW_BLC_SELF_EN);
  1462.         }
  1463.  
  1464.         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  1465.                       srwm);
  1466.  
  1467.         /* 965 has limitations... */
  1468.         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
  1469.                    (8 << 16) | (8 << 8) | (8 << 0));
  1470.         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  1471.         /* update cursor SR watermark */
  1472.         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1473. }
  1474.  
  1475. static void i9xx_update_wm(struct drm_device *dev)
  1476. {
  1477.         struct drm_i915_private *dev_priv = dev->dev_private;
  1478.         const struct intel_watermark_params *wm_info;
  1479.         uint32_t fwater_lo;
  1480.         uint32_t fwater_hi;
  1481.         int cwm, srwm = 1;
  1482.         int fifo_size;
  1483.         int planea_wm, planeb_wm;
  1484.         struct drm_crtc *crtc, *enabled = NULL;
  1485.  
  1486.         if (IS_I945GM(dev))
  1487.                 wm_info = &i945_wm_info;
  1488.         else if (!IS_GEN2(dev))
  1489.                 wm_info = &i915_wm_info;
  1490.         else
  1491.                 wm_info = &i855_wm_info;
  1492.  
  1493.         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  1494.         crtc = intel_get_crtc_for_plane(dev, 0);
  1495.         if (crtc->enabled && crtc->fb) {
  1496.                 planea_wm = intel_calculate_wm(crtc->mode.clock,
  1497.                                                wm_info, fifo_size,
  1498.                                                crtc->fb->bits_per_pixel / 8,
  1499.                                                latency_ns);
  1500.                 enabled = crtc;
  1501.         } else
  1502.                 planea_wm = fifo_size - wm_info->guard_size;
  1503.  
  1504.         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  1505.         crtc = intel_get_crtc_for_plane(dev, 1);
  1506.         if (crtc->enabled && crtc->fb) {
  1507.                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
  1508.                                                wm_info, fifo_size,
  1509.                                                crtc->fb->bits_per_pixel / 8,
  1510.                                                latency_ns);
  1511.                 if (enabled == NULL)
  1512.                         enabled = crtc;
  1513.                 else
  1514.                         enabled = NULL;
  1515.         } else
  1516.                 planeb_wm = fifo_size - wm_info->guard_size;
  1517.  
  1518.         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  1519.  
  1520.         /*
  1521.          * Overlay gets an aggressive default since video jitter is bad.
  1522.          */
  1523.         cwm = 2;
  1524.  
  1525.         /* Play safe and disable self-refresh before adjusting watermarks. */
  1526.         if (IS_I945G(dev) || IS_I945GM(dev))
  1527.                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
  1528.         else if (IS_I915GM(dev))
  1529.                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  1530.  
  1531.         /* Calc sr entries for one plane configs */
  1532.         if (HAS_FW_BLC(dev) && enabled) {
  1533.                 /* self-refresh has much higher latency */
  1534.                 static const int sr_latency_ns = 6000;
  1535.                 int clock = enabled->mode.clock;
  1536.                 int htotal = enabled->mode.htotal;
  1537.                 int hdisplay = enabled->mode.hdisplay;
  1538.                 int pixel_size = enabled->fb->bits_per_pixel / 8;
  1539.                 unsigned long line_time_us;
  1540.                 int entries;
  1541.  
  1542.                 line_time_us = (htotal * 1000) / clock;
  1543.  
  1544.                 /* Use ns/us then divide to preserve precision */
  1545.                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1546.                         pixel_size * hdisplay;
  1547.                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
  1548.                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
  1549.                 srwm = wm_info->fifo_size - entries;
  1550.                 if (srwm < 0)
  1551.                         srwm = 1;
  1552.  
  1553.                 if (IS_I945G(dev) || IS_I945GM(dev))
  1554.                         I915_WRITE(FW_BLC_SELF,
  1555.                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  1556.                 else if (IS_I915GM(dev))
  1557.                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  1558.         }
  1559.  
  1560.         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  1561.                       planea_wm, planeb_wm, cwm, srwm);
  1562.  
  1563.         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  1564.         fwater_hi = (cwm & 0x1f);
  1565.  
  1566.         /* Set request length to 8 cachelines per fetch */
  1567.         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  1568.         fwater_hi = fwater_hi | (1 << 8);
  1569.  
  1570.         I915_WRITE(FW_BLC, fwater_lo);
  1571.         I915_WRITE(FW_BLC2, fwater_hi);
  1572.  
  1573.         if (HAS_FW_BLC(dev)) {
  1574.                 if (enabled) {
  1575.                         if (IS_I945G(dev) || IS_I945GM(dev))
  1576.                                 I915_WRITE(FW_BLC_SELF,
  1577.                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  1578.                         else if (IS_I915GM(dev))
  1579.                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  1580.                         DRM_DEBUG_KMS("memory self refresh enabled\n");
  1581.                 } else
  1582.                         DRM_DEBUG_KMS("memory self refresh disabled\n");
  1583.         }
  1584. }
  1585.  
  1586. static void i830_update_wm(struct drm_device *dev)
  1587. {
  1588.         struct drm_i915_private *dev_priv = dev->dev_private;
  1589.         struct drm_crtc *crtc;
  1590.         uint32_t fwater_lo;
  1591.         int planea_wm;
  1592.  
  1593.         crtc = single_enabled_crtc(dev);
  1594.         if (crtc == NULL)
  1595.                 return;
  1596.  
  1597.         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
  1598.                                        dev_priv->display.get_fifo_size(dev, 0),
  1599.                                        crtc->fb->bits_per_pixel / 8,
  1600.                                        latency_ns);
  1601.         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  1602.         fwater_lo |= (3<<8) | planea_wm;
  1603.  
  1604.         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  1605.  
  1606.         I915_WRITE(FW_BLC, fwater_lo);
  1607. }
  1608.  
  1609. #define ILK_LP0_PLANE_LATENCY           700
  1610. #define ILK_LP0_CURSOR_LATENCY          1300
  1611.  
  1612. /*
  1613.  * Check the wm result.
  1614.  *
  1615.  * If any calculated watermark values is larger than the maximum value that
  1616.  * can be programmed into the associated watermark register, that watermark
  1617.  * must be disabled.
  1618.  */
  1619. static bool ironlake_check_srwm(struct drm_device *dev, int level,
  1620.                                 int fbc_wm, int display_wm, int cursor_wm,
  1621.                                 const struct intel_watermark_params *display,
  1622.                                 const struct intel_watermark_params *cursor)
  1623. {
  1624.         struct drm_i915_private *dev_priv = dev->dev_private;
  1625.  
  1626.         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
  1627.                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
  1628.  
  1629.         if (fbc_wm > SNB_FBC_MAX_SRWM) {
  1630.                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
  1631.                               fbc_wm, SNB_FBC_MAX_SRWM, level);
  1632.  
  1633.                 /* fbc has it's own way to disable FBC WM */
  1634.                 I915_WRITE(DISP_ARB_CTL,
  1635.                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
  1636.                 return false;
  1637.         }
  1638.  
  1639.         if (display_wm > display->max_wm) {
  1640.                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
  1641.                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
  1642.                 return false;
  1643.         }
  1644.  
  1645.         if (cursor_wm > cursor->max_wm) {
  1646.                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
  1647.                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
  1648.                 return false;
  1649.         }
  1650.  
  1651.         if (!(fbc_wm || display_wm || cursor_wm)) {
  1652.                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
  1653.                 return false;
  1654.         }
  1655.  
  1656.         return true;
  1657. }
  1658.  
  1659. /*
  1660.  * Compute watermark values of WM[1-3],
  1661.  */
  1662. static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
  1663.                                   int latency_ns,
  1664.                                   const struct intel_watermark_params *display,
  1665.                                   const struct intel_watermark_params *cursor,
  1666.                                   int *fbc_wm, int *display_wm, int *cursor_wm)
  1667. {
  1668.         struct drm_crtc *crtc;
  1669.         unsigned long line_time_us;
  1670.         int hdisplay, htotal, pixel_size, clock;
  1671.         int line_count, line_size;
  1672.         int small, large;
  1673.         int entries;
  1674.  
  1675.         if (!latency_ns) {
  1676.                 *fbc_wm = *display_wm = *cursor_wm = 0;
  1677.                 return false;
  1678.         }
  1679.  
  1680.         crtc = intel_get_crtc_for_plane(dev, plane);
  1681.         hdisplay = crtc->mode.hdisplay;
  1682.         htotal = crtc->mode.htotal;
  1683.         clock = crtc->mode.clock;
  1684.         pixel_size = crtc->fb->bits_per_pixel / 8;
  1685.  
  1686.         line_time_us = (htotal * 1000) / clock;
  1687.         line_count = (latency_ns / line_time_us + 1000) / 1000;
  1688.         line_size = hdisplay * pixel_size;
  1689.  
  1690.         /* Use the minimum of the small and large buffer method for primary */
  1691.         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1692.         large = line_count * line_size;
  1693.  
  1694.         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1695.         *display_wm = entries + display->guard_size;
  1696.  
  1697.         /*
  1698.          * Spec says:
  1699.          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
  1700.          */
  1701.         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
  1702.  
  1703.         /* calculate the self-refresh watermark for display cursor */
  1704.         entries = line_count * pixel_size * 64;
  1705.         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1706.         *cursor_wm = entries + cursor->guard_size;
  1707.  
  1708.         return ironlake_check_srwm(dev, level,
  1709.                                    *fbc_wm, *display_wm, *cursor_wm,
  1710.                                    display, cursor);
  1711. }
  1712.  
  1713. static void ironlake_update_wm(struct drm_device *dev)
  1714. {
  1715.         struct drm_i915_private *dev_priv = dev->dev_private;
  1716.         int fbc_wm, plane_wm, cursor_wm;
  1717.         unsigned int enabled;
  1718.  
  1719.         enabled = 0;
  1720.         if (g4x_compute_wm0(dev, 0,
  1721.                             &ironlake_display_wm_info,
  1722.                             ILK_LP0_PLANE_LATENCY,
  1723.                             &ironlake_cursor_wm_info,
  1724.                             ILK_LP0_CURSOR_LATENCY,
  1725.                             &plane_wm, &cursor_wm)) {
  1726.                 I915_WRITE(WM0_PIPEA_ILK,
  1727.                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  1728.                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1729.                               " plane %d, " "cursor: %d\n",
  1730.                               plane_wm, cursor_wm);
  1731.                 enabled |= 1;
  1732.         }
  1733.  
  1734.         if (g4x_compute_wm0(dev, 1,
  1735.                             &ironlake_display_wm_info,
  1736.                             ILK_LP0_PLANE_LATENCY,
  1737.                             &ironlake_cursor_wm_info,
  1738.                             ILK_LP0_CURSOR_LATENCY,
  1739.                             &plane_wm, &cursor_wm)) {
  1740.                 I915_WRITE(WM0_PIPEB_ILK,
  1741.                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  1742.                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1743.                               " plane %d, cursor: %d\n",
  1744.                               plane_wm, cursor_wm);
  1745.                 enabled |= 2;
  1746.         }
  1747.  
  1748.         /*
  1749.          * Calculate and update the self-refresh watermark only when one
  1750.          * display plane is used.
  1751.          */
  1752.         I915_WRITE(WM3_LP_ILK, 0);
  1753.         I915_WRITE(WM2_LP_ILK, 0);
  1754.         I915_WRITE(WM1_LP_ILK, 0);
  1755.  
  1756.         if (!single_plane_enabled(enabled))
  1757.                 return;
  1758.         enabled = ffs(enabled) - 1;
  1759.  
  1760.         /* WM1 */
  1761.         if (!ironlake_compute_srwm(dev, 1, enabled,
  1762.                                    ILK_READ_WM1_LATENCY() * 500,
  1763.                                    &ironlake_display_srwm_info,
  1764.                                    &ironlake_cursor_srwm_info,
  1765.                                    &fbc_wm, &plane_wm, &cursor_wm))
  1766.                 return;
  1767.  
  1768.         I915_WRITE(WM1_LP_ILK,
  1769.                    WM1_LP_SR_EN |
  1770.                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1771.                    (fbc_wm << WM1_LP_FBC_SHIFT) |
  1772.                    (plane_wm << WM1_LP_SR_SHIFT) |
  1773.                    cursor_wm);
  1774.  
  1775.         /* WM2 */
  1776.         if (!ironlake_compute_srwm(dev, 2, enabled,
  1777.                                    ILK_READ_WM2_LATENCY() * 500,
  1778.                                    &ironlake_display_srwm_info,
  1779.                                    &ironlake_cursor_srwm_info,
  1780.                                    &fbc_wm, &plane_wm, &cursor_wm))
  1781.                 return;
  1782.  
  1783.         I915_WRITE(WM2_LP_ILK,
  1784.                    WM2_LP_EN |
  1785.                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1786.                    (fbc_wm << WM1_LP_FBC_SHIFT) |
  1787.                    (plane_wm << WM1_LP_SR_SHIFT) |
  1788.                    cursor_wm);
  1789.  
  1790.         /*
  1791.          * WM3 is unsupported on ILK, probably because we don't have latency
  1792.          * data for that power state
  1793.          */
  1794. }
  1795.  
  1796. static void sandybridge_update_wm(struct drm_device *dev)
  1797. {
  1798.         struct drm_i915_private *dev_priv = dev->dev_private;
  1799.         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
  1800.         u32 val;
  1801.         int fbc_wm, plane_wm, cursor_wm;
  1802.         unsigned int enabled;
  1803.  
  1804.         enabled = 0;
  1805.         if (g4x_compute_wm0(dev, 0,
  1806.                             &sandybridge_display_wm_info, latency,
  1807.                             &sandybridge_cursor_wm_info, latency,
  1808.                             &plane_wm, &cursor_wm)) {
  1809.                 val = I915_READ(WM0_PIPEA_ILK);
  1810.                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1811.                 I915_WRITE(WM0_PIPEA_ILK, val |
  1812.                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1813.                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1814.                               " plane %d, " "cursor: %d\n",
  1815.                               plane_wm, cursor_wm);
  1816.                 enabled |= 1;
  1817.         }
  1818.  
  1819.         if (g4x_compute_wm0(dev, 1,
  1820.                             &sandybridge_display_wm_info, latency,
  1821.                             &sandybridge_cursor_wm_info, latency,
  1822.                             &plane_wm, &cursor_wm)) {
  1823.                 val = I915_READ(WM0_PIPEB_ILK);
  1824.                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1825.                 I915_WRITE(WM0_PIPEB_ILK, val |
  1826.                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1827.                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1828.                               " plane %d, cursor: %d\n",
  1829.                               plane_wm, cursor_wm);
  1830.                 enabled |= 2;
  1831.         }
  1832.  
  1833.         if ((dev_priv->num_pipe == 3) &&
  1834.             g4x_compute_wm0(dev, 2,
  1835.                             &sandybridge_display_wm_info, latency,
  1836.                             &sandybridge_cursor_wm_info, latency,
  1837.                             &plane_wm, &cursor_wm)) {
  1838.                 val = I915_READ(WM0_PIPEC_IVB);
  1839.                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1840.                 I915_WRITE(WM0_PIPEC_IVB, val |
  1841.                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1842.                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
  1843.                               " plane %d, cursor: %d\n",
  1844.                               plane_wm, cursor_wm);
  1845.                 enabled |= 3;
  1846.         }
  1847.  
  1848.         /*
  1849.          * Calculate and update the self-refresh watermark only when one
  1850.          * display plane is used.
  1851.          *
  1852.          * SNB support 3 levels of watermark.
  1853.          *
  1854.          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
  1855.          * and disabled in the descending order
  1856.          *
  1857.          */
  1858.         I915_WRITE(WM3_LP_ILK, 0);
  1859.         I915_WRITE(WM2_LP_ILK, 0);
  1860.         I915_WRITE(WM1_LP_ILK, 0);
  1861.  
  1862.         if (!single_plane_enabled(enabled) ||
  1863.             dev_priv->sprite_scaling_enabled)
  1864.                 return;
  1865.         enabled = ffs(enabled) - 1;
  1866.  
  1867.         /* WM1 */
  1868.         if (!ironlake_compute_srwm(dev, 1, enabled,
  1869.                                    SNB_READ_WM1_LATENCY() * 500,
  1870.                                    &sandybridge_display_srwm_info,
  1871.                                    &sandybridge_cursor_srwm_info,
  1872.                                    &fbc_wm, &plane_wm, &cursor_wm))
  1873.                 return;
  1874.  
  1875.         I915_WRITE(WM1_LP_ILK,
  1876.                    WM1_LP_SR_EN |
  1877.                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1878.                    (fbc_wm << WM1_LP_FBC_SHIFT) |
  1879.                    (plane_wm << WM1_LP_SR_SHIFT) |
  1880.                    cursor_wm);
  1881.  
  1882.         /* WM2 */
  1883.         if (!ironlake_compute_srwm(dev, 2, enabled,
  1884.                                    SNB_READ_WM2_LATENCY() * 500,
  1885.                                    &sandybridge_display_srwm_info,
  1886.                                    &sandybridge_cursor_srwm_info,
  1887.                                    &fbc_wm, &plane_wm, &cursor_wm))
  1888.                 return;
  1889.  
  1890.         I915_WRITE(WM2_LP_ILK,
  1891.                    WM2_LP_EN |
  1892.                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1893.                    (fbc_wm << WM1_LP_FBC_SHIFT) |
  1894.                    (plane_wm << WM1_LP_SR_SHIFT) |
  1895.                    cursor_wm);
  1896.  
  1897.         /* WM3 */
  1898.         if (!ironlake_compute_srwm(dev, 3, enabled,
  1899.                                    SNB_READ_WM3_LATENCY() * 500,
  1900.                                    &sandybridge_display_srwm_info,
  1901.                                    &sandybridge_cursor_srwm_info,
  1902.                                    &fbc_wm, &plane_wm, &cursor_wm))
  1903.                 return;
  1904.  
  1905.         I915_WRITE(WM3_LP_ILK,
  1906.                    WM3_LP_EN |
  1907.                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1908.                    (fbc_wm << WM1_LP_FBC_SHIFT) |
  1909.                    (plane_wm << WM1_LP_SR_SHIFT) |
  1910.                    cursor_wm);
  1911. }
  1912.  
  1913. static void
  1914. haswell_update_linetime_wm(struct drm_device *dev, int pipe,
  1915.                                  struct drm_display_mode *mode)
  1916. {
  1917.         struct drm_i915_private *dev_priv = dev->dev_private;
  1918.         u32 temp;
  1919.  
  1920.         temp = I915_READ(PIPE_WM_LINETIME(pipe));
  1921.         temp &= ~PIPE_WM_LINETIME_MASK;
  1922.  
  1923.         /* The WM are computed with base on how long it takes to fill a single
  1924.          * row at the given clock rate, multiplied by 8.
  1925.          * */
  1926.         temp |= PIPE_WM_LINETIME_TIME(
  1927.                 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
  1928.  
  1929.         /* IPS watermarks are only used by pipe A, and are ignored by
  1930.          * pipes B and C.  They are calculated similarly to the common
  1931.          * linetime values, except that we are using CD clock frequency
  1932.          * in MHz instead of pixel rate for the division.
  1933.          *
  1934.          * This is a placeholder for the IPS watermark calculation code.
  1935.          */
  1936.  
  1937.         I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
  1938. }
  1939.  
  1940. static bool
  1941. sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
  1942.                               uint32_t sprite_width, int pixel_size,
  1943.                               const struct intel_watermark_params *display,
  1944.                               int display_latency_ns, int *sprite_wm)
  1945. {
  1946.         struct drm_crtc *crtc;
  1947.         int clock;
  1948.         int entries, tlb_miss;
  1949.  
  1950.         crtc = intel_get_crtc_for_plane(dev, plane);
  1951.         if (crtc->fb == NULL || !crtc->enabled) {
  1952.                 *sprite_wm = display->guard_size;
  1953.                 return false;
  1954.         }
  1955.  
  1956.         clock = crtc->mode.clock;
  1957.  
  1958.         /* Use the small buffer method to calculate the sprite watermark */
  1959.         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  1960.         tlb_miss = display->fifo_size*display->cacheline_size -
  1961.                 sprite_width * 8;
  1962.         if (tlb_miss > 0)
  1963.                 entries += tlb_miss;
  1964.         entries = DIV_ROUND_UP(entries, display->cacheline_size);
  1965.         *sprite_wm = entries + display->guard_size;
  1966.         if (*sprite_wm > (int)display->max_wm)
  1967.                 *sprite_wm = display->max_wm;
  1968.  
  1969.         return true;
  1970. }
  1971.  
  1972. static bool
  1973. sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
  1974.                                 uint32_t sprite_width, int pixel_size,
  1975.                                 const struct intel_watermark_params *display,
  1976.                                 int latency_ns, int *sprite_wm)
  1977. {
  1978.         struct drm_crtc *crtc;
  1979.         unsigned long line_time_us;
  1980.         int clock;
  1981.         int line_count, line_size;
  1982.         int small, large;
  1983.         int entries;
  1984.  
  1985.         if (!latency_ns) {
  1986.                 *sprite_wm = 0;
  1987.                 return false;
  1988.         }
  1989.  
  1990.         crtc = intel_get_crtc_for_plane(dev, plane);
  1991.         clock = crtc->mode.clock;
  1992.         if (!clock) {
  1993.                 *sprite_wm = 0;
  1994.                 return false;
  1995.         }
  1996.  
  1997.         line_time_us = (sprite_width * 1000) / clock;
  1998.         if (!line_time_us) {
  1999.                 *sprite_wm = 0;
  2000.                 return false;
  2001.         }
  2002.  
  2003.         line_count = (latency_ns / line_time_us + 1000) / 1000;
  2004.         line_size = sprite_width * pixel_size;
  2005.  
  2006.         /* Use the minimum of the small and large buffer method for primary */
  2007.         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  2008.         large = line_count * line_size;
  2009.  
  2010.         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  2011.         *sprite_wm = entries + display->guard_size;
  2012.  
  2013.         return *sprite_wm > 0x3ff ? false : true;
  2014. }
  2015.  
  2016. static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
  2017.                                          uint32_t sprite_width, int pixel_size)
  2018. {
  2019.         struct drm_i915_private *dev_priv = dev->dev_private;
  2020.         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
  2021.         u32 val;
  2022.         int sprite_wm, reg;
  2023.         int ret;
  2024.  
  2025.         switch (pipe) {
  2026.         case 0:
  2027.                 reg = WM0_PIPEA_ILK;
  2028.                 break;
  2029.         case 1:
  2030.                 reg = WM0_PIPEB_ILK;
  2031.                 break;
  2032.         case 2:
  2033.                 reg = WM0_PIPEC_IVB;
  2034.                 break;
  2035.         default:
  2036.                 return; /* bad pipe */
  2037.         }
  2038.  
  2039.         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
  2040.                                             &sandybridge_display_wm_info,
  2041.                                             latency, &sprite_wm);
  2042.         if (!ret) {
  2043.                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
  2044.                               pipe);
  2045.                 return;
  2046.         }
  2047.  
  2048.         val = I915_READ(reg);
  2049.         val &= ~WM0_PIPE_SPRITE_MASK;
  2050.         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
  2051.         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
  2052.  
  2053.  
  2054.         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  2055.                                               pixel_size,
  2056.                                               &sandybridge_display_srwm_info,
  2057.                                               SNB_READ_WM1_LATENCY() * 500,
  2058.                                               &sprite_wm);
  2059.         if (!ret) {
  2060.                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
  2061.                               pipe);
  2062.                 return;
  2063.         }
  2064.         I915_WRITE(WM1S_LP_ILK, sprite_wm);
  2065.  
  2066.         /* Only IVB has two more LP watermarks for sprite */
  2067.         if (!IS_IVYBRIDGE(dev))
  2068.                 return;
  2069.  
  2070.         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  2071.                                               pixel_size,
  2072.                                               &sandybridge_display_srwm_info,
  2073.                                               SNB_READ_WM2_LATENCY() * 500,
  2074.                                               &sprite_wm);
  2075.         if (!ret) {
  2076.                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
  2077.                               pipe);
  2078.                 return;
  2079.         }
  2080.         I915_WRITE(WM2S_LP_IVB, sprite_wm);
  2081.  
  2082.         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  2083.                                               pixel_size,
  2084.                                               &sandybridge_display_srwm_info,
  2085.                                               SNB_READ_WM3_LATENCY() * 500,
  2086.                                               &sprite_wm);
  2087.         if (!ret) {
  2088.                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
  2089.                               pipe);
  2090.                 return;
  2091.         }
  2092.         I915_WRITE(WM3S_LP_IVB, sprite_wm);
  2093. }
  2094.  
  2095. /**
  2096.  * intel_update_watermarks - update FIFO watermark values based on current modes
  2097.  *
  2098.  * Calculate watermark values for the various WM regs based on current mode
  2099.  * and plane configuration.
  2100.  *
  2101.  * There are several cases to deal with here:
  2102.  *   - normal (i.e. non-self-refresh)
  2103.  *   - self-refresh (SR) mode
  2104.  *   - lines are large relative to FIFO size (buffer can hold up to 2)
  2105.  *   - lines are small relative to FIFO size (buffer can hold more than 2
  2106.  *     lines), so need to account for TLB latency
  2107.  *
  2108.  *   The normal calculation is:
  2109.  *     watermark = dotclock * bytes per pixel * latency
  2110.  *   where latency is platform & configuration dependent (we assume pessimal
  2111.  *   values here).
  2112.  *
  2113.  *   The SR calculation is:
  2114.  *     watermark = (trunc(latency/line time)+1) * surface width *
  2115.  *       bytes per pixel
  2116.  *   where
  2117.  *     line time = htotal / dotclock
  2118.  *     surface width = hdisplay for normal plane and 64 for cursor
  2119.  *   and latency is assumed to be high, as above.
  2120.  *
  2121.  * The final value programmed to the register should always be rounded up,
  2122.  * and include an extra 2 entries to account for clock crossings.
  2123.  *
  2124.  * We don't use the sprite, so we can ignore that.  And on Crestline we have
  2125.  * to set the non-SR watermarks to 8.
  2126.  */
  2127. void intel_update_watermarks(struct drm_device *dev)
  2128. {
  2129.         struct drm_i915_private *dev_priv = dev->dev_private;
  2130.  
  2131.         if (dev_priv->display.update_wm)
  2132.                 dev_priv->display.update_wm(dev);
  2133. }
  2134.  
  2135. void intel_update_linetime_watermarks(struct drm_device *dev,
  2136.                 int pipe, struct drm_display_mode *mode)
  2137. {
  2138.         struct drm_i915_private *dev_priv = dev->dev_private;
  2139.  
  2140.         if (dev_priv->display.update_linetime_wm)
  2141.                 dev_priv->display.update_linetime_wm(dev, pipe, mode);
  2142. }
  2143.  
  2144. void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
  2145.                                     uint32_t sprite_width, int pixel_size)
  2146. {
  2147.         struct drm_i915_private *dev_priv = dev->dev_private;
  2148.  
  2149.         if (dev_priv->display.update_sprite_wm)
  2150.                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
  2151.                                                    pixel_size);
  2152. }
  2153.  
  2154. static struct drm_i915_gem_object *
  2155. intel_alloc_context_page(struct drm_device *dev)
  2156. {
  2157.         struct drm_i915_gem_object *ctx;
  2158.         int ret;
  2159.  
  2160.         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  2161.  
  2162.         ctx = i915_gem_alloc_object(dev, 4096);
  2163.         if (!ctx) {
  2164.                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  2165.                 return NULL;
  2166.         }
  2167.  
  2168.         ret = i915_gem_object_pin(ctx, 4096, true, false);
  2169.         if (ret) {
  2170.                 DRM_ERROR("failed to pin power context: %d\n", ret);
  2171.                 goto err_unref;
  2172.         }
  2173.  
  2174.         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
  2175.         if (ret) {
  2176.                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  2177.                 goto err_unpin;
  2178.         }
  2179.  
  2180.         return ctx;
  2181.  
  2182. err_unpin:
  2183.         i915_gem_object_unpin(ctx);
  2184. err_unref:
  2185.         drm_gem_object_unreference(&ctx->base);
  2186.         mutex_unlock(&dev->struct_mutex);
  2187.         return NULL;
  2188. }
  2189.  
  2190. /**
  2191.  * Lock protecting IPS related data structures
  2192.  */
  2193. DEFINE_SPINLOCK(mchdev_lock);
  2194.  
  2195. /* Global for IPS driver to get at the current i915 device. Protected by
  2196.  * mchdev_lock. */
  2197. static struct drm_i915_private *i915_mch_dev;
  2198.  
  2199. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  2200. {
  2201.         struct drm_i915_private *dev_priv = dev->dev_private;
  2202.         u16 rgvswctl;
  2203.  
  2204.         assert_spin_locked(&mchdev_lock);
  2205.  
  2206.         rgvswctl = I915_READ16(MEMSWCTL);
  2207.         if (rgvswctl & MEMCTL_CMD_STS) {
  2208.                 DRM_DEBUG("gpu busy, RCS change rejected\n");
  2209.                 return false; /* still busy with another command */
  2210.         }
  2211.  
  2212.         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  2213.                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  2214.         I915_WRITE16(MEMSWCTL, rgvswctl);
  2215.         POSTING_READ16(MEMSWCTL);
  2216.  
  2217.         rgvswctl |= MEMCTL_CMD_STS;
  2218.         I915_WRITE16(MEMSWCTL, rgvswctl);
  2219.  
  2220.         return true;
  2221. }
  2222.  
  2223. static void ironlake_enable_drps(struct drm_device *dev)
  2224. {
  2225.         struct drm_i915_private *dev_priv = dev->dev_private;
  2226.         u32 rgvmodectl = I915_READ(MEMMODECTL);
  2227.         u8 fmax, fmin, fstart, vstart;
  2228.  
  2229.         spin_lock_irq(&mchdev_lock);
  2230.  
  2231.         /* Enable temp reporting */
  2232.         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
  2233.         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
  2234.  
  2235.         /* 100ms RC evaluation intervals */
  2236.         I915_WRITE(RCUPEI, 100000);
  2237.         I915_WRITE(RCDNEI, 100000);
  2238.  
  2239.         /* Set max/min thresholds to 90ms and 80ms respectively */
  2240.         I915_WRITE(RCBMAXAVG, 90000);
  2241.         I915_WRITE(RCBMINAVG, 80000);
  2242.  
  2243.         I915_WRITE(MEMIHYST, 1);
  2244.  
  2245.         /* Set up min, max, and cur for interrupt handling */
  2246.         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  2247.         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  2248.         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  2249.                 MEMMODE_FSTART_SHIFT;
  2250.  
  2251.         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  2252.                 PXVFREQ_PX_SHIFT;
  2253.  
  2254.         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
  2255.         dev_priv->ips.fstart = fstart;
  2256.  
  2257.         dev_priv->ips.max_delay = fstart;
  2258.         dev_priv->ips.min_delay = fmin;
  2259.         dev_priv->ips.cur_delay = fstart;
  2260.  
  2261.         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
  2262.                          fmax, fmin, fstart);
  2263.  
  2264.         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  2265.  
  2266.         /*
  2267.          * Interrupts will be enabled in ironlake_irq_postinstall
  2268.          */
  2269.  
  2270.         I915_WRITE(VIDSTART, vstart);
  2271.         POSTING_READ(VIDSTART);
  2272.  
  2273.         rgvmodectl |= MEMMODE_SWMODE_EN;
  2274.         I915_WRITE(MEMMODECTL, rgvmodectl);
  2275.  
  2276.         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
  2277.                 DRM_ERROR("stuck trying to change perf mode\n");
  2278.         mdelay(1);
  2279.  
  2280.         ironlake_set_drps(dev, fstart);
  2281.  
  2282.         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  2283.                 I915_READ(0x112e0);
  2284.     dev_priv->ips.last_time1 = jiffies_to_msecs(GetTimerTicks());
  2285.         dev_priv->ips.last_count2 = I915_READ(0x112f4);
  2286. //   getrawmonotonic(&dev_priv->ips.last_time2);
  2287.  
  2288.         spin_unlock_irq(&mchdev_lock);
  2289. }
  2290.  
  2291. static void ironlake_disable_drps(struct drm_device *dev)
  2292. {
  2293.         struct drm_i915_private *dev_priv = dev->dev_private;
  2294.         u16 rgvswctl;
  2295.  
  2296.         spin_lock_irq(&mchdev_lock);
  2297.  
  2298.         rgvswctl = I915_READ16(MEMSWCTL);
  2299.  
  2300.         /* Ack interrupts, disable EFC interrupt */
  2301.         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  2302.         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  2303.         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  2304.         I915_WRITE(DEIIR, DE_PCU_EVENT);
  2305.         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  2306.  
  2307.         /* Go back to the starting frequency */
  2308.         ironlake_set_drps(dev, dev_priv->ips.fstart);
  2309.         mdelay(1);
  2310.         rgvswctl |= MEMCTL_CMD_STS;
  2311.         I915_WRITE(MEMSWCTL, rgvswctl);
  2312.         mdelay(1);
  2313.  
  2314.         spin_unlock_irq(&mchdev_lock);
  2315. }
  2316.  
  2317. /* There's a funny hw issue where the hw returns all 0 when reading from
  2318.  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
  2319.  * ourselves, instead of doing a rmw cycle (which might result in us clearing
  2320.  * all limits and the gpu stuck at whatever frequency it is at atm).
  2321.  */
  2322. static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
  2323. {
  2324.         u32 limits;
  2325.  
  2326.         limits = 0;
  2327.  
  2328.         if (*val >= dev_priv->rps.max_delay)
  2329.                 *val = dev_priv->rps.max_delay;
  2330.         limits |= dev_priv->rps.max_delay << 24;
  2331.  
  2332.         /* Only set the down limit when we've reached the lowest level to avoid
  2333.          * getting more interrupts, otherwise leave this clear. This prevents a
  2334.          * race in the hw when coming out of rc6: There's a tiny window where
  2335.          * the hw runs at the minimal clock before selecting the desired
  2336.          * frequency, if the down threshold expires in that window we will not
  2337.          * receive a down interrupt. */
  2338.         if (*val <= dev_priv->rps.min_delay) {
  2339.                 *val = dev_priv->rps.min_delay;
  2340.                 limits |= dev_priv->rps.min_delay << 16;
  2341.         }
  2342.  
  2343.         return limits;
  2344. }
  2345.  
  2346. void gen6_set_rps(struct drm_device *dev, u8 val)
  2347. {
  2348.         struct drm_i915_private *dev_priv = dev->dev_private;
  2349.         u32 limits = gen6_rps_limits(dev_priv, &val);
  2350.  
  2351.         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  2352.         WARN_ON(val > dev_priv->rps.max_delay);
  2353.         WARN_ON(val < dev_priv->rps.min_delay);
  2354.  
  2355.         if (val == dev_priv->rps.cur_delay)
  2356.                 return;
  2357.  
  2358.         I915_WRITE(GEN6_RPNSWREQ,
  2359.                    GEN6_FREQUENCY(val) |
  2360.                    GEN6_OFFSET(0) |
  2361.                    GEN6_AGGRESSIVE_TURBO);
  2362.  
  2363.         /* Make sure we continue to get interrupts
  2364.          * until we hit the minimum or maximum frequencies.
  2365.          */
  2366.         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
  2367.  
  2368.         POSTING_READ(GEN6_RPNSWREQ);
  2369.  
  2370.         dev_priv->rps.cur_delay = val;
  2371.  
  2372.         trace_intel_gpu_freq_change(val * 50);
  2373. }
  2374.  
  2375. static void gen6_disable_rps(struct drm_device *dev)
  2376. {
  2377.         struct drm_i915_private *dev_priv = dev->dev_private;
  2378.  
  2379.         I915_WRITE(GEN6_RC_CONTROL, 0);
  2380.         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
  2381.         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
  2382.         I915_WRITE(GEN6_PMIER, 0);
  2383.         /* Complete PM interrupt masking here doesn't race with the rps work
  2384.          * item again unmasking PM interrupts because that is using a different
  2385.          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
  2386.          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
  2387.  
  2388.         spin_lock_irq(&dev_priv->rps.lock);
  2389.         dev_priv->rps.pm_iir = 0;
  2390.         spin_unlock_irq(&dev_priv->rps.lock);
  2391.  
  2392.         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
  2393. }
  2394.  
  2395. int intel_enable_rc6(const struct drm_device *dev)
  2396. {
  2397.         /* Respect the kernel parameter if it is set */
  2398.         if (i915_enable_rc6 >= 0)
  2399.                 return i915_enable_rc6;
  2400.  
  2401.         if (INTEL_INFO(dev)->gen == 5) {
  2402. #ifdef CONFIG_INTEL_IOMMU
  2403.                 /* Disable rc6 on ilk if VT-d is on. */
  2404.                 if (intel_iommu_gfx_mapped)
  2405.                         return false;
  2406. #endif
  2407.                 DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n");
  2408.                 return INTEL_RC6_ENABLE;
  2409.         }
  2410.  
  2411.         if (IS_HASWELL(dev)) {
  2412.                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
  2413.                 return INTEL_RC6_ENABLE;
  2414.         }
  2415.  
  2416.         /* snb/ivb have more than one rc6 state. */
  2417.         if (INTEL_INFO(dev)->gen == 6) {
  2418.                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
  2419.                 return INTEL_RC6_ENABLE;
  2420.         }
  2421.  
  2422.         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
  2423.         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
  2424. }
  2425.  
  2426. static void gen6_enable_rps(struct drm_device *dev)
  2427. {
  2428.         struct drm_i915_private *dev_priv = dev->dev_private;
  2429.         struct intel_ring_buffer *ring;
  2430.         u32 rp_state_cap;
  2431.         u32 gt_perf_status;
  2432.         u32 pcu_mbox, rc6_mask = 0;
  2433.         u32 gtfifodbg;
  2434.         int rc6_mode;
  2435.         int i;
  2436.  
  2437.         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  2438.  
  2439.         /* Here begins a magic sequence of register writes to enable
  2440.          * auto-downclocking.
  2441.          *
  2442.          * Perhaps there might be some value in exposing these to
  2443.          * userspace...
  2444.          */
  2445.         I915_WRITE(GEN6_RC_STATE, 0);
  2446.  
  2447.         /* Clear the DBG now so we don't confuse earlier errors */
  2448.         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
  2449.                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
  2450.                 I915_WRITE(GTFIFODBG, gtfifodbg);
  2451.         }
  2452.  
  2453.         gen6_gt_force_wake_get(dev_priv);
  2454.  
  2455.         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  2456.         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  2457.  
  2458.         /* In units of 100MHz */
  2459.         dev_priv->rps.max_delay = rp_state_cap & 0xff;
  2460.         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
  2461.         dev_priv->rps.cur_delay = 0;
  2462.  
  2463.         /* disable the counters and set deterministic thresholds */
  2464.         I915_WRITE(GEN6_RC_CONTROL, 0);
  2465.  
  2466.         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
  2467.         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
  2468.         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
  2469.         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
  2470.         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
  2471.  
  2472.         for_each_ring(ring, dev_priv, i)
  2473.                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
  2474.  
  2475.         I915_WRITE(GEN6_RC_SLEEP, 0);
  2476.         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
  2477.         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
  2478.         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
  2479.         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
  2480.  
  2481.         /* Check if we are enabling RC6 */
  2482.         rc6_mode = intel_enable_rc6(dev_priv->dev);
  2483.         if (rc6_mode & INTEL_RC6_ENABLE)
  2484.                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
  2485.  
  2486.         /* We don't use those on Haswell */
  2487.         if (!IS_HASWELL(dev)) {
  2488.                 if (rc6_mode & INTEL_RC6p_ENABLE)
  2489.                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
  2490.  
  2491.                 if (rc6_mode & INTEL_RC6pp_ENABLE)
  2492.                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
  2493.         }
  2494.  
  2495.         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
  2496.                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
  2497.                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
  2498.                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
  2499.  
  2500.         I915_WRITE(GEN6_RC_CONTROL,
  2501.                    rc6_mask |
  2502.                    GEN6_RC_CTL_EI_MODE(1) |
  2503.                    GEN6_RC_CTL_HW_ENABLE);
  2504.  
  2505.         I915_WRITE(GEN6_RPNSWREQ,
  2506.                    GEN6_FREQUENCY(10) |
  2507.                    GEN6_OFFSET(0) |
  2508.                    GEN6_AGGRESSIVE_TURBO);
  2509.         I915_WRITE(GEN6_RC_VIDEO_FREQ,
  2510.                    GEN6_FREQUENCY(12));
  2511.  
  2512.         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
  2513.         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
  2514.                    dev_priv->rps.max_delay << 24 |
  2515.                    dev_priv->rps.min_delay << 16);
  2516.  
  2517.         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
  2518.         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
  2519.         I915_WRITE(GEN6_RP_UP_EI, 66000);
  2520.         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
  2521.  
  2522.         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
  2523.         I915_WRITE(GEN6_RP_CONTROL,
  2524.                    GEN6_RP_MEDIA_TURBO |
  2525.                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
  2526.                    GEN6_RP_MEDIA_IS_GFX |
  2527.                    GEN6_RP_ENABLE |
  2528.                    GEN6_RP_UP_BUSY_AVG |
  2529.                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
  2530.  
  2531.         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2532.                      500))
  2533.                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  2534.  
  2535.         I915_WRITE(GEN6_PCODE_DATA, 0);
  2536.         I915_WRITE(GEN6_PCODE_MAILBOX,
  2537.                    GEN6_PCODE_READY |
  2538.                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
  2539.         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2540.                      500))
  2541.                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  2542.  
  2543.         /* Check for overclock support */
  2544.         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2545.                      500))
  2546.                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  2547.         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
  2548.         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
  2549.         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2550.                      500))
  2551.                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  2552.         if (pcu_mbox & (1<<31)) { /* OC supported */
  2553.                 dev_priv->rps.max_delay = pcu_mbox & 0xff;
  2554.                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
  2555.         }
  2556.  
  2557.         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
  2558.  
  2559.         /* requires MSI enabled */
  2560.         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
  2561.         spin_lock_irq(&dev_priv->rps.lock);
  2562.         WARN_ON(dev_priv->rps.pm_iir != 0);
  2563.         I915_WRITE(GEN6_PMIMR, 0);
  2564.         spin_unlock_irq(&dev_priv->rps.lock);
  2565.         /* enable all PM interrupts */
  2566.         I915_WRITE(GEN6_PMINTRMSK, 0);
  2567.  
  2568.         gen6_gt_force_wake_put(dev_priv);
  2569. }
  2570.  
  2571. #if 0
  2572. static void gen6_update_ring_freq(struct drm_device *dev)
  2573. {
  2574.         struct drm_i915_private *dev_priv = dev->dev_private;
  2575.         int min_freq = 15;
  2576.         int gpu_freq, ia_freq, max_ia_freq;
  2577.         int scaling_factor = 180;
  2578.  
  2579.         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  2580.  
  2581.         max_ia_freq = cpufreq_quick_get_max(0);
  2582.         /*
  2583.          * Default to measured freq if none found, PCU will ensure we don't go
  2584.          * over
  2585.          */
  2586.         if (!max_ia_freq)
  2587.                 max_ia_freq = tsc_khz;
  2588.  
  2589.         /* Convert from kHz to MHz */
  2590.         max_ia_freq /= 1000;
  2591.  
  2592.         /*
  2593.          * For each potential GPU frequency, load a ring frequency we'd like
  2594.          * to use for memory access.  We do this by specifying the IA frequency
  2595.          * the PCU should use as a reference to determine the ring frequency.
  2596.          */
  2597.         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
  2598.              gpu_freq--) {
  2599.                 int diff = dev_priv->rps.max_delay - gpu_freq;
  2600.  
  2601.                 /*
  2602.                  * For GPU frequencies less than 750MHz, just use the lowest
  2603.                  * ring freq.
  2604.                  */
  2605.                 if (gpu_freq < min_freq)
  2606.                         ia_freq = 800;
  2607.                 else
  2608.                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
  2609.                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
  2610.  
  2611.                 I915_WRITE(GEN6_PCODE_DATA,
  2612.                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
  2613.                            gpu_freq);
  2614.                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
  2615.                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
  2616.                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
  2617.                               GEN6_PCODE_READY) == 0, 10)) {
  2618.                         DRM_ERROR("pcode write of freq table timed out\n");
  2619.                         continue;
  2620.                 }
  2621.         }
  2622. }
  2623. #endif
  2624.  
  2625. void ironlake_teardown_rc6(struct drm_device *dev)
  2626. {
  2627.         struct drm_i915_private *dev_priv = dev->dev_private;
  2628.  
  2629.         if (dev_priv->renderctx) {
  2630.                 i915_gem_object_unpin(dev_priv->renderctx);
  2631.                 drm_gem_object_unreference(&dev_priv->renderctx->base);
  2632.                 dev_priv->renderctx = NULL;
  2633.         }
  2634.  
  2635.         if (dev_priv->pwrctx) {
  2636.                 i915_gem_object_unpin(dev_priv->pwrctx);
  2637.                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
  2638.                 dev_priv->pwrctx = NULL;
  2639.         }
  2640. }
  2641.  
  2642. static void ironlake_disable_rc6(struct drm_device *dev)
  2643. {
  2644.         struct drm_i915_private *dev_priv = dev->dev_private;
  2645.  
  2646.         if (I915_READ(PWRCTXA)) {
  2647.                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
  2648.                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
  2649.                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
  2650.                          50);
  2651.  
  2652.                 I915_WRITE(PWRCTXA, 0);
  2653.                 POSTING_READ(PWRCTXA);
  2654.  
  2655.                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  2656.                 POSTING_READ(RSTDBYCTL);
  2657.         }
  2658. }
  2659.  
  2660. static int ironlake_setup_rc6(struct drm_device *dev)
  2661. {
  2662.         struct drm_i915_private *dev_priv = dev->dev_private;
  2663.  
  2664.         if (dev_priv->renderctx == NULL)
  2665.                 dev_priv->renderctx = intel_alloc_context_page(dev);
  2666.         if (!dev_priv->renderctx)
  2667.                 return -ENOMEM;
  2668.  
  2669.         if (dev_priv->pwrctx == NULL)
  2670.                 dev_priv->pwrctx = intel_alloc_context_page(dev);
  2671.         if (!dev_priv->pwrctx) {
  2672.                 ironlake_teardown_rc6(dev);
  2673.                 return -ENOMEM;
  2674.         }
  2675.  
  2676.         return 0;
  2677. }
  2678.  
  2679. static void ironlake_enable_rc6(struct drm_device *dev)
  2680. {
  2681.         struct drm_i915_private *dev_priv = dev->dev_private;
  2682.         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  2683.         int ret;
  2684.  
  2685.         /* rc6 disabled by default due to repeated reports of hanging during
  2686.          * boot and resume.
  2687.          */
  2688.         if (!intel_enable_rc6(dev))
  2689.                 return;
  2690.  
  2691.         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  2692.  
  2693.         ret = ironlake_setup_rc6(dev);
  2694.         if (ret)
  2695.                 return;
  2696.  
  2697.         /*
  2698.          * GPU can automatically power down the render unit if given a page
  2699.          * to save state.
  2700.          */
  2701.         ret = intel_ring_begin(ring, 6);
  2702.         if (ret) {
  2703.                 ironlake_teardown_rc6(dev);
  2704.                 return;
  2705.         }
  2706.  
  2707.         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
  2708.         intel_ring_emit(ring, MI_SET_CONTEXT);
  2709.         intel_ring_emit(ring, dev_priv->renderctx->gtt_offset |
  2710.                         MI_MM_SPACE_GTT |
  2711.                         MI_SAVE_EXT_STATE_EN |
  2712.                         MI_RESTORE_EXT_STATE_EN |
  2713.                         MI_RESTORE_INHIBIT);
  2714.         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
  2715.         intel_ring_emit(ring, MI_NOOP);
  2716.         intel_ring_emit(ring, MI_FLUSH);
  2717.         intel_ring_advance(ring);
  2718.  
  2719.         /*
  2720.          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
  2721.          * does an implicit flush, combined with MI_FLUSH above, it should be
  2722.          * safe to assume that renderctx is valid
  2723.          */
  2724.         ret = intel_wait_ring_idle(ring);
  2725.         if (ret) {
  2726.                 DRM_ERROR("failed to enable ironlake power power savings\n");
  2727.                 ironlake_teardown_rc6(dev);
  2728.                 return;
  2729.         }
  2730.  
  2731.         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
  2732.         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  2733. }
  2734.  
  2735. static unsigned long intel_pxfreq(u32 vidfreq)
  2736. {
  2737.         unsigned long freq;
  2738.         int div = (vidfreq & 0x3f0000) >> 16;
  2739.         int post = (vidfreq & 0x3000) >> 12;
  2740.         int pre = (vidfreq & 0x7);
  2741.  
  2742.         if (!pre)
  2743.                 return 0;
  2744.  
  2745.         freq = ((div * 133333) / ((1<<post) * pre));
  2746.  
  2747.         return freq;
  2748. }
  2749.  
  2750. static const struct cparams {
  2751.         u16 i;
  2752.         u16 t;
  2753.         u16 m;
  2754.         u16 c;
  2755. } cparams[] = {
  2756.         { 1, 1333, 301, 28664 },
  2757.         { 1, 1066, 294, 24460 },
  2758.         { 1, 800, 294, 25192 },
  2759.         { 0, 1333, 276, 27605 },
  2760.         { 0, 1066, 276, 27605 },
  2761.         { 0, 800, 231, 23784 },
  2762. };
  2763.  
  2764. static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
  2765. {
  2766.         u64 total_count, diff, ret;
  2767.         u32 count1, count2, count3, m = 0, c = 0;
  2768.     unsigned long now = jiffies_to_msecs(GetTimerTicks()), diff1;
  2769.         int i;
  2770.  
  2771.         assert_spin_locked(&mchdev_lock);
  2772.  
  2773.         diff1 = now - dev_priv->ips.last_time1;
  2774.  
  2775.         /* Prevent division-by-zero if we are asking too fast.
  2776.          * Also, we don't get interesting results if we are polling
  2777.          * faster than once in 10ms, so just return the saved value
  2778.          * in such cases.
  2779.          */
  2780.         if (diff1 <= 10)
  2781.                 return dev_priv->ips.chipset_power;
  2782.  
  2783.         count1 = I915_READ(DMIEC);
  2784.         count2 = I915_READ(DDREC);
  2785.         count3 = I915_READ(CSIEC);
  2786.  
  2787.         total_count = count1 + count2 + count3;
  2788.  
  2789.         /* FIXME: handle per-counter overflow */
  2790.         if (total_count < dev_priv->ips.last_count1) {
  2791.                 diff = ~0UL - dev_priv->ips.last_count1;
  2792.                 diff += total_count;
  2793.         } else {
  2794.                 diff = total_count - dev_priv->ips.last_count1;
  2795.         }
  2796.  
  2797.         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
  2798.                 if (cparams[i].i == dev_priv->ips.c_m &&
  2799.                     cparams[i].t == dev_priv->ips.r_t) {
  2800.                         m = cparams[i].m;
  2801.                         c = cparams[i].c;
  2802.                         break;
  2803.                 }
  2804.         }
  2805.  
  2806.         diff = div_u64(diff, diff1);
  2807.         ret = ((m * diff) + c);
  2808.         ret = div_u64(ret, 10);
  2809.  
  2810.         dev_priv->ips.last_count1 = total_count;
  2811.         dev_priv->ips.last_time1 = now;
  2812.  
  2813.         dev_priv->ips.chipset_power = ret;
  2814.  
  2815.         return ret;
  2816. }
  2817.  
  2818. unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
  2819. {
  2820.         unsigned long val;
  2821.  
  2822.         if (dev_priv->info->gen != 5)
  2823.                 return 0;
  2824.  
  2825.         spin_lock_irq(&mchdev_lock);
  2826.  
  2827.         val = __i915_chipset_val(dev_priv);
  2828.  
  2829.         spin_unlock_irq(&mchdev_lock);
  2830.  
  2831.         return val;
  2832. }
  2833.  
  2834. unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
  2835. {
  2836.         unsigned long m, x, b;
  2837.         u32 tsfs;
  2838.  
  2839.         tsfs = I915_READ(TSFS);
  2840.  
  2841.         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
  2842.         x = I915_READ8(TR1);
  2843.  
  2844.         b = tsfs & TSFS_INTR_MASK;
  2845.  
  2846.         return ((m * x) / 127) - b;
  2847. }
  2848.  
  2849. static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
  2850. {
  2851.         static const struct v_table {
  2852.                 u16 vd; /* in .1 mil */
  2853.                 u16 vm; /* in .1 mil */
  2854.         } v_table[] = {
  2855.                 { 0, 0, },
  2856.                 { 375, 0, },
  2857.                 { 500, 0, },
  2858.                 { 625, 0, },
  2859.                 { 750, 0, },
  2860.                 { 875, 0, },
  2861.                 { 1000, 0, },
  2862.                 { 1125, 0, },
  2863.                 { 4125, 3000, },
  2864.                 { 4125, 3000, },
  2865.                 { 4125, 3000, },
  2866.                 { 4125, 3000, },
  2867.                 { 4125, 3000, },
  2868.                 { 4125, 3000, },
  2869.                 { 4125, 3000, },
  2870.                 { 4125, 3000, },
  2871.                 { 4125, 3000, },
  2872.                 { 4125, 3000, },
  2873.                 { 4125, 3000, },
  2874.                 { 4125, 3000, },
  2875.                 { 4125, 3000, },
  2876.                 { 4125, 3000, },
  2877.                 { 4125, 3000, },
  2878.                 { 4125, 3000, },
  2879.                 { 4125, 3000, },
  2880.                 { 4125, 3000, },
  2881.                 { 4125, 3000, },
  2882.                 { 4125, 3000, },
  2883.                 { 4125, 3000, },
  2884.                 { 4125, 3000, },
  2885.                 { 4125, 3000, },
  2886.                 { 4125, 3000, },
  2887.                 { 4250, 3125, },
  2888.                 { 4375, 3250, },
  2889.                 { 4500, 3375, },
  2890.                 { 4625, 3500, },
  2891.                 { 4750, 3625, },
  2892.                 { 4875, 3750, },
  2893.                 { 5000, 3875, },
  2894.                 { 5125, 4000, },
  2895.                 { 5250, 4125, },
  2896.                 { 5375, 4250, },
  2897.                 { 5500, 4375, },
  2898.                 { 5625, 4500, },
  2899.                 { 5750, 4625, },
  2900.                 { 5875, 4750, },
  2901.                 { 6000, 4875, },
  2902.                 { 6125, 5000, },
  2903.                 { 6250, 5125, },
  2904.                 { 6375, 5250, },
  2905.                 { 6500, 5375, },
  2906.                 { 6625, 5500, },
  2907.                 { 6750, 5625, },
  2908.                 { 6875, 5750, },
  2909.                 { 7000, 5875, },
  2910.                 { 7125, 6000, },
  2911.                 { 7250, 6125, },
  2912.                 { 7375, 6250, },
  2913.                 { 7500, 6375, },
  2914.                 { 7625, 6500, },
  2915.                 { 7750, 6625, },
  2916.                 { 7875, 6750, },
  2917.                 { 8000, 6875, },
  2918.                 { 8125, 7000, },
  2919.                 { 8250, 7125, },
  2920.                 { 8375, 7250, },
  2921.                 { 8500, 7375, },
  2922.                 { 8625, 7500, },
  2923.                 { 8750, 7625, },
  2924.                 { 8875, 7750, },
  2925.                 { 9000, 7875, },
  2926.                 { 9125, 8000, },
  2927.                 { 9250, 8125, },
  2928.                 { 9375, 8250, },
  2929.                 { 9500, 8375, },
  2930.                 { 9625, 8500, },
  2931.                 { 9750, 8625, },
  2932.                 { 9875, 8750, },
  2933.                 { 10000, 8875, },
  2934.                 { 10125, 9000, },
  2935.                 { 10250, 9125, },
  2936.                 { 10375, 9250, },
  2937.                 { 10500, 9375, },
  2938.                 { 10625, 9500, },
  2939.                 { 10750, 9625, },
  2940.                 { 10875, 9750, },
  2941.                 { 11000, 9875, },
  2942.                 { 11125, 10000, },
  2943.                 { 11250, 10125, },
  2944.                 { 11375, 10250, },
  2945.                 { 11500, 10375, },
  2946.                 { 11625, 10500, },
  2947.                 { 11750, 10625, },
  2948.                 { 11875, 10750, },
  2949.                 { 12000, 10875, },
  2950.                 { 12125, 11000, },
  2951.                 { 12250, 11125, },
  2952.                 { 12375, 11250, },
  2953.                 { 12500, 11375, },
  2954.                 { 12625, 11500, },
  2955.                 { 12750, 11625, },
  2956.                 { 12875, 11750, },
  2957.                 { 13000, 11875, },
  2958.                 { 13125, 12000, },
  2959.                 { 13250, 12125, },
  2960.                 { 13375, 12250, },
  2961.                 { 13500, 12375, },
  2962.                 { 13625, 12500, },
  2963.                 { 13750, 12625, },
  2964.                 { 13875, 12750, },
  2965.                 { 14000, 12875, },
  2966.                 { 14125, 13000, },
  2967.                 { 14250, 13125, },
  2968.                 { 14375, 13250, },
  2969.                 { 14500, 13375, },
  2970.                 { 14625, 13500, },
  2971.                 { 14750, 13625, },
  2972.                 { 14875, 13750, },
  2973.                 { 15000, 13875, },
  2974.                 { 15125, 14000, },
  2975.                 { 15250, 14125, },
  2976.                 { 15375, 14250, },
  2977.                 { 15500, 14375, },
  2978.                 { 15625, 14500, },
  2979.                 { 15750, 14625, },
  2980.                 { 15875, 14750, },
  2981.                 { 16000, 14875, },
  2982.                 { 16125, 15000, },
  2983.         };
  2984.         if (dev_priv->info->is_mobile)
  2985.                 return v_table[pxvid].vm;
  2986.         else
  2987.                 return v_table[pxvid].vd;
  2988. }
  2989.  
  2990. static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
  2991. {
  2992.         struct timespec now, diff1;
  2993.         u64 diff;
  2994.         unsigned long diffms;
  2995.         u32 count;
  2996.  
  2997.         assert_spin_locked(&mchdev_lock);
  2998.  
  2999.         getrawmonotonic(&now);
  3000.         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
  3001.  
  3002.         /* Don't divide by 0 */
  3003.         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
  3004.         if (!diffms)
  3005.                 return;
  3006.  
  3007.         count = I915_READ(GFXEC);
  3008.  
  3009.         if (count < dev_priv->ips.last_count2) {
  3010.                 diff = ~0UL - dev_priv->ips.last_count2;
  3011.                 diff += count;
  3012.         } else {
  3013.                 diff = count - dev_priv->ips.last_count2;
  3014.         }
  3015.  
  3016.         dev_priv->ips.last_count2 = count;
  3017.         dev_priv->ips.last_time2 = now;
  3018.  
  3019.         /* More magic constants... */
  3020.         diff = diff * 1181;
  3021.         diff = div_u64(diff, diffms * 10);
  3022.         dev_priv->ips.gfx_power = diff;
  3023. }
  3024.  
  3025. void i915_update_gfx_val(struct drm_i915_private *dev_priv)
  3026. {
  3027.         if (dev_priv->info->gen != 5)
  3028.                 return;
  3029.  
  3030.         spin_lock_irq(&mchdev_lock);
  3031.  
  3032.         __i915_update_gfx_val(dev_priv);
  3033.  
  3034.         spin_unlock_irq(&mchdev_lock);
  3035. }
  3036.  
  3037. static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
  3038. {
  3039.         unsigned long t, corr, state1, corr2, state2;
  3040.         u32 pxvid, ext_v;
  3041.  
  3042.         assert_spin_locked(&mchdev_lock);
  3043.  
  3044.         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
  3045.         pxvid = (pxvid >> 24) & 0x7f;
  3046.         ext_v = pvid_to_extvid(dev_priv, pxvid);
  3047.  
  3048.         state1 = ext_v;
  3049.  
  3050.         t = i915_mch_val(dev_priv);
  3051.  
  3052.         /* Revel in the empirically derived constants */
  3053.  
  3054.         /* Correction factor in 1/100000 units */
  3055.         if (t > 80)
  3056.                 corr = ((t * 2349) + 135940);
  3057.         else if (t >= 50)
  3058.                 corr = ((t * 964) + 29317);
  3059.         else /* < 50 */
  3060.                 corr = ((t * 301) + 1004);
  3061.  
  3062.         corr = corr * ((150142 * state1) / 10000 - 78642);
  3063.         corr /= 100000;
  3064.         corr2 = (corr * dev_priv->ips.corr);
  3065.  
  3066.         state2 = (corr2 * state1) / 10000;
  3067.         state2 /= 100; /* convert to mW */
  3068.  
  3069.         __i915_update_gfx_val(dev_priv);
  3070.  
  3071.         return dev_priv->ips.gfx_power + state2;
  3072. }
  3073.  
  3074. unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
  3075. {
  3076.         unsigned long val;
  3077.  
  3078.         if (dev_priv->info->gen != 5)
  3079.                 return 0;
  3080.  
  3081.         spin_lock_irq(&mchdev_lock);
  3082.  
  3083.         val = __i915_gfx_val(dev_priv);
  3084.  
  3085.         spin_unlock_irq(&mchdev_lock);
  3086.  
  3087.         return val;
  3088. }
  3089.  
  3090. /**
  3091.  * i915_read_mch_val - return value for IPS use
  3092.  *
  3093.  * Calculate and return a value for the IPS driver to use when deciding whether
  3094.  * we have thermal and power headroom to increase CPU or GPU power budget.
  3095.  */
  3096. unsigned long i915_read_mch_val(void)
  3097. {
  3098.         struct drm_i915_private *dev_priv;
  3099.         unsigned long chipset_val, graphics_val, ret = 0;
  3100.  
  3101.         spin_lock_irq(&mchdev_lock);
  3102.         if (!i915_mch_dev)
  3103.                 goto out_unlock;
  3104.         dev_priv = i915_mch_dev;
  3105.  
  3106.         chipset_val = __i915_chipset_val(dev_priv);
  3107.         graphics_val = __i915_gfx_val(dev_priv);
  3108.  
  3109.         ret = chipset_val + graphics_val;
  3110.  
  3111. out_unlock:
  3112.         spin_unlock_irq(&mchdev_lock);
  3113.  
  3114.         return ret;
  3115. }
  3116. EXPORT_SYMBOL_GPL(i915_read_mch_val);
  3117.  
  3118. /**
  3119.  * i915_gpu_raise - raise GPU frequency limit
  3120.  *
  3121.  * Raise the limit; IPS indicates we have thermal headroom.
  3122.  */
  3123. bool i915_gpu_raise(void)
  3124. {
  3125.         struct drm_i915_private *dev_priv;
  3126.         bool ret = true;
  3127.  
  3128.         spin_lock_irq(&mchdev_lock);
  3129.         if (!i915_mch_dev) {
  3130.                 ret = false;
  3131.                 goto out_unlock;
  3132.         }
  3133.         dev_priv = i915_mch_dev;
  3134.  
  3135.         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
  3136.                 dev_priv->ips.max_delay--;
  3137.  
  3138. out_unlock:
  3139.         spin_unlock_irq(&mchdev_lock);
  3140.  
  3141.         return ret;
  3142. }
  3143. EXPORT_SYMBOL_GPL(i915_gpu_raise);
  3144.  
  3145. /**
  3146.  * i915_gpu_lower - lower GPU frequency limit
  3147.  *
  3148.  * IPS indicates we're close to a thermal limit, so throttle back the GPU
  3149.  * frequency maximum.
  3150.  */
  3151. bool i915_gpu_lower(void)
  3152. {
  3153.         struct drm_i915_private *dev_priv;
  3154.         bool ret = true;
  3155.  
  3156.         spin_lock_irq(&mchdev_lock);
  3157.         if (!i915_mch_dev) {
  3158.                 ret = false;
  3159.                 goto out_unlock;
  3160.         }
  3161.         dev_priv = i915_mch_dev;
  3162.  
  3163.         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
  3164.                 dev_priv->ips.max_delay++;
  3165.  
  3166. out_unlock:
  3167.         spin_unlock_irq(&mchdev_lock);
  3168.  
  3169.         return ret;
  3170. }
  3171. EXPORT_SYMBOL_GPL(i915_gpu_lower);
  3172.  
  3173. /**
  3174.  * i915_gpu_busy - indicate GPU business to IPS
  3175.  *
  3176.  * Tell the IPS driver whether or not the GPU is busy.
  3177.  */
  3178. bool i915_gpu_busy(void)
  3179. {
  3180.         struct drm_i915_private *dev_priv;
  3181.         struct intel_ring_buffer *ring;
  3182.         bool ret = false;
  3183.         int i;
  3184.  
  3185.         spin_lock_irq(&mchdev_lock);
  3186.         if (!i915_mch_dev)
  3187.                 goto out_unlock;
  3188.         dev_priv = i915_mch_dev;
  3189.  
  3190.         for_each_ring(ring, dev_priv, i)
  3191.                 ret |= !list_empty(&ring->request_list);
  3192.  
  3193. out_unlock:
  3194.         spin_unlock_irq(&mchdev_lock);
  3195.  
  3196.         return ret;
  3197. }
  3198. EXPORT_SYMBOL_GPL(i915_gpu_busy);
  3199.  
  3200. /**
  3201.  * i915_gpu_turbo_disable - disable graphics turbo
  3202.  *
  3203.  * Disable graphics turbo by resetting the max frequency and setting the
  3204.  * current frequency to the default.
  3205.  */
  3206. bool i915_gpu_turbo_disable(void)
  3207. {
  3208.         struct drm_i915_private *dev_priv;
  3209.         bool ret = true;
  3210.  
  3211.         spin_lock_irq(&mchdev_lock);
  3212.         if (!i915_mch_dev) {
  3213.                 ret = false;
  3214.                 goto out_unlock;
  3215.         }
  3216.         dev_priv = i915_mch_dev;
  3217.  
  3218.         dev_priv->ips.max_delay = dev_priv->ips.fstart;
  3219.  
  3220.         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
  3221.                 ret = false;
  3222.  
  3223. out_unlock:
  3224.         spin_unlock_irq(&mchdev_lock);
  3225.  
  3226.         return ret;
  3227. }
  3228. EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
  3229.  
  3230. /**
  3231.  * Tells the intel_ips driver that the i915 driver is now loaded, if
  3232.  * IPS got loaded first.
  3233.  *
  3234.  * This awkward dance is so that neither module has to depend on the
  3235.  * other in order for IPS to do the appropriate communication of
  3236.  * GPU turbo limits to i915.
  3237.  */
  3238. static void
  3239. ips_ping_for_i915_load(void)
  3240. {
  3241.         void (*link)(void);
  3242.  
  3243. //   link = symbol_get(ips_link_to_i915_driver);
  3244. //   if (link) {
  3245. //       link();
  3246. //       symbol_put(ips_link_to_i915_driver);
  3247. //   }
  3248. }
  3249.  
  3250. void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
  3251. {
  3252.         /* We only register the i915 ips part with intel-ips once everything is
  3253.          * set up, to avoid intel-ips sneaking in and reading bogus values. */
  3254.         spin_lock_irq(&mchdev_lock);
  3255.         i915_mch_dev = dev_priv;
  3256.         spin_unlock_irq(&mchdev_lock);
  3257.  
  3258.         ips_ping_for_i915_load();
  3259. }
  3260.  
  3261. void intel_gpu_ips_teardown(void)
  3262. {
  3263.         spin_lock_irq(&mchdev_lock);
  3264.         i915_mch_dev = NULL;
  3265.         spin_unlock_irq(&mchdev_lock);
  3266. }
  3267. static void intel_init_emon(struct drm_device *dev)
  3268. {
  3269.         struct drm_i915_private *dev_priv = dev->dev_private;
  3270.         u32 lcfuse;
  3271.         u8 pxw[16];
  3272.         int i;
  3273.  
  3274.         /* Disable to program */
  3275.         I915_WRITE(ECR, 0);
  3276.         POSTING_READ(ECR);
  3277.  
  3278.         /* Program energy weights for various events */
  3279.         I915_WRITE(SDEW, 0x15040d00);
  3280.         I915_WRITE(CSIEW0, 0x007f0000);
  3281.         I915_WRITE(CSIEW1, 0x1e220004);
  3282.         I915_WRITE(CSIEW2, 0x04000004);
  3283.  
  3284.         for (i = 0; i < 5; i++)
  3285.                 I915_WRITE(PEW + (i * 4), 0);
  3286.         for (i = 0; i < 3; i++)
  3287.                 I915_WRITE(DEW + (i * 4), 0);
  3288.  
  3289.         /* Program P-state weights to account for frequency power adjustment */
  3290.         for (i = 0; i < 16; i++) {
  3291.                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  3292.                 unsigned long freq = intel_pxfreq(pxvidfreq);
  3293.                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  3294.                         PXVFREQ_PX_SHIFT;
  3295.                 unsigned long val;
  3296.  
  3297.                 val = vid * vid;
  3298.                 val *= (freq / 1000);
  3299.                 val *= 255;
  3300.                 val /= (127*127*900);
  3301.                 if (val > 0xff)
  3302.                         DRM_ERROR("bad pxval: %ld\n", val);
  3303.                 pxw[i] = val;
  3304.         }
  3305.         /* Render standby states get 0 weight */
  3306.         pxw[14] = 0;
  3307.         pxw[15] = 0;
  3308.  
  3309.         for (i = 0; i < 4; i++) {
  3310.                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  3311.                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  3312.                 I915_WRITE(PXW + (i * 4), val);
  3313.         }
  3314.  
  3315.         /* Adjust magic regs to magic values (more experimental results) */
  3316.         I915_WRITE(OGW0, 0);
  3317.         I915_WRITE(OGW1, 0);
  3318.         I915_WRITE(EG0, 0x00007f00);
  3319.         I915_WRITE(EG1, 0x0000000e);
  3320.         I915_WRITE(EG2, 0x000e0000);
  3321.         I915_WRITE(EG3, 0x68000300);
  3322.         I915_WRITE(EG4, 0x42000000);
  3323.         I915_WRITE(EG5, 0x00140031);
  3324.         I915_WRITE(EG6, 0);
  3325.         I915_WRITE(EG7, 0);
  3326.  
  3327.         for (i = 0; i < 8; i++)
  3328.                 I915_WRITE(PXWL + (i * 4), 0);
  3329.  
  3330.         /* Enable PMON + select events */
  3331.         I915_WRITE(ECR, 0x80000019);
  3332.  
  3333.         lcfuse = I915_READ(LCFUSE02);
  3334.  
  3335.         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
  3336. }
  3337.  
  3338. void intel_disable_gt_powersave(struct drm_device *dev)
  3339. {
  3340.         if (IS_IRONLAKE_M(dev)) {
  3341.                 ironlake_disable_drps(dev);
  3342.                 ironlake_disable_rc6(dev);
  3343.         } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
  3344.                 gen6_disable_rps(dev);
  3345.         }
  3346. }
  3347.  
  3348. void intel_enable_gt_powersave(struct drm_device *dev)
  3349. {
  3350.         if (IS_IRONLAKE_M(dev)) {
  3351.                 ironlake_enable_drps(dev);
  3352.                 ironlake_enable_rc6(dev);
  3353.                 intel_init_emon(dev);
  3354.         } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
  3355. //       gen6_enable_rps(dev);
  3356. //       gen6_update_ring_freq(dev);
  3357.         }
  3358. }
  3359.  
  3360. static void ironlake_init_clock_gating(struct drm_device *dev)
  3361. {
  3362.         struct drm_i915_private *dev_priv = dev->dev_private;
  3363.         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  3364.  
  3365.         /* Required for FBC */
  3366.         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
  3367.                 DPFCRUNIT_CLOCK_GATE_DISABLE |
  3368.                 DPFDUNIT_CLOCK_GATE_DISABLE;
  3369.         /* Required for CxSR */
  3370.         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
  3371.  
  3372.         I915_WRITE(PCH_3DCGDIS0,
  3373.                    MARIUNIT_CLOCK_GATE_DISABLE |
  3374.                    SVSMUNIT_CLOCK_GATE_DISABLE);
  3375.         I915_WRITE(PCH_3DCGDIS1,
  3376.                    VFMUNIT_CLOCK_GATE_DISABLE);
  3377.  
  3378.         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  3379.  
  3380.         /*
  3381.          * According to the spec the following bits should be set in
  3382.          * order to enable memory self-refresh
  3383.          * The bit 22/21 of 0x42004
  3384.          * The bit 5 of 0x42020
  3385.          * The bit 15 of 0x45000
  3386.          */
  3387.         I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3388.                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
  3389.                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  3390.         I915_WRITE(ILK_DSPCLK_GATE,
  3391.                    (I915_READ(ILK_DSPCLK_GATE) |
  3392.                     ILK_DPARB_CLK_GATE));
  3393.         I915_WRITE(DISP_ARB_CTL,
  3394.                    (I915_READ(DISP_ARB_CTL) |
  3395.                     DISP_FBC_WM_DIS));
  3396.         I915_WRITE(WM3_LP_ILK, 0);
  3397.         I915_WRITE(WM2_LP_ILK, 0);
  3398.         I915_WRITE(WM1_LP_ILK, 0);
  3399.  
  3400.         /*
  3401.          * Based on the document from hardware guys the following bits
  3402.          * should be set unconditionally in order to enable FBC.
  3403.          * The bit 22 of 0x42000
  3404.          * The bit 22 of 0x42004
  3405.          * The bit 7,8,9 of 0x42020.
  3406.          */
  3407.         if (IS_IRONLAKE_M(dev)) {
  3408.                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
  3409.                            I915_READ(ILK_DISPLAY_CHICKEN1) |
  3410.                            ILK_FBCQ_DIS);
  3411.                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3412.                            I915_READ(ILK_DISPLAY_CHICKEN2) |
  3413.                            ILK_DPARB_GATE);
  3414.                 I915_WRITE(ILK_DSPCLK_GATE,
  3415.                            I915_READ(ILK_DSPCLK_GATE) |
  3416.                            ILK_DPFC_DIS1 |
  3417.                            ILK_DPFC_DIS2 |
  3418.                            ILK_CLK_FBC);
  3419.         }
  3420.  
  3421.         I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3422.                    I915_READ(ILK_DISPLAY_CHICKEN2) |
  3423.                    ILK_ELPIN_409_SELECT);
  3424.         I915_WRITE(_3D_CHICKEN2,
  3425.                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
  3426.                    _3D_CHICKEN2_WM_READ_PIPELINED);
  3427. }
  3428.  
  3429. static void gen6_init_clock_gating(struct drm_device *dev)
  3430. {
  3431.         struct drm_i915_private *dev_priv = dev->dev_private;
  3432.         int pipe;
  3433.         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  3434.  
  3435.         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  3436.  
  3437.         I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3438.                    I915_READ(ILK_DISPLAY_CHICKEN2) |
  3439.                    ILK_ELPIN_409_SELECT);
  3440.  
  3441.         I915_WRITE(WM3_LP_ILK, 0);
  3442.         I915_WRITE(WM2_LP_ILK, 0);
  3443.         I915_WRITE(WM1_LP_ILK, 0);
  3444.  
  3445.         I915_WRITE(CACHE_MODE_0,
  3446.                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
  3447.  
  3448.         I915_WRITE(GEN6_UCGCTL1,
  3449.                    I915_READ(GEN6_UCGCTL1) |
  3450.                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
  3451.                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
  3452.  
  3453.         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  3454.          * gating disable must be set.  Failure to set it results in
  3455.          * flickering pixels due to Z write ordering failures after
  3456.          * some amount of runtime in the Mesa "fire" demo, and Unigine
  3457.          * Sanctuary and Tropics, and apparently anything else with
  3458.          * alpha test or pixel discard.
  3459.          *
  3460.          * According to the spec, bit 11 (RCCUNIT) must also be set,
  3461.          * but we didn't debug actual testcases to find it out.
  3462.          *
  3463.          * Also apply WaDisableVDSUnitClockGating and
  3464.          * WaDisableRCPBUnitClockGating.
  3465.          */
  3466.         I915_WRITE(GEN6_UCGCTL2,
  3467.                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
  3468.                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
  3469.                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  3470.  
  3471.         /* Bspec says we need to always set all mask bits. */
  3472.         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
  3473.                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
  3474.  
  3475.         /*
  3476.          * According to the spec the following bits should be
  3477.          * set in order to enable memory self-refresh and fbc:
  3478.          * The bit21 and bit22 of 0x42000
  3479.          * The bit21 and bit22 of 0x42004
  3480.          * The bit5 and bit7 of 0x42020
  3481.          * The bit14 of 0x70180
  3482.          * The bit14 of 0x71180
  3483.          */
  3484.         I915_WRITE(ILK_DISPLAY_CHICKEN1,
  3485.                    I915_READ(ILK_DISPLAY_CHICKEN1) |
  3486.                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
  3487.         I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3488.                    I915_READ(ILK_DISPLAY_CHICKEN2) |
  3489.                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
  3490.         I915_WRITE(ILK_DSPCLK_GATE,
  3491.                    I915_READ(ILK_DSPCLK_GATE) |
  3492.                    ILK_DPARB_CLK_GATE  |
  3493.                    ILK_DPFD_CLK_GATE);
  3494.  
  3495.         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  3496.                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
  3497.  
  3498.         for_each_pipe(pipe) {
  3499.                 I915_WRITE(DSPCNTR(pipe),
  3500.                            I915_READ(DSPCNTR(pipe)) |
  3501.                            DISPPLANE_TRICKLE_FEED_DISABLE);
  3502.                 intel_flush_display_plane(dev_priv, pipe);
  3503.         }
  3504.  
  3505.         /* The default value should be 0x200 according to docs, but the two
  3506.          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
  3507.         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
  3508.         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
  3509. }
  3510.  
  3511. static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
  3512. {
  3513.         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
  3514.  
  3515.         reg &= ~GEN7_FF_SCHED_MASK;
  3516.         reg |= GEN7_FF_TS_SCHED_HW;
  3517.         reg |= GEN7_FF_VS_SCHED_HW;
  3518.         reg |= GEN7_FF_DS_SCHED_HW;
  3519.  
  3520.         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
  3521. }
  3522.  
  3523. static void haswell_init_clock_gating(struct drm_device *dev)
  3524. {
  3525.         struct drm_i915_private *dev_priv = dev->dev_private;
  3526.         int pipe;
  3527.         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  3528.  
  3529.         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  3530.  
  3531.         I915_WRITE(WM3_LP_ILK, 0);
  3532.         I915_WRITE(WM2_LP_ILK, 0);
  3533.         I915_WRITE(WM1_LP_ILK, 0);
  3534.  
  3535.         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  3536.          * This implements the WaDisableRCZUnitClockGating workaround.
  3537.          */
  3538.         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
  3539.  
  3540.         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  3541.  
  3542.         I915_WRITE(IVB_CHICKEN3,
  3543.                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  3544.                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
  3545.  
  3546.         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
  3547.         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  3548.                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  3549.  
  3550.         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
  3551.         I915_WRITE(GEN7_L3CNTLREG1,
  3552.                         GEN7_WA_FOR_GEN7_L3_CONTROL);
  3553.         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
  3554.                         GEN7_WA_L3_CHICKEN_MODE);
  3555.  
  3556.         /* This is required by WaCatErrorRejectionIssue */
  3557.         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  3558.                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  3559.                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  3560.  
  3561.         for_each_pipe(pipe) {
  3562.                 I915_WRITE(DSPCNTR(pipe),
  3563.                            I915_READ(DSPCNTR(pipe)) |
  3564.                            DISPPLANE_TRICKLE_FEED_DISABLE);
  3565.                 intel_flush_display_plane(dev_priv, pipe);
  3566.         }
  3567.  
  3568.         gen7_setup_fixed_func_scheduler(dev_priv);
  3569.  
  3570.         /* WaDisable4x2SubspanOptimization */
  3571.         I915_WRITE(CACHE_MODE_1,
  3572.                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  3573.  
  3574.         /* XXX: This is a workaround for early silicon revisions and should be
  3575.          * removed later.
  3576.          */
  3577.         I915_WRITE(WM_DBG,
  3578.                         I915_READ(WM_DBG) |
  3579.                         WM_DBG_DISALLOW_MULTIPLE_LP |
  3580.                         WM_DBG_DISALLOW_SPRITE |
  3581.                         WM_DBG_DISALLOW_MAXFIFO);
  3582.  
  3583. }
  3584.  
  3585. static void ivybridge_init_clock_gating(struct drm_device *dev)
  3586. {
  3587.         struct drm_i915_private *dev_priv = dev->dev_private;
  3588.         int pipe;
  3589.         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  3590.         uint32_t snpcr;
  3591.  
  3592.         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  3593.  
  3594.         I915_WRITE(WM3_LP_ILK, 0);
  3595.         I915_WRITE(WM2_LP_ILK, 0);
  3596.         I915_WRITE(WM1_LP_ILK, 0);
  3597.  
  3598.         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  3599.  
  3600.         I915_WRITE(IVB_CHICKEN3,
  3601.                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  3602.                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
  3603.  
  3604.         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
  3605.         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  3606.                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  3607.  
  3608.         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
  3609.         I915_WRITE(GEN7_L3CNTLREG1,
  3610.                         GEN7_WA_FOR_GEN7_L3_CONTROL);
  3611.         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
  3612.                         GEN7_WA_L3_CHICKEN_MODE);
  3613.  
  3614.         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  3615.          * gating disable must be set.  Failure to set it results in
  3616.          * flickering pixels due to Z write ordering failures after
  3617.          * some amount of runtime in the Mesa "fire" demo, and Unigine
  3618.          * Sanctuary and Tropics, and apparently anything else with
  3619.          * alpha test or pixel discard.
  3620.          *
  3621.          * According to the spec, bit 11 (RCCUNIT) must also be set,
  3622.          * but we didn't debug actual testcases to find it out.
  3623.          *
  3624.          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  3625.          * This implements the WaDisableRCZUnitClockGating workaround.
  3626.          */
  3627.         I915_WRITE(GEN6_UCGCTL2,
  3628.                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
  3629.                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  3630.  
  3631.         /* This is required by WaCatErrorRejectionIssue */
  3632.         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  3633.                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  3634.                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  3635.  
  3636.         for_each_pipe(pipe) {
  3637.                 I915_WRITE(DSPCNTR(pipe),
  3638.                            I915_READ(DSPCNTR(pipe)) |
  3639.                            DISPPLANE_TRICKLE_FEED_DISABLE);
  3640.                 intel_flush_display_plane(dev_priv, pipe);
  3641.         }
  3642.  
  3643.         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  3644.                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
  3645.  
  3646.         gen7_setup_fixed_func_scheduler(dev_priv);
  3647.  
  3648.         /* WaDisable4x2SubspanOptimization */
  3649.         I915_WRITE(CACHE_MODE_1,
  3650.                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  3651.  
  3652.         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  3653.         snpcr &= ~GEN6_MBC_SNPCR_MASK;
  3654.         snpcr |= GEN6_MBC_SNPCR_MED;
  3655.         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  3656. }
  3657.  
  3658. static void valleyview_init_clock_gating(struct drm_device *dev)
  3659. {
  3660.         struct drm_i915_private *dev_priv = dev->dev_private;
  3661.         int pipe;
  3662.         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  3663.  
  3664.         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  3665.  
  3666.         I915_WRITE(WM3_LP_ILK, 0);
  3667.         I915_WRITE(WM2_LP_ILK, 0);
  3668.         I915_WRITE(WM1_LP_ILK, 0);
  3669.  
  3670.         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  3671.  
  3672.         I915_WRITE(IVB_CHICKEN3,
  3673.                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  3674.                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
  3675.  
  3676.         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
  3677.         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  3678.                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  3679.  
  3680.         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
  3681.         I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
  3682.         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
  3683.  
  3684.         /* This is required by WaCatErrorRejectionIssue */
  3685.         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  3686.                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  3687.                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  3688.  
  3689.         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  3690.                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
  3691.  
  3692.  
  3693.         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  3694.          * gating disable must be set.  Failure to set it results in
  3695.          * flickering pixels due to Z write ordering failures after
  3696.          * some amount of runtime in the Mesa "fire" demo, and Unigine
  3697.          * Sanctuary and Tropics, and apparently anything else with
  3698.          * alpha test or pixel discard.
  3699.          *
  3700.          * According to the spec, bit 11 (RCCUNIT) must also be set,
  3701.          * but we didn't debug actual testcases to find it out.
  3702.          *
  3703.          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  3704.          * This implements the WaDisableRCZUnitClockGating workaround.
  3705.          *
  3706.          * Also apply WaDisableVDSUnitClockGating and
  3707.          * WaDisableRCPBUnitClockGating.
  3708.          */
  3709.         I915_WRITE(GEN6_UCGCTL2,
  3710.                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
  3711.                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
  3712.                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
  3713.                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
  3714.                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  3715.  
  3716.         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
  3717.  
  3718.         for_each_pipe(pipe) {
  3719.                 I915_WRITE(DSPCNTR(pipe),
  3720.                            I915_READ(DSPCNTR(pipe)) |
  3721.                            DISPPLANE_TRICKLE_FEED_DISABLE);
  3722.                 intel_flush_display_plane(dev_priv, pipe);
  3723.         }
  3724.  
  3725.         I915_WRITE(CACHE_MODE_1,
  3726.                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  3727.  
  3728.         /*
  3729.          * On ValleyView, the GUnit needs to signal the GT
  3730.          * when flip and other events complete.  So enable
  3731.          * all the GUnit->GT interrupts here
  3732.          */
  3733.         I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
  3734.                    PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
  3735.                    SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
  3736.                    PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
  3737.                    PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
  3738.                    SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
  3739.                    PLANEA_FLIPDONE_INT_EN);
  3740. }
  3741.  
  3742. static void g4x_init_clock_gating(struct drm_device *dev)
  3743. {
  3744.         struct drm_i915_private *dev_priv = dev->dev_private;
  3745.         uint32_t dspclk_gate;
  3746.  
  3747.         I915_WRITE(RENCLK_GATE_D1, 0);
  3748.         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  3749.                    GS_UNIT_CLOCK_GATE_DISABLE |
  3750.                    CL_UNIT_CLOCK_GATE_DISABLE);
  3751.         I915_WRITE(RAMCLK_GATE_D, 0);
  3752.         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  3753.                 OVRUNIT_CLOCK_GATE_DISABLE |
  3754.                 OVCUNIT_CLOCK_GATE_DISABLE;
  3755.         if (IS_GM45(dev))
  3756.                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  3757.         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  3758. }
  3759.  
  3760. static void crestline_init_clock_gating(struct drm_device *dev)
  3761. {
  3762.         struct drm_i915_private *dev_priv = dev->dev_private;
  3763.  
  3764.         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  3765.         I915_WRITE(RENCLK_GATE_D2, 0);
  3766.         I915_WRITE(DSPCLK_GATE_D, 0);
  3767.         I915_WRITE(RAMCLK_GATE_D, 0);
  3768.         I915_WRITE16(DEUC, 0);
  3769. }
  3770.  
  3771. static void broadwater_init_clock_gating(struct drm_device *dev)
  3772. {
  3773.         struct drm_i915_private *dev_priv = dev->dev_private;
  3774.  
  3775.         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  3776.                    I965_RCC_CLOCK_GATE_DISABLE |
  3777.                    I965_RCPB_CLOCK_GATE_DISABLE |
  3778.                    I965_ISC_CLOCK_GATE_DISABLE |
  3779.                    I965_FBC_CLOCK_GATE_DISABLE);
  3780.         I915_WRITE(RENCLK_GATE_D2, 0);
  3781. }
  3782.  
  3783. static void gen3_init_clock_gating(struct drm_device *dev)
  3784. {
  3785.         struct drm_i915_private *dev_priv = dev->dev_private;
  3786.         u32 dstate = I915_READ(D_STATE);
  3787.  
  3788.         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  3789.                 DSTATE_DOT_CLOCK_GATING;
  3790.         I915_WRITE(D_STATE, dstate);
  3791.  
  3792.         if (IS_PINEVIEW(dev))
  3793.                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
  3794.  
  3795.         /* IIR "flip pending" means done if this bit is set */
  3796.         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
  3797. }
  3798.  
  3799. static void i85x_init_clock_gating(struct drm_device *dev)
  3800. {
  3801.         struct drm_i915_private *dev_priv = dev->dev_private;
  3802.  
  3803.         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  3804. }
  3805.  
  3806. static void i830_init_clock_gating(struct drm_device *dev)
  3807. {
  3808.         struct drm_i915_private *dev_priv = dev->dev_private;
  3809.  
  3810.         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  3811. }
  3812.  
  3813. static void ibx_init_clock_gating(struct drm_device *dev)
  3814. {
  3815.         struct drm_i915_private *dev_priv = dev->dev_private;
  3816.  
  3817.         /*
  3818.          * On Ibex Peak and Cougar Point, we need to disable clock
  3819.          * gating for the panel power sequencer or it will fail to
  3820.          * start up when no ports are active.
  3821.          */
  3822.         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  3823. }
  3824.  
  3825. static void cpt_init_clock_gating(struct drm_device *dev)
  3826. {
  3827.         struct drm_i915_private *dev_priv = dev->dev_private;
  3828.         int pipe;
  3829.  
  3830.         /*
  3831.          * On Ibex Peak and Cougar Point, we need to disable clock
  3832.          * gating for the panel power sequencer or it will fail to
  3833.          * start up when no ports are active.
  3834.          */
  3835.         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  3836.         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
  3837.                    DPLS_EDP_PPS_FIX_DIS);
  3838.         /* Without this, mode sets may fail silently on FDI */
  3839.         for_each_pipe(pipe)
  3840.                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
  3841. }
  3842.  
  3843. void intel_init_clock_gating(struct drm_device *dev)
  3844. {
  3845.         struct drm_i915_private *dev_priv = dev->dev_private;
  3846.  
  3847.         dev_priv->display.init_clock_gating(dev);
  3848.  
  3849.         if (dev_priv->display.init_pch_clock_gating)
  3850.                 dev_priv->display.init_pch_clock_gating(dev);
  3851. }
  3852.  
  3853. /* Starting with Haswell, we have different power wells for
  3854.  * different parts of the GPU. This attempts to enable them all.
  3855.  */
  3856. void intel_init_power_wells(struct drm_device *dev)
  3857. {
  3858.         struct drm_i915_private *dev_priv = dev->dev_private;
  3859.         unsigned long power_wells[] = {
  3860.                 HSW_PWR_WELL_CTL1,
  3861.                 HSW_PWR_WELL_CTL2,
  3862.                 HSW_PWR_WELL_CTL4
  3863.         };
  3864.         int i;
  3865.  
  3866.         if (!IS_HASWELL(dev))
  3867.                 return;
  3868.  
  3869.         mutex_lock(&dev->struct_mutex);
  3870.  
  3871.         for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
  3872.                 int well = I915_READ(power_wells[i]);
  3873.  
  3874.                 if ((well & HSW_PWR_WELL_STATE) == 0) {
  3875.                         I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
  3876.                         if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
  3877.                                 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
  3878.                 }
  3879.         }
  3880.  
  3881.         mutex_unlock(&dev->struct_mutex);
  3882. }
  3883.  
  3884. /* Set up chip specific power management-related functions */
  3885. void intel_init_pm(struct drm_device *dev)
  3886. {
  3887.         struct drm_i915_private *dev_priv = dev->dev_private;
  3888.  
  3889.         if (I915_HAS_FBC(dev)) {
  3890.                 if (HAS_PCH_SPLIT(dev)) {
  3891.                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
  3892.                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
  3893.                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
  3894.                 } else if (IS_GM45(dev)) {
  3895.                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  3896.                         dev_priv->display.enable_fbc = g4x_enable_fbc;
  3897.                         dev_priv->display.disable_fbc = g4x_disable_fbc;
  3898.                 } else if (IS_CRESTLINE(dev)) {
  3899.                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  3900.                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
  3901.                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
  3902.                 }
  3903.                 /* 855GM needs testing */
  3904.         }
  3905.  
  3906.         /* For cxsr */
  3907.         if (IS_PINEVIEW(dev))
  3908.                 i915_pineview_get_mem_freq(dev);
  3909.         else if (IS_GEN5(dev))
  3910.                 i915_ironlake_get_mem_freq(dev);
  3911.  
  3912.         /* For FIFO watermark updates */
  3913.         if (HAS_PCH_SPLIT(dev)) {
  3914.                 if (HAS_PCH_IBX(dev))
  3915.                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
  3916.                 else if (HAS_PCH_CPT(dev))
  3917.                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
  3918.  
  3919.                 if (IS_GEN5(dev)) {
  3920.                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  3921.                                 dev_priv->display.update_wm = ironlake_update_wm;
  3922.                         else {
  3923.                                 DRM_DEBUG_KMS("Failed to get proper latency. "
  3924.                                               "Disable CxSR\n");
  3925.                                 dev_priv->display.update_wm = NULL;
  3926.                         }
  3927.                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
  3928.                 } else if (IS_GEN6(dev)) {
  3929.                         if (SNB_READ_WM0_LATENCY()) {
  3930.                                 dev_priv->display.update_wm = sandybridge_update_wm;
  3931.                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  3932.                         } else {
  3933.                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
  3934.                                               "Disable CxSR\n");
  3935.                                 dev_priv->display.update_wm = NULL;
  3936.                         }
  3937.                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
  3938.                 } else if (IS_IVYBRIDGE(dev)) {
  3939.                         /* FIXME: detect B0+ stepping and use auto training */
  3940.                         if (SNB_READ_WM0_LATENCY()) {
  3941.                                 dev_priv->display.update_wm = sandybridge_update_wm;
  3942.                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  3943.                         } else {
  3944.                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
  3945.                                               "Disable CxSR\n");
  3946.                                 dev_priv->display.update_wm = NULL;
  3947.                         }
  3948.                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
  3949.                 } else if (IS_HASWELL(dev)) {
  3950.                         if (SNB_READ_WM0_LATENCY()) {
  3951.                                 dev_priv->display.update_wm = sandybridge_update_wm;
  3952.                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  3953.                                 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
  3954.                         } else {
  3955.                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
  3956.                                               "Disable CxSR\n");
  3957.                                 dev_priv->display.update_wm = NULL;
  3958.                         }
  3959.                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
  3960.                 } else
  3961.                         dev_priv->display.update_wm = NULL;
  3962.         } else if (IS_VALLEYVIEW(dev)) {
  3963.                 dev_priv->display.update_wm = valleyview_update_wm;
  3964.                 dev_priv->display.init_clock_gating =
  3965.                         valleyview_init_clock_gating;
  3966.         } else if (IS_PINEVIEW(dev)) {
  3967.                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  3968.                                             dev_priv->is_ddr3,
  3969.                                             dev_priv->fsb_freq,
  3970.                                             dev_priv->mem_freq)) {
  3971.                         DRM_INFO("failed to find known CxSR latency "
  3972.                                  "(found ddr%s fsb freq %d, mem freq %d), "
  3973.                                  "disabling CxSR\n",
  3974.                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
  3975.                                  dev_priv->fsb_freq, dev_priv->mem_freq);
  3976.                         /* Disable CxSR and never update its watermark again */
  3977.                         pineview_disable_cxsr(dev);
  3978.                         dev_priv->display.update_wm = NULL;
  3979.                 } else
  3980.                         dev_priv->display.update_wm = pineview_update_wm;
  3981.                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  3982.         } else if (IS_G4X(dev)) {
  3983.                 dev_priv->display.update_wm = g4x_update_wm;
  3984.                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
  3985.         } else if (IS_GEN4(dev)) {
  3986.                 dev_priv->display.update_wm = i965_update_wm;
  3987.                 if (IS_CRESTLINE(dev))
  3988.                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
  3989.                 else if (IS_BROADWATER(dev))
  3990.                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
  3991.         } else if (IS_GEN3(dev)) {
  3992.                 dev_priv->display.update_wm = i9xx_update_wm;
  3993.                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  3994.                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  3995.         } else if (IS_I865G(dev)) {
  3996.                 dev_priv->display.update_wm = i830_update_wm;
  3997.                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  3998.                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
  3999.         } else if (IS_I85X(dev)) {
  4000.                 dev_priv->display.update_wm = i9xx_update_wm;
  4001.                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  4002.                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  4003.         } else {
  4004.                 dev_priv->display.update_wm = i830_update_wm;
  4005.                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
  4006.                 if (IS_845G(dev))
  4007.                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
  4008.                 else
  4009.                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
  4010.         }
  4011. }
  4012.  
  4013. static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
  4014. {
  4015.         u32 gt_thread_status_mask;
  4016.  
  4017.         if (IS_HASWELL(dev_priv->dev))
  4018.                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
  4019.         else
  4020.                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
  4021.  
  4022.         /* w/a for a sporadic read returning 0 by waiting for the GT
  4023.          * thread to wake up.
  4024.          */
  4025.         if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
  4026.                 DRM_ERROR("GT thread status wait timed out\n");
  4027. }
  4028.  
  4029. static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  4030. {
  4031.         u32 forcewake_ack;
  4032.  
  4033.         if (IS_HASWELL(dev_priv->dev))
  4034.                 forcewake_ack = FORCEWAKE_ACK_HSW;
  4035.         else
  4036.                 forcewake_ack = FORCEWAKE_ACK;
  4037.  
  4038.         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
  4039.                             FORCEWAKE_ACK_TIMEOUT_MS))
  4040.                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
  4041.  
  4042.         I915_WRITE_NOTRACE(FORCEWAKE, 1);
  4043.         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
  4044.  
  4045.         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
  4046.                             FORCEWAKE_ACK_TIMEOUT_MS))
  4047.                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
  4048.  
  4049.         __gen6_gt_wait_for_thread_c0(dev_priv);
  4050. }
  4051.  
  4052. static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
  4053. {
  4054.         u32 forcewake_ack;
  4055.  
  4056.         if (IS_HASWELL(dev_priv->dev))
  4057.                 forcewake_ack = FORCEWAKE_ACK_HSW;
  4058.         else
  4059.                 forcewake_ack = FORCEWAKE_MT_ACK;
  4060.  
  4061.         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
  4062.                             FORCEWAKE_ACK_TIMEOUT_MS))
  4063.                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
  4064.  
  4065.         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
  4066.         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
  4067.  
  4068.         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
  4069.                             FORCEWAKE_ACK_TIMEOUT_MS))
  4070.                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
  4071.  
  4072.         __gen6_gt_wait_for_thread_c0(dev_priv);
  4073. }
  4074.  
  4075. /*
  4076.  * Generally this is called implicitly by the register read function. However,
  4077.  * if some sequence requires the GT to not power down then this function should
  4078.  * be called at the beginning of the sequence followed by a call to
  4079.  * gen6_gt_force_wake_put() at the end of the sequence.
  4080.  */
  4081. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  4082. {
  4083.         unsigned long irqflags;
  4084.  
  4085.         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
  4086.         if (dev_priv->forcewake_count++ == 0)
  4087.                 dev_priv->gt.force_wake_get(dev_priv);
  4088.         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
  4089. }
  4090.  
  4091. void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
  4092. {
  4093.         u32 gtfifodbg;
  4094.         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
  4095.         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
  4096.              "MMIO read or write has been dropped %x\n", gtfifodbg))
  4097.                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
  4098. }
  4099.  
  4100. static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  4101. {
  4102.         I915_WRITE_NOTRACE(FORCEWAKE, 0);
  4103.         /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
  4104.         gen6_gt_check_fifodbg(dev_priv);
  4105. }
  4106.  
  4107. static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
  4108. {
  4109.         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
  4110.         /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
  4111.         gen6_gt_check_fifodbg(dev_priv);
  4112. }
  4113.  
  4114. /*
  4115.  * see gen6_gt_force_wake_get()
  4116.  */
  4117. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  4118. {
  4119.         unsigned long irqflags;
  4120.  
  4121.         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
  4122.         if (--dev_priv->forcewake_count == 0)
  4123.                 dev_priv->gt.force_wake_put(dev_priv);
  4124.         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
  4125. }
  4126.  
  4127. int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
  4128. {
  4129.         int ret = 0;
  4130.  
  4131.         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
  4132.                 int loop = 500;
  4133.                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  4134.                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
  4135.                         udelay(10);
  4136.                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  4137.                 }
  4138.                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
  4139.                         ++ret;
  4140.                 dev_priv->gt_fifo_count = fifo;
  4141.         }
  4142.         dev_priv->gt_fifo_count--;
  4143.  
  4144.         return ret;
  4145. }
  4146.  
  4147. static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
  4148. {
  4149.         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
  4150.                             FORCEWAKE_ACK_TIMEOUT_MS))
  4151.                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
  4152.  
  4153.         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(1));
  4154.  
  4155.         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
  4156.                             FORCEWAKE_ACK_TIMEOUT_MS))
  4157.                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
  4158.  
  4159.         __gen6_gt_wait_for_thread_c0(dev_priv);
  4160. }
  4161.  
  4162. static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
  4163. {
  4164.         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(1));
  4165.         /* The below doubles as a POSTING_READ */
  4166.         gen6_gt_check_fifodbg(dev_priv);
  4167. }
  4168.  
  4169. void intel_gt_init(struct drm_device *dev)
  4170. {
  4171.         struct drm_i915_private *dev_priv = dev->dev_private;
  4172.  
  4173.         spin_lock_init(&dev_priv->gt_lock);
  4174.  
  4175.         if (IS_VALLEYVIEW(dev)) {
  4176.                 dev_priv->gt.force_wake_get = vlv_force_wake_get;
  4177.                 dev_priv->gt.force_wake_put = vlv_force_wake_put;
  4178.         } else if (INTEL_INFO(dev)->gen >= 6) {
  4179.                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
  4180.                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
  4181.  
  4182.                 /* IVB configs may use multi-threaded forcewake */
  4183.                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  4184.                         u32 ecobus;
  4185.  
  4186.                         /* A small trick here - if the bios hasn't configured
  4187.                          * MT forcewake, and if the device is in RC6, then
  4188.                          * force_wake_mt_get will not wake the device and the
  4189.                          * ECOBUS read will return zero. Which will be
  4190.                          * (correctly) interpreted by the test below as MT
  4191.                          * forcewake being disabled.
  4192.                          */
  4193.                         mutex_lock(&dev->struct_mutex);
  4194.                         __gen6_gt_force_wake_mt_get(dev_priv);
  4195.                         ecobus = I915_READ_NOTRACE(ECOBUS);
  4196.                         __gen6_gt_force_wake_mt_put(dev_priv);
  4197.                         mutex_unlock(&dev->struct_mutex);
  4198.  
  4199.                         if (ecobus & FORCEWAKE_MT_ENABLE) {
  4200.                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
  4201.                                 dev_priv->gt.force_wake_get =
  4202.                                         __gen6_gt_force_wake_mt_get;
  4203.                                 dev_priv->gt.force_wake_put =
  4204.                                         __gen6_gt_force_wake_mt_put;
  4205.                         }
  4206.                 }
  4207.         }
  4208. }
  4209.  
  4210.