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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright © 2006-2008,2010 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23.  * DEALINGS IN THE SOFTWARE.
  24.  *
  25.  * Authors:
  26.  *      Eric Anholt <eric@anholt.net>
  27.  *      Chris Wilson <chris@chris-wilson.co.uk>
  28.  */
  29. #include <linux/i2c.h>
  30. #include <linux/i2c-algo-bit.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "intel_drv.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36.  
  37. #define MSEC_PER_SEC    1000L
  38. #define USEC_PER_MSEC   1000L
  39. #define NSEC_PER_USEC   1000L
  40. #define NSEC_PER_MSEC   1000000L
  41. #define USEC_PER_SEC    1000000L
  42. #define NSEC_PER_SEC    1000000000L
  43. #define FSEC_PER_SEC    1000000000000000L
  44.  
  45. #define HZ_TO_MSEC_MUL32 0xA0000000
  46. #define HZ_TO_MSEC_ADJ32 0x0
  47. #define HZ_TO_MSEC_SHR32 28
  48. #define HZ_TO_MSEC_MUL64 0xA000000000000000
  49. #define HZ_TO_MSEC_ADJ64 0x0
  50. #define HZ_TO_MSEC_SHR64 60
  51. #define MSEC_TO_HZ_MUL32 0xCCCCCCCD
  52. #define MSEC_TO_HZ_ADJ32 0x733333333
  53. #define MSEC_TO_HZ_SHR32 35
  54. #define MSEC_TO_HZ_MUL64 0xCCCCCCCCCCCCCCCD
  55. #define MSEC_TO_HZ_ADJ64 0x73333333333333333
  56. #define MSEC_TO_HZ_SHR64 67
  57. #define HZ_TO_MSEC_NUM 10
  58. #define HZ_TO_MSEC_DEN 1
  59. #define MSEC_TO_HZ_NUM 1
  60. #define MSEC_TO_HZ_DEN 10
  61.  
  62. #define HZ_TO_USEC_MUL32 0x9C400000
  63. #define HZ_TO_USEC_ADJ32 0x0
  64. #define HZ_TO_USEC_SHR32 18
  65. #define HZ_TO_USEC_MUL64 0x9C40000000000000
  66. #define HZ_TO_USEC_ADJ64 0x0
  67. #define HZ_TO_USEC_SHR64 50
  68. #define USEC_TO_HZ_MUL32 0xD1B71759
  69. #define USEC_TO_HZ_ADJ32 0x1FFF2E48E8A7
  70. #define USEC_TO_HZ_SHR32 45
  71. #define USEC_TO_HZ_MUL64 0xD1B71758E219652C
  72. #define USEC_TO_HZ_ADJ64 0x1FFF2E48E8A71DE69AD4
  73. #define USEC_TO_HZ_SHR64 77
  74. #define HZ_TO_USEC_NUM 10000
  75. #define HZ_TO_USEC_DEN 1
  76. #define USEC_TO_HZ_NUM 1
  77. #define USEC_TO_HZ_DEN 10000
  78.  
  79. unsigned int inline jiffies_to_usecs(const unsigned long j)
  80. {
  81. #if HZ <= USEC_PER_SEC && !(USEC_PER_SEC % HZ)
  82.         return (USEC_PER_SEC / HZ) * j;
  83. #elif HZ > USEC_PER_SEC && !(HZ % USEC_PER_SEC)
  84.         return (j + (HZ / USEC_PER_SEC) - 1)/(HZ / USEC_PER_SEC);
  85. #else
  86. # if BITS_PER_LONG == 32
  87.         return (HZ_TO_USEC_MUL32 * j) >> HZ_TO_USEC_SHR32;
  88. # else
  89.         return (j * HZ_TO_USEC_NUM) / HZ_TO_USEC_DEN;
  90. # endif
  91. #endif
  92. }
  93.  
  94. /*
  95. * When we convert to jiffies then we interpret incoming values
  96. * the following way:
  97. *
  98. * - negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET)
  99. *
  100. * - 'too large' values [that would result in larger than
  101. *   MAX_JIFFY_OFFSET values] mean 'infinite timeout' too.
  102. *
  103. * - all other values are converted to jiffies by either multiplying
  104. *   the input value by a factor or dividing it with a factor
  105. *
  106. * We must also be careful about 32-bit overflows.
  107. */
  108. unsigned long msecs_to_jiffies(const unsigned int m)
  109. {
  110.         /*
  111.          * Negative value, means infinite timeout:
  112.          */
  113.         if ((int)m < 0)
  114.                 return MAX_JIFFY_OFFSET;
  115.  
  116. #if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)
  117.         /*
  118.          * HZ is equal to or smaller than 1000, and 1000 is a nice
  119.          * round multiple of HZ, divide with the factor between them,
  120.          * but round upwards:
  121.          */
  122.         return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ);
  123. #elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)
  124.         /*
  125.          * HZ is larger than 1000, and HZ is a nice round multiple of
  126.          * 1000 - simply multiply with the factor between them.
  127.          *
  128.          * But first make sure the multiplication result cannot
  129.          * overflow:
  130.          */
  131.         if (m > jiffies_to_msecs(MAX_JIFFY_OFFSET))
  132.                 return MAX_JIFFY_OFFSET;
  133.  
  134.         return m * (HZ / MSEC_PER_SEC);
  135. #else
  136.         /*
  137.          * Generic case - multiply, round and divide. But first
  138.          * check that if we are doing a net multiplication, that
  139.          * we wouldn't overflow:
  140.          */
  141.         if (HZ > MSEC_PER_SEC && m > jiffies_to_msecs(MAX_JIFFY_OFFSET))
  142.                 return MAX_JIFFY_OFFSET;
  143.  
  144.         return (MSEC_TO_HZ_MUL32 * m + MSEC_TO_HZ_ADJ32)
  145.                 >> MSEC_TO_HZ_SHR32;
  146. #endif
  147. }
  148.  
  149. unsigned long usecs_to_jiffies(const unsigned int u)
  150. {
  151.         if (u > jiffies_to_usecs(MAX_JIFFY_OFFSET))
  152.                 return MAX_JIFFY_OFFSET;
  153. #if HZ <= USEC_PER_SEC && !(USEC_PER_SEC % HZ)
  154.         return (u + (USEC_PER_SEC / HZ) - 1) / (USEC_PER_SEC / HZ);
  155. #elif HZ > USEC_PER_SEC && !(HZ % USEC_PER_SEC)
  156.         return u * (HZ / USEC_PER_SEC);
  157. #else
  158.         return (USEC_TO_HZ_MUL32 * u + USEC_TO_HZ_ADJ32)
  159.                 >> USEC_TO_HZ_SHR32;
  160. #endif
  161. }
  162.  
  163.  
  164.  
  165. /* Intel GPIO access functions */
  166.  
  167. #define I2C_RISEFALL_TIME 20
  168.  
  169. static inline struct intel_gmbus *
  170. to_intel_gmbus(struct i2c_adapter *i2c)
  171. {
  172.         return container_of(i2c, struct intel_gmbus, adapter);
  173. }
  174.  
  175. struct intel_gpio {
  176.         struct i2c_adapter adapter;
  177.         struct i2c_algo_bit_data algo;
  178.         struct drm_i915_private *dev_priv;
  179.         u32 reg;
  180. };
  181.  
  182. void
  183. intel_i2c_reset(struct drm_device *dev)
  184. {
  185.         struct drm_i915_private *dev_priv = dev->dev_private;
  186.         if (HAS_PCH_SPLIT(dev))
  187.                 I915_WRITE(PCH_GMBUS0, 0);
  188.         else
  189.                 I915_WRITE(GMBUS0, 0);
  190. }
  191.  
  192. static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  193. {
  194.         u32 val;
  195.  
  196.         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  197.         if (!IS_PINEVIEW(dev_priv->dev))
  198.                 return;
  199.  
  200.         val = I915_READ(DSPCLK_GATE_D);
  201.         if (enable)
  202.                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  203.         else
  204.                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  205.         I915_WRITE(DSPCLK_GATE_D, val);
  206. }
  207.  
  208. static u32 get_reserved(struct intel_gpio *gpio)
  209. {
  210.         struct drm_i915_private *dev_priv = gpio->dev_priv;
  211.         struct drm_device *dev = dev_priv->dev;
  212.         u32 reserved = 0;
  213.  
  214.         /* On most chips, these bits must be preserved in software. */
  215.         if (!IS_I830(dev) && !IS_845G(dev))
  216.                 reserved = I915_READ_NOTRACE(gpio->reg) &
  217.                                              (GPIO_DATA_PULLUP_DISABLE |
  218.                                               GPIO_CLOCK_PULLUP_DISABLE);
  219.  
  220.         return reserved;
  221. }
  222.  
  223. static int get_clock(void *data)
  224. {
  225.         struct intel_gpio *gpio = data;
  226.         struct drm_i915_private *dev_priv = gpio->dev_priv;
  227.         u32 reserved = get_reserved(gpio);
  228.         I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
  229.         I915_WRITE_NOTRACE(gpio->reg, reserved);
  230.         return (I915_READ_NOTRACE(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
  231. }
  232.  
  233. static int get_data(void *data)
  234. {
  235.         struct intel_gpio *gpio = data;
  236.         struct drm_i915_private *dev_priv = gpio->dev_priv;
  237.         u32 reserved = get_reserved(gpio);
  238.         I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
  239.         I915_WRITE_NOTRACE(gpio->reg, reserved);
  240.         return (I915_READ_NOTRACE(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
  241. }
  242.  
  243. static void set_clock(void *data, int state_high)
  244. {
  245.         struct intel_gpio *gpio = data;
  246.         struct drm_i915_private *dev_priv = gpio->dev_priv;
  247.         u32 reserved = get_reserved(gpio);
  248.         u32 clock_bits;
  249.  
  250.         if (state_high)
  251.                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
  252.         else
  253.                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
  254.                         GPIO_CLOCK_VAL_MASK;
  255.  
  256.         I915_WRITE_NOTRACE(gpio->reg, reserved | clock_bits);
  257.         POSTING_READ(gpio->reg);
  258. }
  259.  
  260. static void set_data(void *data, int state_high)
  261. {
  262.         struct intel_gpio *gpio = data;
  263.         struct drm_i915_private *dev_priv = gpio->dev_priv;
  264.         u32 reserved = get_reserved(gpio);
  265.         u32 data_bits;
  266.  
  267.         if (state_high)
  268.                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
  269.         else
  270.                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
  271.                         GPIO_DATA_VAL_MASK;
  272.  
  273.         I915_WRITE_NOTRACE(gpio->reg, reserved | data_bits);
  274.         POSTING_READ(gpio->reg);
  275. }
  276.  
  277. static struct i2c_adapter *
  278. intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
  279. {
  280.         static const int map_pin_to_reg[] = {
  281.                 0,
  282.                 GPIOB,
  283.                 GPIOA,
  284.                 GPIOC,
  285.                 GPIOD,
  286.                 GPIOE,
  287.                 0,
  288.                 GPIOF,
  289.         };
  290.         struct intel_gpio *gpio;
  291.  
  292.         if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
  293.                 return NULL;
  294.  
  295.         gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
  296.         if (gpio == NULL)
  297.                 return NULL;
  298.  
  299.         gpio->reg = map_pin_to_reg[pin];
  300.         if (HAS_PCH_SPLIT(dev_priv->dev))
  301.                 gpio->reg += PCH_GPIOA - GPIOA;
  302.         gpio->dev_priv = dev_priv;
  303.  
  304.         snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
  305.                  "i915 GPIO%c", "?BACDE?F"[pin]);
  306. //   gpio->adapter.owner = THIS_MODULE;
  307.         gpio->adapter.algo_data = &gpio->algo;
  308.         gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
  309.         gpio->algo.setsda = set_data;
  310.         gpio->algo.setscl = set_clock;
  311.         gpio->algo.getsda = get_data;
  312.         gpio->algo.getscl = get_clock;
  313.         gpio->algo.udelay = I2C_RISEFALL_TIME;
  314.         gpio->algo.timeout = usecs_to_jiffies(2200);
  315.         gpio->algo.data = gpio;
  316.  
  317.     if (i2c_bit_add_bus(&gpio->adapter))
  318.        goto out_free;
  319.  
  320.         return &gpio->adapter;
  321.  
  322. out_free:
  323.         kfree(gpio);
  324.         return NULL;
  325. }
  326.  
  327. static int
  328. intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
  329.                      struct i2c_adapter *adapter,
  330.                      struct i2c_msg *msgs,
  331.                      int num)
  332. {
  333.         struct intel_gpio *gpio = container_of(adapter,
  334.                                                struct intel_gpio,
  335.                                                adapter);
  336.         int ret;
  337.  
  338.         intel_i2c_reset(dev_priv->dev);
  339.  
  340.         intel_i2c_quirk_set(dev_priv, true);
  341.         set_data(gpio, 1);
  342.         set_clock(gpio, 1);
  343.         udelay(I2C_RISEFALL_TIME);
  344.  
  345.         ret = adapter->algo->master_xfer(adapter, msgs, num);
  346.  
  347.         set_data(gpio, 1);
  348.         set_clock(gpio, 1);
  349.         intel_i2c_quirk_set(dev_priv, false);
  350.  
  351.         return ret;
  352. }
  353.  
  354. static int
  355. gmbus_xfer(struct i2c_adapter *adapter,
  356.            struct i2c_msg *msgs,
  357.            int num)
  358. {
  359.         struct intel_gmbus *bus = container_of(adapter,
  360.                                                struct intel_gmbus,
  361.                                                adapter);
  362.         struct drm_i915_private *dev_priv = adapter->algo_data;
  363.         int i, reg_offset;
  364.  
  365.         if (bus->force_bit)
  366.                 return intel_i2c_quirk_xfer(dev_priv,
  367.                                             bus->force_bit, msgs, num);
  368.  
  369.         reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
  370.  
  371.         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
  372.  
  373.         for (i = 0; i < num; i++) {
  374.                 u16 len = msgs[i].len;
  375.                 u8 *buf = msgs[i].buf;
  376.  
  377.                 if (msgs[i].flags & I2C_M_RD) {
  378.                         I915_WRITE(GMBUS1 + reg_offset,
  379.                                    GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
  380.                                    (len << GMBUS_BYTE_COUNT_SHIFT) |
  381.                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
  382.                                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
  383.                         POSTING_READ(GMBUS2+reg_offset);
  384.                         do {
  385.                                 u32 val, loop = 0;
  386.  
  387.                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
  388.                                         goto timeout;
  389.                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
  390.                                         goto clear_err;
  391.  
  392.                                 val = I915_READ(GMBUS3 + reg_offset);
  393.                                 do {
  394.                                         *buf++ = val & 0xff;
  395.                                         val >>= 8;
  396.                                 } while (--len && ++loop < 4);
  397.                         } while (len);
  398.                 } else {
  399.                         u32 val, loop;
  400.  
  401.                         val = loop = 0;
  402.                         do {
  403.                                 val |= *buf++ << (8 * loop);
  404.                         } while (--len && ++loop < 4);
  405.  
  406.                         I915_WRITE(GMBUS3 + reg_offset, val);
  407.                         I915_WRITE(GMBUS1 + reg_offset,
  408.                                    (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
  409.                                    (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
  410.                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
  411.                                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
  412.                         POSTING_READ(GMBUS2+reg_offset);
  413.  
  414.                         while (len) {
  415.                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
  416.                                         goto timeout;
  417.                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
  418.                                         goto clear_err;
  419.  
  420.                                 val = loop = 0;
  421.                                 do {
  422.                                         val |= *buf++ << (8 * loop);
  423.                                 } while (--len && ++loop < 4);
  424.  
  425.                                 I915_WRITE(GMBUS3 + reg_offset, val);
  426.                                 POSTING_READ(GMBUS2+reg_offset);
  427.                         }
  428.                 }
  429.  
  430.                 if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
  431.                         goto timeout;
  432.                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
  433.                         goto clear_err;
  434.         }
  435.  
  436.         goto done;
  437.  
  438. clear_err:
  439.         /* Toggle the Software Clear Interrupt bit. This has the effect
  440.          * of resetting the GMBUS controller and so clearing the
  441.          * BUS_ERROR raised by the slave's NAK.
  442.          */
  443.         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
  444.         I915_WRITE(GMBUS1 + reg_offset, 0);
  445.  
  446. done:
  447.         /* Mark the GMBUS interface as disabled. We will re-enable it at the
  448.          * start of the next xfer, till then let it sleep.
  449.          */
  450.         I915_WRITE(GMBUS0 + reg_offset, 0);
  451.         return i;
  452.  
  453. timeout:
  454.         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
  455.                  bus->reg0 & 0xff, bus->adapter.name);
  456.         I915_WRITE(GMBUS0 + reg_offset, 0);
  457.  
  458.         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
  459.         bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
  460.         if (!bus->force_bit)
  461.                 return -ENOMEM;
  462.  
  463.         return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
  464. }
  465.  
  466. static u32 gmbus_func(struct i2c_adapter *adapter)
  467. {
  468.         struct intel_gmbus *bus = container_of(adapter,
  469.                                                struct intel_gmbus,
  470.                                                adapter);
  471.  
  472.         if (bus->force_bit)
  473.                 bus->force_bit->algo->functionality(bus->force_bit);
  474.  
  475.         return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
  476.                 /* I2C_FUNC_10BIT_ADDR | */
  477.                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
  478.                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
  479. }
  480.  
  481. static const struct i2c_algorithm gmbus_algorithm = {
  482.         .master_xfer    = gmbus_xfer,
  483.         .functionality  = gmbus_func
  484. };
  485.  
  486. /**
  487.  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
  488.  * @dev: DRM device
  489.  */
  490. int intel_setup_gmbus(struct drm_device *dev)
  491. {
  492.         static const char *names[GMBUS_NUM_PORTS] = {
  493.                 "disabled",
  494.                 "ssc",
  495.                 "vga",
  496.                 "panel",
  497.                 "dpc",
  498.                 "dpb",
  499.                 "reserved",
  500.                 "dpd",
  501.         };
  502.         struct drm_i915_private *dev_priv = dev->dev_private;
  503.         int ret, i;
  504.  
  505.         dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
  506.                                   GFP_KERNEL);
  507.         if (dev_priv->gmbus == NULL)
  508.                 return -ENOMEM;
  509.  
  510.         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  511.                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
  512.  
  513. //       bus->adapter.owner = THIS_MODULE;
  514.                 bus->adapter.class = I2C_CLASS_DDC;
  515.                 snprintf(bus->adapter.name,
  516.                          sizeof(bus->adapter.name),
  517.                          "i915 gmbus %s",
  518.                          names[i]);
  519.  
  520.                 bus->adapter.dev.parent = &dev->pdev->dev;
  521.                 bus->adapter.algo_data  = dev_priv;
  522.  
  523.                 bus->adapter.algo = &gmbus_algorithm;
  524. //       ret = i2c_add_adapter(&bus->adapter);
  525. //       if (ret)
  526. //           goto err;
  527.  
  528.                 /* By default use a conservative clock rate */
  529.                 bus->reg0 = i | GMBUS_RATE_100KHZ;
  530.  
  531.                 /* XXX force bit banging until GMBUS is fully debugged */
  532.                 bus->force_bit = intel_gpio_create(dev_priv, i);
  533.         }
  534.  
  535.         intel_i2c_reset(dev_priv->dev);
  536.  
  537.         return 0;
  538.  
  539. err:
  540. //   while (--i) {
  541. //       struct intel_gmbus *bus = &dev_priv->gmbus[i];
  542. //       i2c_del_adapter(&bus->adapter);
  543. //   }
  544.         kfree(dev_priv->gmbus);
  545.         dev_priv->gmbus = NULL;
  546.         return ret;
  547. }
  548.  
  549. void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
  550. {
  551.         struct intel_gmbus *bus = to_intel_gmbus(adapter);
  552.  
  553.         /* speed:
  554.          * 0x0 = 100 KHz
  555.          * 0x1 = 50 KHz
  556.          * 0x2 = 400 KHz
  557.          * 0x3 = 1000 Khz
  558.          */
  559.         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
  560. }
  561.  
  562. void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
  563. {
  564.         struct intel_gmbus *bus = to_intel_gmbus(adapter);
  565.  
  566.         if (force_bit) {
  567.                 if (bus->force_bit == NULL) {
  568.                         struct drm_i915_private *dev_priv = adapter->algo_data;
  569.                         bus->force_bit = intel_gpio_create(dev_priv,
  570.                                                            bus->reg0 & 0xff);
  571.                 }
  572.         } else {
  573.                 if (bus->force_bit) {
  574. //           i2c_del_adapter(bus->force_bit);
  575.                         kfree(bus->force_bit);
  576.                         bus->force_bit = NULL;
  577.                 }
  578.         }
  579. }
  580.  
  581. void intel_teardown_gmbus(struct drm_device *dev)
  582. {
  583.         struct drm_i915_private *dev_priv = dev->dev_private;
  584.         int i;
  585.  
  586.         if (dev_priv->gmbus == NULL)
  587.                 return;
  588.  
  589.         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  590.                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
  591.                 if (bus->force_bit) {
  592. //           i2c_del_adapter(bus->force_bit);
  593.                         kfree(bus->force_bit);
  594.                 }
  595. //       i2c_del_adapter(&bus->adapter);
  596.         }
  597.  
  598.         kfree(dev_priv->gmbus);
  599.         dev_priv->gmbus = NULL;
  600. }
  601.