Subversion Repositories Kolibri OS

Rev

Rev 6937 | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright © 2006-2009 Intel Corporation
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the "Software"),
  7.  * to deal in the Software without restriction, including without limitation
  8.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9.  * and/or sell copies of the Software, and to permit persons to whom the
  10.  * Software is furnished to do so, subject to the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the next
  13.  * paragraph) shall be included in all copies or substantial portions of the
  14.  * Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22.  * DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *      Eric Anholt <eric@anholt.net>
  26.  *      Jesse Barnes <jesse.barnes@intel.com>
  27.  */
  28.  
  29. #include <linux/i2c.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include <linux/hdmi.h>
  33. #include <drm/drmP.h>
  34. #include <drm/drm_atomic_helper.h>
  35. #include <drm/drm_crtc.h>
  36. #include <drm/drm_edid.h>
  37. #include "intel_drv.h"
  38. #include <drm/i915_drm.h>
  39. #include "i915_drv.h"
  40.  
  41. static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  42. {
  43.         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  44. }
  45.  
  46. static void
  47. assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  48. {
  49.         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  50.         struct drm_i915_private *dev_priv = dev->dev_private;
  51.         uint32_t enabled_bits;
  52.  
  53.         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  54.  
  55.         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  56.              "HDMI port enabled, expecting disabled\n");
  57. }
  58.  
  59. struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  60. {
  61.         struct intel_digital_port *intel_dig_port =
  62.                 container_of(encoder, struct intel_digital_port, base.base);
  63.         return &intel_dig_port->hdmi;
  64. }
  65.  
  66. static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  67. {
  68.         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  69. }
  70.  
  71. static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  72. {
  73.         switch (type) {
  74.         case HDMI_INFOFRAME_TYPE_AVI:
  75.                 return VIDEO_DIP_SELECT_AVI;
  76.         case HDMI_INFOFRAME_TYPE_SPD:
  77.                 return VIDEO_DIP_SELECT_SPD;
  78.         case HDMI_INFOFRAME_TYPE_VENDOR:
  79.                 return VIDEO_DIP_SELECT_VENDOR;
  80.         default:
  81.                 MISSING_CASE(type);
  82.                 return 0;
  83.         }
  84. }
  85.  
  86. static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  87. {
  88.         switch (type) {
  89.         case HDMI_INFOFRAME_TYPE_AVI:
  90.                 return VIDEO_DIP_ENABLE_AVI;
  91.         case HDMI_INFOFRAME_TYPE_SPD:
  92.                 return VIDEO_DIP_ENABLE_SPD;
  93.         case HDMI_INFOFRAME_TYPE_VENDOR:
  94.                 return VIDEO_DIP_ENABLE_VENDOR;
  95.         default:
  96.                 MISSING_CASE(type);
  97.                 return 0;
  98.         }
  99. }
  100.  
  101. static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
  102. {
  103.         switch (type) {
  104.         case HDMI_INFOFRAME_TYPE_AVI:
  105.                 return VIDEO_DIP_ENABLE_AVI_HSW;
  106.         case HDMI_INFOFRAME_TYPE_SPD:
  107.                 return VIDEO_DIP_ENABLE_SPD_HSW;
  108.         case HDMI_INFOFRAME_TYPE_VENDOR:
  109.                 return VIDEO_DIP_ENABLE_VS_HSW;
  110.         default:
  111.                 MISSING_CASE(type);
  112.                 return 0;
  113.         }
  114. }
  115.  
  116. static i915_reg_t
  117. hsw_dip_data_reg(struct drm_i915_private *dev_priv,
  118.                  enum transcoder cpu_transcoder,
  119.                  enum hdmi_infoframe_type type,
  120.                  int i)
  121. {
  122.         switch (type) {
  123.         case HDMI_INFOFRAME_TYPE_AVI:
  124.                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
  125.         case HDMI_INFOFRAME_TYPE_SPD:
  126.                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
  127.         case HDMI_INFOFRAME_TYPE_VENDOR:
  128.                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
  129.         default:
  130.                 MISSING_CASE(type);
  131.                 return INVALID_MMIO_REG;
  132.         }
  133. }
  134.  
  135. static void g4x_write_infoframe(struct drm_encoder *encoder,
  136.                                 enum hdmi_infoframe_type type,
  137.                                 const void *frame, ssize_t len)
  138. {
  139.         const uint32_t *data = frame;
  140.         struct drm_device *dev = encoder->dev;
  141.         struct drm_i915_private *dev_priv = dev->dev_private;
  142.         u32 val = I915_READ(VIDEO_DIP_CTL);
  143.         int i;
  144.  
  145.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  146.  
  147.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  148.         val |= g4x_infoframe_index(type);
  149.  
  150.         val &= ~g4x_infoframe_enable(type);
  151.  
  152.         I915_WRITE(VIDEO_DIP_CTL, val);
  153.  
  154.         mmiowb();
  155.         for (i = 0; i < len; i += 4) {
  156.                 I915_WRITE(VIDEO_DIP_DATA, *data);
  157.                 data++;
  158.         }
  159.         /* Write every possible data byte to force correct ECC calculation. */
  160.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  161.                 I915_WRITE(VIDEO_DIP_DATA, 0);
  162.         mmiowb();
  163.  
  164.         val |= g4x_infoframe_enable(type);
  165.         val &= ~VIDEO_DIP_FREQ_MASK;
  166.         val |= VIDEO_DIP_FREQ_VSYNC;
  167.  
  168.         I915_WRITE(VIDEO_DIP_CTL, val);
  169.         POSTING_READ(VIDEO_DIP_CTL);
  170. }
  171.  
  172. static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
  173.                                   const struct intel_crtc_state *pipe_config)
  174. {
  175.         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
  176.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  177.         u32 val = I915_READ(VIDEO_DIP_CTL);
  178.  
  179.         if ((val & VIDEO_DIP_ENABLE) == 0)
  180.                 return false;
  181.  
  182.         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
  183.                 return false;
  184.  
  185.         return val & (VIDEO_DIP_ENABLE_AVI |
  186.                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
  187. }
  188.  
  189. static void ibx_write_infoframe(struct drm_encoder *encoder,
  190.                                 enum hdmi_infoframe_type type,
  191.                                 const void *frame, ssize_t len)
  192. {
  193.         const uint32_t *data = frame;
  194.         struct drm_device *dev = encoder->dev;
  195.         struct drm_i915_private *dev_priv = dev->dev_private;
  196.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  197.         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  198.         u32 val = I915_READ(reg);
  199.         int i;
  200.  
  201.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  202.  
  203.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  204.         val |= g4x_infoframe_index(type);
  205.  
  206.         val &= ~g4x_infoframe_enable(type);
  207.  
  208.         I915_WRITE(reg, val);
  209.  
  210.         mmiowb();
  211.         for (i = 0; i < len; i += 4) {
  212.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  213.                 data++;
  214.         }
  215.         /* Write every possible data byte to force correct ECC calculation. */
  216.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  217.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  218.         mmiowb();
  219.  
  220.         val |= g4x_infoframe_enable(type);
  221.         val &= ~VIDEO_DIP_FREQ_MASK;
  222.         val |= VIDEO_DIP_FREQ_VSYNC;
  223.  
  224.         I915_WRITE(reg, val);
  225.         POSTING_READ(reg);
  226. }
  227.  
  228. static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
  229.                                   const struct intel_crtc_state *pipe_config)
  230. {
  231.         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
  232.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  233.         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
  234.         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
  235.         u32 val = I915_READ(reg);
  236.  
  237.         if ((val & VIDEO_DIP_ENABLE) == 0)
  238.                 return false;
  239.  
  240.         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
  241.                 return false;
  242.  
  243.         return val & (VIDEO_DIP_ENABLE_AVI |
  244.                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  245.                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  246. }
  247.  
  248. static void cpt_write_infoframe(struct drm_encoder *encoder,
  249.                                 enum hdmi_infoframe_type type,
  250.                                 const void *frame, ssize_t len)
  251. {
  252.         const uint32_t *data = frame;
  253.         struct drm_device *dev = encoder->dev;
  254.         struct drm_i915_private *dev_priv = dev->dev_private;
  255.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  256.         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  257.         u32 val = I915_READ(reg);
  258.         int i;
  259.  
  260.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  261.  
  262.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  263.         val |= g4x_infoframe_index(type);
  264.  
  265.         /* The DIP control register spec says that we need to update the AVI
  266.          * infoframe without clearing its enable bit */
  267.         if (type != HDMI_INFOFRAME_TYPE_AVI)
  268.                 val &= ~g4x_infoframe_enable(type);
  269.  
  270.         I915_WRITE(reg, val);
  271.  
  272.         mmiowb();
  273.         for (i = 0; i < len; i += 4) {
  274.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  275.                 data++;
  276.         }
  277.         /* Write every possible data byte to force correct ECC calculation. */
  278.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  279.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  280.         mmiowb();
  281.  
  282.         val |= g4x_infoframe_enable(type);
  283.         val &= ~VIDEO_DIP_FREQ_MASK;
  284.         val |= VIDEO_DIP_FREQ_VSYNC;
  285.  
  286.         I915_WRITE(reg, val);
  287.         POSTING_READ(reg);
  288. }
  289.  
  290. static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
  291.                                   const struct intel_crtc_state *pipe_config)
  292. {
  293.         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
  294.         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
  295.         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
  296.  
  297.         if ((val & VIDEO_DIP_ENABLE) == 0)
  298.                 return false;
  299.  
  300.         return val & (VIDEO_DIP_ENABLE_AVI |
  301.                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  302.                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  303. }
  304.  
  305. static void vlv_write_infoframe(struct drm_encoder *encoder,
  306.                                 enum hdmi_infoframe_type type,
  307.                                 const void *frame, ssize_t len)
  308. {
  309.         const uint32_t *data = frame;
  310.         struct drm_device *dev = encoder->dev;
  311.         struct drm_i915_private *dev_priv = dev->dev_private;
  312.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  313.         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  314.         u32 val = I915_READ(reg);
  315.         int i;
  316.  
  317.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  318.  
  319.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  320.         val |= g4x_infoframe_index(type);
  321.  
  322.         val &= ~g4x_infoframe_enable(type);
  323.  
  324.         I915_WRITE(reg, val);
  325.  
  326.         mmiowb();
  327.         for (i = 0; i < len; i += 4) {
  328.                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  329.                 data++;
  330.         }
  331.         /* Write every possible data byte to force correct ECC calculation. */
  332.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  333.                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  334.         mmiowb();
  335.  
  336.         val |= g4x_infoframe_enable(type);
  337.         val &= ~VIDEO_DIP_FREQ_MASK;
  338.         val |= VIDEO_DIP_FREQ_VSYNC;
  339.  
  340.         I915_WRITE(reg, val);
  341.         POSTING_READ(reg);
  342. }
  343.  
  344. static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
  345.                                   const struct intel_crtc_state *pipe_config)
  346. {
  347.         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
  348.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  349.         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
  350.         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
  351.  
  352.         if ((val & VIDEO_DIP_ENABLE) == 0)
  353.                 return false;
  354.  
  355.         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
  356.                 return false;
  357.  
  358.         return val & (VIDEO_DIP_ENABLE_AVI |
  359.                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  360.                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  361. }
  362.  
  363. static void hsw_write_infoframe(struct drm_encoder *encoder,
  364.                                 enum hdmi_infoframe_type type,
  365.                                 const void *frame, ssize_t len)
  366. {
  367.         const uint32_t *data = frame;
  368.         struct drm_device *dev = encoder->dev;
  369.         struct drm_i915_private *dev_priv = dev->dev_private;
  370.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  371.         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  372.         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
  373.         i915_reg_t data_reg;
  374.         int i;
  375.         u32 val = I915_READ(ctl_reg);
  376.  
  377.         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
  378.  
  379.         val &= ~hsw_infoframe_enable(type);
  380.         I915_WRITE(ctl_reg, val);
  381.  
  382.         mmiowb();
  383.         for (i = 0; i < len; i += 4) {
  384.                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
  385.                                             type, i >> 2), *data);
  386.                 data++;
  387.         }
  388.         /* Write every possible data byte to force correct ECC calculation. */
  389.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  390.                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
  391.                                             type, i >> 2), 0);
  392.         mmiowb();
  393.  
  394.         val |= hsw_infoframe_enable(type);
  395.         I915_WRITE(ctl_reg, val);
  396.         POSTING_READ(ctl_reg);
  397. }
  398.  
  399. static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
  400.                                   const struct intel_crtc_state *pipe_config)
  401. {
  402.         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
  403.         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
  404.  
  405.         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
  406.                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
  407.                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
  408. }
  409.  
  410. /*
  411.  * The data we write to the DIP data buffer registers is 1 byte bigger than the
  412.  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
  413.  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
  414.  * used for both technologies.
  415.  *
  416.  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
  417.  * DW1:       DB3       | DB2 | DB1 | DB0
  418.  * DW2:       DB7       | DB6 | DB5 | DB4
  419.  * DW3: ...
  420.  *
  421.  * (HB is Header Byte, DB is Data Byte)
  422.  *
  423.  * The hdmi pack() functions don't know about that hardware specific hole so we
  424.  * trick them by giving an offset into the buffer and moving back the header
  425.  * bytes by one.
  426.  */
  427. static void intel_write_infoframe(struct drm_encoder *encoder,
  428.                                   union hdmi_infoframe *frame)
  429. {
  430.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  431.         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
  432.         ssize_t len;
  433.  
  434.         /* see comment above for the reason for this offset */
  435.         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
  436.         if (len < 0)
  437.                 return;
  438.  
  439.         /* Insert the 'hole' (see big comment above) at position 3 */
  440.         buffer[0] = buffer[1];
  441.         buffer[1] = buffer[2];
  442.         buffer[2] = buffer[3];
  443.         buffer[3] = 0;
  444.         len++;
  445.  
  446.         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
  447. }
  448.  
  449. static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
  450.                                          const struct drm_display_mode *adjusted_mode)
  451. {
  452.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  453.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  454.         union hdmi_infoframe frame;
  455.         int ret;
  456.  
  457.         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
  458.                                                        adjusted_mode);
  459.         if (ret < 0) {
  460.                 DRM_ERROR("couldn't fill AVI infoframe\n");
  461.                 return;
  462.         }
  463.  
  464.         if (intel_hdmi->rgb_quant_range_selectable) {
  465.                 if (intel_crtc->config->limited_color_range)
  466.                         frame.avi.quantization_range =
  467.                                 HDMI_QUANTIZATION_RANGE_LIMITED;
  468.                 else
  469.                         frame.avi.quantization_range =
  470.                                 HDMI_QUANTIZATION_RANGE_FULL;
  471.         }
  472.  
  473.         intel_write_infoframe(encoder, &frame);
  474. }
  475.  
  476. static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
  477. {
  478.         union hdmi_infoframe frame;
  479.         int ret;
  480.  
  481.         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
  482.         if (ret < 0) {
  483.                 DRM_ERROR("couldn't fill SPD infoframe\n");
  484.                 return;
  485.         }
  486.  
  487.         frame.spd.sdi = HDMI_SPD_SDI_PC;
  488.  
  489.         intel_write_infoframe(encoder, &frame);
  490. }
  491.  
  492. static void
  493. intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
  494.                               const struct drm_display_mode *adjusted_mode)
  495. {
  496.         union hdmi_infoframe frame;
  497.         int ret;
  498.  
  499.         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
  500.                                                           adjusted_mode);
  501.         if (ret < 0)
  502.                 return;
  503.  
  504.         intel_write_infoframe(encoder, &frame);
  505. }
  506.  
  507. static void g4x_set_infoframes(struct drm_encoder *encoder,
  508.                                bool enable,
  509.                                const struct drm_display_mode *adjusted_mode)
  510. {
  511.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  512.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  513.         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  514.         i915_reg_t reg = VIDEO_DIP_CTL;
  515.         u32 val = I915_READ(reg);
  516.         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
  517.  
  518.         assert_hdmi_port_disabled(intel_hdmi);
  519.  
  520.         /* If the registers were not initialized yet, they might be zeroes,
  521.          * which means we're selecting the AVI DIP and we're setting its
  522.          * frequency to once. This seems to really confuse the HW and make
  523.          * things stop working (the register spec says the AVI always needs to
  524.          * be sent every VSync). So here we avoid writing to the register more
  525.          * than we need and also explicitly select the AVI DIP and explicitly
  526.          * set its frequency to every VSync. Avoiding to write it twice seems to
  527.          * be enough to solve the problem, but being defensive shouldn't hurt us
  528.          * either. */
  529.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  530.  
  531.         if (!enable) {
  532.                 if (!(val & VIDEO_DIP_ENABLE))
  533.                         return;
  534.                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
  535.                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
  536.                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
  537.                         return;
  538.                 }
  539.                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
  540.                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
  541.                 I915_WRITE(reg, val);
  542.                 POSTING_READ(reg);
  543.                 return;
  544.         }
  545.  
  546.         if (port != (val & VIDEO_DIP_PORT_MASK)) {
  547.                 if (val & VIDEO_DIP_ENABLE) {
  548.                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
  549.                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
  550.                         return;
  551.                 }
  552.                 val &= ~VIDEO_DIP_PORT_MASK;
  553.                 val |= port;
  554.         }
  555.  
  556.         val |= VIDEO_DIP_ENABLE;
  557.         val &= ~(VIDEO_DIP_ENABLE_AVI |
  558.                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
  559.  
  560.         I915_WRITE(reg, val);
  561.         POSTING_READ(reg);
  562.  
  563.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  564.         intel_hdmi_set_spd_infoframe(encoder);
  565.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  566. }
  567.  
  568. static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
  569. {
  570.         struct drm_device *dev = encoder->dev;
  571.         struct drm_connector *connector;
  572.  
  573.         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
  574.  
  575.         /*
  576.          * HDMI cloning is only supported on g4x which doesn't
  577.          * support deep color or GCP infoframes anyway so no
  578.          * need to worry about multiple HDMI sinks here.
  579.          */
  580.         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  581.                 if (connector->encoder == encoder)
  582.                         return connector->display_info.bpc > 8;
  583.  
  584.         return false;
  585. }
  586.  
  587. /*
  588.  * Determine if default_phase=1 can be indicated in the GCP infoframe.
  589.  *
  590.  * From HDMI specification 1.4a:
  591.  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
  592.  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
  593.  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
  594.  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
  595.  *   phase of 0
  596.  */
  597. static bool gcp_default_phase_possible(int pipe_bpp,
  598.                                        const struct drm_display_mode *mode)
  599. {
  600.         unsigned int pixels_per_group;
  601.  
  602.         switch (pipe_bpp) {
  603.         case 30:
  604.                 /* 4 pixels in 5 clocks */
  605.                 pixels_per_group = 4;
  606.                 break;
  607.         case 36:
  608.                 /* 2 pixels in 3 clocks */
  609.                 pixels_per_group = 2;
  610.                 break;
  611.         case 48:
  612.                 /* 1 pixel in 2 clocks */
  613.                 pixels_per_group = 1;
  614.                 break;
  615.         default:
  616.                 /* phase information not relevant for 8bpc */
  617.                 return false;
  618.         }
  619.  
  620.         return mode->crtc_hdisplay % pixels_per_group == 0 &&
  621.                 mode->crtc_htotal % pixels_per_group == 0 &&
  622.                 mode->crtc_hblank_start % pixels_per_group == 0 &&
  623.                 mode->crtc_hblank_end % pixels_per_group == 0 &&
  624.                 mode->crtc_hsync_start % pixels_per_group == 0 &&
  625.                 mode->crtc_hsync_end % pixels_per_group == 0 &&
  626.                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
  627.                  mode->crtc_htotal/2 % pixels_per_group == 0);
  628. }
  629.  
  630. static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
  631. {
  632.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  633.         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
  634.         i915_reg_t reg;
  635.         u32 val = 0;
  636.  
  637.         if (HAS_DDI(dev_priv))
  638.                 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
  639.         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
  640.                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
  641.         else if (HAS_PCH_SPLIT(dev_priv->dev))
  642.                 reg = TVIDEO_DIP_GCP(crtc->pipe);
  643.         else
  644.                 return false;
  645.  
  646.         /* Indicate color depth whenever the sink supports deep color */
  647.         if (hdmi_sink_is_deep_color(encoder))
  648.                 val |= GCP_COLOR_INDICATION;
  649.  
  650.         /* Enable default_phase whenever the display mode is suitably aligned */
  651.         if (gcp_default_phase_possible(crtc->config->pipe_bpp,
  652.                                        &crtc->config->base.adjusted_mode))
  653.                 val |= GCP_DEFAULT_PHASE_ENABLE;
  654.  
  655.         I915_WRITE(reg, val);
  656.  
  657.         return val != 0;
  658. }
  659.  
  660. static void ibx_set_infoframes(struct drm_encoder *encoder,
  661.                                bool enable,
  662.                                const struct drm_display_mode *adjusted_mode)
  663. {
  664.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  665.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  666.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  667.         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  668.         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  669.         u32 val = I915_READ(reg);
  670.         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
  671.  
  672.         assert_hdmi_port_disabled(intel_hdmi);
  673.  
  674.         /* See the big comment in g4x_set_infoframes() */
  675.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  676.  
  677.         if (!enable) {
  678.                 if (!(val & VIDEO_DIP_ENABLE))
  679.                         return;
  680.                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
  681.                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  682.                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  683.                 I915_WRITE(reg, val);
  684.                 POSTING_READ(reg);
  685.                 return;
  686.         }
  687.  
  688.         if (port != (val & VIDEO_DIP_PORT_MASK)) {
  689.                 WARN(val & VIDEO_DIP_ENABLE,
  690.                      "DIP already enabled on port %c\n",
  691.                      (val & VIDEO_DIP_PORT_MASK) >> 29);
  692.                 val &= ~VIDEO_DIP_PORT_MASK;
  693.                 val |= port;
  694.         }
  695.  
  696.         val |= VIDEO_DIP_ENABLE;
  697.         val &= ~(VIDEO_DIP_ENABLE_AVI |
  698.                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  699.                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  700.  
  701.         if (intel_hdmi_set_gcp_infoframe(encoder))
  702.                 val |= VIDEO_DIP_ENABLE_GCP;
  703.  
  704.         I915_WRITE(reg, val);
  705.         POSTING_READ(reg);
  706.  
  707.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  708.         intel_hdmi_set_spd_infoframe(encoder);
  709.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  710. }
  711.  
  712. static void cpt_set_infoframes(struct drm_encoder *encoder,
  713.                                bool enable,
  714.                                const struct drm_display_mode *adjusted_mode)
  715. {
  716.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  717.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  718.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  719.         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  720.         u32 val = I915_READ(reg);
  721.  
  722.         assert_hdmi_port_disabled(intel_hdmi);
  723.  
  724.         /* See the big comment in g4x_set_infoframes() */
  725.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  726.  
  727.         if (!enable) {
  728.                 if (!(val & VIDEO_DIP_ENABLE))
  729.                         return;
  730.                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
  731.                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  732.                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  733.                 I915_WRITE(reg, val);
  734.                 POSTING_READ(reg);
  735.                 return;
  736.         }
  737.  
  738.         /* Set both together, unset both together: see the spec. */
  739.         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
  740.         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  741.                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  742.  
  743.         if (intel_hdmi_set_gcp_infoframe(encoder))
  744.                 val |= VIDEO_DIP_ENABLE_GCP;
  745.  
  746.         I915_WRITE(reg, val);
  747.         POSTING_READ(reg);
  748.  
  749.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  750.         intel_hdmi_set_spd_infoframe(encoder);
  751.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  752. }
  753.  
  754. static void vlv_set_infoframes(struct drm_encoder *encoder,
  755.                                bool enable,
  756.                                const struct drm_display_mode *adjusted_mode)
  757. {
  758.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  759.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  760.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  761.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  762.         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  763.         u32 val = I915_READ(reg);
  764.         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
  765.  
  766.         assert_hdmi_port_disabled(intel_hdmi);
  767.  
  768.         /* See the big comment in g4x_set_infoframes() */
  769.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  770.  
  771.         if (!enable) {
  772.                 if (!(val & VIDEO_DIP_ENABLE))
  773.                         return;
  774.                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
  775.                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  776.                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  777.                 I915_WRITE(reg, val);
  778.                 POSTING_READ(reg);
  779.                 return;
  780.         }
  781.  
  782.         if (port != (val & VIDEO_DIP_PORT_MASK)) {
  783.                 WARN(val & VIDEO_DIP_ENABLE,
  784.                      "DIP already enabled on port %c\n",
  785.                      (val & VIDEO_DIP_PORT_MASK) >> 29);
  786.                 val &= ~VIDEO_DIP_PORT_MASK;
  787.                 val |= port;
  788.         }
  789.  
  790.         val |= VIDEO_DIP_ENABLE;
  791.         val &= ~(VIDEO_DIP_ENABLE_AVI |
  792.                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  793.                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  794.  
  795.         if (intel_hdmi_set_gcp_infoframe(encoder))
  796.                 val |= VIDEO_DIP_ENABLE_GCP;
  797.  
  798.         I915_WRITE(reg, val);
  799.         POSTING_READ(reg);
  800.  
  801.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  802.         intel_hdmi_set_spd_infoframe(encoder);
  803.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  804. }
  805.  
  806. static void hsw_set_infoframes(struct drm_encoder *encoder,
  807.                                bool enable,
  808.                                const struct drm_display_mode *adjusted_mode)
  809. {
  810.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  811.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  812.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  813.         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
  814.         u32 val = I915_READ(reg);
  815.  
  816.         assert_hdmi_port_disabled(intel_hdmi);
  817.  
  818.         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
  819.                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
  820.                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
  821.  
  822.         if (!enable) {
  823.                 I915_WRITE(reg, val);
  824.                 POSTING_READ(reg);
  825.                 return;
  826.         }
  827.  
  828.         if (intel_hdmi_set_gcp_infoframe(encoder))
  829.                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
  830.  
  831.         I915_WRITE(reg, val);
  832.         POSTING_READ(reg);
  833.  
  834.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  835.         intel_hdmi_set_spd_infoframe(encoder);
  836.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  837. }
  838.  
  839. void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
  840. {
  841.         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
  842.         struct i2c_adapter *adapter =
  843.                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
  844.  
  845.         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
  846.                 return;
  847.  
  848.         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
  849.                       enable ? "Enabling" : "Disabling");
  850.  
  851.         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
  852.                                          adapter, enable);
  853. }
  854.  
  855. static void intel_hdmi_prepare(struct intel_encoder *encoder)
  856. {
  857.         struct drm_device *dev = encoder->base.dev;
  858.         struct drm_i915_private *dev_priv = dev->dev_private;
  859.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  860.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  861.         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  862.         u32 hdmi_val;
  863.  
  864.         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
  865.  
  866.         hdmi_val = SDVO_ENCODING_HDMI;
  867.         if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
  868.                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
  869.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  870.                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
  871.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  872.                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
  873.  
  874.         if (crtc->config->pipe_bpp > 24)
  875.                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
  876.         else
  877.                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
  878.  
  879.         if (crtc->config->has_hdmi_sink)
  880.                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
  881.  
  882.         if (HAS_PCH_CPT(dev))
  883.                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
  884.         else if (IS_CHERRYVIEW(dev))
  885.                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
  886.         else
  887.                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
  888.  
  889.         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
  890.         POSTING_READ(intel_hdmi->hdmi_reg);
  891. }
  892.  
  893. static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
  894.                                     enum pipe *pipe)
  895. {
  896.         struct drm_device *dev = encoder->base.dev;
  897.         struct drm_i915_private *dev_priv = dev->dev_private;
  898.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  899.         enum intel_display_power_domain power_domain;
  900.         u32 tmp;
  901.         bool ret;
  902.  
  903.         power_domain = intel_display_port_power_domain(encoder);
  904.         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
  905.                 return false;
  906.  
  907.         ret = false;
  908.  
  909.         tmp = I915_READ(intel_hdmi->hdmi_reg);
  910.  
  911.         if (!(tmp & SDVO_ENABLE))
  912.                 goto out;
  913.  
  914.         if (HAS_PCH_CPT(dev))
  915.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  916.         else if (IS_CHERRYVIEW(dev))
  917.                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
  918.         else
  919.                 *pipe = PORT_TO_PIPE(tmp);
  920.  
  921.         ret = true;
  922.  
  923. out:
  924.         intel_display_power_put(dev_priv, power_domain);
  925.  
  926.         return ret;
  927. }
  928.  
  929. static void intel_hdmi_get_config(struct intel_encoder *encoder,
  930.                                   struct intel_crtc_state *pipe_config)
  931. {
  932.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  933.         struct drm_device *dev = encoder->base.dev;
  934.         struct drm_i915_private *dev_priv = dev->dev_private;
  935.         u32 tmp, flags = 0;
  936.         int dotclock;
  937.  
  938.         tmp = I915_READ(intel_hdmi->hdmi_reg);
  939.  
  940.         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
  941.                 flags |= DRM_MODE_FLAG_PHSYNC;
  942.         else
  943.                 flags |= DRM_MODE_FLAG_NHSYNC;
  944.  
  945.         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
  946.                 flags |= DRM_MODE_FLAG_PVSYNC;
  947.         else
  948.                 flags |= DRM_MODE_FLAG_NVSYNC;
  949.  
  950.         if (tmp & HDMI_MODE_SELECT_HDMI)
  951.                 pipe_config->has_hdmi_sink = true;
  952.  
  953.         if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
  954.                 pipe_config->has_infoframe = true;
  955.  
  956.         if (tmp & SDVO_AUDIO_ENABLE)
  957.                 pipe_config->has_audio = true;
  958.  
  959.         if (!HAS_PCH_SPLIT(dev) &&
  960.             tmp & HDMI_COLOR_RANGE_16_235)
  961.                 pipe_config->limited_color_range = true;
  962.  
  963.         pipe_config->base.adjusted_mode.flags |= flags;
  964.  
  965.         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
  966.                 dotclock = pipe_config->port_clock * 2 / 3;
  967.         else
  968.                 dotclock = pipe_config->port_clock;
  969.  
  970.         if (pipe_config->pixel_multiplier)
  971.                 dotclock /= pipe_config->pixel_multiplier;
  972.  
  973.         if (HAS_PCH_SPLIT(dev_priv->dev))
  974.                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
  975.  
  976.         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
  977. }
  978.  
  979. static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
  980. {
  981.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  982.  
  983.         WARN_ON(!crtc->config->has_hdmi_sink);
  984.         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
  985.                          pipe_name(crtc->pipe));
  986.         intel_audio_codec_enable(encoder);
  987. }
  988.  
  989. static void g4x_enable_hdmi(struct intel_encoder *encoder)
  990. {
  991.         struct drm_device *dev = encoder->base.dev;
  992.         struct drm_i915_private *dev_priv = dev->dev_private;
  993.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  994.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  995.         u32 temp;
  996.  
  997.         temp = I915_READ(intel_hdmi->hdmi_reg);
  998.  
  999.         temp |= SDVO_ENABLE;
  1000.         if (crtc->config->has_audio)
  1001.                 temp |= SDVO_AUDIO_ENABLE;
  1002.  
  1003.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1004.         POSTING_READ(intel_hdmi->hdmi_reg);
  1005.  
  1006.         if (crtc->config->has_audio)
  1007.                 intel_enable_hdmi_audio(encoder);
  1008. }
  1009.  
  1010. static void ibx_enable_hdmi(struct intel_encoder *encoder)
  1011. {
  1012.         struct drm_device *dev = encoder->base.dev;
  1013.         struct drm_i915_private *dev_priv = dev->dev_private;
  1014.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1015.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  1016.         u32 temp;
  1017.  
  1018.         temp = I915_READ(intel_hdmi->hdmi_reg);
  1019.  
  1020.         temp |= SDVO_ENABLE;
  1021.         if (crtc->config->has_audio)
  1022.                 temp |= SDVO_AUDIO_ENABLE;
  1023.  
  1024.         /*
  1025.          * HW workaround, need to write this twice for issue
  1026.          * that may result in first write getting masked.
  1027.          */
  1028.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1029.         POSTING_READ(intel_hdmi->hdmi_reg);
  1030.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1031.         POSTING_READ(intel_hdmi->hdmi_reg);
  1032.  
  1033.         /*
  1034.          * HW workaround, need to toggle enable bit off and on
  1035.          * for 12bpc with pixel repeat.
  1036.          *
  1037.          * FIXME: BSpec says this should be done at the end of
  1038.          * of the modeset sequence, so not sure if this isn't too soon.
  1039.          */
  1040.         if (crtc->config->pipe_bpp > 24 &&
  1041.             crtc->config->pixel_multiplier > 1) {
  1042.                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
  1043.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1044.  
  1045.                 /*
  1046.                  * HW workaround, need to write this twice for issue
  1047.                  * that may result in first write getting masked.
  1048.                  */
  1049.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1050.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1051.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1052.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1053.         }
  1054.  
  1055.         if (crtc->config->has_audio)
  1056.                 intel_enable_hdmi_audio(encoder);
  1057. }
  1058.  
  1059. static void cpt_enable_hdmi(struct intel_encoder *encoder)
  1060. {
  1061.         struct drm_device *dev = encoder->base.dev;
  1062.         struct drm_i915_private *dev_priv = dev->dev_private;
  1063.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1064.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  1065.         enum pipe pipe = crtc->pipe;
  1066.         u32 temp;
  1067.  
  1068.         temp = I915_READ(intel_hdmi->hdmi_reg);
  1069.  
  1070.         temp |= SDVO_ENABLE;
  1071.         if (crtc->config->has_audio)
  1072.                 temp |= SDVO_AUDIO_ENABLE;
  1073.  
  1074.         /*
  1075.          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
  1076.          *
  1077.          * The procedure for 12bpc is as follows:
  1078.          * 1. disable HDMI clock gating
  1079.          * 2. enable HDMI with 8bpc
  1080.          * 3. enable HDMI with 12bpc
  1081.          * 4. enable HDMI clock gating
  1082.          */
  1083.  
  1084.         if (crtc->config->pipe_bpp > 24) {
  1085.                 I915_WRITE(TRANS_CHICKEN1(pipe),
  1086.                            I915_READ(TRANS_CHICKEN1(pipe)) |
  1087.                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
  1088.  
  1089.                 temp &= ~SDVO_COLOR_FORMAT_MASK;
  1090.                 temp |= SDVO_COLOR_FORMAT_8bpc;
  1091.         }
  1092.  
  1093.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1094.         POSTING_READ(intel_hdmi->hdmi_reg);
  1095.  
  1096.         if (crtc->config->pipe_bpp > 24) {
  1097.                 temp &= ~SDVO_COLOR_FORMAT_MASK;
  1098.                 temp |= HDMI_COLOR_FORMAT_12bpc;
  1099.  
  1100.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1101.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1102.  
  1103.                 I915_WRITE(TRANS_CHICKEN1(pipe),
  1104.                            I915_READ(TRANS_CHICKEN1(pipe)) &
  1105.                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
  1106.         }
  1107.  
  1108.         if (crtc->config->has_audio)
  1109.                 intel_enable_hdmi_audio(encoder);
  1110. }
  1111.  
  1112. static void vlv_enable_hdmi(struct intel_encoder *encoder)
  1113. {
  1114. }
  1115.  
  1116. static void intel_disable_hdmi(struct intel_encoder *encoder)
  1117. {
  1118.         struct drm_device *dev = encoder->base.dev;
  1119.         struct drm_i915_private *dev_priv = dev->dev_private;
  1120.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  1121.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1122.         u32 temp;
  1123.  
  1124.         temp = I915_READ(intel_hdmi->hdmi_reg);
  1125.  
  1126.         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
  1127.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1128.         POSTING_READ(intel_hdmi->hdmi_reg);
  1129.  
  1130.         /*
  1131.          * HW workaround for IBX, we need to move the port
  1132.          * to transcoder A after disabling it to allow the
  1133.          * matching DP port to be enabled on transcoder A.
  1134.          */
  1135.         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
  1136.                 /*
  1137.                  * We get CPU/PCH FIFO underruns on the other pipe when
  1138.                  * doing the workaround. Sweep them under the rug.
  1139.                  */
  1140.                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
  1141.                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
  1142.  
  1143.                 temp &= ~SDVO_PIPE_B_SELECT;
  1144.                 temp |= SDVO_ENABLE;
  1145.                 /*
  1146.                  * HW workaround, need to write this twice for issue
  1147.                  * that may result in first write getting masked.
  1148.                  */
  1149.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1150.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1151.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1152.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1153.  
  1154.                 temp &= ~SDVO_ENABLE;
  1155.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1156.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1157.  
  1158.                 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
  1159.                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
  1160.                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
  1161.         }
  1162.  
  1163.         intel_hdmi->set_infoframes(&encoder->base, false, NULL);
  1164.  
  1165.         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
  1166. }
  1167.  
  1168. static void g4x_disable_hdmi(struct intel_encoder *encoder)
  1169. {
  1170.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1171.  
  1172.         if (crtc->config->has_audio)
  1173.                 intel_audio_codec_disable(encoder);
  1174.  
  1175.         intel_disable_hdmi(encoder);
  1176. }
  1177.  
  1178. static void pch_disable_hdmi(struct intel_encoder *encoder)
  1179. {
  1180.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1181.  
  1182.         if (crtc->config->has_audio)
  1183.                 intel_audio_codec_disable(encoder);
  1184. }
  1185.  
  1186. static void pch_post_disable_hdmi(struct intel_encoder *encoder)
  1187. {
  1188.         intel_disable_hdmi(encoder);
  1189. }
  1190.  
  1191. static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
  1192. {
  1193.         if (IS_G4X(dev_priv))
  1194.                 return 165000;
  1195.         else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
  1196.                 return 300000;
  1197.         else
  1198.                 return 225000;
  1199. }
  1200.  
  1201. static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
  1202.                                  bool respect_downstream_limits)
  1203. {
  1204.         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
  1205.         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
  1206.  
  1207.         if (respect_downstream_limits) {
  1208.                 if (hdmi->dp_dual_mode.max_tmds_clock)
  1209.                         max_tmds_clock = min(max_tmds_clock,
  1210.                                              hdmi->dp_dual_mode.max_tmds_clock);
  1211.                 if (!hdmi->has_hdmi_sink)
  1212.                         max_tmds_clock = min(max_tmds_clock, 165000);
  1213.         }
  1214.  
  1215.         return max_tmds_clock;
  1216. }
  1217.  
  1218. static enum drm_mode_status
  1219. hdmi_port_clock_valid(struct intel_hdmi *hdmi,
  1220.                       int clock, bool respect_downstream_limits)
  1221. {
  1222.         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
  1223.  
  1224.         if (clock < 25000)
  1225.                 return MODE_CLOCK_LOW;
  1226.         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits))
  1227.                 return MODE_CLOCK_HIGH;
  1228.  
  1229.         /* BXT DPLL can't generate 223-240 MHz */
  1230.         if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
  1231.                 return MODE_CLOCK_RANGE;
  1232.  
  1233.         /* CHV DPLL can't generate 216-240 MHz */
  1234.         if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
  1235.                 return MODE_CLOCK_RANGE;
  1236.  
  1237.         return MODE_OK;
  1238. }
  1239.  
  1240. static enum drm_mode_status
  1241. intel_hdmi_mode_valid(struct drm_connector *connector,
  1242.                       struct drm_display_mode *mode)
  1243. {
  1244.         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
  1245.         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
  1246.         enum drm_mode_status status;
  1247.         int clock;
  1248.         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
  1249.  
  1250.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1251.                 return MODE_NO_DBLESCAN;
  1252.  
  1253.         clock = mode->clock;
  1254.  
  1255.         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
  1256.                 clock *= 2;
  1257.  
  1258.         if (clock > max_dotclk)
  1259.                 return MODE_CLOCK_HIGH;
  1260.  
  1261.         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  1262.                 clock *= 2;
  1263.  
  1264.         /* check if we can do 8bpc */
  1265.         status = hdmi_port_clock_valid(hdmi, clock, true);
  1266.  
  1267.         /* if we can't do 8bpc we may still be able to do 12bpc */
  1268.         if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
  1269.                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
  1270.  
  1271.         return status;
  1272. }
  1273.  
  1274. static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
  1275. {
  1276.         struct drm_device *dev = crtc_state->base.crtc->dev;
  1277.         struct drm_atomic_state *state;
  1278.         struct intel_encoder *encoder;
  1279.         struct drm_connector *connector;
  1280.         struct drm_connector_state *connector_state;
  1281.         int count = 0, count_hdmi = 0;
  1282.         int i;
  1283.  
  1284.         if (HAS_GMCH_DISPLAY(dev))
  1285.                 return false;
  1286.  
  1287.         state = crtc_state->base.state;
  1288.  
  1289.         for_each_connector_in_state(state, connector, connector_state, i) {
  1290.                 if (connector_state->crtc != crtc_state->base.crtc)
  1291.                         continue;
  1292.  
  1293.                 encoder = to_intel_encoder(connector_state->best_encoder);
  1294.  
  1295.                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
  1296.                 count++;
  1297.         }
  1298.  
  1299.         /*
  1300.          * HDMI 12bpc affects the clocks, so it's only possible
  1301.          * when not cloning with other encoder types.
  1302.          */
  1303.         return count_hdmi > 0 && count_hdmi == count;
  1304. }
  1305.  
  1306. bool intel_hdmi_compute_config(struct intel_encoder *encoder,
  1307.                                struct intel_crtc_state *pipe_config)
  1308. {
  1309.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  1310.         struct drm_device *dev = encoder->base.dev;
  1311.         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
  1312.         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
  1313.         int clock_12bpc = clock_8bpc * 3 / 2;
  1314.         int desired_bpp;
  1315.  
  1316.         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
  1317.  
  1318.         if (pipe_config->has_hdmi_sink)
  1319.                 pipe_config->has_infoframe = true;
  1320.  
  1321.         if (intel_hdmi->color_range_auto) {
  1322.                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
  1323.                 pipe_config->limited_color_range =
  1324.                         pipe_config->has_hdmi_sink &&
  1325.                         drm_match_cea_mode(adjusted_mode) > 1;
  1326.         } else {
  1327.                 pipe_config->limited_color_range =
  1328.                         intel_hdmi->limited_color_range;
  1329.         }
  1330.  
  1331.         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
  1332.                 pipe_config->pixel_multiplier = 2;
  1333.                 clock_8bpc *= 2;
  1334.                 clock_12bpc *= 2;
  1335.         }
  1336.  
  1337.         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
  1338.                 pipe_config->has_pch_encoder = true;
  1339.  
  1340.         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
  1341.                 pipe_config->has_audio = true;
  1342.  
  1343.         /*
  1344.          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
  1345.          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
  1346.          * outputs. We also need to check that the higher clock still fits
  1347.          * within limits.
  1348.          */
  1349.         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
  1350.             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
  1351.             hdmi_12bpc_possible(pipe_config)) {
  1352.                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
  1353.                 desired_bpp = 12*3;
  1354.  
  1355.                 /* Need to adjust the port link by 1.5x for 12bpc. */
  1356.                 pipe_config->port_clock = clock_12bpc;
  1357.         } else {
  1358.                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
  1359.                 desired_bpp = 8*3;
  1360.  
  1361.                 pipe_config->port_clock = clock_8bpc;
  1362.         }
  1363.  
  1364.         if (!pipe_config->bw_constrained) {
  1365.                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
  1366.                 pipe_config->pipe_bpp = desired_bpp;
  1367.         }
  1368.  
  1369.         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
  1370.                                   false) != MODE_OK) {
  1371.                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
  1372.                 return false;
  1373.         }
  1374.  
  1375.         /* Set user selected PAR to incoming mode's member */
  1376.         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
  1377.  
  1378.         return true;
  1379. }
  1380.  
  1381. static void
  1382. intel_hdmi_unset_edid(struct drm_connector *connector)
  1383. {
  1384.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1385.  
  1386.         intel_hdmi->has_hdmi_sink = false;
  1387.         intel_hdmi->has_audio = false;
  1388.         intel_hdmi->rgb_quant_range_selectable = false;
  1389.  
  1390.         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
  1391.         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
  1392.  
  1393.         kfree(to_intel_connector(connector)->detect_edid);
  1394.         to_intel_connector(connector)->detect_edid = NULL;
  1395. }
  1396.  
  1397. static void
  1398. intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
  1399. {
  1400.         struct drm_i915_private *dev_priv = to_i915(connector->dev);
  1401.         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
  1402.         struct i2c_adapter *adapter =
  1403.                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
  1404.         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
  1405.  
  1406.         if (type == DRM_DP_DUAL_MODE_NONE ||
  1407.             type == DRM_DP_DUAL_MODE_UNKNOWN)
  1408.                 return;
  1409.  
  1410.         hdmi->dp_dual_mode.type = type;
  1411.         hdmi->dp_dual_mode.max_tmds_clock =
  1412.                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
  1413.  
  1414.         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
  1415.                       drm_dp_get_dual_mode_type_name(type),
  1416.                       hdmi->dp_dual_mode.max_tmds_clock);
  1417. }
  1418.  
  1419. static bool
  1420. intel_hdmi_set_edid(struct drm_connector *connector, bool force)
  1421. {
  1422.         struct drm_i915_private *dev_priv = to_i915(connector->dev);
  1423.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1424.         struct edid *edid = NULL;
  1425.         bool connected = false;
  1426.  
  1427.         if (force) {
  1428.                 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
  1429.  
  1430.                 edid = drm_get_edid(connector,
  1431.                                     intel_gmbus_get_adapter(dev_priv,
  1432.                                     intel_hdmi->ddc_bus));
  1433.  
  1434.                 intel_hdmi_dp_dual_mode_detect(connector);
  1435.  
  1436.                 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
  1437.         }
  1438.  
  1439.         to_intel_connector(connector)->detect_edid = edid;
  1440.         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
  1441.                 intel_hdmi->rgb_quant_range_selectable =
  1442.                         drm_rgb_quant_range_selectable(edid);
  1443.  
  1444.                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
  1445.                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
  1446.                         intel_hdmi->has_audio =
  1447.                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
  1448.  
  1449.                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
  1450.                         intel_hdmi->has_hdmi_sink =
  1451.                                 drm_detect_hdmi_monitor(edid);
  1452.  
  1453.                 connected = true;
  1454.         }
  1455.  
  1456.         return connected;
  1457. }
  1458.  
  1459. static enum drm_connector_status
  1460. intel_hdmi_detect(struct drm_connector *connector, bool force)
  1461. {
  1462.         enum drm_connector_status status;
  1463.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1464.         struct drm_i915_private *dev_priv = to_i915(connector->dev);
  1465.         bool live_status = false;
  1466.         unsigned int try;
  1467.  
  1468.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  1469.                       connector->base.id, connector->name);
  1470.  
  1471.         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
  1472.  
  1473.         for (try = 0; !live_status && try < 9; try++) {
  1474.                 if (try)
  1475.                         msleep(10);
  1476.                 live_status = intel_digital_port_connected(dev_priv,
  1477.                                 hdmi_to_dig_port(intel_hdmi));
  1478.         }
  1479.  
  1480.         if (!live_status) {
  1481.                 DRM_DEBUG_KMS("HDMI live status down\n");
  1482.                 /*
  1483.                  * Live status register is not reliable on all intel platforms.
  1484.                  * So consider live_status only for certain platforms, for
  1485.                  * others, read EDID to determine presence of sink.
  1486.                  */
  1487.                 if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv))
  1488.                         live_status = true;
  1489.         }
  1490.  
  1491.         intel_hdmi_unset_edid(connector);
  1492.  
  1493.         if (intel_hdmi_set_edid(connector, live_status)) {
  1494.                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1495.  
  1496.                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
  1497.                 status = connector_status_connected;
  1498.         } else
  1499.                 status = connector_status_disconnected;
  1500.  
  1501.         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
  1502.  
  1503.         return status;
  1504. }
  1505.  
  1506. static void
  1507. intel_hdmi_force(struct drm_connector *connector)
  1508. {
  1509.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1510.  
  1511.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  1512.                       connector->base.id, connector->name);
  1513.  
  1514.         intel_hdmi_unset_edid(connector);
  1515.  
  1516.         if (connector->status != connector_status_connected)
  1517.                 return;
  1518.  
  1519.         intel_hdmi_set_edid(connector, true);
  1520.         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
  1521. }
  1522.  
  1523. static int intel_hdmi_get_modes(struct drm_connector *connector)
  1524. {
  1525.         struct edid *edid;
  1526.  
  1527.         edid = to_intel_connector(connector)->detect_edid;
  1528.         if (edid == NULL)
  1529.                 return 0;
  1530.  
  1531.         return intel_connector_update_modes(connector, edid);
  1532. }
  1533.  
  1534. static bool
  1535. intel_hdmi_detect_audio(struct drm_connector *connector)
  1536. {
  1537.         bool has_audio = false;
  1538.         struct edid *edid;
  1539.  
  1540.         edid = to_intel_connector(connector)->detect_edid;
  1541.         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
  1542.                 has_audio = drm_detect_monitor_audio(edid);
  1543.  
  1544.         return has_audio;
  1545. }
  1546.  
  1547. static int
  1548. intel_hdmi_set_property(struct drm_connector *connector,
  1549.                         struct drm_property *property,
  1550.                         uint64_t val)
  1551. {
  1552.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1553.         struct intel_digital_port *intel_dig_port =
  1554.                 hdmi_to_dig_port(intel_hdmi);
  1555.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1556.         int ret;
  1557.  
  1558.         ret = drm_object_property_set_value(&connector->base, property, val);
  1559.         if (ret)
  1560.                 return ret;
  1561.  
  1562.         if (property == dev_priv->force_audio_property) {
  1563.                 enum hdmi_force_audio i = val;
  1564.                 bool has_audio;
  1565.  
  1566.                 if (i == intel_hdmi->force_audio)
  1567.                         return 0;
  1568.  
  1569.                 intel_hdmi->force_audio = i;
  1570.  
  1571.                 if (i == HDMI_AUDIO_AUTO)
  1572.                         has_audio = intel_hdmi_detect_audio(connector);
  1573.                 else
  1574.                         has_audio = (i == HDMI_AUDIO_ON);
  1575.  
  1576.                 if (i == HDMI_AUDIO_OFF_DVI)
  1577.                         intel_hdmi->has_hdmi_sink = 0;
  1578.  
  1579.                 intel_hdmi->has_audio = has_audio;
  1580.                 goto done;
  1581.         }
  1582.  
  1583.         if (property == dev_priv->broadcast_rgb_property) {
  1584.                 bool old_auto = intel_hdmi->color_range_auto;
  1585.                 bool old_range = intel_hdmi->limited_color_range;
  1586.  
  1587.                 switch (val) {
  1588.                 case INTEL_BROADCAST_RGB_AUTO:
  1589.                         intel_hdmi->color_range_auto = true;
  1590.                         break;
  1591.                 case INTEL_BROADCAST_RGB_FULL:
  1592.                         intel_hdmi->color_range_auto = false;
  1593.                         intel_hdmi->limited_color_range = false;
  1594.                         break;
  1595.                 case INTEL_BROADCAST_RGB_LIMITED:
  1596.                         intel_hdmi->color_range_auto = false;
  1597.                         intel_hdmi->limited_color_range = true;
  1598.                         break;
  1599.                 default:
  1600.                         return -EINVAL;
  1601.                 }
  1602.  
  1603.                 if (old_auto == intel_hdmi->color_range_auto &&
  1604.                     old_range == intel_hdmi->limited_color_range)
  1605.                         return 0;
  1606.  
  1607.                 goto done;
  1608.         }
  1609.  
  1610.         if (property == connector->dev->mode_config.aspect_ratio_property) {
  1611.                 switch (val) {
  1612.                 case DRM_MODE_PICTURE_ASPECT_NONE:
  1613.                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
  1614.                         break;
  1615.                 case DRM_MODE_PICTURE_ASPECT_4_3:
  1616.                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
  1617.                         break;
  1618.                 case DRM_MODE_PICTURE_ASPECT_16_9:
  1619.                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
  1620.                         break;
  1621.                 default:
  1622.                         return -EINVAL;
  1623.                 }
  1624.                 goto done;
  1625.         }
  1626.  
  1627.         return -EINVAL;
  1628.  
  1629. done:
  1630.         if (intel_dig_port->base.base.crtc)
  1631.                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
  1632.  
  1633.         return 0;
  1634. }
  1635.  
  1636. static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
  1637. {
  1638.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  1639.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1640.         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
  1641.  
  1642.         intel_hdmi_prepare(encoder);
  1643.  
  1644.         intel_hdmi->set_infoframes(&encoder->base,
  1645.                                    intel_crtc->config->has_hdmi_sink,
  1646.                                    adjusted_mode);
  1647. }
  1648.  
  1649. static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
  1650. {
  1651.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1652.         struct intel_hdmi *intel_hdmi = &dport->hdmi;
  1653.         struct drm_device *dev = encoder->base.dev;
  1654.         struct drm_i915_private *dev_priv = dev->dev_private;
  1655.         struct intel_crtc *intel_crtc =
  1656.                 to_intel_crtc(encoder->base.crtc);
  1657.         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
  1658.         enum dpio_channel port = vlv_dport_to_channel(dport);
  1659.         int pipe = intel_crtc->pipe;
  1660.         u32 val;
  1661.  
  1662.         /* Enable clock channels for this port */
  1663.         mutex_lock(&dev_priv->sb_lock);
  1664.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
  1665.         val = 0;
  1666.         if (pipe)
  1667.                 val |= (1<<21);
  1668.         else
  1669.                 val &= ~(1<<21);
  1670.         val |= 0x001000c4;
  1671.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
  1672.  
  1673.         /* HDMI 1.0V-2dB */
  1674.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
  1675.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
  1676.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
  1677.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
  1678.         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
  1679.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
  1680.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
  1681.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
  1682.  
  1683.         /* Program lane clock */
  1684.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
  1685.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
  1686.         mutex_unlock(&dev_priv->sb_lock);
  1687.  
  1688.         intel_hdmi->set_infoframes(&encoder->base,
  1689.                                    intel_crtc->config->has_hdmi_sink,
  1690.                                    adjusted_mode);
  1691.  
  1692.         g4x_enable_hdmi(encoder);
  1693.  
  1694.         vlv_wait_port_ready(dev_priv, dport, 0x0);
  1695. }
  1696.  
  1697. static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
  1698. {
  1699.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1700.         struct drm_device *dev = encoder->base.dev;
  1701.         struct drm_i915_private *dev_priv = dev->dev_private;
  1702.         struct intel_crtc *intel_crtc =
  1703.                 to_intel_crtc(encoder->base.crtc);
  1704.         enum dpio_channel port = vlv_dport_to_channel(dport);
  1705.         int pipe = intel_crtc->pipe;
  1706.  
  1707.         intel_hdmi_prepare(encoder);
  1708.  
  1709.         /* Program Tx lane resets to default */
  1710.         mutex_lock(&dev_priv->sb_lock);
  1711.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
  1712.                          DPIO_PCS_TX_LANE2_RESET |
  1713.                          DPIO_PCS_TX_LANE1_RESET);
  1714.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
  1715.                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
  1716.                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
  1717.                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
  1718.                          DPIO_PCS_CLK_SOFT_RESET);
  1719.  
  1720.         /* Fix up inter-pair skew failure */
  1721.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
  1722.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
  1723.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
  1724.  
  1725.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
  1726.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
  1727.         mutex_unlock(&dev_priv->sb_lock);
  1728. }
  1729.  
  1730. static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
  1731.                                      bool reset)
  1732. {
  1733.         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  1734.         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
  1735.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1736.         enum pipe pipe = crtc->pipe;
  1737.         uint32_t val;
  1738.  
  1739.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
  1740.         if (reset)
  1741.                 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
  1742.         else
  1743.                 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
  1744.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
  1745.  
  1746.         if (crtc->config->lane_count > 2) {
  1747.                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
  1748.                 if (reset)
  1749.                         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
  1750.                 else
  1751.                         val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
  1752.                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
  1753.         }
  1754.  
  1755.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
  1756.         val |= CHV_PCS_REQ_SOFTRESET_EN;
  1757.         if (reset)
  1758.                 val &= ~DPIO_PCS_CLK_SOFT_RESET;
  1759.         else
  1760.                 val |= DPIO_PCS_CLK_SOFT_RESET;
  1761.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
  1762.  
  1763.         if (crtc->config->lane_count > 2) {
  1764.                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
  1765.                 val |= CHV_PCS_REQ_SOFTRESET_EN;
  1766.                 if (reset)
  1767.                         val &= ~DPIO_PCS_CLK_SOFT_RESET;
  1768.                 else
  1769.                         val |= DPIO_PCS_CLK_SOFT_RESET;
  1770.                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
  1771.         }
  1772. }
  1773.  
  1774. static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
  1775. {
  1776.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1777.         struct drm_device *dev = encoder->base.dev;
  1778.         struct drm_i915_private *dev_priv = dev->dev_private;
  1779.         struct intel_crtc *intel_crtc =
  1780.                 to_intel_crtc(encoder->base.crtc);
  1781.         enum dpio_channel ch = vlv_dport_to_channel(dport);
  1782.         enum pipe pipe = intel_crtc->pipe;
  1783.         u32 val;
  1784.  
  1785.         intel_hdmi_prepare(encoder);
  1786.  
  1787.         /*
  1788.          * Must trick the second common lane into life.
  1789.          * Otherwise we can't even access the PLL.
  1790.          */
  1791.         if (ch == DPIO_CH0 && pipe == PIPE_B)
  1792.                 dport->release_cl2_override =
  1793.                         !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
  1794.  
  1795.         chv_phy_powergate_lanes(encoder, true, 0x0);
  1796.  
  1797.         mutex_lock(&dev_priv->sb_lock);
  1798.  
  1799.         /* Assert data lane reset */
  1800.         chv_data_lane_soft_reset(encoder, true);
  1801.  
  1802.         /* program left/right clock distribution */
  1803.         if (pipe != PIPE_B) {
  1804.                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
  1805.                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
  1806.                 if (ch == DPIO_CH0)
  1807.                         val |= CHV_BUFLEFTENA1_FORCE;
  1808.                 if (ch == DPIO_CH1)
  1809.                         val |= CHV_BUFRIGHTENA1_FORCE;
  1810.                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
  1811.         } else {
  1812.                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
  1813.                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
  1814.                 if (ch == DPIO_CH0)
  1815.                         val |= CHV_BUFLEFTENA2_FORCE;
  1816.                 if (ch == DPIO_CH1)
  1817.                         val |= CHV_BUFRIGHTENA2_FORCE;
  1818.                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
  1819.         }
  1820.  
  1821.         /* program clock channel usage */
  1822.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
  1823.         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
  1824.         if (pipe != PIPE_B)
  1825.                 val &= ~CHV_PCS_USEDCLKCHANNEL;
  1826.         else
  1827.                 val |= CHV_PCS_USEDCLKCHANNEL;
  1828.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
  1829.  
  1830.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
  1831.         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
  1832.         if (pipe != PIPE_B)
  1833.                 val &= ~CHV_PCS_USEDCLKCHANNEL;
  1834.         else
  1835.                 val |= CHV_PCS_USEDCLKCHANNEL;
  1836.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
  1837.  
  1838.         /*
  1839.          * This a a bit weird since generally CL
  1840.          * matches the pipe, but here we need to
  1841.          * pick the CL based on the port.
  1842.          */
  1843.         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
  1844.         if (pipe != PIPE_B)
  1845.                 val &= ~CHV_CMN_USEDCLKCHANNEL;
  1846.         else
  1847.                 val |= CHV_CMN_USEDCLKCHANNEL;
  1848.         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
  1849.  
  1850.         mutex_unlock(&dev_priv->sb_lock);
  1851. }
  1852.  
  1853. static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
  1854. {
  1855.         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  1856.         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
  1857.         u32 val;
  1858.  
  1859.         mutex_lock(&dev_priv->sb_lock);
  1860.  
  1861.         /* disable left/right clock distribution */
  1862.         if (pipe != PIPE_B) {
  1863.                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
  1864.                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
  1865.                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
  1866.         } else {
  1867.                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
  1868.                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
  1869.                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
  1870.         }
  1871.  
  1872.         mutex_unlock(&dev_priv->sb_lock);
  1873.  
  1874.         /*
  1875.          * Leave the power down bit cleared for at least one
  1876.          * lane so that chv_powergate_phy_ch() will power
  1877.          * on something when the channel is otherwise unused.
  1878.          * When the port is off and the override is removed
  1879.          * the lanes power down anyway, so otherwise it doesn't
  1880.          * really matter what the state of power down bits is
  1881.          * after this.
  1882.          */
  1883.         chv_phy_powergate_lanes(encoder, false, 0x0);
  1884. }
  1885.  
  1886. static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
  1887. {
  1888.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1889.         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1890.         struct intel_crtc *intel_crtc =
  1891.                 to_intel_crtc(encoder->base.crtc);
  1892.         enum dpio_channel port = vlv_dport_to_channel(dport);
  1893.         int pipe = intel_crtc->pipe;
  1894.  
  1895.         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
  1896.         mutex_lock(&dev_priv->sb_lock);
  1897.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
  1898.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
  1899.         mutex_unlock(&dev_priv->sb_lock);
  1900. }
  1901.  
  1902. static void chv_hdmi_post_disable(struct intel_encoder *encoder)
  1903. {
  1904.         struct drm_device *dev = encoder->base.dev;
  1905.         struct drm_i915_private *dev_priv = dev->dev_private;
  1906.  
  1907.         mutex_lock(&dev_priv->sb_lock);
  1908.  
  1909.         /* Assert data lane reset */
  1910.         chv_data_lane_soft_reset(encoder, true);
  1911.  
  1912.         mutex_unlock(&dev_priv->sb_lock);
  1913. }
  1914.  
  1915. static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
  1916. {
  1917.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1918.         struct intel_hdmi *intel_hdmi = &dport->hdmi;
  1919.         struct drm_device *dev = encoder->base.dev;
  1920.         struct drm_i915_private *dev_priv = dev->dev_private;
  1921.         struct intel_crtc *intel_crtc =
  1922.                 to_intel_crtc(encoder->base.crtc);
  1923.         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
  1924.         enum dpio_channel ch = vlv_dport_to_channel(dport);
  1925.         int pipe = intel_crtc->pipe;
  1926.         int data, i, stagger;
  1927.         u32 val;
  1928.  
  1929.         mutex_lock(&dev_priv->sb_lock);
  1930.  
  1931.         /* allow hardware to manage TX FIFO reset source */
  1932.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
  1933.         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
  1934.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
  1935.  
  1936.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
  1937.         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
  1938.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
  1939.  
  1940.         /* Program Tx latency optimal setting */
  1941.         for (i = 0; i < 4; i++) {
  1942.                 /* Set the upar bit */
  1943.                 data = (i == 1) ? 0x0 : 0x1;
  1944.                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
  1945.                                 data << DPIO_UPAR_SHIFT);
  1946.         }
  1947.  
  1948.         /* Data lane stagger programming */
  1949.         if (intel_crtc->config->port_clock > 270000)
  1950.                 stagger = 0x18;
  1951.         else if (intel_crtc->config->port_clock > 135000)
  1952.                 stagger = 0xd;
  1953.         else if (intel_crtc->config->port_clock > 67500)
  1954.                 stagger = 0x7;
  1955.         else if (intel_crtc->config->port_clock > 33750)
  1956.                 stagger = 0x4;
  1957.         else
  1958.                 stagger = 0x2;
  1959.  
  1960.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
  1961.         val |= DPIO_TX2_STAGGER_MASK(0x1f);
  1962.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
  1963.  
  1964.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
  1965.         val |= DPIO_TX2_STAGGER_MASK(0x1f);
  1966.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
  1967.  
  1968.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
  1969.                        DPIO_LANESTAGGER_STRAP(stagger) |
  1970.                        DPIO_LANESTAGGER_STRAP_OVRD |
  1971.                        DPIO_TX1_STAGGER_MASK(0x1f) |
  1972.                        DPIO_TX1_STAGGER_MULT(6) |
  1973.                        DPIO_TX2_STAGGER_MULT(0));
  1974.  
  1975.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
  1976.                        DPIO_LANESTAGGER_STRAP(stagger) |
  1977.                        DPIO_LANESTAGGER_STRAP_OVRD |
  1978.                        DPIO_TX1_STAGGER_MASK(0x1f) |
  1979.                        DPIO_TX1_STAGGER_MULT(7) |
  1980.                        DPIO_TX2_STAGGER_MULT(5));
  1981.  
  1982.         /* Deassert data lane reset */
  1983.         chv_data_lane_soft_reset(encoder, false);
  1984.  
  1985.         /* Clear calc init */
  1986.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
  1987.         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
  1988.         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
  1989.         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
  1990.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
  1991.  
  1992.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
  1993.         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
  1994.         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
  1995.         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
  1996.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
  1997.  
  1998.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
  1999.         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
  2000.         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
  2001.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
  2002.  
  2003.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
  2004.         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
  2005.         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
  2006.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
  2007.  
  2008.         /* FIXME: Program the support xxx V-dB */
  2009.         /* Use 800mV-0dB */
  2010.         for (i = 0; i < 4; i++) {
  2011.                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
  2012.                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
  2013.                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
  2014.                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
  2015.         }
  2016.  
  2017.         for (i = 0; i < 4; i++) {
  2018.                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
  2019.  
  2020.                 val &= ~DPIO_SWING_MARGIN000_MASK;
  2021.                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
  2022.  
  2023.                 /*
  2024.                  * Supposedly this value shouldn't matter when unique transition
  2025.                  * scale is disabled, but in fact it does matter. Let's just
  2026.                  * always program the same value and hope it's OK.
  2027.                  */
  2028.                 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
  2029.                 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
  2030.  
  2031.                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
  2032.         }
  2033.  
  2034.         /*
  2035.          * The document said it needs to set bit 27 for ch0 and bit 26
  2036.          * for ch1. Might be a typo in the doc.
  2037.          * For now, for this unique transition scale selection, set bit
  2038.          * 27 for ch0 and ch1.
  2039.          */
  2040.         for (i = 0; i < 4; i++) {
  2041.                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
  2042.                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
  2043.                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
  2044.         }
  2045.  
  2046.         /* Start swing calculation */
  2047.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
  2048.         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
  2049.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
  2050.  
  2051.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
  2052.         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
  2053.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
  2054.  
  2055.         mutex_unlock(&dev_priv->sb_lock);
  2056.  
  2057.         intel_hdmi->set_infoframes(&encoder->base,
  2058.                                    intel_crtc->config->has_hdmi_sink,
  2059.                                    adjusted_mode);
  2060.  
  2061.         g4x_enable_hdmi(encoder);
  2062.  
  2063.         vlv_wait_port_ready(dev_priv, dport, 0x0);
  2064.  
  2065.         /* Second common lane will stay alive on its own now */
  2066.         if (dport->release_cl2_override) {
  2067.                 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
  2068.                 dport->release_cl2_override = false;
  2069.         }
  2070. }
  2071.  
  2072. static void intel_hdmi_destroy(struct drm_connector *connector)
  2073. {
  2074.         kfree(to_intel_connector(connector)->detect_edid);
  2075.         drm_connector_cleanup(connector);
  2076.         kfree(connector);
  2077. }
  2078.  
  2079. static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
  2080.         .dpms = drm_atomic_helper_connector_dpms,
  2081.         .detect = intel_hdmi_detect,
  2082.         .force = intel_hdmi_force,
  2083.         .fill_modes = drm_helper_probe_single_connector_modes,
  2084.         .set_property = intel_hdmi_set_property,
  2085.         .atomic_get_property = intel_connector_atomic_get_property,
  2086.         .destroy = intel_hdmi_destroy,
  2087.         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  2088.         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  2089. };
  2090.  
  2091. static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
  2092.         .get_modes = intel_hdmi_get_modes,
  2093.         .mode_valid = intel_hdmi_mode_valid,
  2094.         .best_encoder = intel_best_encoder,
  2095. };
  2096.  
  2097. static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
  2098.         .destroy = intel_encoder_destroy,
  2099. };
  2100.  
  2101. static void
  2102. intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
  2103. {
  2104.         intel_attach_force_audio_property(connector);
  2105.         intel_attach_broadcast_rgb_property(connector);
  2106.         intel_hdmi->color_range_auto = true;
  2107.         intel_attach_aspect_ratio_property(connector);
  2108.         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
  2109. }
  2110.  
  2111. void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  2112.                                struct intel_connector *intel_connector)
  2113. {
  2114.         struct drm_connector *connector = &intel_connector->base;
  2115.         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  2116.         struct intel_encoder *intel_encoder = &intel_dig_port->base;
  2117.         struct drm_device *dev = intel_encoder->base.dev;
  2118.         struct drm_i915_private *dev_priv = dev->dev_private;
  2119.         enum port port = intel_dig_port->port;
  2120.         uint8_t alternate_ddc_pin;
  2121.  
  2122.         if (WARN(intel_dig_port->max_lanes < 4,
  2123.                  "Not enough lanes (%d) for HDMI on port %c\n",
  2124.                  intel_dig_port->max_lanes, port_name(port)))
  2125.                 return;
  2126.  
  2127.         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
  2128.                            DRM_MODE_CONNECTOR_HDMIA);
  2129.         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
  2130.  
  2131.         connector->interlace_allowed = 1;
  2132.         connector->doublescan_allowed = 0;
  2133.         connector->stereo_allowed = 1;
  2134.  
  2135.         switch (port) {
  2136.         case PORT_B:
  2137.                 if (IS_BROXTON(dev_priv))
  2138.                         intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
  2139.                 else
  2140.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
  2141.                 /*
  2142.                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
  2143.                  * interrupts to check the external panel connection.
  2144.                  */
  2145.                 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
  2146.                         intel_encoder->hpd_pin = HPD_PORT_A;
  2147.                 else
  2148.                         intel_encoder->hpd_pin = HPD_PORT_B;
  2149.                 break;
  2150.         case PORT_C:
  2151.                 if (IS_BROXTON(dev_priv))
  2152.                         intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
  2153.                 else
  2154.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
  2155.                 intel_encoder->hpd_pin = HPD_PORT_C;
  2156.                 break;
  2157.         case PORT_D:
  2158.                 if (WARN_ON(IS_BROXTON(dev_priv)))
  2159.                         intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
  2160.                 else if (IS_CHERRYVIEW(dev_priv))
  2161.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
  2162.                 else
  2163.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
  2164.                 intel_encoder->hpd_pin = HPD_PORT_D;
  2165.                 break;
  2166.         case PORT_E:
  2167.                 /* On SKL PORT E doesn't have seperate GMBUS pin
  2168.                  *  We rely on VBT to set a proper alternate GMBUS pin. */
  2169.                 alternate_ddc_pin =
  2170.                         dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
  2171.                 switch (alternate_ddc_pin) {
  2172.                 case DDC_PIN_B:
  2173.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
  2174.                         break;
  2175.                 case DDC_PIN_C:
  2176.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
  2177.                         break;
  2178.                 case DDC_PIN_D:
  2179.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
  2180.                         break;
  2181.                 default:
  2182.                         MISSING_CASE(alternate_ddc_pin);
  2183.                 }
  2184.                 intel_encoder->hpd_pin = HPD_PORT_E;
  2185.                 break;
  2186.         case PORT_A:
  2187.                 intel_encoder->hpd_pin = HPD_PORT_A;
  2188.                 /* Internal port only for eDP. */
  2189.         default:
  2190.                 BUG();
  2191.         }
  2192.  
  2193.         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
  2194.                 intel_hdmi->write_infoframe = vlv_write_infoframe;
  2195.                 intel_hdmi->set_infoframes = vlv_set_infoframes;
  2196.                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
  2197.         } else if (IS_G4X(dev)) {
  2198.                 intel_hdmi->write_infoframe = g4x_write_infoframe;
  2199.                 intel_hdmi->set_infoframes = g4x_set_infoframes;
  2200.                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
  2201.         } else if (HAS_DDI(dev)) {
  2202.                 intel_hdmi->write_infoframe = hsw_write_infoframe;
  2203.                 intel_hdmi->set_infoframes = hsw_set_infoframes;
  2204.                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
  2205.         } else if (HAS_PCH_IBX(dev)) {
  2206.                 intel_hdmi->write_infoframe = ibx_write_infoframe;
  2207.                 intel_hdmi->set_infoframes = ibx_set_infoframes;
  2208.                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
  2209.         } else {
  2210.                 intel_hdmi->write_infoframe = cpt_write_infoframe;
  2211.                 intel_hdmi->set_infoframes = cpt_set_infoframes;
  2212.                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
  2213.         }
  2214.  
  2215.         if (HAS_DDI(dev))
  2216.                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
  2217.         else
  2218.                 intel_connector->get_hw_state = intel_connector_get_hw_state;
  2219.         intel_connector->unregister = intel_connector_unregister;
  2220.  
  2221.         intel_hdmi_add_properties(intel_hdmi, connector);
  2222.  
  2223.         intel_connector_attach_encoder(intel_connector, intel_encoder);
  2224.         drm_connector_register(connector);
  2225.         intel_hdmi->attached_connector = intel_connector;
  2226.  
  2227.         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  2228.          * 0xd.  Failure to do so will result in spurious interrupts being
  2229.          * generated on the port when a cable is not attached.
  2230.          */
  2231.         if (IS_G4X(dev) && !IS_GM45(dev)) {
  2232.                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  2233.                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  2234.         }
  2235. }
  2236.  
  2237. void intel_hdmi_init(struct drm_device *dev,
  2238.                      i915_reg_t hdmi_reg, enum port port)
  2239. {
  2240.         struct intel_digital_port *intel_dig_port;
  2241.         struct intel_encoder *intel_encoder;
  2242.         struct intel_connector *intel_connector;
  2243.  
  2244.         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
  2245.         if (!intel_dig_port)
  2246.                 return;
  2247.  
  2248.         intel_connector = intel_connector_alloc();
  2249.         if (!intel_connector) {
  2250.                 kfree(intel_dig_port);
  2251.                 return;
  2252.         }
  2253.  
  2254.         intel_encoder = &intel_dig_port->base;
  2255.  
  2256.         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
  2257.                          DRM_MODE_ENCODER_TMDS, NULL);
  2258.  
  2259.         intel_encoder->compute_config = intel_hdmi_compute_config;
  2260.         if (HAS_PCH_SPLIT(dev)) {
  2261.                 intel_encoder->disable = pch_disable_hdmi;
  2262.                 intel_encoder->post_disable = pch_post_disable_hdmi;
  2263.         } else {
  2264.                 intel_encoder->disable = g4x_disable_hdmi;
  2265.         }
  2266.         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
  2267.         intel_encoder->get_config = intel_hdmi_get_config;
  2268.         if (IS_CHERRYVIEW(dev)) {
  2269.                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
  2270.                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
  2271.                 intel_encoder->enable = vlv_enable_hdmi;
  2272.                 intel_encoder->post_disable = chv_hdmi_post_disable;
  2273.                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
  2274.         } else if (IS_VALLEYVIEW(dev)) {
  2275.                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
  2276.                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
  2277.                 intel_encoder->enable = vlv_enable_hdmi;
  2278.                 intel_encoder->post_disable = vlv_hdmi_post_disable;
  2279.         } else {
  2280.                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
  2281.                 if (HAS_PCH_CPT(dev))
  2282.                         intel_encoder->enable = cpt_enable_hdmi;
  2283.                 else if (HAS_PCH_IBX(dev))
  2284.                         intel_encoder->enable = ibx_enable_hdmi;
  2285.                 else
  2286.                         intel_encoder->enable = g4x_enable_hdmi;
  2287.         }
  2288.  
  2289.         intel_encoder->type = INTEL_OUTPUT_HDMI;
  2290.         if (IS_CHERRYVIEW(dev)) {
  2291.                 if (port == PORT_D)
  2292.                         intel_encoder->crtc_mask = 1 << 2;
  2293.                 else
  2294.                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
  2295.         } else {
  2296.                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2297.         }
  2298.         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
  2299.         /*
  2300.          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
  2301.          * to work on real hardware. And since g4x can send infoframes to
  2302.          * only one port anyway, nothing is lost by allowing it.
  2303.          */
  2304.         if (IS_G4X(dev))
  2305.                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
  2306.  
  2307.         intel_dig_port->port = port;
  2308.         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
  2309.         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
  2310.         intel_dig_port->max_lanes = 4;
  2311.  
  2312.         intel_hdmi_init_connector(intel_dig_port, intel_connector);
  2313. }
  2314.