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  1. /*
  2.  * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright © 2006-2009 Intel Corporation
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the "Software"),
  7.  * to deal in the Software without restriction, including without limitation
  8.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9.  * and/or sell copies of the Software, and to permit persons to whom the
  10.  * Software is furnished to do so, subject to the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the next
  13.  * paragraph) shall be included in all copies or substantial portions of the
  14.  * Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22.  * DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *      Eric Anholt <eric@anholt.net>
  26.  *      Jesse Barnes <jesse.barnes@intel.com>
  27.  */
  28.  
  29. #include <linux/i2c.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include <linux/hdmi.h>
  33. #include <drm/drmP.h>
  34. #include <drm/drm_atomic_helper.h>
  35. #include <drm/drm_crtc.h>
  36. #include <drm/drm_edid.h>
  37. #include "intel_drv.h"
  38. #include <drm/i915_drm.h>
  39. #include "i915_drv.h"
  40.  
  41. static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  42. {
  43.         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  44. }
  45.  
  46. static void
  47. assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  48. {
  49.         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  50.         struct drm_i915_private *dev_priv = dev->dev_private;
  51.         uint32_t enabled_bits;
  52.  
  53.         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  54.  
  55.         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  56.              "HDMI port enabled, expecting disabled\n");
  57. }
  58.  
  59. struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  60. {
  61.         struct intel_digital_port *intel_dig_port =
  62.                 container_of(encoder, struct intel_digital_port, base.base);
  63.         return &intel_dig_port->hdmi;
  64. }
  65.  
  66. static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  67. {
  68.         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  69. }
  70.  
  71. static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  72. {
  73.         switch (type) {
  74.         case HDMI_INFOFRAME_TYPE_AVI:
  75.                 return VIDEO_DIP_SELECT_AVI;
  76.         case HDMI_INFOFRAME_TYPE_SPD:
  77.                 return VIDEO_DIP_SELECT_SPD;
  78.         case HDMI_INFOFRAME_TYPE_VENDOR:
  79.                 return VIDEO_DIP_SELECT_VENDOR;
  80.         default:
  81.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  82.                 return 0;
  83.         }
  84. }
  85.  
  86. static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  87. {
  88.         switch (type) {
  89.         case HDMI_INFOFRAME_TYPE_AVI:
  90.                 return VIDEO_DIP_ENABLE_AVI;
  91.         case HDMI_INFOFRAME_TYPE_SPD:
  92.                 return VIDEO_DIP_ENABLE_SPD;
  93.         case HDMI_INFOFRAME_TYPE_VENDOR:
  94.                 return VIDEO_DIP_ENABLE_VENDOR;
  95.         default:
  96.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  97.                 return 0;
  98.         }
  99. }
  100.  
  101. static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
  102. {
  103.         switch (type) {
  104.         case HDMI_INFOFRAME_TYPE_AVI:
  105.                 return VIDEO_DIP_ENABLE_AVI_HSW;
  106.         case HDMI_INFOFRAME_TYPE_SPD:
  107.                 return VIDEO_DIP_ENABLE_SPD_HSW;
  108.         case HDMI_INFOFRAME_TYPE_VENDOR:
  109.                 return VIDEO_DIP_ENABLE_VS_HSW;
  110.         default:
  111.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  112.                 return 0;
  113.         }
  114. }
  115.  
  116. static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
  117.                             enum transcoder cpu_transcoder,
  118.                             enum hdmi_infoframe_type type,
  119.                             int i)
  120. {
  121.         switch (type) {
  122.         case HDMI_INFOFRAME_TYPE_AVI:
  123.                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
  124.         case HDMI_INFOFRAME_TYPE_SPD:
  125.                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
  126.         case HDMI_INFOFRAME_TYPE_VENDOR:
  127.                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
  128.         default:
  129.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  130.                 return 0;
  131.         }
  132. }
  133.  
  134. static void g4x_write_infoframe(struct drm_encoder *encoder,
  135.                                 enum hdmi_infoframe_type type,
  136.                                 const void *frame, ssize_t len)
  137. {
  138.         const uint32_t *data = frame;
  139.         struct drm_device *dev = encoder->dev;
  140.         struct drm_i915_private *dev_priv = dev->dev_private;
  141.         u32 val = I915_READ(VIDEO_DIP_CTL);
  142.         int i;
  143.  
  144.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  145.  
  146.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  147.         val |= g4x_infoframe_index(type);
  148.  
  149.         val &= ~g4x_infoframe_enable(type);
  150.  
  151.         I915_WRITE(VIDEO_DIP_CTL, val);
  152.  
  153.         mmiowb();
  154.         for (i = 0; i < len; i += 4) {
  155.                 I915_WRITE(VIDEO_DIP_DATA, *data);
  156.                 data++;
  157.         }
  158.         /* Write every possible data byte to force correct ECC calculation. */
  159.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  160.                 I915_WRITE(VIDEO_DIP_DATA, 0);
  161.         mmiowb();
  162.  
  163.         val |= g4x_infoframe_enable(type);
  164.         val &= ~VIDEO_DIP_FREQ_MASK;
  165.         val |= VIDEO_DIP_FREQ_VSYNC;
  166.  
  167.         I915_WRITE(VIDEO_DIP_CTL, val);
  168.         POSTING_READ(VIDEO_DIP_CTL);
  169. }
  170.  
  171. static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
  172. {
  173.         struct drm_device *dev = encoder->dev;
  174.         struct drm_i915_private *dev_priv = dev->dev_private;
  175.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  176.         u32 val = I915_READ(VIDEO_DIP_CTL);
  177.  
  178.         if ((val & VIDEO_DIP_ENABLE) == 0)
  179.                 return false;
  180.  
  181.         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
  182.                 return false;
  183.  
  184.         return val & (VIDEO_DIP_ENABLE_AVI |
  185.                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
  186. }
  187.  
  188. static void ibx_write_infoframe(struct drm_encoder *encoder,
  189.                                 enum hdmi_infoframe_type type,
  190.                                 const void *frame, ssize_t len)
  191. {
  192.         const uint32_t *data = frame;
  193.         struct drm_device *dev = encoder->dev;
  194.         struct drm_i915_private *dev_priv = dev->dev_private;
  195.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  196.         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  197.         u32 val = I915_READ(reg);
  198.  
  199.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  200.  
  201.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  202.         val |= g4x_infoframe_index(type);
  203.  
  204.         val &= ~g4x_infoframe_enable(type);
  205.  
  206.         I915_WRITE(reg, val);
  207.  
  208.         mmiowb();
  209.         for (i = 0; i < len; i += 4) {
  210.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  211.                 data++;
  212.         }
  213.         /* Write every possible data byte to force correct ECC calculation. */
  214.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  215.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  216.         mmiowb();
  217.  
  218.         val |= g4x_infoframe_enable(type);
  219.         val &= ~VIDEO_DIP_FREQ_MASK;
  220.         val |= VIDEO_DIP_FREQ_VSYNC;
  221.  
  222.         I915_WRITE(reg, val);
  223.         POSTING_READ(reg);
  224. }
  225.  
  226. static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
  227. {
  228.         struct drm_device *dev = encoder->dev;
  229.         struct drm_i915_private *dev_priv = dev->dev_private;
  230.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  231.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  232.         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  233.         u32 val = I915_READ(reg);
  234.  
  235.         if ((val & VIDEO_DIP_ENABLE) == 0)
  236.                 return false;
  237.  
  238.         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
  239.                 return false;
  240.  
  241.         return val & (VIDEO_DIP_ENABLE_AVI |
  242.                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  243.                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  244. }
  245.  
  246. static void cpt_write_infoframe(struct drm_encoder *encoder,
  247.                                 enum hdmi_infoframe_type type,
  248.                                 const void *frame, ssize_t len)
  249. {
  250.         const uint32_t *data = frame;
  251.         struct drm_device *dev = encoder->dev;
  252.         struct drm_i915_private *dev_priv = dev->dev_private;
  253.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  254.         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  255.         u32 val = I915_READ(reg);
  256.  
  257.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  258.  
  259.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  260.         val |= g4x_infoframe_index(type);
  261.  
  262.         /* The DIP control register spec says that we need to update the AVI
  263.          * infoframe without clearing its enable bit */
  264.         if (type != HDMI_INFOFRAME_TYPE_AVI)
  265.                 val &= ~g4x_infoframe_enable(type);
  266.  
  267.         I915_WRITE(reg, val);
  268.  
  269.         mmiowb();
  270.         for (i = 0; i < len; i += 4) {
  271.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  272.                 data++;
  273.         }
  274.         /* Write every possible data byte to force correct ECC calculation. */
  275.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  276.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  277.         mmiowb();
  278.  
  279.         val |= g4x_infoframe_enable(type);
  280.         val &= ~VIDEO_DIP_FREQ_MASK;
  281.         val |= VIDEO_DIP_FREQ_VSYNC;
  282.  
  283.         I915_WRITE(reg, val);
  284.         POSTING_READ(reg);
  285. }
  286.  
  287. static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
  288. {
  289.         struct drm_device *dev = encoder->dev;
  290.         struct drm_i915_private *dev_priv = dev->dev_private;
  291.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  292.         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  293.         u32 val = I915_READ(reg);
  294.  
  295.         if ((val & VIDEO_DIP_ENABLE) == 0)
  296.                 return false;
  297.  
  298.         return val & (VIDEO_DIP_ENABLE_AVI |
  299.                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  300.                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  301. }
  302.  
  303. static void vlv_write_infoframe(struct drm_encoder *encoder,
  304.                                 enum hdmi_infoframe_type type,
  305.                                 const void *frame, ssize_t len)
  306. {
  307.         const uint32_t *data = frame;
  308.         struct drm_device *dev = encoder->dev;
  309.         struct drm_i915_private *dev_priv = dev->dev_private;
  310.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  311.         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  312.         u32 val = I915_READ(reg);
  313.  
  314.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  315.  
  316.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  317.         val |= g4x_infoframe_index(type);
  318.  
  319.         val &= ~g4x_infoframe_enable(type);
  320.  
  321.         I915_WRITE(reg, val);
  322.  
  323.         mmiowb();
  324.         for (i = 0; i < len; i += 4) {
  325.                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  326.                 data++;
  327.         }
  328.         /* Write every possible data byte to force correct ECC calculation. */
  329.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  330.                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  331.         mmiowb();
  332.  
  333.         val |= g4x_infoframe_enable(type);
  334.         val &= ~VIDEO_DIP_FREQ_MASK;
  335.         val |= VIDEO_DIP_FREQ_VSYNC;
  336.  
  337.         I915_WRITE(reg, val);
  338.         POSTING_READ(reg);
  339. }
  340.  
  341. static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
  342. {
  343.         struct drm_device *dev = encoder->dev;
  344.         struct drm_i915_private *dev_priv = dev->dev_private;
  345.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  346.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  347.         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  348.         u32 val = I915_READ(reg);
  349.  
  350.         if ((val & VIDEO_DIP_ENABLE) == 0)
  351.                 return false;
  352.  
  353.         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
  354.                 return false;
  355.  
  356.         return val & (VIDEO_DIP_ENABLE_AVI |
  357.                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  358.                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  359. }
  360.  
  361. static void hsw_write_infoframe(struct drm_encoder *encoder,
  362.                                 enum hdmi_infoframe_type type,
  363.                                 const void *frame, ssize_t len)
  364. {
  365.         const uint32_t *data = frame;
  366.         struct drm_device *dev = encoder->dev;
  367.         struct drm_i915_private *dev_priv = dev->dev_private;
  368.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  369.         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  370.         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
  371.         u32 data_reg;
  372.         int i;
  373.         u32 val = I915_READ(ctl_reg);
  374.  
  375.         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
  376.         if (data_reg == 0)
  377.                 return;
  378.  
  379.         val &= ~hsw_infoframe_enable(type);
  380.         I915_WRITE(ctl_reg, val);
  381.  
  382.         mmiowb();
  383.         for (i = 0; i < len; i += 4) {
  384.                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
  385.                                             type, i >> 2), *data);
  386.                 data++;
  387.         }
  388.         /* Write every possible data byte to force correct ECC calculation. */
  389.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  390.                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
  391.                                             type, i >> 2), 0);
  392.         mmiowb();
  393.  
  394.         val |= hsw_infoframe_enable(type);
  395.         I915_WRITE(ctl_reg, val);
  396.         POSTING_READ(ctl_reg);
  397. }
  398.  
  399. static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
  400. {
  401.         struct drm_device *dev = encoder->dev;
  402.         struct drm_i915_private *dev_priv = dev->dev_private;
  403.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  404.         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
  405.         u32 val = I915_READ(ctl_reg);
  406.  
  407.         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
  408.                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
  409.                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
  410. }
  411.  
  412. /*
  413.  * The data we write to the DIP data buffer registers is 1 byte bigger than the
  414.  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
  415.  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
  416.  * used for both technologies.
  417.  *
  418.  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
  419.  * DW1:       DB3       | DB2 | DB1 | DB0
  420.  * DW2:       DB7       | DB6 | DB5 | DB4
  421.  * DW3: ...
  422.  *
  423.  * (HB is Header Byte, DB is Data Byte)
  424.  *
  425.  * The hdmi pack() functions don't know about that hardware specific hole so we
  426.  * trick them by giving an offset into the buffer and moving back the header
  427.  * bytes by one.
  428.  */
  429. static void intel_write_infoframe(struct drm_encoder *encoder,
  430.                                   union hdmi_infoframe *frame)
  431. {
  432.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  433.         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
  434.         ssize_t len;
  435.  
  436.         /* see comment above for the reason for this offset */
  437.         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
  438.         if (len < 0)
  439.                 return;
  440.  
  441.         /* Insert the 'hole' (see big comment above) at position 3 */
  442.         buffer[0] = buffer[1];
  443.         buffer[1] = buffer[2];
  444.         buffer[2] = buffer[3];
  445.         buffer[3] = 0;
  446.         len++;
  447.  
  448.         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
  449. }
  450.  
  451. static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
  452.                                          const struct drm_display_mode *adjusted_mode)
  453. {
  454.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  455.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  456.         union hdmi_infoframe frame;
  457.         int ret;
  458.  
  459.         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
  460.                                                        adjusted_mode);
  461.         if (ret < 0) {
  462.                 DRM_ERROR("couldn't fill AVI infoframe\n");
  463.                 return;
  464.         }
  465.  
  466.         if (intel_hdmi->rgb_quant_range_selectable) {
  467.                 if (intel_crtc->config->limited_color_range)
  468.                         frame.avi.quantization_range =
  469.                                 HDMI_QUANTIZATION_RANGE_LIMITED;
  470.                 else
  471.                         frame.avi.quantization_range =
  472.                                 HDMI_QUANTIZATION_RANGE_FULL;
  473.         }
  474.  
  475.         intel_write_infoframe(encoder, &frame);
  476. }
  477.  
  478. static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
  479. {
  480.         union hdmi_infoframe frame;
  481.         int ret;
  482.  
  483.         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
  484.         if (ret < 0) {
  485.                 DRM_ERROR("couldn't fill SPD infoframe\n");
  486.                 return;
  487.         }
  488.  
  489.         frame.spd.sdi = HDMI_SPD_SDI_PC;
  490.  
  491.         intel_write_infoframe(encoder, &frame);
  492. }
  493.  
  494. static void
  495. intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
  496.                               const struct drm_display_mode *adjusted_mode)
  497. {
  498.         union hdmi_infoframe frame;
  499.         int ret;
  500.  
  501.         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
  502.                                                           adjusted_mode);
  503.         if (ret < 0)
  504.                 return;
  505.  
  506.         intel_write_infoframe(encoder, &frame);
  507. }
  508.  
  509. static void g4x_set_infoframes(struct drm_encoder *encoder,
  510.                                bool enable,
  511.                                const struct drm_display_mode *adjusted_mode)
  512. {
  513.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  514.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  515.         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  516.         u32 reg = VIDEO_DIP_CTL;
  517.         u32 val = I915_READ(reg);
  518.         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
  519.  
  520.         assert_hdmi_port_disabled(intel_hdmi);
  521.  
  522.         /* If the registers were not initialized yet, they might be zeroes,
  523.          * which means we're selecting the AVI DIP and we're setting its
  524.          * frequency to once. This seems to really confuse the HW and make
  525.          * things stop working (the register spec says the AVI always needs to
  526.          * be sent every VSync). So here we avoid writing to the register more
  527.          * than we need and also explicitly select the AVI DIP and explicitly
  528.          * set its frequency to every VSync. Avoiding to write it twice seems to
  529.          * be enough to solve the problem, but being defensive shouldn't hurt us
  530.          * either. */
  531.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  532.  
  533.         if (!enable) {
  534.                 if (!(val & VIDEO_DIP_ENABLE))
  535.                         return;
  536.                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
  537.                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
  538.                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
  539.                         return;
  540.                 }
  541.                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
  542.                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
  543.                 I915_WRITE(reg, val);
  544.                 POSTING_READ(reg);
  545.                 return;
  546.         }
  547.  
  548.         if (port != (val & VIDEO_DIP_PORT_MASK)) {
  549.                 if (val & VIDEO_DIP_ENABLE) {
  550.                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
  551.                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
  552.                         return;
  553.                 }
  554.                 val &= ~VIDEO_DIP_PORT_MASK;
  555.                 val |= port;
  556.         }
  557.  
  558.         val |= VIDEO_DIP_ENABLE;
  559.         val &= ~(VIDEO_DIP_ENABLE_AVI |
  560.                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
  561.  
  562.         I915_WRITE(reg, val);
  563.         POSTING_READ(reg);
  564.  
  565.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  566.         intel_hdmi_set_spd_infoframe(encoder);
  567.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  568. }
  569.  
  570. static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
  571. {
  572.         struct drm_device *dev = encoder->dev;
  573.         struct drm_connector *connector;
  574.  
  575.         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
  576.  
  577.         /*
  578.          * HDMI cloning is only supported on g4x which doesn't
  579.          * support deep color or GCP infoframes anyway so no
  580.          * need to worry about multiple HDMI sinks here.
  581.          */
  582.         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
  583.                 if (connector->encoder == encoder)
  584.                         return connector->display_info.bpc > 8;
  585.  
  586.         return false;
  587. }
  588.  
  589. /*
  590.  * Determine if default_phase=1 can be indicated in the GCP infoframe.
  591.  *
  592.  * From HDMI specification 1.4a:
  593.  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
  594.  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
  595.  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
  596.  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
  597.  *   phase of 0
  598.  */
  599. static bool gcp_default_phase_possible(int pipe_bpp,
  600.                                        const struct drm_display_mode *mode)
  601. {
  602.         unsigned int pixels_per_group;
  603.  
  604.         switch (pipe_bpp) {
  605.         case 30:
  606.                 /* 4 pixels in 5 clocks */
  607.                 pixels_per_group = 4;
  608.                 break;
  609.         case 36:
  610.                 /* 2 pixels in 3 clocks */
  611.                 pixels_per_group = 2;
  612.                 break;
  613.         case 48:
  614.                 /* 1 pixel in 2 clocks */
  615.                 pixels_per_group = 1;
  616.                 break;
  617.         default:
  618.                 /* phase information not relevant for 8bpc */
  619.                 return false;
  620.         }
  621.  
  622.         return mode->crtc_hdisplay % pixels_per_group == 0 &&
  623.                 mode->crtc_htotal % pixels_per_group == 0 &&
  624.                 mode->crtc_hblank_start % pixels_per_group == 0 &&
  625.                 mode->crtc_hblank_end % pixels_per_group == 0 &&
  626.                 mode->crtc_hsync_start % pixels_per_group == 0 &&
  627.                 mode->crtc_hsync_end % pixels_per_group == 0 &&
  628.                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
  629.                  mode->crtc_htotal/2 % pixels_per_group == 0);
  630. }
  631.  
  632. static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
  633. {
  634.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  635.         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
  636.         u32 reg, val = 0;
  637.  
  638.         if (HAS_DDI(dev_priv))
  639.                 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
  640.         else if (IS_VALLEYVIEW(dev_priv))
  641.                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
  642.         else if (HAS_PCH_SPLIT(dev_priv->dev))
  643.                 reg = TVIDEO_DIP_GCP(crtc->pipe);
  644.         else
  645.                 return false;
  646.  
  647.         /* Indicate color depth whenever the sink supports deep color */
  648.         if (hdmi_sink_is_deep_color(encoder))
  649.                 val |= GCP_COLOR_INDICATION;
  650.  
  651.         /* Enable default_phase whenever the display mode is suitably aligned */
  652.         if (gcp_default_phase_possible(crtc->config->pipe_bpp,
  653.                                        &crtc->config->base.adjusted_mode))
  654.                 val |= GCP_DEFAULT_PHASE_ENABLE;
  655.  
  656.         I915_WRITE(reg, val);
  657.  
  658.         return val != 0;
  659. }
  660.  
  661. static void ibx_set_infoframes(struct drm_encoder *encoder,
  662.                                bool enable,
  663.                                const struct drm_display_mode *adjusted_mode)
  664. {
  665.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  666.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  667.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  668.         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  669.         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  670.         u32 val = I915_READ(reg);
  671.         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
  672.  
  673.         assert_hdmi_port_disabled(intel_hdmi);
  674.  
  675.         /* See the big comment in g4x_set_infoframes() */
  676.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  677.  
  678.         if (!enable) {
  679.                 if (!(val & VIDEO_DIP_ENABLE))
  680.                         return;
  681.                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
  682.                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  683.                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  684.                 I915_WRITE(reg, val);
  685.                 POSTING_READ(reg);
  686.                 return;
  687.         }
  688.  
  689.         if (port != (val & VIDEO_DIP_PORT_MASK)) {
  690.                 WARN(val & VIDEO_DIP_ENABLE,
  691.                      "DIP already enabled on port %c\n",
  692.                      (val & VIDEO_DIP_PORT_MASK) >> 29);
  693.                 val &= ~VIDEO_DIP_PORT_MASK;
  694.                 val |= port;
  695.         }
  696.  
  697.         val |= VIDEO_DIP_ENABLE;
  698.         val &= ~(VIDEO_DIP_ENABLE_AVI |
  699.                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  700.                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  701.  
  702.         if (intel_hdmi_set_gcp_infoframe(encoder))
  703.                 val |= VIDEO_DIP_ENABLE_GCP;
  704.  
  705.         I915_WRITE(reg, val);
  706.         POSTING_READ(reg);
  707.  
  708.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  709.         intel_hdmi_set_spd_infoframe(encoder);
  710.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  711. }
  712.  
  713. static void cpt_set_infoframes(struct drm_encoder *encoder,
  714.                                bool enable,
  715.                                const struct drm_display_mode *adjusted_mode)
  716. {
  717.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  718.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  719.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  720.         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  721.         u32 val = I915_READ(reg);
  722.  
  723.         assert_hdmi_port_disabled(intel_hdmi);
  724.  
  725.         /* See the big comment in g4x_set_infoframes() */
  726.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  727.  
  728.         if (!enable) {
  729.                 if (!(val & VIDEO_DIP_ENABLE))
  730.                         return;
  731.                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
  732.                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  733.                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  734.                 I915_WRITE(reg, val);
  735.                 POSTING_READ(reg);
  736.                 return;
  737.         }
  738.  
  739.         /* Set both together, unset both together: see the spec. */
  740.         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
  741.         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  742.                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  743.  
  744.         if (intel_hdmi_set_gcp_infoframe(encoder))
  745.                 val |= VIDEO_DIP_ENABLE_GCP;
  746.  
  747.         I915_WRITE(reg, val);
  748.         POSTING_READ(reg);
  749.  
  750.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  751.         intel_hdmi_set_spd_infoframe(encoder);
  752.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  753. }
  754.  
  755. static void vlv_set_infoframes(struct drm_encoder *encoder,
  756.                                bool enable,
  757.                                const struct drm_display_mode *adjusted_mode)
  758. {
  759.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  760.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  761.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  762.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  763.         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  764.         u32 val = I915_READ(reg);
  765.         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
  766.  
  767.         assert_hdmi_port_disabled(intel_hdmi);
  768.  
  769.         /* See the big comment in g4x_set_infoframes() */
  770.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  771.  
  772.         if (!enable) {
  773.                 if (!(val & VIDEO_DIP_ENABLE))
  774.                         return;
  775.                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
  776.                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  777.                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  778.                 I915_WRITE(reg, val);
  779.                 POSTING_READ(reg);
  780.                 return;
  781.         }
  782.  
  783.         if (port != (val & VIDEO_DIP_PORT_MASK)) {
  784.                 WARN(val & VIDEO_DIP_ENABLE,
  785.                      "DIP already enabled on port %c\n",
  786.                      (val & VIDEO_DIP_PORT_MASK) >> 29);
  787.                 val &= ~VIDEO_DIP_PORT_MASK;
  788.                 val |= port;
  789.         }
  790.  
  791.         val |= VIDEO_DIP_ENABLE;
  792.         val &= ~(VIDEO_DIP_ENABLE_AVI |
  793.                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  794.                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  795.  
  796.         if (intel_hdmi_set_gcp_infoframe(encoder))
  797.                 val |= VIDEO_DIP_ENABLE_GCP;
  798.  
  799.         I915_WRITE(reg, val);
  800.         POSTING_READ(reg);
  801.  
  802.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  803.         intel_hdmi_set_spd_infoframe(encoder);
  804.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  805. }
  806.  
  807. static void hsw_set_infoframes(struct drm_encoder *encoder,
  808.                                bool enable,
  809.                                const struct drm_display_mode *adjusted_mode)
  810. {
  811.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  812.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  813.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  814.         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
  815.         u32 val = I915_READ(reg);
  816.  
  817.         assert_hdmi_port_disabled(intel_hdmi);
  818.  
  819.         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
  820.                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
  821.                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
  822.  
  823.         if (!enable) {
  824.                 I915_WRITE(reg, val);
  825.                 POSTING_READ(reg);
  826.                 return;
  827.         }
  828.  
  829.         if (intel_hdmi_set_gcp_infoframe(encoder))
  830.                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
  831.  
  832.         I915_WRITE(reg, val);
  833.         POSTING_READ(reg);
  834.  
  835.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  836.         intel_hdmi_set_spd_infoframe(encoder);
  837.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  838. }
  839.  
  840. static void intel_hdmi_prepare(struct intel_encoder *encoder)
  841. {
  842.         struct drm_device *dev = encoder->base.dev;
  843.         struct drm_i915_private *dev_priv = dev->dev_private;
  844.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  845.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  846.         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  847.         u32 hdmi_val;
  848.  
  849.         hdmi_val = SDVO_ENCODING_HDMI;
  850.         if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
  851.                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
  852.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  853.                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
  854.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  855.                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
  856.  
  857.         if (crtc->config->pipe_bpp > 24)
  858.                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
  859.         else
  860.                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
  861.  
  862.         if (crtc->config->has_hdmi_sink)
  863.                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
  864.  
  865.         if (HAS_PCH_CPT(dev))
  866.                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
  867.         else if (IS_CHERRYVIEW(dev))
  868.                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
  869.         else
  870.                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
  871.  
  872.         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
  873.         POSTING_READ(intel_hdmi->hdmi_reg);
  874. }
  875.  
  876. static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
  877.                                     enum pipe *pipe)
  878. {
  879.         struct drm_device *dev = encoder->base.dev;
  880.         struct drm_i915_private *dev_priv = dev->dev_private;
  881.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  882.         enum intel_display_power_domain power_domain;
  883.         u32 tmp;
  884.  
  885.         power_domain = intel_display_port_power_domain(encoder);
  886.         if (!intel_display_power_is_enabled(dev_priv, power_domain))
  887.                 return false;
  888.  
  889.         tmp = I915_READ(intel_hdmi->hdmi_reg);
  890.  
  891.         if (!(tmp & SDVO_ENABLE))
  892.                 return false;
  893.  
  894.         if (HAS_PCH_CPT(dev))
  895.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  896.         else if (IS_CHERRYVIEW(dev))
  897.                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
  898.         else
  899.                 *pipe = PORT_TO_PIPE(tmp);
  900.  
  901.         return true;
  902. }
  903.  
  904. static void intel_hdmi_get_config(struct intel_encoder *encoder,
  905.                                   struct intel_crtc_state *pipe_config)
  906. {
  907.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  908.         struct drm_device *dev = encoder->base.dev;
  909.         struct drm_i915_private *dev_priv = dev->dev_private;
  910.         u32 tmp, flags = 0;
  911.         int dotclock;
  912.  
  913.         tmp = I915_READ(intel_hdmi->hdmi_reg);
  914.  
  915.         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
  916.                 flags |= DRM_MODE_FLAG_PHSYNC;
  917.         else
  918.                 flags |= DRM_MODE_FLAG_NHSYNC;
  919.  
  920.         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
  921.                 flags |= DRM_MODE_FLAG_PVSYNC;
  922.         else
  923.                 flags |= DRM_MODE_FLAG_NVSYNC;
  924.  
  925.         if (tmp & HDMI_MODE_SELECT_HDMI)
  926.                 pipe_config->has_hdmi_sink = true;
  927.  
  928.         if (intel_hdmi->infoframe_enabled(&encoder->base))
  929.                 pipe_config->has_infoframe = true;
  930.  
  931.         if (tmp & SDVO_AUDIO_ENABLE)
  932.                 pipe_config->has_audio = true;
  933.  
  934.         if (!HAS_PCH_SPLIT(dev) &&
  935.             tmp & HDMI_COLOR_RANGE_16_235)
  936.                 pipe_config->limited_color_range = true;
  937.  
  938.         pipe_config->base.adjusted_mode.flags |= flags;
  939.  
  940.         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
  941.                 dotclock = pipe_config->port_clock * 2 / 3;
  942.         else
  943.                 dotclock = pipe_config->port_clock;
  944.  
  945.         if (pipe_config->pixel_multiplier)
  946.                 dotclock /= pipe_config->pixel_multiplier;
  947.  
  948.         if (HAS_PCH_SPLIT(dev_priv->dev))
  949.                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
  950.  
  951.         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
  952. }
  953.  
  954. static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
  955. {
  956.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  957.  
  958.         WARN_ON(!crtc->config->has_hdmi_sink);
  959.         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
  960.                          pipe_name(crtc->pipe));
  961.         intel_audio_codec_enable(encoder);
  962. }
  963.  
  964. static void g4x_enable_hdmi(struct intel_encoder *encoder)
  965. {
  966.         struct drm_device *dev = encoder->base.dev;
  967.         struct drm_i915_private *dev_priv = dev->dev_private;
  968.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  969.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  970.         u32 temp;
  971.  
  972.         temp = I915_READ(intel_hdmi->hdmi_reg);
  973.  
  974.         temp |= SDVO_ENABLE;
  975.         if (crtc->config->has_audio)
  976.                 temp |= SDVO_AUDIO_ENABLE;
  977.  
  978.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  979.         POSTING_READ(intel_hdmi->hdmi_reg);
  980.  
  981.         if (crtc->config->has_audio)
  982.                 intel_enable_hdmi_audio(encoder);
  983. }
  984.  
  985. static void ibx_enable_hdmi(struct intel_encoder *encoder)
  986. {
  987.         struct drm_device *dev = encoder->base.dev;
  988.         struct drm_i915_private *dev_priv = dev->dev_private;
  989.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  990.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  991.         u32 temp;
  992.  
  993.         temp = I915_READ(intel_hdmi->hdmi_reg);
  994.  
  995.         temp |= SDVO_ENABLE;
  996.         if (crtc->config->has_audio)
  997.                 temp |= SDVO_AUDIO_ENABLE;
  998.  
  999.         /*
  1000.          * HW workaround, need to write this twice for issue
  1001.          * that may result in first write getting masked.
  1002.          */
  1003.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1004.         POSTING_READ(intel_hdmi->hdmi_reg);
  1005.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1006.         POSTING_READ(intel_hdmi->hdmi_reg);
  1007.  
  1008.         /*
  1009.          * HW workaround, need to toggle enable bit off and on
  1010.          * for 12bpc with pixel repeat.
  1011.          *
  1012.          * FIXME: BSpec says this should be done at the end of
  1013.          * of the modeset sequence, so not sure if this isn't too soon.
  1014.          */
  1015.         if (crtc->config->pipe_bpp > 24 &&
  1016.             crtc->config->pixel_multiplier > 1) {
  1017.                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
  1018.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1019.  
  1020.                 /*
  1021.                  * HW workaround, need to write this twice for issue
  1022.                  * that may result in first write getting masked.
  1023.                  */
  1024.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1025.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1026.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1027.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1028.         }
  1029.  
  1030.         if (crtc->config->has_audio)
  1031.                 intel_enable_hdmi_audio(encoder);
  1032. }
  1033.  
  1034. static void cpt_enable_hdmi(struct intel_encoder *encoder)
  1035. {
  1036.         struct drm_device *dev = encoder->base.dev;
  1037.         struct drm_i915_private *dev_priv = dev->dev_private;
  1038.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1039.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  1040.         enum pipe pipe = crtc->pipe;
  1041.         u32 temp;
  1042.  
  1043.         temp = I915_READ(intel_hdmi->hdmi_reg);
  1044.  
  1045.         temp |= SDVO_ENABLE;
  1046.         if (crtc->config->has_audio)
  1047.                 temp |= SDVO_AUDIO_ENABLE;
  1048.  
  1049.         /*
  1050.          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
  1051.          *
  1052.          * The procedure for 12bpc is as follows:
  1053.          * 1. disable HDMI clock gating
  1054.          * 2. enable HDMI with 8bpc
  1055.          * 3. enable HDMI with 12bpc
  1056.          * 4. enable HDMI clock gating
  1057.          */
  1058.  
  1059.         if (crtc->config->pipe_bpp > 24) {
  1060.                 I915_WRITE(TRANS_CHICKEN1(pipe),
  1061.                            I915_READ(TRANS_CHICKEN1(pipe)) |
  1062.                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
  1063.  
  1064.                 temp &= ~SDVO_COLOR_FORMAT_MASK;
  1065.                 temp |= SDVO_COLOR_FORMAT_8bpc;
  1066.         }
  1067.  
  1068.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1069.         POSTING_READ(intel_hdmi->hdmi_reg);
  1070.  
  1071.         if (crtc->config->pipe_bpp > 24) {
  1072.                 temp &= ~SDVO_COLOR_FORMAT_MASK;
  1073.                 temp |= HDMI_COLOR_FORMAT_12bpc;
  1074.  
  1075.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1076.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1077.  
  1078.                 I915_WRITE(TRANS_CHICKEN1(pipe),
  1079.                            I915_READ(TRANS_CHICKEN1(pipe)) &
  1080.                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
  1081.         }
  1082.  
  1083.         if (crtc->config->has_audio)
  1084.                 intel_enable_hdmi_audio(encoder);
  1085. }
  1086.  
  1087. static void vlv_enable_hdmi(struct intel_encoder *encoder)
  1088. {
  1089. }
  1090.  
  1091. static void intel_disable_hdmi(struct intel_encoder *encoder)
  1092. {
  1093.         struct drm_device *dev = encoder->base.dev;
  1094.         struct drm_i915_private *dev_priv = dev->dev_private;
  1095.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  1096.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1097.         u32 temp;
  1098.  
  1099.         temp = I915_READ(intel_hdmi->hdmi_reg);
  1100.  
  1101.         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
  1102.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1103.         POSTING_READ(intel_hdmi->hdmi_reg);
  1104.  
  1105.         /*
  1106.          * HW workaround for IBX, we need to move the port
  1107.          * to transcoder A after disabling it to allow the
  1108.          * matching DP port to be enabled on transcoder A.
  1109.          */
  1110.         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
  1111.                 temp &= ~SDVO_PIPE_B_SELECT;
  1112.                 temp |= SDVO_ENABLE;
  1113.                 /*
  1114.                  * HW workaround, need to write this twice for issue
  1115.                  * that may result in first write getting masked.
  1116.                  */
  1117.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1118.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1119.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1120.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1121.  
  1122.                 temp &= ~SDVO_ENABLE;
  1123.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  1124.                 POSTING_READ(intel_hdmi->hdmi_reg);
  1125.         }
  1126.  
  1127.         intel_hdmi->set_infoframes(&encoder->base, false, NULL);
  1128. }
  1129.  
  1130. static void g4x_disable_hdmi(struct intel_encoder *encoder)
  1131. {
  1132.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1133.  
  1134.         if (crtc->config->has_audio)
  1135.                 intel_audio_codec_disable(encoder);
  1136.  
  1137.         intel_disable_hdmi(encoder);
  1138. }
  1139.  
  1140. static void pch_disable_hdmi(struct intel_encoder *encoder)
  1141. {
  1142.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1143.  
  1144.         if (crtc->config->has_audio)
  1145.                 intel_audio_codec_disable(encoder);
  1146. }
  1147.  
  1148. static void pch_post_disable_hdmi(struct intel_encoder *encoder)
  1149. {
  1150.         intel_disable_hdmi(encoder);
  1151. }
  1152.  
  1153. static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
  1154. {
  1155.         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
  1156.  
  1157.         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
  1158.                 return 165000;
  1159.         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
  1160.                 return 300000;
  1161.         else
  1162.                 return 225000;
  1163. }
  1164.  
  1165. static enum drm_mode_status
  1166. hdmi_port_clock_valid(struct intel_hdmi *hdmi,
  1167.                       int clock, bool respect_dvi_limit)
  1168. {
  1169.         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
  1170.  
  1171.         if (clock < 25000)
  1172.                 return MODE_CLOCK_LOW;
  1173.         if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
  1174.                 return MODE_CLOCK_HIGH;
  1175.  
  1176.         /* BXT DPLL can't generate 223-240 MHz */
  1177.         if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
  1178.                 return MODE_CLOCK_RANGE;
  1179.  
  1180.         /* CHV DPLL can't generate 216-240 MHz */
  1181.         if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
  1182.                 return MODE_CLOCK_RANGE;
  1183.  
  1184.         return MODE_OK;
  1185. }
  1186.  
  1187. static enum drm_mode_status
  1188. intel_hdmi_mode_valid(struct drm_connector *connector,
  1189.                       struct drm_display_mode *mode)
  1190. {
  1191.         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
  1192.         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
  1193.         enum drm_mode_status status;
  1194.         int clock;
  1195.  
  1196.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1197.                 return MODE_NO_DBLESCAN;
  1198.  
  1199.         clock = mode->clock;
  1200.         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  1201.                 clock *= 2;
  1202.  
  1203.         /* check if we can do 8bpc */
  1204.         status = hdmi_port_clock_valid(hdmi, clock, true);
  1205.  
  1206.         /* if we can't do 8bpc we may still be able to do 12bpc */
  1207.         if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
  1208.                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
  1209.  
  1210.         return status;
  1211. }
  1212.  
  1213. static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
  1214. {
  1215.         struct drm_device *dev = crtc_state->base.crtc->dev;
  1216.         struct drm_atomic_state *state;
  1217.         struct intel_encoder *encoder;
  1218.         struct drm_connector *connector;
  1219.         struct drm_connector_state *connector_state;
  1220.         int count = 0, count_hdmi = 0;
  1221.         int i;
  1222.  
  1223.         if (HAS_GMCH_DISPLAY(dev))
  1224.                 return false;
  1225.  
  1226.         state = crtc_state->base.state;
  1227.  
  1228.         for_each_connector_in_state(state, connector, connector_state, i) {
  1229.                 if (connector_state->crtc != crtc_state->base.crtc)
  1230.                         continue;
  1231.  
  1232.                 encoder = to_intel_encoder(connector_state->best_encoder);
  1233.  
  1234.                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
  1235.                 count++;
  1236.         }
  1237.  
  1238.         /*
  1239.          * HDMI 12bpc affects the clocks, so it's only possible
  1240.          * when not cloning with other encoder types.
  1241.          */
  1242.         return count_hdmi > 0 && count_hdmi == count;
  1243. }
  1244.  
  1245. bool intel_hdmi_compute_config(struct intel_encoder *encoder,
  1246.                                struct intel_crtc_state *pipe_config)
  1247. {
  1248.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  1249.         struct drm_device *dev = encoder->base.dev;
  1250.         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
  1251.         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
  1252.         int clock_12bpc = clock_8bpc * 3 / 2;
  1253.         int desired_bpp;
  1254.  
  1255.         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
  1256.  
  1257.         if (pipe_config->has_hdmi_sink)
  1258.                 pipe_config->has_infoframe = true;
  1259.  
  1260.         if (intel_hdmi->color_range_auto) {
  1261.                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
  1262.                 pipe_config->limited_color_range =
  1263.                         pipe_config->has_hdmi_sink &&
  1264.                         drm_match_cea_mode(adjusted_mode) > 1;
  1265.         } else {
  1266.                 pipe_config->limited_color_range =
  1267.                         intel_hdmi->limited_color_range;
  1268.         }
  1269.  
  1270.         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
  1271.                 pipe_config->pixel_multiplier = 2;
  1272.                 clock_8bpc *= 2;
  1273.                 clock_12bpc *= 2;
  1274.         }
  1275.  
  1276.         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
  1277.                 pipe_config->has_pch_encoder = true;
  1278.  
  1279.         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
  1280.                 pipe_config->has_audio = true;
  1281.  
  1282.         /*
  1283.          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
  1284.          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
  1285.          * outputs. We also need to check that the higher clock still fits
  1286.          * within limits.
  1287.          */
  1288.         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
  1289.             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
  1290.             hdmi_12bpc_possible(pipe_config)) {
  1291.                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
  1292.                 desired_bpp = 12*3;
  1293.  
  1294.                 /* Need to adjust the port link by 1.5x for 12bpc. */
  1295.                 pipe_config->port_clock = clock_12bpc;
  1296.         } else {
  1297.                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
  1298.                 desired_bpp = 8*3;
  1299.  
  1300.                 pipe_config->port_clock = clock_8bpc;
  1301.         }
  1302.  
  1303.         if (!pipe_config->bw_constrained) {
  1304.                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
  1305.                 pipe_config->pipe_bpp = desired_bpp;
  1306.         }
  1307.  
  1308.         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
  1309.                                   false) != MODE_OK) {
  1310.                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
  1311.                 return false;
  1312.         }
  1313.  
  1314.         /* Set user selected PAR to incoming mode's member */
  1315.         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
  1316.  
  1317.         return true;
  1318. }
  1319.  
  1320. static void
  1321. intel_hdmi_unset_edid(struct drm_connector *connector)
  1322. {
  1323.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1324.  
  1325.         intel_hdmi->has_hdmi_sink = false;
  1326.         intel_hdmi->has_audio = false;
  1327.         intel_hdmi->rgb_quant_range_selectable = false;
  1328.  
  1329.         kfree(to_intel_connector(connector)->detect_edid);
  1330.         to_intel_connector(connector)->detect_edid = NULL;
  1331. }
  1332.  
  1333. static bool
  1334. intel_hdmi_set_edid(struct drm_connector *connector, bool force)
  1335. {
  1336.         struct drm_i915_private *dev_priv = to_i915(connector->dev);
  1337.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1338.         struct edid *edid = NULL;
  1339.         bool connected = false;
  1340.  
  1341.         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
  1342.  
  1343.         if (force)
  1344.                 edid = drm_get_edid(connector,
  1345.                                     intel_gmbus_get_adapter(dev_priv,
  1346.                                     intel_hdmi->ddc_bus));
  1347.  
  1348.         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
  1349.  
  1350.         to_intel_connector(connector)->detect_edid = edid;
  1351.         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
  1352.                 intel_hdmi->rgb_quant_range_selectable =
  1353.                         drm_rgb_quant_range_selectable(edid);
  1354.  
  1355.                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
  1356.                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
  1357.                         intel_hdmi->has_audio =
  1358.                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
  1359.  
  1360.                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
  1361.                         intel_hdmi->has_hdmi_sink =
  1362.                                 drm_detect_hdmi_monitor(edid);
  1363.  
  1364.                 connected = true;
  1365.         }
  1366.  
  1367.         return connected;
  1368. }
  1369.  
  1370. static enum drm_connector_status
  1371. intel_hdmi_detect(struct drm_connector *connector, bool force)
  1372. {
  1373.         enum drm_connector_status status;
  1374.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1375.         struct drm_i915_private *dev_priv = to_i915(connector->dev);
  1376.         bool live_status = false;
  1377.         unsigned int try;
  1378.  
  1379.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  1380.                       connector->base.id, connector->name);
  1381.  
  1382.         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
  1383.  
  1384.         for (try = 0; !live_status && try < 9; try++) {
  1385.                 if (try)
  1386.                         msleep(10);
  1387.                 live_status = intel_digital_port_connected(dev_priv,
  1388.                                 hdmi_to_dig_port(intel_hdmi));
  1389.         }
  1390.  
  1391.         if (!live_status)
  1392.                 DRM_DEBUG_KMS("Live status not up!");
  1393.  
  1394.         intel_hdmi_unset_edid(connector);
  1395.  
  1396.         if (intel_hdmi_set_edid(connector, live_status)) {
  1397.                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1398.  
  1399.                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
  1400.                 status = connector_status_connected;
  1401.         } else
  1402.                 status = connector_status_disconnected;
  1403.  
  1404.         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
  1405.  
  1406.         return status;
  1407. }
  1408.  
  1409. static void
  1410. intel_hdmi_force(struct drm_connector *connector)
  1411. {
  1412.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1413.  
  1414.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  1415.                       connector->base.id, connector->name);
  1416.  
  1417.         intel_hdmi_unset_edid(connector);
  1418.  
  1419.         if (connector->status != connector_status_connected)
  1420.                 return;
  1421.  
  1422.         intel_hdmi_set_edid(connector, true);
  1423.         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
  1424. }
  1425.  
  1426. static int intel_hdmi_get_modes(struct drm_connector *connector)
  1427. {
  1428.         struct edid *edid;
  1429.  
  1430.         edid = to_intel_connector(connector)->detect_edid;
  1431.         if (edid == NULL)
  1432.                 return 0;
  1433.  
  1434.         return intel_connector_update_modes(connector, edid);
  1435. }
  1436.  
  1437. static bool
  1438. intel_hdmi_detect_audio(struct drm_connector *connector)
  1439. {
  1440.         bool has_audio = false;
  1441.         struct edid *edid;
  1442.  
  1443.         edid = to_intel_connector(connector)->detect_edid;
  1444.         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
  1445.                 has_audio = drm_detect_monitor_audio(edid);
  1446.  
  1447.         return has_audio;
  1448. }
  1449.  
  1450. static int
  1451. intel_hdmi_set_property(struct drm_connector *connector,
  1452.                         struct drm_property *property,
  1453.                         uint64_t val)
  1454. {
  1455.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1456.         struct intel_digital_port *intel_dig_port =
  1457.                 hdmi_to_dig_port(intel_hdmi);
  1458.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1459.         int ret;
  1460.  
  1461.         ret = drm_object_property_set_value(&connector->base, property, val);
  1462.         if (ret)
  1463.                 return ret;
  1464.  
  1465.         if (property == dev_priv->force_audio_property) {
  1466.                 enum hdmi_force_audio i = val;
  1467.                 bool has_audio;
  1468.  
  1469.                 if (i == intel_hdmi->force_audio)
  1470.                         return 0;
  1471.  
  1472.                 intel_hdmi->force_audio = i;
  1473.  
  1474.                 if (i == HDMI_AUDIO_AUTO)
  1475.                         has_audio = intel_hdmi_detect_audio(connector);
  1476.                 else
  1477.                         has_audio = (i == HDMI_AUDIO_ON);
  1478.  
  1479.                 if (i == HDMI_AUDIO_OFF_DVI)
  1480.                         intel_hdmi->has_hdmi_sink = 0;
  1481.  
  1482.                 intel_hdmi->has_audio = has_audio;
  1483.                 goto done;
  1484.         }
  1485.  
  1486.         if (property == dev_priv->broadcast_rgb_property) {
  1487.                 bool old_auto = intel_hdmi->color_range_auto;
  1488.                 bool old_range = intel_hdmi->limited_color_range;
  1489.  
  1490.                 switch (val) {
  1491.                 case INTEL_BROADCAST_RGB_AUTO:
  1492.                         intel_hdmi->color_range_auto = true;
  1493.                         break;
  1494.                 case INTEL_BROADCAST_RGB_FULL:
  1495.                         intel_hdmi->color_range_auto = false;
  1496.                         intel_hdmi->limited_color_range = false;
  1497.                         break;
  1498.                 case INTEL_BROADCAST_RGB_LIMITED:
  1499.                         intel_hdmi->color_range_auto = false;
  1500.                         intel_hdmi->limited_color_range = true;
  1501.                         break;
  1502.                 default:
  1503.                         return -EINVAL;
  1504.                 }
  1505.  
  1506.                 if (old_auto == intel_hdmi->color_range_auto &&
  1507.                     old_range == intel_hdmi->limited_color_range)
  1508.                         return 0;
  1509.  
  1510.                 goto done;
  1511.         }
  1512.  
  1513.         if (property == connector->dev->mode_config.aspect_ratio_property) {
  1514.                 switch (val) {
  1515.                 case DRM_MODE_PICTURE_ASPECT_NONE:
  1516.                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
  1517.                         break;
  1518.                 case DRM_MODE_PICTURE_ASPECT_4_3:
  1519.                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
  1520.                         break;
  1521.                 case DRM_MODE_PICTURE_ASPECT_16_9:
  1522.                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
  1523.                         break;
  1524.                 default:
  1525.                         return -EINVAL;
  1526.                 }
  1527.                 goto done;
  1528.         }
  1529.  
  1530.         return -EINVAL;
  1531.  
  1532. done:
  1533.         if (intel_dig_port->base.base.crtc)
  1534.                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
  1535.  
  1536.         return 0;
  1537. }
  1538.  
  1539. static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
  1540. {
  1541.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  1542.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1543.         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
  1544.  
  1545.         intel_hdmi_prepare(encoder);
  1546.  
  1547.         intel_hdmi->set_infoframes(&encoder->base,
  1548.                                    intel_crtc->config->has_hdmi_sink,
  1549.                                    adjusted_mode);
  1550. }
  1551.  
  1552. static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
  1553. {
  1554.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1555.         struct intel_hdmi *intel_hdmi = &dport->hdmi;
  1556.         struct drm_device *dev = encoder->base.dev;
  1557.         struct drm_i915_private *dev_priv = dev->dev_private;
  1558.         struct intel_crtc *intel_crtc =
  1559.                 to_intel_crtc(encoder->base.crtc);
  1560.         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
  1561.         enum dpio_channel port = vlv_dport_to_channel(dport);
  1562.         int pipe = intel_crtc->pipe;
  1563.         u32 val;
  1564.  
  1565.         /* Enable clock channels for this port */
  1566.         mutex_lock(&dev_priv->sb_lock);
  1567.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
  1568.         val = 0;
  1569.         if (pipe)
  1570.                 val |= (1<<21);
  1571.         else
  1572.                 val &= ~(1<<21);
  1573.         val |= 0x001000c4;
  1574.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
  1575.  
  1576.         /* HDMI 1.0V-2dB */
  1577.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
  1578.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
  1579.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
  1580.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
  1581.         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
  1582.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
  1583.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
  1584.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
  1585.  
  1586.         /* Program lane clock */
  1587.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
  1588.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
  1589.         mutex_unlock(&dev_priv->sb_lock);
  1590.  
  1591.         intel_hdmi->set_infoframes(&encoder->base,
  1592.                                    intel_crtc->config->has_hdmi_sink,
  1593.                                    adjusted_mode);
  1594.  
  1595.         g4x_enable_hdmi(encoder);
  1596.  
  1597.         vlv_wait_port_ready(dev_priv, dport, 0x0);
  1598. }
  1599.  
  1600. static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
  1601. {
  1602.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1603.         struct drm_device *dev = encoder->base.dev;
  1604.         struct drm_i915_private *dev_priv = dev->dev_private;
  1605.         struct intel_crtc *intel_crtc =
  1606.                 to_intel_crtc(encoder->base.crtc);
  1607.         enum dpio_channel port = vlv_dport_to_channel(dport);
  1608.         int pipe = intel_crtc->pipe;
  1609.  
  1610.         intel_hdmi_prepare(encoder);
  1611.  
  1612.         /* Program Tx lane resets to default */
  1613.         mutex_lock(&dev_priv->sb_lock);
  1614.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
  1615.                          DPIO_PCS_TX_LANE2_RESET |
  1616.                          DPIO_PCS_TX_LANE1_RESET);
  1617.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
  1618.                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
  1619.                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
  1620.                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
  1621.                          DPIO_PCS_CLK_SOFT_RESET);
  1622.  
  1623.         /* Fix up inter-pair skew failure */
  1624.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
  1625.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
  1626.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
  1627.  
  1628.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
  1629.         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
  1630.         mutex_unlock(&dev_priv->sb_lock);
  1631. }
  1632.  
  1633. static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
  1634.                                      bool reset)
  1635. {
  1636.         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  1637.         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
  1638.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1639.         enum pipe pipe = crtc->pipe;
  1640.         uint32_t val;
  1641.  
  1642.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
  1643.         if (reset)
  1644.                 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
  1645.         else
  1646.                 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
  1647.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
  1648.  
  1649.         if (crtc->config->lane_count > 2) {
  1650.                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
  1651.                 if (reset)
  1652.                         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
  1653.                 else
  1654.                         val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
  1655.                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
  1656.         }
  1657.  
  1658.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
  1659.         val |= CHV_PCS_REQ_SOFTRESET_EN;
  1660.         if (reset)
  1661.                 val &= ~DPIO_PCS_CLK_SOFT_RESET;
  1662.         else
  1663.                 val |= DPIO_PCS_CLK_SOFT_RESET;
  1664.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
  1665.  
  1666.         if (crtc->config->lane_count > 2) {
  1667.                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
  1668.                 val |= CHV_PCS_REQ_SOFTRESET_EN;
  1669.                 if (reset)
  1670.                         val &= ~DPIO_PCS_CLK_SOFT_RESET;
  1671.                 else
  1672.                         val |= DPIO_PCS_CLK_SOFT_RESET;
  1673.                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
  1674.         }
  1675. }
  1676.  
  1677. static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
  1678. {
  1679.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1680.         struct drm_device *dev = encoder->base.dev;
  1681.         struct drm_i915_private *dev_priv = dev->dev_private;
  1682.         struct intel_crtc *intel_crtc =
  1683.                 to_intel_crtc(encoder->base.crtc);
  1684.         enum dpio_channel ch = vlv_dport_to_channel(dport);
  1685.         enum pipe pipe = intel_crtc->pipe;
  1686.         u32 val;
  1687.  
  1688.         intel_hdmi_prepare(encoder);
  1689.  
  1690.         /*
  1691.          * Must trick the second common lane into life.
  1692.          * Otherwise we can't even access the PLL.
  1693.          */
  1694.         if (ch == DPIO_CH0 && pipe == PIPE_B)
  1695.                 dport->release_cl2_override =
  1696.                         !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
  1697.  
  1698.         chv_phy_powergate_lanes(encoder, true, 0x0);
  1699.  
  1700.         mutex_lock(&dev_priv->sb_lock);
  1701.  
  1702.         /* Assert data lane reset */
  1703.         chv_data_lane_soft_reset(encoder, true);
  1704.  
  1705.         /* program left/right clock distribution */
  1706.         if (pipe != PIPE_B) {
  1707.                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
  1708.                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
  1709.                 if (ch == DPIO_CH0)
  1710.                         val |= CHV_BUFLEFTENA1_FORCE;
  1711.                 if (ch == DPIO_CH1)
  1712.                         val |= CHV_BUFRIGHTENA1_FORCE;
  1713.                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
  1714.         } else {
  1715.                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
  1716.                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
  1717.                 if (ch == DPIO_CH0)
  1718.                         val |= CHV_BUFLEFTENA2_FORCE;
  1719.                 if (ch == DPIO_CH1)
  1720.                         val |= CHV_BUFRIGHTENA2_FORCE;
  1721.                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
  1722.         }
  1723.  
  1724.         /* program clock channel usage */
  1725.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
  1726.         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
  1727.         if (pipe != PIPE_B)
  1728.                 val &= ~CHV_PCS_USEDCLKCHANNEL;
  1729.         else
  1730.                 val |= CHV_PCS_USEDCLKCHANNEL;
  1731.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
  1732.  
  1733.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
  1734.         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
  1735.         if (pipe != PIPE_B)
  1736.                 val &= ~CHV_PCS_USEDCLKCHANNEL;
  1737.         else
  1738.                 val |= CHV_PCS_USEDCLKCHANNEL;
  1739.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
  1740.  
  1741.         /*
  1742.          * This a a bit weird since generally CL
  1743.          * matches the pipe, but here we need to
  1744.          * pick the CL based on the port.
  1745.          */
  1746.         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
  1747.         if (pipe != PIPE_B)
  1748.                 val &= ~CHV_CMN_USEDCLKCHANNEL;
  1749.         else
  1750.                 val |= CHV_CMN_USEDCLKCHANNEL;
  1751.         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
  1752.  
  1753.         mutex_unlock(&dev_priv->sb_lock);
  1754. }
  1755.  
  1756. static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
  1757. {
  1758.         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  1759.         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
  1760.         u32 val;
  1761.  
  1762.         mutex_lock(&dev_priv->sb_lock);
  1763.  
  1764.         /* disable left/right clock distribution */
  1765.         if (pipe != PIPE_B) {
  1766.                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
  1767.                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
  1768.                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
  1769.         } else {
  1770.                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
  1771.                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
  1772.                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
  1773.         }
  1774.  
  1775.         mutex_unlock(&dev_priv->sb_lock);
  1776.  
  1777.         /*
  1778.          * Leave the power down bit cleared for at least one
  1779.          * lane so that chv_powergate_phy_ch() will power
  1780.          * on something when the channel is otherwise unused.
  1781.          * When the port is off and the override is removed
  1782.          * the lanes power down anyway, so otherwise it doesn't
  1783.          * really matter what the state of power down bits is
  1784.          * after this.
  1785.          */
  1786.         chv_phy_powergate_lanes(encoder, false, 0x0);
  1787. }
  1788.  
  1789. static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
  1790. {
  1791.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1792.         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1793.         struct intel_crtc *intel_crtc =
  1794.                 to_intel_crtc(encoder->base.crtc);
  1795.         enum dpio_channel port = vlv_dport_to_channel(dport);
  1796.         int pipe = intel_crtc->pipe;
  1797.  
  1798.         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
  1799.         mutex_lock(&dev_priv->sb_lock);
  1800.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
  1801.         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
  1802.         mutex_unlock(&dev_priv->sb_lock);
  1803. }
  1804.  
  1805. static void chv_hdmi_post_disable(struct intel_encoder *encoder)
  1806. {
  1807.         struct drm_device *dev = encoder->base.dev;
  1808.         struct drm_i915_private *dev_priv = dev->dev_private;
  1809.  
  1810.         mutex_lock(&dev_priv->sb_lock);
  1811.  
  1812.         /* Assert data lane reset */
  1813.         chv_data_lane_soft_reset(encoder, true);
  1814.  
  1815.         mutex_unlock(&dev_priv->sb_lock);
  1816. }
  1817.  
  1818. static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
  1819. {
  1820.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1821.         struct intel_hdmi *intel_hdmi = &dport->hdmi;
  1822.         struct drm_device *dev = encoder->base.dev;
  1823.         struct drm_i915_private *dev_priv = dev->dev_private;
  1824.         struct intel_crtc *intel_crtc =
  1825.                 to_intel_crtc(encoder->base.crtc);
  1826.         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
  1827.         enum dpio_channel ch = vlv_dport_to_channel(dport);
  1828.         int pipe = intel_crtc->pipe;
  1829.         int data, i, stagger;
  1830.         u32 val;
  1831.  
  1832.         mutex_lock(&dev_priv->sb_lock);
  1833.  
  1834.         /* allow hardware to manage TX FIFO reset source */
  1835.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
  1836.         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
  1837.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
  1838.  
  1839.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
  1840.         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
  1841.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
  1842.  
  1843.         /* Program Tx latency optimal setting */
  1844.         for (i = 0; i < 4; i++) {
  1845.                 /* Set the upar bit */
  1846.                 data = (i == 1) ? 0x0 : 0x1;
  1847.                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
  1848.                                 data << DPIO_UPAR_SHIFT);
  1849.         }
  1850.  
  1851.         /* Data lane stagger programming */
  1852.         if (intel_crtc->config->port_clock > 270000)
  1853.                 stagger = 0x18;
  1854.         else if (intel_crtc->config->port_clock > 135000)
  1855.                 stagger = 0xd;
  1856.         else if (intel_crtc->config->port_clock > 67500)
  1857.                 stagger = 0x7;
  1858.         else if (intel_crtc->config->port_clock > 33750)
  1859.                 stagger = 0x4;
  1860.         else
  1861.                 stagger = 0x2;
  1862.  
  1863.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
  1864.         val |= DPIO_TX2_STAGGER_MASK(0x1f);
  1865.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
  1866.  
  1867.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
  1868.         val |= DPIO_TX2_STAGGER_MASK(0x1f);
  1869.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
  1870.  
  1871.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
  1872.                        DPIO_LANESTAGGER_STRAP(stagger) |
  1873.                        DPIO_LANESTAGGER_STRAP_OVRD |
  1874.                        DPIO_TX1_STAGGER_MASK(0x1f) |
  1875.                        DPIO_TX1_STAGGER_MULT(6) |
  1876.                        DPIO_TX2_STAGGER_MULT(0));
  1877.  
  1878.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
  1879.                        DPIO_LANESTAGGER_STRAP(stagger) |
  1880.                        DPIO_LANESTAGGER_STRAP_OVRD |
  1881.                        DPIO_TX1_STAGGER_MASK(0x1f) |
  1882.                        DPIO_TX1_STAGGER_MULT(7) |
  1883.                        DPIO_TX2_STAGGER_MULT(5));
  1884.  
  1885.         /* Deassert data lane reset */
  1886.         chv_data_lane_soft_reset(encoder, false);
  1887.  
  1888.         /* Clear calc init */
  1889.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
  1890.         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
  1891.         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
  1892.         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
  1893.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
  1894.  
  1895.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
  1896.         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
  1897.         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
  1898.         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
  1899.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
  1900.  
  1901.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
  1902.         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
  1903.         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
  1904.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
  1905.  
  1906.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
  1907.         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
  1908.         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
  1909.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
  1910.  
  1911.         /* FIXME: Program the support xxx V-dB */
  1912.         /* Use 800mV-0dB */
  1913.         for (i = 0; i < 4; i++) {
  1914.                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
  1915.                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
  1916.                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
  1917.                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
  1918.         }
  1919.  
  1920.         for (i = 0; i < 4; i++) {
  1921.                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
  1922.  
  1923.                 val &= ~DPIO_SWING_MARGIN000_MASK;
  1924.                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
  1925.  
  1926.                 /*
  1927.                  * Supposedly this value shouldn't matter when unique transition
  1928.                  * scale is disabled, but in fact it does matter. Let's just
  1929.                  * always program the same value and hope it's OK.
  1930.                  */
  1931.                 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
  1932.                 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
  1933.  
  1934.                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
  1935.         }
  1936.  
  1937.         /*
  1938.          * The document said it needs to set bit 27 for ch0 and bit 26
  1939.          * for ch1. Might be a typo in the doc.
  1940.          * For now, for this unique transition scale selection, set bit
  1941.          * 27 for ch0 and ch1.
  1942.          */
  1943.         for (i = 0; i < 4; i++) {
  1944.                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
  1945.                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
  1946.                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
  1947.         }
  1948.  
  1949.         /* Start swing calculation */
  1950.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
  1951.         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
  1952.         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
  1953.  
  1954.         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
  1955.         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
  1956.         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
  1957.  
  1958.         mutex_unlock(&dev_priv->sb_lock);
  1959.  
  1960.         intel_hdmi->set_infoframes(&encoder->base,
  1961.                                    intel_crtc->config->has_hdmi_sink,
  1962.                                    adjusted_mode);
  1963.  
  1964.         g4x_enable_hdmi(encoder);
  1965.  
  1966.         vlv_wait_port_ready(dev_priv, dport, 0x0);
  1967.  
  1968.         /* Second common lane will stay alive on its own now */
  1969.         if (dport->release_cl2_override) {
  1970.                 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
  1971.                 dport->release_cl2_override = false;
  1972.         }
  1973. }
  1974.  
  1975. static void intel_hdmi_destroy(struct drm_connector *connector)
  1976. {
  1977.         kfree(to_intel_connector(connector)->detect_edid);
  1978.         drm_connector_cleanup(connector);
  1979.         kfree(connector);
  1980. }
  1981.  
  1982. static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
  1983.         .dpms = drm_atomic_helper_connector_dpms,
  1984.         .detect = intel_hdmi_detect,
  1985.         .force = intel_hdmi_force,
  1986.         .fill_modes = drm_helper_probe_single_connector_modes,
  1987.         .set_property = intel_hdmi_set_property,
  1988.         .atomic_get_property = intel_connector_atomic_get_property,
  1989.         .destroy = intel_hdmi_destroy,
  1990.         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  1991.         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  1992. };
  1993.  
  1994. static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
  1995.         .get_modes = intel_hdmi_get_modes,
  1996.         .mode_valid = intel_hdmi_mode_valid,
  1997.         .best_encoder = intel_best_encoder,
  1998. };
  1999.  
  2000. static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
  2001.         .destroy = intel_encoder_destroy,
  2002. };
  2003.  
  2004. static void
  2005. intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
  2006. {
  2007.         intel_attach_force_audio_property(connector);
  2008.         intel_attach_broadcast_rgb_property(connector);
  2009.         intel_hdmi->color_range_auto = true;
  2010.         intel_attach_aspect_ratio_property(connector);
  2011.         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
  2012. }
  2013.  
  2014. void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  2015.                                struct intel_connector *intel_connector)
  2016. {
  2017.         struct drm_connector *connector = &intel_connector->base;
  2018.         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  2019.         struct intel_encoder *intel_encoder = &intel_dig_port->base;
  2020.         struct drm_device *dev = intel_encoder->base.dev;
  2021.         struct drm_i915_private *dev_priv = dev->dev_private;
  2022.         enum port port = intel_dig_port->port;
  2023.         uint8_t alternate_ddc_pin;
  2024.  
  2025.         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
  2026.                            DRM_MODE_CONNECTOR_HDMIA);
  2027.         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
  2028.  
  2029.         connector->interlace_allowed = 1;
  2030.         connector->doublescan_allowed = 0;
  2031.         connector->stereo_allowed = 1;
  2032.  
  2033.         switch (port) {
  2034.         case PORT_B:
  2035.                 if (IS_BROXTON(dev_priv))
  2036.                         intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
  2037.                 else
  2038.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
  2039.                 /*
  2040.                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
  2041.                  * interrupts to check the external panel connection.
  2042.                  */
  2043.                 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
  2044.                         intel_encoder->hpd_pin = HPD_PORT_A;
  2045.                 else
  2046.                         intel_encoder->hpd_pin = HPD_PORT_B;
  2047.                 break;
  2048.         case PORT_C:
  2049.                 if (IS_BROXTON(dev_priv))
  2050.                         intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
  2051.                 else
  2052.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
  2053.                 intel_encoder->hpd_pin = HPD_PORT_C;
  2054.                 break;
  2055.         case PORT_D:
  2056.                 if (WARN_ON(IS_BROXTON(dev_priv)))
  2057.                         intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
  2058.                 else if (IS_CHERRYVIEW(dev_priv))
  2059.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
  2060.                 else
  2061.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
  2062.                 intel_encoder->hpd_pin = HPD_PORT_D;
  2063.                 break;
  2064.         case PORT_E:
  2065.                 /* On SKL PORT E doesn't have seperate GMBUS pin
  2066.                  *  We rely on VBT to set a proper alternate GMBUS pin. */
  2067.                 alternate_ddc_pin =
  2068.                         dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
  2069.                 switch (alternate_ddc_pin) {
  2070.                 case DDC_PIN_B:
  2071.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
  2072.                         break;
  2073.                 case DDC_PIN_C:
  2074.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
  2075.                         break;
  2076.                 case DDC_PIN_D:
  2077.                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
  2078.                         break;
  2079.                 default:
  2080.                         MISSING_CASE(alternate_ddc_pin);
  2081.                 }
  2082.                 intel_encoder->hpd_pin = HPD_PORT_E;
  2083.                 break;
  2084.         case PORT_A:
  2085.                 intel_encoder->hpd_pin = HPD_PORT_A;
  2086.                 /* Internal port only for eDP. */
  2087.         default:
  2088.                 BUG();
  2089.         }
  2090.  
  2091.         if (IS_VALLEYVIEW(dev)) {
  2092.                 intel_hdmi->write_infoframe = vlv_write_infoframe;
  2093.                 intel_hdmi->set_infoframes = vlv_set_infoframes;
  2094.                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
  2095.         } else if (IS_G4X(dev)) {
  2096.                 intel_hdmi->write_infoframe = g4x_write_infoframe;
  2097.                 intel_hdmi->set_infoframes = g4x_set_infoframes;
  2098.                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
  2099.         } else if (HAS_DDI(dev)) {
  2100.                 intel_hdmi->write_infoframe = hsw_write_infoframe;
  2101.                 intel_hdmi->set_infoframes = hsw_set_infoframes;
  2102.                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
  2103.         } else if (HAS_PCH_IBX(dev)) {
  2104.                 intel_hdmi->write_infoframe = ibx_write_infoframe;
  2105.                 intel_hdmi->set_infoframes = ibx_set_infoframes;
  2106.                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
  2107.         } else {
  2108.                 intel_hdmi->write_infoframe = cpt_write_infoframe;
  2109.                 intel_hdmi->set_infoframes = cpt_set_infoframes;
  2110.                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
  2111.         }
  2112.  
  2113.         if (HAS_DDI(dev))
  2114.                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
  2115.         else
  2116.                 intel_connector->get_hw_state = intel_connector_get_hw_state;
  2117.         intel_connector->unregister = intel_connector_unregister;
  2118.  
  2119.         intel_hdmi_add_properties(intel_hdmi, connector);
  2120.  
  2121.         intel_connector_attach_encoder(intel_connector, intel_encoder);
  2122.         drm_connector_register(connector);
  2123.         intel_hdmi->attached_connector = intel_connector;
  2124.  
  2125.         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  2126.          * 0xd.  Failure to do so will result in spurious interrupts being
  2127.          * generated on the port when a cable is not attached.
  2128.          */
  2129.         if (IS_G4X(dev) && !IS_GM45(dev)) {
  2130.                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  2131.                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  2132.         }
  2133. }
  2134.  
  2135. void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
  2136. {
  2137.         struct intel_digital_port *intel_dig_port;
  2138.         struct intel_encoder *intel_encoder;
  2139.         struct intel_connector *intel_connector;
  2140.  
  2141.         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
  2142.         if (!intel_dig_port)
  2143.                 return;
  2144.  
  2145.         intel_connector = intel_connector_alloc();
  2146.         if (!intel_connector) {
  2147.                 kfree(intel_dig_port);
  2148.                 return;
  2149.         }
  2150.  
  2151.         intel_encoder = &intel_dig_port->base;
  2152.  
  2153.         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
  2154.                          DRM_MODE_ENCODER_TMDS);
  2155.  
  2156.         intel_encoder->compute_config = intel_hdmi_compute_config;
  2157.         if (HAS_PCH_SPLIT(dev)) {
  2158.                 intel_encoder->disable = pch_disable_hdmi;
  2159.                 intel_encoder->post_disable = pch_post_disable_hdmi;
  2160.         } else {
  2161.                 intel_encoder->disable = g4x_disable_hdmi;
  2162.         }
  2163.         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
  2164.         intel_encoder->get_config = intel_hdmi_get_config;
  2165.         if (IS_CHERRYVIEW(dev)) {
  2166.                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
  2167.                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
  2168.                 intel_encoder->enable = vlv_enable_hdmi;
  2169.                 intel_encoder->post_disable = chv_hdmi_post_disable;
  2170.                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
  2171.         } else if (IS_VALLEYVIEW(dev)) {
  2172.                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
  2173.                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
  2174.                 intel_encoder->enable = vlv_enable_hdmi;
  2175.                 intel_encoder->post_disable = vlv_hdmi_post_disable;
  2176.         } else {
  2177.                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
  2178.                 if (HAS_PCH_CPT(dev))
  2179.                         intel_encoder->enable = cpt_enable_hdmi;
  2180.                 else if (HAS_PCH_IBX(dev))
  2181.                         intel_encoder->enable = ibx_enable_hdmi;
  2182.                 else
  2183.                         intel_encoder->enable = g4x_enable_hdmi;
  2184.         }
  2185.  
  2186.         intel_encoder->type = INTEL_OUTPUT_HDMI;
  2187.         if (IS_CHERRYVIEW(dev)) {
  2188.                 if (port == PORT_D)
  2189.                         intel_encoder->crtc_mask = 1 << 2;
  2190.                 else
  2191.                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
  2192.         } else {
  2193.                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2194.         }
  2195.         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
  2196.         /*
  2197.          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
  2198.          * to work on real hardware. And since g4x can send infoframes to
  2199.          * only one port anyway, nothing is lost by allowing it.
  2200.          */
  2201.         if (IS_G4X(dev))
  2202.                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
  2203.  
  2204.         intel_dig_port->port = port;
  2205.         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
  2206.         intel_dig_port->dp.output_reg = 0;
  2207.  
  2208.         intel_hdmi_init_connector(intel_dig_port, intel_connector);
  2209. }
  2210.