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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright (c) 2007-2008 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23.  * IN THE SOFTWARE.
  24.  */
  25. #ifndef __INTEL_DRV_H__
  26. #define __INTEL_DRV_H__
  27.  
  28. #include <linux/async.h>
  29. #include <linux/i2c.h>
  30. #include <linux/hdmi.h>
  31. #include <drm/i915_drm.h>
  32. #include "i915_drv.h"
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_crtc_helper.h>
  35. #include <drm/drm_fb_helper.h>
  36. #include <drm/drm_dp_mst_helper.h>
  37. #include <drm/drm_rect.h>
  38. #include <drm/drm_atomic.h>
  39.  
  40. /**
  41.  * _wait_for - magic (register) wait macro
  42.  *
  43.  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44.  * contexts. Note that it's important that we check the condition again after
  45.  * having timed out, since the timeout could be due to preemption or similar and
  46.  * we've never had a chance to check the condition before the timeout.
  47.  */
  48. #define _wait_for(COND, MS, W) ({ \
  49.         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50.         int ret__ = 0;                                                  \
  51.         while (!(COND)) {                                               \
  52.                 if (time_after(jiffies, timeout__)) {                   \
  53.                         if (!(COND))                                    \
  54.                                 ret__ = -ETIMEDOUT;                     \
  55.                         break;                                          \
  56.                 }                                                       \
  57.                 if (W )  {                              \
  58.          msleep(W); \
  59.                 } else {                                                \
  60.                         cpu_relax();                                    \
  61.                 }                                                       \
  62.         }                                                               \
  63.         ret__;                                                          \
  64. })
  65.  
  66. #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67. #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68. #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69.                                                DIV_ROUND_UP((US), 1000), 0)
  70.  
  71. #define KHz(x) (1000 * (x))
  72. #define MHz(x) KHz(1000 * (x))
  73.  
  74. /*
  75.  * Display related stuff
  76.  */
  77.  
  78. /* store information about an Ixxx DVO */
  79. /* The i830->i865 use multiple DVOs with multiple i2cs */
  80. /* the i915, i945 have a single sDVO i2c bus - which is different */
  81. #define MAX_OUTPUTS 6
  82. /* maximum connectors per crtcs in the mode set */
  83.  
  84. /* Maximum cursor sizes */
  85. #define GEN2_CURSOR_WIDTH 64
  86. #define GEN2_CURSOR_HEIGHT 64
  87. #define MAX_CURSOR_WIDTH 256
  88. #define MAX_CURSOR_HEIGHT 256
  89.  
  90. #define INTEL_I2C_BUS_DVO 1
  91. #define INTEL_I2C_BUS_SDVO 2
  92.  
  93. /* these are outputs from the chip - integrated only
  94.    external chips are via DVO or SDVO output */
  95. enum intel_output_type {
  96.         INTEL_OUTPUT_UNUSED = 0,
  97.         INTEL_OUTPUT_ANALOG = 1,
  98.         INTEL_OUTPUT_DVO = 2,
  99.         INTEL_OUTPUT_SDVO = 3,
  100.         INTEL_OUTPUT_LVDS = 4,
  101.         INTEL_OUTPUT_TVOUT = 5,
  102.         INTEL_OUTPUT_HDMI = 6,
  103.         INTEL_OUTPUT_DISPLAYPORT = 7,
  104.         INTEL_OUTPUT_EDP = 8,
  105.         INTEL_OUTPUT_DSI = 9,
  106.         INTEL_OUTPUT_UNKNOWN = 10,
  107.         INTEL_OUTPUT_DP_MST = 11,
  108. };
  109.  
  110. #define INTEL_DVO_CHIP_NONE 0
  111. #define INTEL_DVO_CHIP_LVDS 1
  112. #define INTEL_DVO_CHIP_TMDS 2
  113. #define INTEL_DVO_CHIP_TVOUT 4
  114.  
  115. #define INTEL_DSI_VIDEO_MODE    0
  116. #define INTEL_DSI_COMMAND_MODE  1
  117.  
  118. struct intel_framebuffer {
  119.         struct drm_framebuffer base;
  120.         struct drm_i915_gem_object *obj;
  121.     void   *private;
  122. };
  123.  
  124. struct intel_fbdev {
  125.         struct drm_fb_helper helper;
  126.         struct intel_framebuffer *fb;
  127.         struct list_head fbdev_list;
  128.         struct drm_display_mode *our_mode;
  129.         int preferred_bpp;
  130. };
  131.  
  132. struct intel_encoder {
  133.         struct drm_encoder base;
  134.  
  135.         enum intel_output_type type;
  136.         unsigned int cloneable;
  137.         void (*hot_plug)(struct intel_encoder *);
  138.         bool (*compute_config)(struct intel_encoder *,
  139.                                struct intel_crtc_state *);
  140.         void (*pre_pll_enable)(struct intel_encoder *);
  141.         void (*pre_enable)(struct intel_encoder *);
  142.         void (*enable)(struct intel_encoder *);
  143.         void (*mode_set)(struct intel_encoder *intel_encoder);
  144.         void (*disable)(struct intel_encoder *);
  145.         void (*post_disable)(struct intel_encoder *);
  146.         void (*post_pll_disable)(struct intel_encoder *);
  147.         /* Read out the current hw state of this connector, returning true if
  148.          * the encoder is active. If the encoder is enabled it also set the pipe
  149.          * it is connected to in the pipe parameter. */
  150.         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
  151.         /* Reconstructs the equivalent mode flags for the current hardware
  152.          * state. This must be called _after_ display->get_pipe_config has
  153.          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
  154.          * be set correctly before calling this function. */
  155.         void (*get_config)(struct intel_encoder *,
  156.                            struct intel_crtc_state *pipe_config);
  157.         /*
  158.          * Called during system suspend after all pending requests for the
  159.          * encoder are flushed (for example for DP AUX transactions) and
  160.          * device interrupts are disabled.
  161.          */
  162.         void (*suspend)(struct intel_encoder *);
  163.         int crtc_mask;
  164.         enum hpd_pin hpd_pin;
  165. };
  166.  
  167. struct intel_panel {
  168.         struct drm_display_mode *fixed_mode;
  169.         struct drm_display_mode *downclock_mode;
  170.         int fitting_mode;
  171.  
  172.         /* backlight */
  173.         struct {
  174.                 bool present;
  175.                 u32 level;
  176.                 u32 min;
  177.                 u32 max;
  178.                 bool enabled;
  179.                 bool combination_mode;  /* gen 2/4 only */
  180.                 bool active_low_pwm;
  181.  
  182.                 /* PWM chip */
  183.                 bool util_pin_active_low;       /* bxt+ */
  184.                 u8 controller;          /* bxt+ only */
  185.                 struct pwm_device *pwm;
  186.  
  187.                 struct backlight_device *device;
  188.  
  189.                 /* Connector and platform specific backlight functions */
  190.                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
  191.                 uint32_t (*get)(struct intel_connector *connector);
  192.                 void (*set)(struct intel_connector *connector, uint32_t level);
  193.                 void (*disable)(struct intel_connector *connector);
  194.                 void (*enable)(struct intel_connector *connector);
  195.                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
  196.                                       uint32_t hz);
  197.                 void (*power)(struct intel_connector *, bool enable);
  198.         } backlight;
  199. };
  200.  
  201. struct intel_connector {
  202.         struct drm_connector base;
  203.         /*
  204.          * The fixed encoder this connector is connected to.
  205.          */
  206.         struct intel_encoder *encoder;
  207.  
  208.         /* Reads out the current hw, returning true if the connector is enabled
  209.          * and active (i.e. dpms ON state). */
  210.         bool (*get_hw_state)(struct intel_connector *);
  211.  
  212.         /*
  213.          * Removes all interfaces through which the connector is accessible
  214.          * - like sysfs, debugfs entries -, so that no new operations can be
  215.          * started on the connector. Also makes sure all currently pending
  216.          * operations finish before returing.
  217.          */
  218.         void (*unregister)(struct intel_connector *);
  219.  
  220.         /* Panel info for eDP and LVDS */
  221.         struct intel_panel panel;
  222.  
  223.         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
  224.         struct edid *edid;
  225.         struct edid *detect_edid;
  226.  
  227.         /* since POLL and HPD connectors may use the same HPD line keep the native
  228.            state of connector->polled in case hotplug storm detection changes it */
  229.         u8 polled;
  230.  
  231.         void *port; /* store this opaque as its illegal to dereference it */
  232.  
  233.         struct intel_dp *mst_port;
  234. };
  235.  
  236. typedef struct dpll {
  237.         /* given values */
  238.         int n;
  239.         int m1, m2;
  240.         int p1, p2;
  241.         /* derived values */
  242.         int     dot;
  243.         int     vco;
  244.         int     m;
  245.         int     p;
  246. } intel_clock_t;
  247.  
  248. struct intel_atomic_state {
  249.         struct drm_atomic_state base;
  250.  
  251.         unsigned int cdclk;
  252.         bool dpll_set;
  253.         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
  254. };
  255.  
  256. struct intel_plane_state {
  257.         struct drm_plane_state base;
  258.         struct drm_rect src;
  259.         struct drm_rect dst;
  260.         struct drm_rect clip;
  261.         bool visible;
  262.  
  263.         /*
  264.          * scaler_id
  265.          *    = -1 : not using a scaler
  266.          *    >=  0 : using a scalers
  267.          *
  268.          * plane requiring a scaler:
  269.          *   - During check_plane, its bit is set in
  270.          *     crtc_state->scaler_state.scaler_users by calling helper function
  271.          *     update_scaler_plane.
  272.          *   - scaler_id indicates the scaler it got assigned.
  273.          *
  274.          * plane doesn't require a scaler:
  275.          *   - this can happen when scaling is no more required or plane simply
  276.          *     got disabled.
  277.          *   - During check_plane, corresponding bit is reset in
  278.          *     crtc_state->scaler_state.scaler_users by calling helper function
  279.          *     update_scaler_plane.
  280.          */
  281.         int scaler_id;
  282.  
  283.         struct drm_intel_sprite_colorkey ckey;
  284. };
  285.  
  286. struct intel_initial_plane_config {
  287.         struct intel_framebuffer *fb;
  288.         unsigned int tiling;
  289.         int size;
  290.         u32 base;
  291. };
  292.  
  293. #define SKL_MIN_SRC_W 8
  294. #define SKL_MAX_SRC_W 4096
  295. #define SKL_MIN_SRC_H 8
  296. #define SKL_MAX_SRC_H 4096
  297. #define SKL_MIN_DST_W 8
  298. #define SKL_MAX_DST_W 4096
  299. #define SKL_MIN_DST_H 8
  300. #define SKL_MAX_DST_H 4096
  301.  
  302. struct intel_scaler {
  303.         int in_use;
  304.         uint32_t mode;
  305. };
  306.  
  307. struct intel_crtc_scaler_state {
  308. #define SKL_NUM_SCALERS 2
  309.         struct intel_scaler scalers[SKL_NUM_SCALERS];
  310.  
  311.         /*
  312.          * scaler_users: keeps track of users requesting scalers on this crtc.
  313.          *
  314.          *     If a bit is set, a user is using a scaler.
  315.          *     Here user can be a plane or crtc as defined below:
  316.          *       bits 0-30 - plane (bit position is index from drm_plane_index)
  317.          *       bit 31    - crtc
  318.          *
  319.          * Instead of creating a new index to cover planes and crtc, using
  320.          * existing drm_plane_index for planes which is well less than 31
  321.          * planes and bit 31 for crtc. This should be fine to cover all
  322.          * our platforms.
  323.          *
  324.          * intel_atomic_setup_scalers will setup available scalers to users
  325.          * requesting scalers. It will gracefully fail if request exceeds
  326.          * avilability.
  327.          */
  328. #define SKL_CRTC_INDEX 31
  329.         unsigned scaler_users;
  330.  
  331.         /* scaler used by crtc for panel fitting purpose */
  332.         int scaler_id;
  333. };
  334.  
  335. /* drm_mode->private_flags */
  336. #define I915_MODE_FLAG_INHERITED 1
  337.  
  338. struct intel_crtc_state {
  339.         struct drm_crtc_state base;
  340.  
  341.         /**
  342.          * quirks - bitfield with hw state readout quirks
  343.          *
  344.          * For various reasons the hw state readout code might not be able to
  345.          * completely faithfully read out the current state. These cases are
  346.          * tracked with quirk flags so that fastboot and state checker can act
  347.          * accordingly.
  348.          */
  349. #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
  350.         unsigned long quirks;
  351.  
  352.         bool update_pipe;
  353.  
  354.         /* Pipe source size (ie. panel fitter input size)
  355.          * All planes will be positioned inside this space,
  356.          * and get clipped at the edges. */
  357.         int pipe_src_w, pipe_src_h;
  358.  
  359.         /* Whether to set up the PCH/FDI. Note that we never allow sharing
  360.          * between pch encoders and cpu encoders. */
  361.         bool has_pch_encoder;
  362.  
  363.         /* Are we sending infoframes on the attached port */
  364.         bool has_infoframe;
  365.  
  366.         /* CPU Transcoder for the pipe. Currently this can only differ from the
  367.          * pipe on Haswell (where we have a special eDP transcoder). */
  368.         enum transcoder cpu_transcoder;
  369.  
  370.         /*
  371.          * Use reduced/limited/broadcast rbg range, compressing from the full
  372.          * range fed into the crtcs.
  373.          */
  374.         bool limited_color_range;
  375.  
  376.         /* DP has a bunch of special case unfortunately, so mark the pipe
  377.          * accordingly. */
  378.         bool has_dp_encoder;
  379.  
  380.         /* Whether we should send NULL infoframes. Required for audio. */
  381.         bool has_hdmi_sink;
  382.  
  383.         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
  384.          * has_dp_encoder is set. */
  385.         bool has_audio;
  386.  
  387.         /*
  388.          * Enable dithering, used when the selected pipe bpp doesn't match the
  389.          * plane bpp.
  390.          */
  391.         bool dither;
  392.  
  393.         /* Controls for the clock computation, to override various stages. */
  394.         bool clock_set;
  395.  
  396.         /* SDVO TV has a bunch of special case. To make multifunction encoders
  397.          * work correctly, we need to track this at runtime.*/
  398.         bool sdvo_tv_clock;
  399.  
  400.         /*
  401.          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
  402.          * required. This is set in the 2nd loop of calling encoder's
  403.          * ->compute_config if the first pick doesn't work out.
  404.          */
  405.         bool bw_constrained;
  406.  
  407.         /* Settings for the intel dpll used on pretty much everything but
  408.          * haswell. */
  409.         struct dpll dpll;
  410.  
  411.         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
  412.         enum intel_dpll_id shared_dpll;
  413.  
  414.         /*
  415.          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
  416.          * - enum skl_dpll on SKL
  417.          */
  418.         uint32_t ddi_pll_sel;
  419.  
  420.         /* Actual register state of the dpll, for shared dpll cross-checking. */
  421.         struct intel_dpll_hw_state dpll_hw_state;
  422.  
  423.         int pipe_bpp;
  424.         struct intel_link_m_n dp_m_n;
  425.  
  426.         /* m2_n2 for eDP downclock */
  427.         struct intel_link_m_n dp_m2_n2;
  428.         bool has_drrs;
  429.  
  430.         /*
  431.          * Frequence the dpll for the port should run at. Differs from the
  432.          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
  433.          * already multiplied by pixel_multiplier.
  434.          */
  435.         int port_clock;
  436.  
  437.         /* Used by SDVO (and if we ever fix it, HDMI). */
  438.         unsigned pixel_multiplier;
  439.  
  440.         uint8_t lane_count;
  441.  
  442.         /* Panel fitter controls for gen2-gen4 + VLV */
  443.         struct {
  444.                 u32 control;
  445.                 u32 pgm_ratios;
  446.                 u32 lvds_border_bits;
  447.         } gmch_pfit;
  448.  
  449.         /* Panel fitter placement and size for Ironlake+ */
  450.         struct {
  451.                 u32 pos;
  452.                 u32 size;
  453.                 bool enabled;
  454.                 bool force_thru;
  455.         } pch_pfit;
  456.  
  457.         /* FDI configuration, only valid if has_pch_encoder is set. */
  458.         int fdi_lanes;
  459.         struct intel_link_m_n fdi_m_n;
  460.  
  461.         bool ips_enabled;
  462.  
  463.         bool double_wide;
  464.  
  465.         bool dp_encoder_is_mst;
  466.         int pbn;
  467.  
  468.         struct intel_crtc_scaler_state scaler_state;
  469.  
  470.         /* w/a for waiting 2 vblanks during crtc enable */
  471.         enum pipe hsw_workaround_pipe;
  472. };
  473.  
  474. struct vlv_wm_state {
  475.         struct vlv_pipe_wm wm[3];
  476.         struct vlv_sr_wm sr[3];
  477.         uint8_t num_active_planes;
  478.         uint8_t num_levels;
  479.         uint8_t level;
  480.         bool cxsr;
  481. };
  482.  
  483. struct intel_pipe_wm {
  484.         struct intel_wm_level wm[5];
  485.         uint32_t linetime;
  486.         bool fbc_wm_enabled;
  487.         bool pipe_enabled;
  488.         bool sprites_enabled;
  489.         bool sprites_scaled;
  490. };
  491.  
  492. struct intel_mmio_flip {
  493.         struct work_struct work;
  494.         struct drm_i915_private *i915;
  495.         struct drm_i915_gem_request *req;
  496.         struct intel_crtc *crtc;
  497. };
  498.  
  499. struct skl_pipe_wm {
  500.         struct skl_wm_level wm[8];
  501.         struct skl_wm_level trans_wm;
  502.         uint32_t linetime;
  503. };
  504.  
  505. /*
  506.  * Tracking of operations that need to be performed at the beginning/end of an
  507.  * atomic commit, outside the atomic section where interrupts are disabled.
  508.  * These are generally operations that grab mutexes or might otherwise sleep
  509.  * and thus can't be run with interrupts disabled.
  510.  */
  511. struct intel_crtc_atomic_commit {
  512.         /* Sleepable operations to perform before commit */
  513.         bool wait_for_flips;
  514.         bool disable_fbc;
  515.         bool disable_ips;
  516.         bool disable_cxsr;
  517.         bool pre_disable_primary;
  518.         bool update_wm_pre, update_wm_post;
  519.         unsigned disabled_planes;
  520.  
  521.         /* Sleepable operations to perform after commit */
  522.         unsigned fb_bits;
  523.         bool wait_vblank;
  524.         bool update_fbc;
  525.         bool post_enable_primary;
  526.         unsigned update_sprite_watermarks;
  527. };
  528.  
  529. struct intel_crtc {
  530.         struct drm_crtc base;
  531.         enum pipe pipe;
  532.         enum plane plane;
  533.         u8 lut_r[256], lut_g[256], lut_b[256];
  534.         /*
  535.          * Whether the crtc and the connected output pipeline is active. Implies
  536.          * that crtc->enabled is set, i.e. the current mode configuration has
  537.          * some outputs connected to this crtc.
  538.          */
  539.         bool active;
  540.         unsigned long enabled_power_domains;
  541.         bool lowfreq_avail;
  542.         struct intel_overlay *overlay;
  543.         struct intel_unpin_work *unpin_work;
  544.  
  545.         atomic_t unpin_work_count;
  546.  
  547.         /* Display surface base address adjustement for pageflips. Note that on
  548.          * gen4+ this only adjusts up to a tile, offsets within a tile are
  549.          * handled in the hw itself (with the TILEOFF register). */
  550.         unsigned long dspaddr_offset;
  551.         int adjusted_x;
  552.         int adjusted_y;
  553.  
  554.         uint32_t cursor_addr;
  555.         uint32_t cursor_cntl;
  556.         uint32_t cursor_size;
  557.         uint32_t cursor_base;
  558.  
  559.         struct intel_crtc_state *config;
  560.  
  561.         /* reset counter value when the last flip was submitted */
  562.         unsigned int reset_counter;
  563.  
  564.         /* Access to these should be protected by dev_priv->irq_lock. */
  565.         bool cpu_fifo_underrun_disabled;
  566.         bool pch_fifo_underrun_disabled;
  567.  
  568.         /* per-pipe watermark state */
  569.         struct {
  570.                 /* watermarks currently being used  */
  571.                 struct intel_pipe_wm active;
  572.                 /* SKL wm values currently in use */
  573.                 struct skl_pipe_wm skl_active;
  574.                 /* allow CxSR on this pipe */
  575.                 bool cxsr_allowed;
  576.         } wm;
  577.  
  578.         int scanline_offset;
  579.  
  580.         struct {
  581.                 unsigned start_vbl_count;
  582.                 ktime_t start_vbl_time;
  583.                 int min_vbl, max_vbl;
  584.                 int scanline_start;
  585.         } debug;
  586.  
  587.         struct intel_crtc_atomic_commit atomic;
  588.  
  589.         /* scalers available on this crtc */
  590.         int num_scalers;
  591.  
  592.         struct vlv_wm_state wm_state;
  593. };
  594.  
  595. struct intel_plane_wm_parameters {
  596.         uint32_t horiz_pixels;
  597.         uint32_t vert_pixels;
  598.         /*
  599.          *   For packed pixel formats:
  600.          *     bytes_per_pixel - holds bytes per pixel
  601.          *   For planar pixel formats:
  602.          *     bytes_per_pixel - holds bytes per pixel for uv-plane
  603.          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
  604.          */
  605.         uint8_t bytes_per_pixel;
  606.         uint8_t y_bytes_per_pixel;
  607.         bool enabled;
  608.         bool scaled;
  609.         u64 tiling;
  610.         unsigned int rotation;
  611.         uint16_t fifo_size;
  612. };
  613.  
  614. struct intel_plane {
  615.         struct drm_plane base;
  616.         int plane;
  617.         enum pipe pipe;
  618.         bool can_scale;
  619.         int max_downscale;
  620.         uint32_t frontbuffer_bit;
  621.  
  622.         /* Since we need to change the watermarks before/after
  623.          * enabling/disabling the planes, we need to store the parameters here
  624.          * as the other pieces of the struct may not reflect the values we want
  625.          * for the watermark calculations. Currently only Haswell uses this.
  626.          */
  627.         struct intel_plane_wm_parameters wm;
  628.  
  629.         /*
  630.          * NOTE: Do not place new plane state fields here (e.g., when adding
  631.          * new plane properties).  New runtime state should now be placed in
  632.          * the intel_plane_state structure and accessed via drm_plane->state.
  633.          */
  634.  
  635.         void (*update_plane)(struct drm_plane *plane,
  636.                              struct drm_crtc *crtc,
  637.                              struct drm_framebuffer *fb,
  638.                              int crtc_x, int crtc_y,
  639.                              unsigned int crtc_w, unsigned int crtc_h,
  640.                              uint32_t x, uint32_t y,
  641.                              uint32_t src_w, uint32_t src_h);
  642.         void (*disable_plane)(struct drm_plane *plane,
  643.                               struct drm_crtc *crtc);
  644.         int (*check_plane)(struct drm_plane *plane,
  645.                            struct intel_crtc_state *crtc_state,
  646.                            struct intel_plane_state *state);
  647.         void (*commit_plane)(struct drm_plane *plane,
  648.                              struct intel_plane_state *state);
  649. };
  650.  
  651. struct intel_watermark_params {
  652.         unsigned long fifo_size;
  653.         unsigned long max_wm;
  654.         unsigned long default_wm;
  655.         unsigned long guard_size;
  656.         unsigned long cacheline_size;
  657. };
  658.  
  659. struct cxsr_latency {
  660.         int is_desktop;
  661.         int is_ddr3;
  662.         unsigned long fsb_freq;
  663.         unsigned long mem_freq;
  664.         unsigned long display_sr;
  665.         unsigned long display_hpll_disable;
  666.         unsigned long cursor_sr;
  667.         unsigned long cursor_hpll_disable;
  668. };
  669.  
  670. #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
  671. #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
  672. #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
  673. #define to_intel_connector(x) container_of(x, struct intel_connector, base)
  674. #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
  675. #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
  676. #define to_intel_plane(x) container_of(x, struct intel_plane, base)
  677. #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
  678. #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
  679.  
  680. struct intel_hdmi {
  681.         u32 hdmi_reg;
  682.         int ddc_bus;
  683.         bool limited_color_range;
  684.         bool color_range_auto;
  685.         bool has_hdmi_sink;
  686.         bool has_audio;
  687.         enum hdmi_force_audio force_audio;
  688.         bool rgb_quant_range_selectable;
  689.         enum hdmi_picture_aspect aspect_ratio;
  690.         struct intel_connector *attached_connector;
  691.         void (*write_infoframe)(struct drm_encoder *encoder,
  692.                                 enum hdmi_infoframe_type type,
  693.                                 const void *frame, ssize_t len);
  694.         void (*set_infoframes)(struct drm_encoder *encoder,
  695.                                bool enable,
  696.                                const struct drm_display_mode *adjusted_mode);
  697.         bool (*infoframe_enabled)(struct drm_encoder *encoder);
  698. };
  699.  
  700. struct intel_dp_mst_encoder;
  701. #define DP_MAX_DOWNSTREAM_PORTS         0x10
  702.  
  703. /*
  704.  * enum link_m_n_set:
  705.  *      When platform provides two set of M_N registers for dp, we can
  706.  *      program them and switch between them incase of DRRS.
  707.  *      But When only one such register is provided, we have to program the
  708.  *      required divider value on that registers itself based on the DRRS state.
  709.  *
  710.  * M1_N1        : Program dp_m_n on M1_N1 registers
  711.  *                        dp_m2_n2 on M2_N2 registers (If supported)
  712.  *
  713.  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
  714.  *                        M2_N2 registers are not supported
  715.  */
  716.  
  717. enum link_m_n_set {
  718.         /* Sets the m1_n1 and m2_n2 */
  719.         M1_N1 = 0,
  720.         M2_N2
  721. };
  722.  
  723. struct sink_crc {
  724.         bool started;
  725.         u8 last_crc[6];
  726.         int last_count;
  727. };
  728.  
  729. struct intel_dp {
  730.         uint32_t output_reg;
  731.         uint32_t aux_ch_ctl_reg;
  732.         uint32_t DP;
  733.         int link_rate;
  734.         uint8_t lane_count;
  735.         bool has_audio;
  736.         enum hdmi_force_audio force_audio;
  737.         bool limited_color_range;
  738.         bool color_range_auto;
  739.         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  740.         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
  741.         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
  742.         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
  743.         uint8_t num_sink_rates;
  744.         int sink_rates[DP_MAX_SUPPORTED_RATES];
  745.         struct sink_crc sink_crc;
  746.         struct drm_dp_aux aux;
  747.         uint8_t train_set[4];
  748.         int panel_power_up_delay;
  749.         int panel_power_down_delay;
  750.         int panel_power_cycle_delay;
  751.         int backlight_on_delay;
  752.         int backlight_off_delay;
  753.         struct delayed_work panel_vdd_work;
  754.         bool want_panel_vdd;
  755.         unsigned long last_power_cycle;
  756.         unsigned long last_power_on;
  757.         unsigned long last_backlight_off;
  758.  
  759.         /*
  760.          * Pipe whose power sequencer is currently locked into
  761.          * this port. Only relevant on VLV/CHV.
  762.          */
  763.         enum pipe pps_pipe;
  764.         struct edp_power_seq pps_delays;
  765.  
  766.         bool can_mst; /* this port supports mst */
  767.         bool is_mst;
  768.         int active_mst_links;
  769.         /* connector directly attached - won't be use for modeset in mst world */
  770.         struct intel_connector *attached_connector;
  771.  
  772.         /* mst connector list */
  773.         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
  774.         struct drm_dp_mst_topology_mgr mst_mgr;
  775.  
  776.         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
  777.         /*
  778.          * This function returns the value we have to program the AUX_CTL
  779.          * register with to kick off an AUX transaction.
  780.          */
  781.         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
  782.                                      bool has_aux_irq,
  783.                                      int send_bytes,
  784.                                      uint32_t aux_clock_divider);
  785.         bool train_set_valid;
  786.  
  787.         /* Displayport compliance testing */
  788.         unsigned long compliance_test_type;
  789.         unsigned long compliance_test_data;
  790.         bool compliance_test_active;
  791. };
  792.  
  793. struct intel_digital_port {
  794.         struct intel_encoder base;
  795.         enum port port;
  796.         u32 saved_port_bits;
  797.         struct intel_dp dp;
  798.         struct intel_hdmi hdmi;
  799.         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
  800.         bool release_cl2_override;
  801. };
  802.  
  803. struct intel_dp_mst_encoder {
  804.         struct intel_encoder base;
  805.         enum pipe pipe;
  806.         struct intel_digital_port *primary;
  807.         void *port; /* store this opaque as its illegal to dereference it */
  808. };
  809.  
  810. static inline enum dpio_channel
  811. vlv_dport_to_channel(struct intel_digital_port *dport)
  812. {
  813.         switch (dport->port) {
  814.         case PORT_B:
  815.         case PORT_D:
  816.                 return DPIO_CH0;
  817.         case PORT_C:
  818.                 return DPIO_CH1;
  819.         default:
  820.                 BUG();
  821.         }
  822. }
  823.  
  824. static inline enum dpio_phy
  825. vlv_dport_to_phy(struct intel_digital_port *dport)
  826. {
  827.         switch (dport->port) {
  828.         case PORT_B:
  829.         case PORT_C:
  830.                 return DPIO_PHY0;
  831.         case PORT_D:
  832.                 return DPIO_PHY1;
  833.         default:
  834.                 BUG();
  835.         }
  836. }
  837.  
  838. static inline enum dpio_channel
  839. vlv_pipe_to_channel(enum pipe pipe)
  840. {
  841.         switch (pipe) {
  842.         case PIPE_A:
  843.         case PIPE_C:
  844.                 return DPIO_CH0;
  845.         case PIPE_B:
  846.                 return DPIO_CH1;
  847.         default:
  848.                 BUG();
  849.         }
  850. }
  851.  
  852. static inline struct drm_crtc *
  853. intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
  854. {
  855.         struct drm_i915_private *dev_priv = dev->dev_private;
  856.         return dev_priv->pipe_to_crtc_mapping[pipe];
  857. }
  858.  
  859. static inline struct drm_crtc *
  860. intel_get_crtc_for_plane(struct drm_device *dev, int plane)
  861. {
  862.         struct drm_i915_private *dev_priv = dev->dev_private;
  863.         return dev_priv->plane_to_crtc_mapping[plane];
  864. }
  865.  
  866. struct intel_unpin_work {
  867.         struct work_struct work;
  868.         struct drm_crtc *crtc;
  869.         struct drm_framebuffer *old_fb;
  870.         struct drm_i915_gem_object *pending_flip_obj;
  871.         struct drm_pending_vblank_event *event;
  872.         atomic_t pending;
  873. #define INTEL_FLIP_INACTIVE     0
  874. #define INTEL_FLIP_PENDING      1
  875. #define INTEL_FLIP_COMPLETE     2
  876.         u32 flip_count;
  877.         u32 gtt_offset;
  878.         struct drm_i915_gem_request *flip_queued_req;
  879.         u32 flip_queued_vblank;
  880.         u32 flip_ready_vblank;
  881.         bool enable_stall_check;
  882. };
  883.  
  884. struct intel_load_detect_pipe {
  885.         struct drm_framebuffer *release_fb;
  886.         bool load_detect_temp;
  887.         int dpms_mode;
  888. };
  889.  
  890. static inline struct intel_encoder *
  891. intel_attached_encoder(struct drm_connector *connector)
  892. {
  893.         return to_intel_connector(connector)->encoder;
  894. }
  895.  
  896. static inline struct intel_digital_port *
  897. enc_to_dig_port(struct drm_encoder *encoder)
  898. {
  899.         return container_of(encoder, struct intel_digital_port, base.base);
  900. }
  901.  
  902. static inline struct intel_dp_mst_encoder *
  903. enc_to_mst(struct drm_encoder *encoder)
  904. {
  905.         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
  906. }
  907.  
  908. static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  909. {
  910.         return &enc_to_dig_port(encoder)->dp;
  911. }
  912.  
  913. static inline struct intel_digital_port *
  914. dp_to_dig_port(struct intel_dp *intel_dp)
  915. {
  916.         return container_of(intel_dp, struct intel_digital_port, dp);
  917. }
  918.  
  919. static inline struct intel_digital_port *
  920. hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
  921. {
  922.         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
  923. }
  924.  
  925. /*
  926.  * Returns the number of planes for this pipe, ie the number of sprites + 1
  927.  * (primary plane). This doesn't count the cursor plane then.
  928.  */
  929. static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
  930. {
  931.         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
  932. }
  933.  
  934. /* intel_fifo_underrun.c */
  935. bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
  936.                                            enum pipe pipe, bool enable);
  937. bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
  938.                                            enum transcoder pch_transcoder,
  939.                                            bool enable);
  940. void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
  941.                                          enum pipe pipe);
  942. void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
  943.                                          enum transcoder pch_transcoder);
  944. void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
  945.  
  946. /* i915_irq.c */
  947. void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  948. void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  949. void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  950. void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  951. void gen6_reset_rps_interrupts(struct drm_device *dev);
  952. void gen6_enable_rps_interrupts(struct drm_device *dev);
  953. void gen6_disable_rps_interrupts(struct drm_device *dev);
  954. u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
  955. void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
  956. void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
  957. static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
  958. {
  959.         /*
  960.          * We only use drm_irq_uninstall() at unload and VT switch, so
  961.          * this is the only thing we need to check.
  962.          */
  963.         return dev_priv->pm.irqs_enabled;
  964. }
  965.  
  966. int intel_get_crtc_scanline(struct intel_crtc *crtc);
  967. void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
  968.                                      unsigned int pipe_mask);
  969.  
  970. /* intel_crt.c */
  971. void intel_crt_init(struct drm_device *dev);
  972.  
  973.  
  974. /* intel_ddi.c */
  975. void intel_prepare_ddi(struct drm_device *dev);
  976. void hsw_fdi_link_train(struct drm_crtc *crtc);
  977. void intel_ddi_init(struct drm_device *dev, enum port port);
  978. enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
  979. bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
  980. void intel_ddi_pll_init(struct drm_device *dev);
  981. void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
  982. void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
  983.                                        enum transcoder cpu_transcoder);
  984. void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
  985. void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
  986. bool intel_ddi_pll_select(struct intel_crtc *crtc,
  987.                           struct intel_crtc_state *crtc_state);
  988. void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
  989. void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
  990. bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
  991. void intel_ddi_fdi_disable(struct drm_crtc *crtc);
  992. void intel_ddi_get_config(struct intel_encoder *encoder,
  993.                           struct intel_crtc_state *pipe_config);
  994. struct intel_encoder *
  995. intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
  996.  
  997. void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
  998. void intel_ddi_clock_get(struct intel_encoder *encoder,
  999.                          struct intel_crtc_state *pipe_config);
  1000. void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
  1001. uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
  1002.  
  1003. /* intel_frontbuffer.c */
  1004. void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
  1005.                              enum fb_op_origin origin);
  1006. void intel_frontbuffer_flip_prepare(struct drm_device *dev,
  1007.                                     unsigned frontbuffer_bits);
  1008. void intel_frontbuffer_flip_complete(struct drm_device *dev,
  1009.                                      unsigned frontbuffer_bits);
  1010. void intel_frontbuffer_flip(struct drm_device *dev,
  1011.                             unsigned frontbuffer_bits);
  1012. unsigned int intel_fb_align_height(struct drm_device *dev,
  1013.                                    unsigned int height,
  1014.                                    uint32_t pixel_format,
  1015.                                    uint64_t fb_format_modifier);
  1016. void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
  1017.                         enum fb_op_origin origin);
  1018. u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
  1019.                               uint32_t pixel_format);
  1020.  
  1021. /* intel_audio.c */
  1022. void intel_init_audio(struct drm_device *dev);
  1023. void intel_audio_codec_enable(struct intel_encoder *encoder);
  1024. void intel_audio_codec_disable(struct intel_encoder *encoder);
  1025. void i915_audio_component_init(struct drm_i915_private *dev_priv);
  1026. void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
  1027.  
  1028. /* intel_display.c */
  1029. extern const struct drm_plane_funcs intel_plane_funcs;
  1030. bool intel_has_pending_fb_unpin(struct drm_device *dev);
  1031. int intel_pch_rawclk(struct drm_device *dev);
  1032. int intel_hrawclk(struct drm_device *dev);
  1033. void intel_mark_busy(struct drm_device *dev);
  1034. void intel_mark_idle(struct drm_device *dev);
  1035. void intel_crtc_restore_mode(struct drm_crtc *crtc);
  1036. int intel_display_suspend(struct drm_device *dev);
  1037. void intel_encoder_destroy(struct drm_encoder *encoder);
  1038. int intel_connector_init(struct intel_connector *);
  1039. struct intel_connector *intel_connector_alloc(void);
  1040. bool intel_connector_get_hw_state(struct intel_connector *connector);
  1041. void intel_connector_attach_encoder(struct intel_connector *connector,
  1042.                                     struct intel_encoder *encoder);
  1043. struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
  1044. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  1045.                                              struct drm_crtc *crtc);
  1046. enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
  1047. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  1048.                                 struct drm_file *file_priv);
  1049. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  1050.                                              enum pipe pipe);
  1051. bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
  1052. static inline void
  1053. intel_wait_for_vblank(struct drm_device *dev, int pipe)
  1054. {
  1055.         drm_wait_one_vblank(dev, pipe);
  1056. }
  1057. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
  1058. void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
  1059.                          struct intel_digital_port *dport,
  1060.                          unsigned int expected_mask);
  1061. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  1062.                                 struct drm_display_mode *mode,
  1063.                                 struct intel_load_detect_pipe *old,
  1064.                                 struct drm_modeset_acquire_ctx *ctx);
  1065. void intel_release_load_detect_pipe(struct drm_connector *connector,
  1066.                                     struct intel_load_detect_pipe *old,
  1067.                                     struct drm_modeset_acquire_ctx *ctx);
  1068. int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
  1069.                                struct drm_framebuffer *fb,
  1070.                                const struct drm_plane_state *plane_state,
  1071.                                struct intel_engine_cs *pipelined,
  1072.                                struct drm_i915_gem_request **pipelined_request);
  1073. struct drm_framebuffer *
  1074. __intel_framebuffer_create(struct drm_device *dev,
  1075.                            struct drm_mode_fb_cmd2 *mode_cmd,
  1076.                            struct drm_i915_gem_object *obj);
  1077. void intel_prepare_page_flip(struct drm_device *dev, int plane);
  1078. void intel_finish_page_flip(struct drm_device *dev, int pipe);
  1079. void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
  1080. void intel_check_page_flip(struct drm_device *dev, int pipe);
  1081. int intel_prepare_plane_fb(struct drm_plane *plane,
  1082.                            const struct drm_plane_state *new_state);
  1083. void intel_cleanup_plane_fb(struct drm_plane *plane,
  1084.                             const struct drm_plane_state *old_state);
  1085. int intel_plane_atomic_get_property(struct drm_plane *plane,
  1086.                                     const struct drm_plane_state *state,
  1087.                                     struct drm_property *property,
  1088.                                     uint64_t *val);
  1089. int intel_plane_atomic_set_property(struct drm_plane *plane,
  1090.                                     struct drm_plane_state *state,
  1091.                                     struct drm_property *property,
  1092.                                     uint64_t val);
  1093. int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
  1094.                                     struct drm_plane_state *plane_state);
  1095.  
  1096. unsigned int
  1097. intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
  1098.                   uint64_t fb_format_modifier, unsigned int plane);
  1099.  
  1100. static inline bool
  1101. intel_rotation_90_or_270(unsigned int rotation)
  1102. {
  1103.         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
  1104. }
  1105.  
  1106. void intel_create_rotation_property(struct drm_device *dev,
  1107.                                         struct intel_plane *plane);
  1108.  
  1109. /* shared dpll functions */
  1110. struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
  1111. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  1112.                         struct intel_shared_dpll *pll,
  1113.                         bool state);
  1114. #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
  1115. #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
  1116. struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
  1117.                                                 struct intel_crtc_state *state);
  1118.  
  1119. void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
  1120.                       const struct dpll *dpll);
  1121. void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
  1122.  
  1123. /* modesetting asserts */
  1124. void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  1125.                            enum pipe pipe);
  1126. void assert_pll(struct drm_i915_private *dev_priv,
  1127.                 enum pipe pipe, bool state);
  1128. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  1129. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  1130. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  1131.                        enum pipe pipe, bool state);
  1132. #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
  1133. #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
  1134. void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
  1135. #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
  1136. #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
  1137. unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
  1138.                                              int *x, int *y,
  1139.                                              unsigned int tiling_mode,
  1140.                                              unsigned int bpp,
  1141.                                              unsigned int pitch);
  1142. void intel_prepare_reset(struct drm_device *dev);
  1143. void intel_finish_reset(struct drm_device *dev);
  1144. void hsw_enable_pc8(struct drm_i915_private *dev_priv);
  1145. void hsw_disable_pc8(struct drm_i915_private *dev_priv);
  1146. void broxton_init_cdclk(struct drm_device *dev);
  1147. void broxton_uninit_cdclk(struct drm_device *dev);
  1148. void broxton_ddi_phy_init(struct drm_device *dev);
  1149. void broxton_ddi_phy_uninit(struct drm_device *dev);
  1150. void bxt_enable_dc9(struct drm_i915_private *dev_priv);
  1151. void bxt_disable_dc9(struct drm_i915_private *dev_priv);
  1152. void skl_init_cdclk(struct drm_i915_private *dev_priv);
  1153. void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
  1154. void intel_dp_get_m_n(struct intel_crtc *crtc,
  1155.                       struct intel_crtc_state *pipe_config);
  1156. void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
  1157. int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
  1158. void
  1159. ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
  1160.                                 int dotclock);
  1161. bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
  1162.                         intel_clock_t *best_clock);
  1163. int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
  1164.  
  1165. bool intel_crtc_active(struct drm_crtc *crtc);
  1166. void hsw_enable_ips(struct intel_crtc *crtc);
  1167. void hsw_disable_ips(struct intel_crtc *crtc);
  1168. enum intel_display_power_domain
  1169. intel_display_port_power_domain(struct intel_encoder *intel_encoder);
  1170. enum intel_display_power_domain
  1171. intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
  1172. void intel_mode_from_pipe_config(struct drm_display_mode *mode,
  1173.                                  struct intel_crtc_state *pipe_config);
  1174. void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
  1175. void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
  1176.  
  1177. int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
  1178. int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
  1179.  
  1180. unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
  1181.                                      struct drm_i915_gem_object *obj,
  1182.                                      unsigned int plane);
  1183.  
  1184. u32 skl_plane_ctl_format(uint32_t pixel_format);
  1185. u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
  1186. u32 skl_plane_ctl_rotation(unsigned int rotation);
  1187.  
  1188. /* intel_csr.c */
  1189. void intel_csr_ucode_init(struct drm_device *dev);
  1190. enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
  1191. void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
  1192.                                         enum csr_state state);
  1193. void intel_csr_load_program(struct drm_device *dev);
  1194. void intel_csr_ucode_fini(struct drm_device *dev);
  1195. void assert_csr_loaded(struct drm_i915_private *dev_priv);
  1196.  
  1197. /* intel_dp.c */
  1198. void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
  1199. bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  1200.                              struct intel_connector *intel_connector);
  1201. void intel_dp_set_link_params(struct intel_dp *intel_dp,
  1202.                               const struct intel_crtc_state *pipe_config);
  1203. void intel_dp_start_link_train(struct intel_dp *intel_dp);
  1204. void intel_dp_stop_link_train(struct intel_dp *intel_dp);
  1205. void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
  1206. void intel_dp_encoder_destroy(struct drm_encoder *encoder);
  1207. int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
  1208. bool intel_dp_compute_config(struct intel_encoder *encoder,
  1209.                              struct intel_crtc_state *pipe_config);
  1210. bool intel_dp_is_edp(struct drm_device *dev, enum port port);
  1211. enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
  1212.                                   bool long_hpd);
  1213. void intel_edp_backlight_on(struct intel_dp *intel_dp);
  1214. void intel_edp_backlight_off(struct intel_dp *intel_dp);
  1215. void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
  1216. void intel_edp_panel_on(struct intel_dp *intel_dp);
  1217. void intel_edp_panel_off(struct intel_dp *intel_dp);
  1218. void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
  1219. void intel_dp_mst_suspend(struct drm_device *dev);
  1220. void intel_dp_mst_resume(struct drm_device *dev);
  1221. int intel_dp_max_link_rate(struct intel_dp *intel_dp);
  1222. int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
  1223. void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
  1224. void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
  1225. uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
  1226. void intel_plane_destroy(struct drm_plane *plane);
  1227. void intel_edp_drrs_enable(struct intel_dp *intel_dp);
  1228. void intel_edp_drrs_disable(struct intel_dp *intel_dp);
  1229. void intel_edp_drrs_invalidate(struct drm_device *dev,
  1230.                 unsigned frontbuffer_bits);
  1231. void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
  1232. bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
  1233.                                          struct intel_digital_port *port);
  1234. void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
  1235.  
  1236. /* intel_dp_mst.c */
  1237. int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
  1238. void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
  1239. /* intel_dsi.c */
  1240. void intel_dsi_init(struct drm_device *dev);
  1241.  
  1242.  
  1243. /* intel_dvo.c */
  1244. void intel_dvo_init(struct drm_device *dev);
  1245.  
  1246.  
  1247. /* legacy fbdev emulation in intel_fbdev.c */
  1248. #ifdef CONFIG_DRM_FBDEV_EMULATION
  1249. extern int intel_fbdev_init(struct drm_device *dev);
  1250. extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
  1251. extern void intel_fbdev_fini(struct drm_device *dev);
  1252. extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
  1253. extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
  1254. extern void intel_fbdev_restore_mode(struct drm_device *dev);
  1255. #else
  1256. static inline int intel_fbdev_init(struct drm_device *dev)
  1257. {
  1258.         return 0;
  1259. }
  1260.  
  1261. static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
  1262. {
  1263. }
  1264.  
  1265. static inline void intel_fbdev_fini(struct drm_device *dev)
  1266. {
  1267. }
  1268.  
  1269. static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
  1270. {
  1271. }
  1272.  
  1273. static inline void intel_fbdev_restore_mode(struct drm_device *dev)
  1274. {
  1275. }
  1276. #endif
  1277.  
  1278. /* intel_fbc.c */
  1279. bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
  1280. void intel_fbc_update(struct drm_i915_private *dev_priv);
  1281. void intel_fbc_init(struct drm_i915_private *dev_priv);
  1282. void intel_fbc_disable(struct drm_i915_private *dev_priv);
  1283. void intel_fbc_disable_crtc(struct intel_crtc *crtc);
  1284. void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
  1285.                           unsigned int frontbuffer_bits,
  1286.                           enum fb_op_origin origin);
  1287. void intel_fbc_flush(struct drm_i915_private *dev_priv,
  1288.                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
  1289. const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
  1290. void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
  1291.  
  1292. /* intel_hdmi.c */
  1293. void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
  1294. void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  1295.                                struct intel_connector *intel_connector);
  1296. struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
  1297. bool intel_hdmi_compute_config(struct intel_encoder *encoder,
  1298.                                struct intel_crtc_state *pipe_config);
  1299.  
  1300.  
  1301. /* intel_lvds.c */
  1302. void intel_lvds_init(struct drm_device *dev);
  1303. bool intel_is_dual_link_lvds(struct drm_device *dev);
  1304.  
  1305.  
  1306. /* intel_modes.c */
  1307. int intel_connector_update_modes(struct drm_connector *connector,
  1308.                                  struct edid *edid);
  1309. int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
  1310. void intel_attach_force_audio_property(struct drm_connector *connector);
  1311. void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
  1312. void intel_attach_aspect_ratio_property(struct drm_connector *connector);
  1313.  
  1314.  
  1315. /* intel_overlay.c */
  1316. void intel_setup_overlay(struct drm_device *dev);
  1317. void intel_cleanup_overlay(struct drm_device *dev);
  1318. int intel_overlay_switch_off(struct intel_overlay *overlay);
  1319. int intel_overlay_put_image(struct drm_device *dev, void *data,
  1320.                             struct drm_file *file_priv);
  1321. int intel_overlay_attrs(struct drm_device *dev, void *data,
  1322.                         struct drm_file *file_priv);
  1323. void intel_overlay_reset(struct drm_i915_private *dev_priv);
  1324.  
  1325.  
  1326. /* intel_panel.c */
  1327. int intel_panel_init(struct intel_panel *panel,
  1328.                      struct drm_display_mode *fixed_mode,
  1329.                      struct drm_display_mode *downclock_mode);
  1330. void intel_panel_fini(struct intel_panel *panel);
  1331. void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
  1332.                             struct drm_display_mode *adjusted_mode);
  1333. void intel_pch_panel_fitting(struct intel_crtc *crtc,
  1334.                              struct intel_crtc_state *pipe_config,
  1335.                              int fitting_mode);
  1336. void intel_gmch_panel_fitting(struct intel_crtc *crtc,
  1337.                               struct intel_crtc_state *pipe_config,
  1338.                               int fitting_mode);
  1339. void intel_panel_set_backlight_acpi(struct intel_connector *connector,
  1340.                                     u32 level, u32 max);
  1341. int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
  1342. void intel_panel_enable_backlight(struct intel_connector *connector);
  1343. void intel_panel_disable_backlight(struct intel_connector *connector);
  1344. void intel_panel_destroy_backlight(struct drm_connector *connector);
  1345. enum drm_connector_status intel_panel_detect(struct drm_device *dev);
  1346. extern struct drm_display_mode *intel_find_panel_downclock(
  1347.                                 struct drm_device *dev,
  1348.                                 struct drm_display_mode *fixed_mode,
  1349.                                 struct drm_connector *connector);
  1350. void intel_backlight_register(struct drm_device *dev);
  1351. void intel_backlight_unregister(struct drm_device *dev);
  1352.  
  1353.  
  1354. /* intel_psr.c */
  1355. void intel_psr_enable(struct intel_dp *intel_dp);
  1356. void intel_psr_disable(struct intel_dp *intel_dp);
  1357. void intel_psr_invalidate(struct drm_device *dev,
  1358.                           unsigned frontbuffer_bits);
  1359. void intel_psr_flush(struct drm_device *dev,
  1360.                      unsigned frontbuffer_bits,
  1361.                      enum fb_op_origin origin);
  1362. void intel_psr_init(struct drm_device *dev);
  1363. void intel_psr_single_frame_update(struct drm_device *dev,
  1364.                                    unsigned frontbuffer_bits);
  1365.  
  1366. /* intel_runtime_pm.c */
  1367. int intel_power_domains_init(struct drm_i915_private *);
  1368. void intel_power_domains_fini(struct drm_i915_private *);
  1369. void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
  1370. void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
  1371.  
  1372. bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
  1373.                                     enum intel_display_power_domain domain);
  1374. bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
  1375.                                       enum intel_display_power_domain domain);
  1376. void intel_display_power_get(struct drm_i915_private *dev_priv,
  1377.                              enum intel_display_power_domain domain);
  1378. void intel_display_power_put(struct drm_i915_private *dev_priv,
  1379.                              enum intel_display_power_domain domain);
  1380. void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
  1381. void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
  1382. void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
  1383.  
  1384. void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
  1385.  
  1386. void chv_phy_powergate_lanes(struct intel_encoder *encoder,
  1387.                              bool override, unsigned int mask);
  1388. bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
  1389.                           enum dpio_channel ch, bool override);
  1390.  
  1391.  
  1392. /* intel_pm.c */
  1393. void intel_init_clock_gating(struct drm_device *dev);
  1394. void intel_suspend_hw(struct drm_device *dev);
  1395. int ilk_wm_max_level(const struct drm_device *dev);
  1396. void intel_update_watermarks(struct drm_crtc *crtc);
  1397. void intel_update_sprite_watermarks(struct drm_plane *plane,
  1398.                                     struct drm_crtc *crtc,
  1399.                                     uint32_t sprite_width,
  1400.                                     uint32_t sprite_height,
  1401.                                     int pixel_size,
  1402.                                     bool enabled, bool scaled);
  1403. void intel_init_pm(struct drm_device *dev);
  1404. void intel_pm_setup(struct drm_device *dev);
  1405. void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
  1406. void intel_gpu_ips_teardown(void);
  1407. void intel_init_gt_powersave(struct drm_device *dev);
  1408. void intel_cleanup_gt_powersave(struct drm_device *dev);
  1409. void intel_enable_gt_powersave(struct drm_device *dev);
  1410. void intel_disable_gt_powersave(struct drm_device *dev);
  1411. void intel_suspend_gt_powersave(struct drm_device *dev);
  1412. void intel_reset_gt_powersave(struct drm_device *dev);
  1413. void gen6_update_ring_freq(struct drm_device *dev);
  1414. void gen6_rps_busy(struct drm_i915_private *dev_priv);
  1415. void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
  1416. void gen6_rps_idle(struct drm_i915_private *dev_priv);
  1417. void gen6_rps_boost(struct drm_i915_private *dev_priv,
  1418.                     struct intel_rps_client *rps,
  1419.                     unsigned long submitted);
  1420. void intel_queue_rps_boost_for_request(struct drm_device *dev,
  1421.                                        struct drm_i915_gem_request *req);
  1422. void vlv_wm_get_hw_state(struct drm_device *dev);
  1423. void ilk_wm_get_hw_state(struct drm_device *dev);
  1424. void skl_wm_get_hw_state(struct drm_device *dev);
  1425. void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
  1426.                           struct skl_ddb_allocation *ddb /* out */);
  1427. uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
  1428.  
  1429. /* intel_sdvo.c */
  1430. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
  1431.  
  1432.  
  1433. /* intel_sprite.c */
  1434. int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
  1435. int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  1436.                               struct drm_file *file_priv);
  1437. void intel_pipe_update_start(struct intel_crtc *crtc);
  1438. void intel_pipe_update_end(struct intel_crtc *crtc);
  1439.  
  1440. /* intel_tv.c */
  1441. void intel_tv_init(struct drm_device *dev);
  1442.  
  1443. /* intel_atomic.c */
  1444. int intel_connector_atomic_get_property(struct drm_connector *connector,
  1445.                                         const struct drm_connector_state *state,
  1446.                                         struct drm_property *property,
  1447.                                         uint64_t *val);
  1448. struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
  1449. void intel_crtc_destroy_state(struct drm_crtc *crtc,
  1450.                                struct drm_crtc_state *state);
  1451. struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
  1452. void intel_atomic_state_clear(struct drm_atomic_state *);
  1453. struct intel_shared_dpll_config *
  1454. intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
  1455.  
  1456. static inline struct intel_crtc_state *
  1457. intel_atomic_get_crtc_state(struct drm_atomic_state *state,
  1458.                             struct intel_crtc *crtc)
  1459. {
  1460.         struct drm_crtc_state *crtc_state;
  1461.         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
  1462.         if (IS_ERR(crtc_state))
  1463.                 return ERR_CAST(crtc_state);
  1464.  
  1465.         return to_intel_crtc_state(crtc_state);
  1466. }
  1467. int intel_atomic_setup_scalers(struct drm_device *dev,
  1468.         struct intel_crtc *intel_crtc,
  1469.         struct intel_crtc_state *crtc_state);
  1470.  
  1471. /* intel_atomic_plane.c */
  1472. struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
  1473. struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
  1474. void intel_plane_destroy_state(struct drm_plane *plane,
  1475.                                struct drm_plane_state *state);
  1476. extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
  1477.  
  1478. #endif /* __INTEL_DRV_H__ */
  1479.