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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright (c) 2007-2008 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23.  * IN THE SOFTWARE.
  24.  */
  25. #ifndef __INTEL_DRV_H__
  26. #define __INTEL_DRV_H__
  27.  
  28. #include <linux/async.h>
  29. #include <linux/i2c.h>
  30. #include <linux/hdmi.h>
  31. #include <drm/i915_drm.h>
  32. #include "i915_drv.h"
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_crtc_helper.h>
  35. #include <drm/drm_fb_helper.h>
  36. #include <drm/drm_dp_mst_helper.h>
  37. #include <drm/drm_rect.h>
  38.  
  39. #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  40. ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  41.  
  42. /**
  43.  * _wait_for - magic (register) wait macro
  44.  *
  45.  * Does the right thing for modeset paths when run under kdgb or similar atomic
  46.  * contexts. Note that it's important that we check the condition again after
  47.  * having timed out, since the timeout could be due to preemption or similar and
  48.  * we've never had a chance to check the condition before the timeout.
  49.  */
  50. #define _wait_for(COND, MS, W) ({ \
  51.         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  52.         int ret__ = 0;                                                  \
  53.         while (!(COND)) {                                               \
  54.                 if (time_after(jiffies, timeout__)) {                   \
  55.                         if (!(COND))                                    \
  56.                         ret__ = -ETIMEDOUT;                             \
  57.                         break;                                          \
  58.                 }                                                       \
  59.                 if (W )  {                              \
  60.          msleep(W); \
  61.                 } else {                                                \
  62.                         cpu_relax();                                    \
  63.                 }                                                       \
  64.         }                                                               \
  65.         ret__;                                                          \
  66. })
  67.  
  68. #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  69. #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  70. #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  71.                                                DIV_ROUND_UP((US), 1000), 0)
  72.  
  73. #define KHz(x) (1000 * (x))
  74. #define MHz(x) KHz(1000 * (x))
  75.  
  76. /*
  77.  * Display related stuff
  78.  */
  79.  
  80. /* store information about an Ixxx DVO */
  81. /* The i830->i865 use multiple DVOs with multiple i2cs */
  82. /* the i915, i945 have a single sDVO i2c bus - which is different */
  83. #define MAX_OUTPUTS 6
  84. /* maximum connectors per crtcs in the mode set */
  85.  
  86. /* Maximum cursor sizes */
  87. #define GEN2_CURSOR_WIDTH 64
  88. #define GEN2_CURSOR_HEIGHT 64
  89. #define MAX_CURSOR_WIDTH 256
  90. #define MAX_CURSOR_HEIGHT 256
  91.  
  92. #define INTEL_I2C_BUS_DVO 1
  93. #define INTEL_I2C_BUS_SDVO 2
  94.  
  95. /* these are outputs from the chip - integrated only
  96.    external chips are via DVO or SDVO output */
  97. enum intel_output_type {
  98.         INTEL_OUTPUT_UNUSED = 0,
  99.         INTEL_OUTPUT_ANALOG = 1,
  100.         INTEL_OUTPUT_DVO = 2,
  101.         INTEL_OUTPUT_SDVO = 3,
  102.         INTEL_OUTPUT_LVDS = 4,
  103.         INTEL_OUTPUT_TVOUT = 5,
  104.         INTEL_OUTPUT_HDMI = 6,
  105.         INTEL_OUTPUT_DISPLAYPORT = 7,
  106.         INTEL_OUTPUT_EDP = 8,
  107.         INTEL_OUTPUT_DSI = 9,
  108.         INTEL_OUTPUT_UNKNOWN = 10,
  109.         INTEL_OUTPUT_DP_MST = 11,
  110. };
  111.  
  112. #define INTEL_DVO_CHIP_NONE 0
  113. #define INTEL_DVO_CHIP_LVDS 1
  114. #define INTEL_DVO_CHIP_TMDS 2
  115. #define INTEL_DVO_CHIP_TVOUT 4
  116.  
  117. #define INTEL_DSI_VIDEO_MODE    0
  118. #define INTEL_DSI_COMMAND_MODE  1
  119.  
  120. struct intel_framebuffer {
  121.         struct drm_framebuffer base;
  122.         struct drm_i915_gem_object *obj;
  123. };
  124.  
  125. struct intel_fbdev {
  126.         struct drm_fb_helper helper;
  127.         struct intel_framebuffer *fb;
  128.         struct list_head fbdev_list;
  129.         struct drm_display_mode *our_mode;
  130.         int preferred_bpp;
  131. };
  132.  
  133. struct intel_encoder {
  134.         struct drm_encoder base;
  135.         /*
  136.          * The new crtc this encoder will be driven from. Only differs from
  137.          * base->crtc while a modeset is in progress.
  138.          */
  139.         struct intel_crtc *new_crtc;
  140.  
  141.         enum intel_output_type type;
  142.         unsigned int cloneable;
  143.         bool connectors_active;
  144.         void (*hot_plug)(struct intel_encoder *);
  145.         bool (*compute_config)(struct intel_encoder *,
  146.                                struct intel_crtc_config *);
  147.         void (*pre_pll_enable)(struct intel_encoder *);
  148.         void (*pre_enable)(struct intel_encoder *);
  149.         void (*enable)(struct intel_encoder *);
  150.         void (*mode_set)(struct intel_encoder *intel_encoder);
  151.         void (*disable)(struct intel_encoder *);
  152.         void (*post_disable)(struct intel_encoder *);
  153.         /* Read out the current hw state of this connector, returning true if
  154.          * the encoder is active. If the encoder is enabled it also set the pipe
  155.          * it is connected to in the pipe parameter. */
  156.         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
  157.         /* Reconstructs the equivalent mode flags for the current hardware
  158.          * state. This must be called _after_ display->get_pipe_config has
  159.          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
  160.          * be set correctly before calling this function. */
  161.         void (*get_config)(struct intel_encoder *,
  162.                            struct intel_crtc_config *pipe_config);
  163.         /*
  164.          * Called during system suspend after all pending requests for the
  165.          * encoder are flushed (for example for DP AUX transactions) and
  166.          * device interrupts are disabled.
  167.          */
  168.         void (*suspend)(struct intel_encoder *);
  169.         int crtc_mask;
  170.         enum hpd_pin hpd_pin;
  171. };
  172.  
  173. struct intel_panel {
  174.         struct drm_display_mode *fixed_mode;
  175.         struct drm_display_mode *downclock_mode;
  176.         int fitting_mode;
  177.  
  178.         /* backlight */
  179.         struct {
  180.                 bool present;
  181.                 u32 level;
  182.                 u32 min;
  183.                 u32 max;
  184.                 bool enabled;
  185.                 bool combination_mode;  /* gen 2/4 only */
  186.                 bool active_low_pwm;
  187.                 struct backlight_device *device;
  188.         } backlight;
  189.  
  190.         void (*backlight_power)(struct intel_connector *, bool enable);
  191. };
  192.  
  193. struct intel_connector {
  194.         struct drm_connector base;
  195.         /*
  196.          * The fixed encoder this connector is connected to.
  197.          */
  198.         struct intel_encoder *encoder;
  199.  
  200.         /*
  201.          * The new encoder this connector will be driven. Only differs from
  202.          * encoder while a modeset is in progress.
  203.          */
  204.         struct intel_encoder *new_encoder;
  205.  
  206.         /* Reads out the current hw, returning true if the connector is enabled
  207.          * and active (i.e. dpms ON state). */
  208.         bool (*get_hw_state)(struct intel_connector *);
  209.  
  210.         /*
  211.          * Removes all interfaces through which the connector is accessible
  212.          * - like sysfs, debugfs entries -, so that no new operations can be
  213.          * started on the connector. Also makes sure all currently pending
  214.          * operations finish before returing.
  215.          */
  216.         void (*unregister)(struct intel_connector *);
  217.  
  218.         /* Panel info for eDP and LVDS */
  219.         struct intel_panel panel;
  220.  
  221.         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
  222.         struct edid *edid;
  223.         struct edid *detect_edid;
  224.  
  225.         /* since POLL and HPD connectors may use the same HPD line keep the native
  226.            state of connector->polled in case hotplug storm detection changes it */
  227.         u8 polled;
  228.  
  229.         void *port; /* store this opaque as its illegal to dereference it */
  230.  
  231.         struct intel_dp *mst_port;
  232. };
  233.  
  234. typedef struct dpll {
  235.         /* given values */
  236.         int n;
  237.         int m1, m2;
  238.         int p1, p2;
  239.         /* derived values */
  240.         int     dot;
  241.         int     vco;
  242.         int     m;
  243.         int     p;
  244. } intel_clock_t;
  245.  
  246. struct intel_plane_state {
  247.         struct drm_crtc *crtc;
  248.         struct drm_framebuffer *fb;
  249.         struct drm_rect src;
  250.         struct drm_rect dst;
  251.         struct drm_rect clip;
  252.         struct drm_rect orig_src;
  253.         struct drm_rect orig_dst;
  254.         bool visible;
  255. };
  256.  
  257. struct intel_plane_config {
  258.         bool tiled;
  259.         int size;
  260.         u32 base;
  261. };
  262.  
  263. struct intel_crtc_config {
  264.         /**
  265.          * quirks - bitfield with hw state readout quirks
  266.          *
  267.          * For various reasons the hw state readout code might not be able to
  268.          * completely faithfully read out the current state. These cases are
  269.          * tracked with quirk flags so that fastboot and state checker can act
  270.          * accordingly.
  271.          */
  272. #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
  273. #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
  274.         unsigned long quirks;
  275.  
  276.         /* User requested mode, only valid as a starting point to
  277.          * compute adjusted_mode, except in the case of (S)DVO where
  278.          * it's also for the output timings of the (S)DVO chip.
  279.          * adjusted_mode will then correspond to the S(DVO) chip's
  280.          * preferred input timings. */
  281.         struct drm_display_mode requested_mode;
  282.         /* Actual pipe timings ie. what we program into the pipe timing
  283.          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
  284.         struct drm_display_mode adjusted_mode;
  285.  
  286.         /* Pipe source size (ie. panel fitter input size)
  287.          * All planes will be positioned inside this space,
  288.          * and get clipped at the edges. */
  289.         int pipe_src_w, pipe_src_h;
  290.  
  291.         /* Whether to set up the PCH/FDI. Note that we never allow sharing
  292.          * between pch encoders and cpu encoders. */
  293.         bool has_pch_encoder;
  294.  
  295.         /* Are we sending infoframes on the attached port */
  296.         bool has_infoframe;
  297.  
  298.         /* CPU Transcoder for the pipe. Currently this can only differ from the
  299.          * pipe on Haswell (where we have a special eDP transcoder). */
  300.         enum transcoder cpu_transcoder;
  301.  
  302.         /*
  303.          * Use reduced/limited/broadcast rbg range, compressing from the full
  304.          * range fed into the crtcs.
  305.          */
  306.         bool limited_color_range;
  307.  
  308.         /* DP has a bunch of special case unfortunately, so mark the pipe
  309.          * accordingly. */
  310.         bool has_dp_encoder;
  311.  
  312.         /* Whether we should send NULL infoframes. Required for audio. */
  313.         bool has_hdmi_sink;
  314.  
  315.         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
  316.          * has_dp_encoder is set. */
  317.         bool has_audio;
  318.  
  319.         /*
  320.          * Enable dithering, used when the selected pipe bpp doesn't match the
  321.          * plane bpp.
  322.          */
  323.         bool dither;
  324.  
  325.         /* Controls for the clock computation, to override various stages. */
  326.         bool clock_set;
  327.  
  328.         /* SDVO TV has a bunch of special case. To make multifunction encoders
  329.          * work correctly, we need to track this at runtime.*/
  330.         bool sdvo_tv_clock;
  331.  
  332.         /*
  333.          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
  334.          * required. This is set in the 2nd loop of calling encoder's
  335.          * ->compute_config if the first pick doesn't work out.
  336.          */
  337.         bool bw_constrained;
  338.  
  339.         /* Settings for the intel dpll used on pretty much everything but
  340.          * haswell. */
  341.         struct dpll dpll;
  342.  
  343.         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
  344.         enum intel_dpll_id shared_dpll;
  345.  
  346.         /*
  347.          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
  348.          * - enum skl_dpll on SKL
  349.          */
  350.         uint32_t ddi_pll_sel;
  351.  
  352.         /* Actual register state of the dpll, for shared dpll cross-checking. */
  353.         struct intel_dpll_hw_state dpll_hw_state;
  354.  
  355.         int pipe_bpp;
  356.         struct intel_link_m_n dp_m_n;
  357.  
  358.         /* m2_n2 for eDP downclock */
  359.         struct intel_link_m_n dp_m2_n2;
  360.         bool has_drrs;
  361.  
  362.         /*
  363.          * Frequence the dpll for the port should run at. Differs from the
  364.          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
  365.          * already multiplied by pixel_multiplier.
  366.          */
  367.         int port_clock;
  368.  
  369.         /* Used by SDVO (and if we ever fix it, HDMI). */
  370.         unsigned pixel_multiplier;
  371.  
  372.         /* Panel fitter controls for gen2-gen4 + VLV */
  373.         struct {
  374.                 u32 control;
  375.                 u32 pgm_ratios;
  376.                 u32 lvds_border_bits;
  377.         } gmch_pfit;
  378.  
  379.         /* Panel fitter placement and size for Ironlake+ */
  380.         struct {
  381.                 u32 pos;
  382.                 u32 size;
  383.                 bool enabled;
  384.                 bool force_thru;
  385.         } pch_pfit;
  386.  
  387.         /* FDI configuration, only valid if has_pch_encoder is set. */
  388.         int fdi_lanes;
  389.         struct intel_link_m_n fdi_m_n;
  390.  
  391.         bool ips_enabled;
  392.  
  393.         bool double_wide;
  394.  
  395.         bool dp_encoder_is_mst;
  396.         int pbn;
  397. };
  398.  
  399. struct intel_pipe_wm {
  400.         struct intel_wm_level wm[5];
  401.         uint32_t linetime;
  402.         bool fbc_wm_enabled;
  403.         bool pipe_enabled;
  404.         bool sprites_enabled;
  405.         bool sprites_scaled;
  406. };
  407.  
  408. struct intel_mmio_flip {
  409.         u32 seqno;
  410.         struct intel_engine_cs *ring;
  411.         struct work_struct work;
  412. };
  413.  
  414. struct skl_pipe_wm {
  415.         struct skl_wm_level wm[8];
  416.         struct skl_wm_level trans_wm;
  417.         uint32_t linetime;
  418. };
  419.  
  420. struct intel_crtc {
  421.         struct drm_crtc base;
  422.         enum pipe pipe;
  423.         enum plane plane;
  424.         u8 lut_r[256], lut_g[256], lut_b[256];
  425.         /*
  426.          * Whether the crtc and the connected output pipeline is active. Implies
  427.          * that crtc->enabled is set, i.e. the current mode configuration has
  428.          * some outputs connected to this crtc.
  429.          */
  430.         bool active;
  431.         unsigned long enabled_power_domains;
  432.         bool primary_enabled; /* is the primary plane (partially) visible? */
  433.         bool lowfreq_avail;
  434.         struct intel_overlay *overlay;
  435.         struct intel_unpin_work *unpin_work;
  436.  
  437.         atomic_t unpin_work_count;
  438.  
  439.         /* Display surface base address adjustement for pageflips. Note that on
  440.          * gen4+ this only adjusts up to a tile, offsets within a tile are
  441.          * handled in the hw itself (with the TILEOFF register). */
  442.         unsigned long dspaddr_offset;
  443.  
  444.         struct drm_i915_gem_object *cursor_bo;
  445.         uint32_t cursor_addr;
  446.         int16_t cursor_width, cursor_height;
  447.         uint32_t cursor_cntl;
  448.         uint32_t cursor_size;
  449.         uint32_t cursor_base;
  450.  
  451.         struct intel_plane_config plane_config;
  452.         struct intel_crtc_config config;
  453.         struct intel_crtc_config *new_config;
  454.         bool new_enabled;
  455.  
  456.         /* reset counter value when the last flip was submitted */
  457.         unsigned int reset_counter;
  458.  
  459.         /* Access to these should be protected by dev_priv->irq_lock. */
  460.         bool cpu_fifo_underrun_disabled;
  461.         bool pch_fifo_underrun_disabled;
  462.  
  463.         /* per-pipe watermark state */
  464.         struct {
  465.                 /* watermarks currently being used  */
  466.                 struct intel_pipe_wm active;
  467.                 /* SKL wm values currently in use */
  468.                 struct skl_pipe_wm skl_active;
  469.         } wm;
  470.  
  471.         int scanline_offset;
  472.         struct intel_mmio_flip mmio_flip;
  473. };
  474.  
  475. struct intel_plane_wm_parameters {
  476.         uint32_t horiz_pixels;
  477.         uint32_t vert_pixels;
  478.         uint8_t bytes_per_pixel;
  479.         bool enabled;
  480.         bool scaled;
  481. };
  482.  
  483. struct intel_plane {
  484.         struct drm_plane base;
  485.         int plane;
  486.         enum pipe pipe;
  487.         struct drm_i915_gem_object *obj;
  488.         bool can_scale;
  489.         int max_downscale;
  490.         int crtc_x, crtc_y;
  491.         unsigned int crtc_w, crtc_h;
  492.         uint32_t src_x, src_y;
  493.         uint32_t src_w, src_h;
  494.         unsigned int rotation;
  495.  
  496.         /* Since we need to change the watermarks before/after
  497.          * enabling/disabling the planes, we need to store the parameters here
  498.          * as the other pieces of the struct may not reflect the values we want
  499.          * for the watermark calculations. Currently only Haswell uses this.
  500.          */
  501.         struct intel_plane_wm_parameters wm;
  502.  
  503.         void (*update_plane)(struct drm_plane *plane,
  504.                              struct drm_crtc *crtc,
  505.                              struct drm_framebuffer *fb,
  506.                              struct drm_i915_gem_object *obj,
  507.                              int crtc_x, int crtc_y,
  508.                              unsigned int crtc_w, unsigned int crtc_h,
  509.                              uint32_t x, uint32_t y,
  510.                              uint32_t src_w, uint32_t src_h);
  511.         void (*disable_plane)(struct drm_plane *plane,
  512.                               struct drm_crtc *crtc);
  513.         int (*update_colorkey)(struct drm_plane *plane,
  514.                                struct drm_intel_sprite_colorkey *key);
  515.         void (*get_colorkey)(struct drm_plane *plane,
  516.                              struct drm_intel_sprite_colorkey *key);
  517. };
  518.  
  519. struct intel_watermark_params {
  520.         unsigned long fifo_size;
  521.         unsigned long max_wm;
  522.         unsigned long default_wm;
  523.         unsigned long guard_size;
  524.         unsigned long cacheline_size;
  525. };
  526.  
  527. struct cxsr_latency {
  528.         int is_desktop;
  529.         int is_ddr3;
  530.         unsigned long fsb_freq;
  531.         unsigned long mem_freq;
  532.         unsigned long display_sr;
  533.         unsigned long display_hpll_disable;
  534.         unsigned long cursor_sr;
  535.         unsigned long cursor_hpll_disable;
  536. };
  537.  
  538. #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
  539. #define to_intel_connector(x) container_of(x, struct intel_connector, base)
  540. #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
  541. #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
  542. #define to_intel_plane(x) container_of(x, struct intel_plane, base)
  543. #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
  544.  
  545. struct intel_hdmi {
  546.         u32 hdmi_reg;
  547.         int ddc_bus;
  548.         uint32_t color_range;
  549.         bool color_range_auto;
  550.         bool has_hdmi_sink;
  551.         bool has_audio;
  552.         enum hdmi_force_audio force_audio;
  553.         bool rgb_quant_range_selectable;
  554.         enum hdmi_picture_aspect aspect_ratio;
  555.         void (*write_infoframe)(struct drm_encoder *encoder,
  556.                                 enum hdmi_infoframe_type type,
  557.                                 const void *frame, ssize_t len);
  558.         void (*set_infoframes)(struct drm_encoder *encoder,
  559.                                bool enable,
  560.                                struct drm_display_mode *adjusted_mode);
  561.         bool (*infoframe_enabled)(struct drm_encoder *encoder);
  562. };
  563.  
  564. struct intel_dp_mst_encoder;
  565. #define DP_MAX_DOWNSTREAM_PORTS         0x10
  566.  
  567. /**
  568.  * HIGH_RR is the highest eDP panel refresh rate read from EDID
  569.  * LOW_RR is the lowest eDP panel refresh rate found from EDID
  570.  * parsing for same resolution.
  571.  */
  572. enum edp_drrs_refresh_rate_type {
  573.         DRRS_HIGH_RR,
  574.         DRRS_LOW_RR,
  575.         DRRS_MAX_RR, /* RR count */
  576. };
  577.  
  578. struct intel_dp {
  579.         uint32_t output_reg;
  580.         uint32_t aux_ch_ctl_reg;
  581.         uint32_t DP;
  582.         bool has_audio;
  583.         enum hdmi_force_audio force_audio;
  584.         uint32_t color_range;
  585.         bool color_range_auto;
  586.         uint8_t link_bw;
  587.         uint8_t lane_count;
  588.         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  589.         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
  590.         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
  591.         struct drm_dp_aux aux;
  592.         uint8_t train_set[4];
  593.         int panel_power_up_delay;
  594.         int panel_power_down_delay;
  595.         int panel_power_cycle_delay;
  596.         int backlight_on_delay;
  597.         int backlight_off_delay;
  598.         struct delayed_work panel_vdd_work;
  599.         bool want_panel_vdd;
  600.         unsigned long last_power_cycle;
  601.         unsigned long last_power_on;
  602.         unsigned long last_backlight_off;
  603.  
  604.         /*
  605.          * Pipe whose power sequencer is currently locked into
  606.          * this port. Only relevant on VLV/CHV.
  607.          */
  608.         enum pipe pps_pipe;
  609.         struct edp_power_seq pps_delays;
  610.  
  611.         bool use_tps3;
  612.         bool can_mst; /* this port supports mst */
  613.         bool is_mst;
  614.         int active_mst_links;
  615.         /* connector directly attached - won't be use for modeset in mst world */
  616.         struct intel_connector *attached_connector;
  617.  
  618.         /* mst connector list */
  619.         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
  620.         struct drm_dp_mst_topology_mgr mst_mgr;
  621.  
  622.         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
  623.         /*
  624.          * This function returns the value we have to program the AUX_CTL
  625.          * register with to kick off an AUX transaction.
  626.          */
  627.         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
  628.                                      bool has_aux_irq,
  629.                                      int send_bytes,
  630.                                      uint32_t aux_clock_divider);
  631.         struct {
  632.                 enum drrs_support_type type;
  633.                 enum edp_drrs_refresh_rate_type refresh_rate_type;
  634.                 struct mutex mutex;
  635.         } drrs_state;
  636.  
  637. };
  638.  
  639. struct intel_digital_port {
  640.         struct intel_encoder base;
  641.         enum port port;
  642.         u32 saved_port_bits;
  643.         struct intel_dp dp;
  644.         struct intel_hdmi hdmi;
  645.         bool (*hpd_pulse)(struct intel_digital_port *, bool);
  646. };
  647.  
  648. struct intel_dp_mst_encoder {
  649.         struct intel_encoder base;
  650.         enum pipe pipe;
  651.         struct intel_digital_port *primary;
  652.         void *port; /* store this opaque as its illegal to dereference it */
  653. };
  654.  
  655. static inline int
  656. vlv_dport_to_channel(struct intel_digital_port *dport)
  657. {
  658.         switch (dport->port) {
  659.         case PORT_B:
  660.         case PORT_D:
  661.                 return DPIO_CH0;
  662.         case PORT_C:
  663.                 return DPIO_CH1;
  664.         default:
  665.                 BUG();
  666.         }
  667. }
  668.  
  669. static inline int
  670. vlv_pipe_to_channel(enum pipe pipe)
  671. {
  672.         switch (pipe) {
  673.         case PIPE_A:
  674.         case PIPE_C:
  675.                 return DPIO_CH0;
  676.         case PIPE_B:
  677.                 return DPIO_CH1;
  678.         default:
  679.                 BUG();
  680.         }
  681. }
  682.  
  683. static inline struct drm_crtc *
  684. intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
  685. {
  686.         struct drm_i915_private *dev_priv = dev->dev_private;
  687.         return dev_priv->pipe_to_crtc_mapping[pipe];
  688. }
  689.  
  690. static inline struct drm_crtc *
  691. intel_get_crtc_for_plane(struct drm_device *dev, int plane)
  692. {
  693.         struct drm_i915_private *dev_priv = dev->dev_private;
  694.         return dev_priv->plane_to_crtc_mapping[plane];
  695. }
  696.  
  697. struct intel_unpin_work {
  698.         struct work_struct work;
  699.         struct drm_crtc *crtc;
  700.         struct drm_i915_gem_object *old_fb_obj;
  701.         struct drm_i915_gem_object *pending_flip_obj;
  702.         struct drm_pending_vblank_event *event;
  703.         atomic_t pending;
  704. #define INTEL_FLIP_INACTIVE     0
  705. #define INTEL_FLIP_PENDING      1
  706. #define INTEL_FLIP_COMPLETE     2
  707.         u32 flip_count;
  708.         u32 gtt_offset;
  709.         struct intel_engine_cs *flip_queued_ring;
  710.         u32 flip_queued_seqno;
  711.         int flip_queued_vblank;
  712.         int flip_ready_vblank;
  713.         bool enable_stall_check;
  714. };
  715.  
  716. struct intel_set_config {
  717.         struct drm_encoder **save_connector_encoders;
  718.         struct drm_crtc **save_encoder_crtcs;
  719.         bool *save_crtc_enabled;
  720.  
  721.         bool fb_changed;
  722.         bool mode_changed;
  723. };
  724.  
  725. struct intel_load_detect_pipe {
  726.         struct drm_framebuffer *release_fb;
  727.         bool load_detect_temp;
  728.         int dpms_mode;
  729. };
  730.  
  731. static inline struct intel_encoder *
  732. intel_attached_encoder(struct drm_connector *connector)
  733. {
  734.         return to_intel_connector(connector)->encoder;
  735. }
  736.  
  737. static inline struct intel_digital_port *
  738. enc_to_dig_port(struct drm_encoder *encoder)
  739. {
  740.         return container_of(encoder, struct intel_digital_port, base.base);
  741. }
  742.  
  743. static inline struct intel_dp_mst_encoder *
  744. enc_to_mst(struct drm_encoder *encoder)
  745. {
  746.         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
  747. }
  748.  
  749. static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  750. {
  751.         return &enc_to_dig_port(encoder)->dp;
  752. }
  753.  
  754. static inline struct intel_digital_port *
  755. dp_to_dig_port(struct intel_dp *intel_dp)
  756. {
  757.         return container_of(intel_dp, struct intel_digital_port, dp);
  758. }
  759.  
  760. static inline struct intel_digital_port *
  761. hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
  762. {
  763.         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
  764. }
  765.  
  766. /*
  767.  * Returns the number of planes for this pipe, ie the number of sprites + 1
  768.  * (primary plane). This doesn't count the cursor plane then.
  769.  */
  770. static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
  771. {
  772.         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
  773. }
  774.  
  775. /* intel_fifo_underrun.c */
  776. bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
  777.                                            enum pipe pipe, bool enable);
  778. bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
  779.                                            enum transcoder pch_transcoder,
  780.                                            bool enable);
  781. void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
  782.                                          enum pipe pipe);
  783. void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
  784.                                          enum transcoder pch_transcoder);
  785. void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
  786.  
  787. /* i915_irq.c */
  788. void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  789. void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  790. void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  791. void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  792. void gen6_reset_rps_interrupts(struct drm_device *dev);
  793. void gen6_enable_rps_interrupts(struct drm_device *dev);
  794. void gen6_disable_rps_interrupts(struct drm_device *dev);
  795. void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
  796. void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
  797. static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
  798. {
  799.         /*
  800.          * We only use drm_irq_uninstall() at unload and VT switch, so
  801.          * this is the only thing we need to check.
  802.          */
  803.         return dev_priv->pm.irqs_enabled;
  804. }
  805.  
  806. int intel_get_crtc_scanline(struct intel_crtc *crtc);
  807. void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
  808.  
  809. /* intel_crt.c */
  810. void intel_crt_init(struct drm_device *dev);
  811.  
  812.  
  813. /* intel_ddi.c */
  814. void intel_prepare_ddi(struct drm_device *dev);
  815. void hsw_fdi_link_train(struct drm_crtc *crtc);
  816. void intel_ddi_init(struct drm_device *dev, enum port port);
  817. enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
  818. bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
  819. int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
  820. void intel_ddi_pll_init(struct drm_device *dev);
  821. void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
  822. void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
  823.                                        enum transcoder cpu_transcoder);
  824. void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
  825. void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
  826. bool intel_ddi_pll_select(struct intel_crtc *crtc);
  827. void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
  828. void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
  829. bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
  830. void intel_ddi_fdi_disable(struct drm_crtc *crtc);
  831. void intel_ddi_get_config(struct intel_encoder *encoder,
  832.                           struct intel_crtc_config *pipe_config);
  833.  
  834. void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
  835. void intel_ddi_clock_get(struct intel_encoder *encoder,
  836.                          struct intel_crtc_config *pipe_config);
  837. void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
  838.  
  839. /* intel_frontbuffer.c */
  840. void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
  841.                         struct intel_engine_cs *ring);
  842. void intel_frontbuffer_flip_prepare(struct drm_device *dev,
  843.                                     unsigned frontbuffer_bits);
  844. void intel_frontbuffer_flip_complete(struct drm_device *dev,
  845.                                      unsigned frontbuffer_bits);
  846. void intel_frontbuffer_flush(struct drm_device *dev,
  847.                              unsigned frontbuffer_bits);
  848. /**
  849.  * intel_frontbuffer_flip - synchronous frontbuffer flip
  850.  * @dev: DRM device
  851.  * @frontbuffer_bits: frontbuffer plane tracking bits
  852.  *
  853.  * This function gets called after scheduling a flip on @obj. This is for
  854.  * synchronous plane updates which will happen on the next vblank and which will
  855.  * not get delayed by pending gpu rendering.
  856.  *
  857.  * Can be called without any locks held.
  858.  */
  859. static inline
  860. void intel_frontbuffer_flip(struct drm_device *dev,
  861.                             unsigned frontbuffer_bits)
  862. {
  863.         intel_frontbuffer_flush(dev, frontbuffer_bits);
  864. }
  865.  
  866. void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
  867.  
  868.  
  869. /* intel_audio.c */
  870. void intel_init_audio(struct drm_device *dev);
  871. void intel_audio_codec_enable(struct intel_encoder *encoder);
  872. void intel_audio_codec_disable(struct intel_encoder *encoder);
  873.  
  874. /* intel_display.c */
  875. const char *intel_output_name(int output);
  876. bool intel_has_pending_fb_unpin(struct drm_device *dev);
  877. int intel_pch_rawclk(struct drm_device *dev);
  878. void intel_mark_busy(struct drm_device *dev);
  879. void intel_mark_idle(struct drm_device *dev);
  880. void intel_crtc_restore_mode(struct drm_crtc *crtc);
  881. void intel_crtc_control(struct drm_crtc *crtc, bool enable);
  882. void intel_crtc_update_dpms(struct drm_crtc *crtc);
  883. void intel_encoder_destroy(struct drm_encoder *encoder);
  884. void intel_connector_dpms(struct drm_connector *, int mode);
  885. bool intel_connector_get_hw_state(struct intel_connector *connector);
  886. void intel_modeset_check_state(struct drm_device *dev);
  887. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  888.                                 struct intel_digital_port *port);
  889. void intel_connector_attach_encoder(struct intel_connector *connector,
  890.                                            struct intel_encoder *encoder);
  891. struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
  892. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  893.                                                     struct drm_crtc *crtc);
  894. enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
  895. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  896.                                 struct drm_file *file_priv);
  897. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  898.                              enum pipe pipe);
  899. bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
  900. static inline void
  901. intel_wait_for_vblank(struct drm_device *dev, int pipe)
  902. {
  903.         drm_wait_one_vblank(dev, pipe);
  904. }
  905. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
  906. void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
  907.                          struct intel_digital_port *dport);
  908. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  909.                                        struct drm_display_mode *mode,
  910.                                 struct intel_load_detect_pipe *old,
  911.                                 struct drm_modeset_acquire_ctx *ctx);
  912. void intel_release_load_detect_pipe(struct drm_connector *connector,
  913.                                     struct intel_load_detect_pipe *old);
  914. int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
  915.                                struct drm_framebuffer *fb,
  916.                                struct intel_engine_cs *pipelined);
  917. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
  918. struct drm_framebuffer *
  919. __intel_framebuffer_create(struct drm_device *dev,
  920.                                   struct drm_mode_fb_cmd2 *mode_cmd,
  921.                                   struct drm_i915_gem_object *obj);
  922. void intel_prepare_page_flip(struct drm_device *dev, int plane);
  923. void intel_finish_page_flip(struct drm_device *dev, int pipe);
  924. void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
  925. void intel_check_page_flip(struct drm_device *dev, int pipe);
  926.  
  927. /* shared dpll functions */
  928. struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
  929. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  930.                         struct intel_shared_dpll *pll,
  931.                         bool state);
  932. #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
  933. #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
  934. struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
  935. void intel_put_shared_dpll(struct intel_crtc *crtc);
  936.  
  937. void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
  938.                       const struct dpll *dpll);
  939. void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
  940.  
  941. /* modesetting asserts */
  942. void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  943.                            enum pipe pipe);
  944. void assert_pll(struct drm_i915_private *dev_priv,
  945.                 enum pipe pipe, bool state);
  946. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  947. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  948. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  949.                        enum pipe pipe, bool state);
  950. #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
  951. #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
  952. void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
  953. #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
  954. #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
  955. unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  956.                                                     unsigned int tiling_mode,
  957.                                                       unsigned int bpp,
  958.                                                       unsigned int pitch);
  959. void intel_prepare_reset(struct drm_device *dev);
  960. void intel_finish_reset(struct drm_device *dev);
  961. void hsw_enable_pc8(struct drm_i915_private *dev_priv);
  962. void hsw_disable_pc8(struct drm_i915_private *dev_priv);
  963. void intel_dp_get_m_n(struct intel_crtc *crtc,
  964.                       struct intel_crtc_config *pipe_config);
  965. void intel_dp_set_m_n(struct intel_crtc *crtc);
  966. int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
  967. void
  968. ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
  969.                                 int dotclock);
  970. bool intel_crtc_active(struct drm_crtc *crtc);
  971. void hsw_enable_ips(struct intel_crtc *crtc);
  972. void hsw_disable_ips(struct intel_crtc *crtc);
  973. enum intel_display_power_domain
  974. intel_display_port_power_domain(struct intel_encoder *intel_encoder);
  975. void intel_mode_from_pipe_config(struct drm_display_mode *mode,
  976.                                  struct intel_crtc_config *pipe_config);
  977. int intel_format_to_fourcc(int format);
  978. void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
  979. void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
  980.  
  981. /* intel_dp.c */
  982. void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
  983. bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  984.                              struct intel_connector *intel_connector);
  985. void intel_dp_start_link_train(struct intel_dp *intel_dp);
  986. void intel_dp_complete_link_train(struct intel_dp *intel_dp);
  987. void intel_dp_stop_link_train(struct intel_dp *intel_dp);
  988. void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
  989. void intel_dp_encoder_destroy(struct drm_encoder *encoder);
  990. void intel_dp_check_link_status(struct intel_dp *intel_dp);
  991. int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
  992. bool intel_dp_compute_config(struct intel_encoder *encoder,
  993.                              struct intel_crtc_config *pipe_config);
  994. bool intel_dp_is_edp(struct drm_device *dev, enum port port);
  995. bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
  996.                         bool long_hpd);
  997. void intel_edp_backlight_on(struct intel_dp *intel_dp);
  998. void intel_edp_backlight_off(struct intel_dp *intel_dp);
  999. void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
  1000. void intel_edp_panel_on(struct intel_dp *intel_dp);
  1001. void intel_edp_panel_off(struct intel_dp *intel_dp);
  1002. void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
  1003. void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
  1004. void intel_dp_mst_suspend(struct drm_device *dev);
  1005. void intel_dp_mst_resume(struct drm_device *dev);
  1006. int intel_dp_max_link_bw(struct intel_dp *intel_dp);
  1007. void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
  1008. void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
  1009. uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
  1010. void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes);
  1011.  
  1012. /* intel_dp_mst.c */
  1013. int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
  1014. void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
  1015. /* intel_dsi.c */
  1016. void intel_dsi_init(struct drm_device *dev);
  1017.  
  1018.  
  1019. /* intel_dvo.c */
  1020. void intel_dvo_init(struct drm_device *dev);
  1021.  
  1022.  
  1023. /* legacy fbdev emulation in intel_fbdev.c */
  1024. #ifdef CONFIG_DRM_I915_FBDEV
  1025. extern int intel_fbdev_init(struct drm_device *dev);
  1026. extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
  1027. extern void intel_fbdev_fini(struct drm_device *dev);
  1028. extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
  1029. extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
  1030. extern void intel_fbdev_restore_mode(struct drm_device *dev);
  1031. #else
  1032. static inline int intel_fbdev_init(struct drm_device *dev)
  1033. {
  1034.         return 0;
  1035. }
  1036.  
  1037. static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
  1038. {
  1039. }
  1040.  
  1041. static inline void intel_fbdev_fini(struct drm_device *dev)
  1042. {
  1043. }
  1044.  
  1045. static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
  1046. {
  1047. }
  1048.  
  1049. static inline void intel_fbdev_restore_mode(struct drm_device *dev)
  1050. {
  1051. }
  1052. #endif
  1053.  
  1054. /* intel_hdmi.c */
  1055. void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
  1056. void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  1057.                                struct intel_connector *intel_connector);
  1058. struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
  1059. bool intel_hdmi_compute_config(struct intel_encoder *encoder,
  1060.                                struct intel_crtc_config *pipe_config);
  1061.  
  1062.  
  1063. /* intel_lvds.c */
  1064. void intel_lvds_init(struct drm_device *dev);
  1065. bool intel_is_dual_link_lvds(struct drm_device *dev);
  1066.  
  1067.  
  1068. /* intel_modes.c */
  1069. int intel_connector_update_modes(struct drm_connector *connector,
  1070.                                  struct edid *edid);
  1071. int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
  1072. void intel_attach_force_audio_property(struct drm_connector *connector);
  1073. void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
  1074.  
  1075.  
  1076. /* intel_overlay.c */
  1077. void intel_setup_overlay(struct drm_device *dev);
  1078. void intel_cleanup_overlay(struct drm_device *dev);
  1079. int intel_overlay_switch_off(struct intel_overlay *overlay);
  1080. int intel_overlay_put_image(struct drm_device *dev, void *data,
  1081.                                      struct drm_file *file_priv);
  1082. int intel_overlay_attrs(struct drm_device *dev, void *data,
  1083.                                      struct drm_file *file_priv);
  1084.  
  1085.  
  1086. /* intel_panel.c */
  1087. int intel_panel_init(struct intel_panel *panel,
  1088.                      struct drm_display_mode *fixed_mode,
  1089.                      struct drm_display_mode *downclock_mode);
  1090. void intel_panel_fini(struct intel_panel *panel);
  1091. void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
  1092.                             struct drm_display_mode *adjusted_mode);
  1093. void intel_pch_panel_fitting(struct intel_crtc *crtc,
  1094.                              struct intel_crtc_config *pipe_config,
  1095.                              int fitting_mode);
  1096. void intel_gmch_panel_fitting(struct intel_crtc *crtc,
  1097.                               struct intel_crtc_config *pipe_config,
  1098.                               int fitting_mode);
  1099. void intel_panel_set_backlight_acpi(struct intel_connector *connector,
  1100.                                     u32 level, u32 max);
  1101. int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
  1102. void intel_panel_enable_backlight(struct intel_connector *connector);
  1103. void intel_panel_disable_backlight(struct intel_connector *connector);
  1104. void intel_panel_destroy_backlight(struct drm_connector *connector);
  1105. void intel_panel_init_backlight_funcs(struct drm_device *dev);
  1106. enum drm_connector_status intel_panel_detect(struct drm_device *dev);
  1107. extern struct drm_display_mode *intel_find_panel_downclock(
  1108.                                 struct drm_device *dev,
  1109.                                 struct drm_display_mode *fixed_mode,
  1110.                                 struct drm_connector *connector);
  1111. void intel_backlight_register(struct drm_device *dev);
  1112. void intel_backlight_unregister(struct drm_device *dev);
  1113.  
  1114.  
  1115. /* intel_psr.c */
  1116. bool intel_psr_is_enabled(struct drm_device *dev);
  1117. void intel_psr_enable(struct intel_dp *intel_dp);
  1118. void intel_psr_disable(struct intel_dp *intel_dp);
  1119. void intel_psr_invalidate(struct drm_device *dev,
  1120.                               unsigned frontbuffer_bits);
  1121. void intel_psr_flush(struct drm_device *dev,
  1122.                          unsigned frontbuffer_bits);
  1123. void intel_psr_init(struct drm_device *dev);
  1124.  
  1125. /* intel_runtime_pm.c */
  1126. int intel_power_domains_init(struct drm_i915_private *);
  1127. void intel_power_domains_fini(struct drm_i915_private *);
  1128. void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
  1129. void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
  1130.  
  1131. bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
  1132.                                     enum intel_display_power_domain domain);
  1133. bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
  1134.                                       enum intel_display_power_domain domain);
  1135. void intel_display_power_get(struct drm_i915_private *dev_priv,
  1136.                              enum intel_display_power_domain domain);
  1137. void intel_display_power_put(struct drm_i915_private *dev_priv,
  1138.                              enum intel_display_power_domain domain);
  1139. void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
  1140. void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
  1141. void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
  1142. void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
  1143. void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
  1144.  
  1145. void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
  1146.  
  1147. /* intel_pm.c */
  1148. void intel_init_clock_gating(struct drm_device *dev);
  1149. void intel_suspend_hw(struct drm_device *dev);
  1150. int ilk_wm_max_level(const struct drm_device *dev);
  1151. void intel_update_watermarks(struct drm_crtc *crtc);
  1152. void intel_update_sprite_watermarks(struct drm_plane *plane,
  1153.                                     struct drm_crtc *crtc,
  1154.                                     uint32_t sprite_width,
  1155.                                     uint32_t sprite_height,
  1156.                                     int pixel_size,
  1157.                                     bool enabled, bool scaled);
  1158. void intel_init_pm(struct drm_device *dev);
  1159. void intel_pm_setup(struct drm_device *dev);
  1160. bool intel_fbc_enabled(struct drm_device *dev);
  1161. void intel_update_fbc(struct drm_device *dev);
  1162. void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
  1163. void intel_gpu_ips_teardown(void);
  1164. void intel_init_gt_powersave(struct drm_device *dev);
  1165. void intel_cleanup_gt_powersave(struct drm_device *dev);
  1166. void intel_enable_gt_powersave(struct drm_device *dev);
  1167. void intel_disable_gt_powersave(struct drm_device *dev);
  1168. void intel_suspend_gt_powersave(struct drm_device *dev);
  1169. void intel_reset_gt_powersave(struct drm_device *dev);
  1170. void ironlake_teardown_rc6(struct drm_device *dev);
  1171. void gen6_update_ring_freq(struct drm_device *dev);
  1172. void gen6_rps_idle(struct drm_i915_private *dev_priv);
  1173. void gen6_rps_boost(struct drm_i915_private *dev_priv);
  1174. void ilk_wm_get_hw_state(struct drm_device *dev);
  1175. void skl_wm_get_hw_state(struct drm_device *dev);
  1176. void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
  1177.                           struct skl_ddb_allocation *ddb /* out */);
  1178.  
  1179.  
  1180. /* intel_sdvo.c */
  1181. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
  1182.  
  1183.  
  1184. /* intel_sprite.c */
  1185. int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
  1186. void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
  1187.                                enum plane plane);
  1188. int intel_plane_set_property(struct drm_plane *plane,
  1189.                              struct drm_property *prop,
  1190.                              uint64_t val);
  1191. int intel_plane_restore(struct drm_plane *plane);
  1192. void intel_plane_disable(struct drm_plane *plane);
  1193. int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  1194.                               struct drm_file *file_priv);
  1195. int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
  1196.                               struct drm_file *file_priv);
  1197. bool intel_pipe_update_start(struct intel_crtc *crtc,
  1198.                              uint32_t *start_vbl_count);
  1199. void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
  1200.  
  1201. /* intel_tv.c */
  1202. void intel_tv_init(struct drm_device *dev);
  1203.  
  1204. #endif /* __INTEL_DRV_H__ */
  1205.