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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright (c) 2007-2008 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23.  * IN THE SOFTWARE.
  24.  */
  25. #ifndef __INTEL_DRV_H__
  26. #define __INTEL_DRV_H__
  27.  
  28. #include <linux/i2c.h>
  29. #include <drm/i915_drm.h>
  30. #include "i915_drv.h"
  31. #include <drm/drm_crtc.h>
  32. #include <drm/drm_crtc_helper.h>
  33. #include <drm/drm_fb_helper.h>
  34. #include <drm/drm_dp_helper.h>
  35.  
  36. #define cpu_relax()     asm volatile("rep; nop")
  37.  
  38. #define _wait_for(COND, MS, W) ({ \
  39.     unsigned long timeout__ = GetTimerTicks() + msecs_to_jiffies(MS);  \
  40.         int ret__ = 0;                                                  \
  41.         while (!(COND)) {                                               \
  42.         if (time_after(GetTimerTicks(), timeout__)) {          \
  43.                         ret__ = -ETIMEDOUT;                             \
  44.                         break;                                          \
  45.                 }                                                       \
  46.                 if (W )  {                              \
  47.          msleep(W); \
  48.                 } else {                                                \
  49.                         cpu_relax();                                    \
  50.                 }                                                       \
  51.         }                                                               \
  52.         ret__;                                                          \
  53. })
  54.  
  55. #define wait_for_atomic_us(COND, US) ({ \
  56.         unsigned long timeout__ = GetTimerTicks() + usecs_to_jiffies(US);       \
  57.         int ret__ = 0;                                                  \
  58.         while (!(COND)) {                                               \
  59.                 if (time_after(GetTimerTicks(), timeout__)) {                   \
  60.                         ret__ = -ETIMEDOUT;                             \
  61.                         break;                                          \
  62.                 }                                                       \
  63.                 cpu_relax();                                            \
  64.         }                                                               \
  65.         ret__;                                                          \
  66. })
  67.  
  68. #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  69. #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  70.  
  71. #define MSLEEP(x) do { \
  72.         if (in_dbg_master()) \
  73.                 mdelay(x); \
  74.         else \
  75.                 msleep(x); \
  76. } while(0)
  77.  
  78. #define KHz(x) (1000*x)
  79. #define MHz(x) KHz(1000*x)
  80.  
  81. /*
  82.  * Display related stuff
  83.  */
  84.  
  85. /* store information about an Ixxx DVO */
  86. /* The i830->i865 use multiple DVOs with multiple i2cs */
  87. /* the i915, i945 have a single sDVO i2c bus - which is different */
  88. #define MAX_OUTPUTS 6
  89. /* maximum connectors per crtcs in the mode set */
  90. #define INTELFB_CONN_LIMIT 4
  91.  
  92. #define INTEL_I2C_BUS_DVO 1
  93. #define INTEL_I2C_BUS_SDVO 2
  94.  
  95. /* these are outputs from the chip - integrated only
  96.    external chips are via DVO or SDVO output */
  97. #define INTEL_OUTPUT_UNUSED 0
  98. #define INTEL_OUTPUT_ANALOG 1
  99. #define INTEL_OUTPUT_DVO 2
  100. #define INTEL_OUTPUT_SDVO 3
  101. #define INTEL_OUTPUT_LVDS 4
  102. #define INTEL_OUTPUT_TVOUT 5
  103. #define INTEL_OUTPUT_HDMI 6
  104. #define INTEL_OUTPUT_DISPLAYPORT 7
  105. #define INTEL_OUTPUT_EDP 8
  106. #define INTEL_OUTPUT_UNKNOWN 9
  107.  
  108. #define INTEL_DVO_CHIP_NONE 0
  109. #define INTEL_DVO_CHIP_LVDS 1
  110. #define INTEL_DVO_CHIP_TMDS 2
  111. #define INTEL_DVO_CHIP_TVOUT 4
  112.  
  113. /* drm_display_mode->private_flags */
  114. #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
  115. #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
  116. #define INTEL_MODE_DP_FORCE_6BPC (0x10)
  117. /* This flag must be set by the encoder's mode_fixup if it changes the crtc
  118.  * timings in the mode to prevent the crtc fixup from overwriting them.
  119.  * Currently only lvds needs that. */
  120. #define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
  121. /*
  122.  * Set when limited 16-235 (as opposed to full 0-255) RGB color range is
  123.  * to be used.
  124.  */
  125. #define INTEL_MODE_LIMITED_COLOR_RANGE (0x40)
  126.  
  127. static inline void
  128. intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
  129.                                 int multiplier)
  130. {
  131.         mode->clock *= multiplier;
  132.         mode->private_flags |= multiplier;
  133. }
  134.  
  135. static inline int
  136. intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
  137. {
  138.         return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
  139. }
  140.  
  141. struct intel_framebuffer {
  142.         struct drm_framebuffer base;
  143.         struct drm_i915_gem_object *obj;
  144. };
  145.  
  146. struct intel_fbdev {
  147.         struct drm_fb_helper helper;
  148.         struct intel_framebuffer ifb;
  149.         struct list_head fbdev_list;
  150.         struct drm_display_mode *our_mode;
  151. };
  152.  
  153. struct intel_encoder {
  154.         struct drm_encoder base;
  155.         /*
  156.          * The new crtc this encoder will be driven from. Only differs from
  157.          * base->crtc while a modeset is in progress.
  158.          */
  159.         struct intel_crtc *new_crtc;
  160.  
  161.         int type;
  162.         bool needs_tv_clock;
  163.         /*
  164.          * Intel hw has only one MUX where encoders could be clone, hence a
  165.          * simple flag is enough to compute the possible_clones mask.
  166.          */
  167.         bool cloneable;
  168.         bool connectors_active;
  169.         void (*hot_plug)(struct intel_encoder *);
  170.         void (*pre_pll_enable)(struct intel_encoder *);
  171.         void (*pre_enable)(struct intel_encoder *);
  172.         void (*enable)(struct intel_encoder *);
  173.         void (*disable)(struct intel_encoder *);
  174.         void (*post_disable)(struct intel_encoder *);
  175.         /* Read out the current hw state of this connector, returning true if
  176.          * the encoder is active. If the encoder is enabled it also set the pipe
  177.          * it is connected to in the pipe parameter. */
  178.         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
  179.         int crtc_mask;
  180. };
  181.  
  182. struct intel_panel {
  183.         struct drm_display_mode *fixed_mode;
  184.         int fitting_mode;
  185. };
  186.  
  187. struct intel_connector {
  188.         struct drm_connector base;
  189.         /*
  190.          * The fixed encoder this connector is connected to.
  191.          */
  192.         struct intel_encoder *encoder;
  193.  
  194.         /*
  195.          * The new encoder this connector will be driven. Only differs from
  196.          * encoder while a modeset is in progress.
  197.          */
  198.         struct intel_encoder *new_encoder;
  199.  
  200.         /* Reads out the current hw, returning true if the connector is enabled
  201.          * and active (i.e. dpms ON state). */
  202.         bool (*get_hw_state)(struct intel_connector *);
  203.  
  204.         /* Panel info for eDP and LVDS */
  205.         struct intel_panel panel;
  206.  
  207.         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
  208.         struct edid *edid;
  209. };
  210.  
  211. struct intel_crtc {
  212.         struct drm_crtc base;
  213.         enum pipe pipe;
  214.         enum plane plane;
  215.         enum transcoder cpu_transcoder;
  216.         u8 lut_r[256], lut_g[256], lut_b[256];
  217.         /*
  218.          * Whether the crtc and the connected output pipeline is active. Implies
  219.          * that crtc->enabled is set, i.e. the current mode configuration has
  220.          * some outputs connected to this crtc.
  221.          */
  222.         bool active;
  223.         bool eld_vld;
  224.         bool primary_disabled; /* is the crtc obscured by a plane? */
  225.         bool lowfreq_avail;
  226.         struct intel_overlay *overlay;
  227.         struct intel_unpin_work *unpin_work;
  228.         int fdi_lanes;
  229.  
  230.         atomic_t unpin_work_count;
  231.  
  232.         /* Display surface base address adjustement for pageflips. Note that on
  233.          * gen4+ this only adjusts up to a tile, offsets within a tile are
  234.          * handled in the hw itself (with the TILEOFF register). */
  235.         unsigned long dspaddr_offset;
  236.  
  237.         struct drm_i915_gem_object *cursor_bo;
  238.         uint32_t cursor_addr;
  239.         int16_t cursor_x, cursor_y;
  240.         int16_t cursor_width, cursor_height;
  241.         bool cursor_visible;
  242.         unsigned int bpp;
  243.  
  244.         /* We can share PLLs across outputs if the timings match */
  245.         struct intel_pch_pll *pch_pll;
  246.         uint32_t ddi_pll_sel;
  247.  
  248.         /* reset counter value when the last flip was submitted */
  249.         unsigned int reset_counter;
  250. };
  251.  
  252. struct intel_plane {
  253.         struct drm_plane base;
  254.         enum pipe pipe;
  255.         struct drm_i915_gem_object *obj;
  256.         bool can_scale;
  257.         int max_downscale;
  258.         u32 lut_r[1024], lut_g[1024], lut_b[1024];
  259.         void (*update_plane)(struct drm_plane *plane,
  260.                              struct drm_framebuffer *fb,
  261.                              struct drm_i915_gem_object *obj,
  262.                              int crtc_x, int crtc_y,
  263.                              unsigned int crtc_w, unsigned int crtc_h,
  264.                              uint32_t x, uint32_t y,
  265.                              uint32_t src_w, uint32_t src_h);
  266.         void (*disable_plane)(struct drm_plane *plane);
  267.         int (*update_colorkey)(struct drm_plane *plane,
  268.                                struct drm_intel_sprite_colorkey *key);
  269.         void (*get_colorkey)(struct drm_plane *plane,
  270.                              struct drm_intel_sprite_colorkey *key);
  271. };
  272.  
  273. struct intel_watermark_params {
  274.         unsigned long fifo_size;
  275.         unsigned long max_wm;
  276.         unsigned long default_wm;
  277.         unsigned long guard_size;
  278.         unsigned long cacheline_size;
  279. };
  280.  
  281. struct cxsr_latency {
  282.         int is_desktop;
  283.         int is_ddr3;
  284.         unsigned long fsb_freq;
  285.         unsigned long mem_freq;
  286.         unsigned long display_sr;
  287.         unsigned long display_hpll_disable;
  288.         unsigned long cursor_sr;
  289.         unsigned long cursor_hpll_disable;
  290. };
  291.  
  292. #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
  293. #define to_intel_connector(x) container_of(x, struct intel_connector, base)
  294. #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
  295. #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
  296. #define to_intel_plane(x) container_of(x, struct intel_plane, base)
  297.  
  298. #define DIP_HEADER_SIZE 5
  299.  
  300. #define DIP_TYPE_AVI    0x82
  301. #define DIP_VERSION_AVI 0x2
  302. #define DIP_LEN_AVI     13
  303. #define DIP_AVI_PR_1    0
  304. #define DIP_AVI_PR_2    1
  305. #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
  306. #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
  307. #define DIP_AVI_RGB_QUANT_RANGE_FULL    (2 << 2)
  308.  
  309. #define DIP_TYPE_SPD    0x83
  310. #define DIP_VERSION_SPD 0x1
  311. #define DIP_LEN_SPD     25
  312. #define DIP_SPD_UNKNOWN 0
  313. #define DIP_SPD_DSTB    0x1
  314. #define DIP_SPD_DVDP    0x2
  315. #define DIP_SPD_DVHS    0x3
  316. #define DIP_SPD_HDDVR   0x4
  317. #define DIP_SPD_DVC     0x5
  318. #define DIP_SPD_DSC     0x6
  319. #define DIP_SPD_VCD     0x7
  320. #define DIP_SPD_GAME    0x8
  321. #define DIP_SPD_PC      0x9
  322. #define DIP_SPD_BD      0xa
  323. #define DIP_SPD_SCD     0xb
  324.  
  325. struct dip_infoframe {
  326.         uint8_t type;           /* HB0 */
  327.         uint8_t ver;            /* HB1 */
  328.         uint8_t len;            /* HB2 - body len, not including checksum */
  329.         uint8_t ecc;            /* Header ECC */
  330.         uint8_t checksum;       /* PB0 */
  331.         union {
  332.                 struct {
  333.                         /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
  334.                         uint8_t Y_A_B_S;
  335.                         /* PB2 - C 7:6, M 5:4, R 3:0 */
  336.                         uint8_t C_M_R;
  337.                         /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
  338.                         uint8_t ITC_EC_Q_SC;
  339.                         /* PB4 - VIC 6:0 */
  340.                         uint8_t VIC;
  341.                         /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
  342.                         uint8_t YQ_CN_PR;
  343.                         /* PB6 to PB13 */
  344.                         uint16_t top_bar_end;
  345.                         uint16_t bottom_bar_start;
  346.                         uint16_t left_bar_end;
  347.                         uint16_t right_bar_start;
  348.                 } __attribute__ ((packed)) avi;
  349.                 struct {
  350.                         uint8_t vn[8];
  351.                         uint8_t pd[16];
  352.                         uint8_t sdi;
  353.                 } __attribute__ ((packed)) spd;
  354.                 uint8_t payload[27];
  355.         } __attribute__ ((packed)) body;
  356. } __attribute__((packed));
  357.  
  358. struct intel_hdmi {
  359.         u32 sdvox_reg;
  360.         int ddc_bus;
  361.         uint32_t color_range;
  362.         bool color_range_auto;
  363.         bool has_hdmi_sink;
  364.         bool has_audio;
  365.         enum hdmi_force_audio force_audio;
  366.         bool rgb_quant_range_selectable;
  367.         void (*write_infoframe)(struct drm_encoder *encoder,
  368.                                 struct dip_infoframe *frame);
  369.         void (*set_infoframes)(struct drm_encoder *encoder,
  370.                                struct drm_display_mode *adjusted_mode);
  371. };
  372.  
  373. #define DP_MAX_DOWNSTREAM_PORTS         0x10
  374. #define DP_LINK_CONFIGURATION_SIZE      9
  375.  
  376. struct intel_dp {
  377.         uint32_t output_reg;
  378.         uint32_t DP;
  379.         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  380.         bool has_audio;
  381.         enum hdmi_force_audio force_audio;
  382.         uint32_t color_range;
  383.         bool color_range_auto;
  384.         uint8_t link_bw;
  385.         uint8_t lane_count;
  386.         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  387.         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
  388.         struct i2c_adapter adapter;
  389.         struct i2c_algo_dp_aux_data algo;
  390.         bool is_pch_edp;
  391.         uint8_t train_set[4];
  392.         int panel_power_up_delay;
  393.         int panel_power_down_delay;
  394.         int panel_power_cycle_delay;
  395.         int backlight_on_delay;
  396.         int backlight_off_delay;
  397.         struct delayed_work panel_vdd_work;
  398.         bool want_panel_vdd;
  399.         struct intel_connector *attached_connector;
  400. };
  401.  
  402. struct intel_digital_port {
  403.         struct intel_encoder base;
  404.         enum port port;
  405.         u32 port_reversal;
  406.         struct intel_dp dp;
  407.         struct intel_hdmi hdmi;
  408. };
  409.  
  410. static inline struct drm_crtc *
  411. intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
  412. {
  413.         struct drm_i915_private *dev_priv = dev->dev_private;
  414.         return dev_priv->pipe_to_crtc_mapping[pipe];
  415. }
  416.  
  417. static inline struct drm_crtc *
  418. intel_get_crtc_for_plane(struct drm_device *dev, int plane)
  419. {
  420.         struct drm_i915_private *dev_priv = dev->dev_private;
  421.         return dev_priv->plane_to_crtc_mapping[plane];
  422. }
  423.  
  424. struct intel_unpin_work {
  425.         struct work_struct work;
  426.         struct drm_crtc *crtc;
  427.         struct drm_i915_gem_object *old_fb_obj;
  428.         struct drm_i915_gem_object *pending_flip_obj;
  429.         struct drm_pending_vblank_event *event;
  430.         atomic_t pending;
  431. #define INTEL_FLIP_INACTIVE     0
  432. #define INTEL_FLIP_PENDING      1
  433. #define INTEL_FLIP_COMPLETE     2
  434.         bool enable_stall_check;
  435. };
  436.  
  437. struct intel_fbc_work {
  438.         struct delayed_work work;
  439.         struct drm_crtc *crtc;
  440.         struct drm_framebuffer *fb;
  441.         int interval;
  442. };
  443.  
  444. int intel_pch_rawclk(struct drm_device *dev);
  445.  
  446. int intel_connector_update_modes(struct drm_connector *connector,
  447.                                 struct edid *edid);
  448. int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
  449.  
  450. extern void intel_attach_force_audio_property(struct drm_connector *connector);
  451. extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
  452.  
  453. extern void intel_crt_init(struct drm_device *dev);
  454. extern void intel_hdmi_init(struct drm_device *dev,
  455.                             int sdvox_reg, enum port port);
  456. extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  457.                                       struct intel_connector *intel_connector);
  458. extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
  459. extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
  460.                                   const struct drm_display_mode *mode,
  461.                                   struct drm_display_mode *adjusted_mode);
  462. extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
  463. extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
  464.                             bool is_sdvob);
  465. extern void intel_dvo_init(struct drm_device *dev);
  466. extern void intel_tv_init(struct drm_device *dev);
  467. extern void intel_mark_busy(struct drm_device *dev);
  468. extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
  469. extern void intel_mark_idle(struct drm_device *dev);
  470. extern bool intel_lvds_init(struct drm_device *dev);
  471. extern bool intel_is_dual_link_lvds(struct drm_device *dev);
  472. extern void intel_dp_init(struct drm_device *dev, int output_reg,
  473.                           enum port port);
  474. extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  475.                                     struct intel_connector *intel_connector);
  476. void
  477. intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
  478.                  struct drm_display_mode *adjusted_mode);
  479. extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
  480. extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
  481. extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
  482. extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
  483. extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
  484. extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
  485. extern bool intel_dp_mode_fixup(struct drm_encoder *encoder,
  486.                                 const struct drm_display_mode *mode,
  487.                                 struct drm_display_mode *adjusted_mode);
  488. extern bool intel_dpd_is_edp(struct drm_device *dev);
  489. extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
  490. extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
  491. extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
  492. extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
  493. extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
  494. extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  495. extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
  496. extern int intel_edp_target_clock(struct intel_encoder *,
  497.                                   struct drm_display_mode *mode);
  498. extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
  499. extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
  500. extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  501.                                       enum plane plane);
  502.  
  503. /* intel_panel.c */
  504. extern int intel_panel_init(struct intel_panel *panel,
  505.                             struct drm_display_mode *fixed_mode);
  506. extern void intel_panel_fini(struct intel_panel *panel);
  507.  
  508. extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
  509.                                    struct drm_display_mode *adjusted_mode);
  510. extern void intel_pch_panel_fitting(struct drm_device *dev,
  511.                                     int fitting_mode,
  512.                                     const struct drm_display_mode *mode,
  513.                                     struct drm_display_mode *adjusted_mode);
  514. extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
  515. extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
  516. extern int intel_panel_setup_backlight(struct drm_connector *connector);
  517. extern void intel_panel_enable_backlight(struct drm_device *dev,
  518.                                          enum pipe pipe);
  519. extern void intel_panel_disable_backlight(struct drm_device *dev);
  520. extern void intel_panel_destroy_backlight(struct drm_device *dev);
  521. extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
  522.  
  523. struct intel_set_config {
  524.         struct drm_encoder **save_connector_encoders;
  525.         struct drm_crtc **save_encoder_crtcs;
  526.  
  527.         bool fb_changed;
  528.         bool mode_changed;
  529. };
  530.  
  531. extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  532.                            int x, int y, struct drm_framebuffer *old_fb);
  533. extern void intel_modeset_disable(struct drm_device *dev);
  534. extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
  535. extern void intel_crtc_load_lut(struct drm_crtc *crtc);
  536. extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
  537. extern void intel_encoder_destroy(struct drm_encoder *encoder);
  538. extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
  539. extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
  540. extern void intel_connector_dpms(struct drm_connector *, int mode);
  541. extern bool intel_connector_get_hw_state(struct intel_connector *connector);
  542. extern void intel_modeset_check_state(struct drm_device *dev);
  543.  
  544.  
  545. static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
  546. {
  547.         return to_intel_connector(connector)->encoder;
  548. }
  549.  
  550. static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  551. {
  552.         struct intel_digital_port *intel_dig_port =
  553.                 container_of(encoder, struct intel_digital_port, base.base);
  554.         return &intel_dig_port->dp;
  555. }
  556.  
  557. static inline struct intel_digital_port *
  558. enc_to_dig_port(struct drm_encoder *encoder)
  559. {
  560.         return container_of(encoder, struct intel_digital_port, base.base);
  561. }
  562.  
  563. static inline struct intel_digital_port *
  564. dp_to_dig_port(struct intel_dp *intel_dp)
  565. {
  566.         return container_of(intel_dp, struct intel_digital_port, dp);
  567. }
  568.  
  569. static inline struct intel_digital_port *
  570. hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
  571. {
  572.         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
  573. }
  574.  
  575. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  576.                                 struct intel_digital_port *port);
  577.  
  578. extern void intel_connector_attach_encoder(struct intel_connector *connector,
  579.                                            struct intel_encoder *encoder);
  580. extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
  581.  
  582. extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  583.                                                     struct drm_crtc *crtc);
  584. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  585.                                 struct drm_file *file_priv);
  586. extern enum transcoder
  587. intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  588.                              enum pipe pipe);
  589. extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
  590. extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
  591. extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
  592.  
  593. struct intel_load_detect_pipe {
  594.         struct drm_framebuffer *release_fb;
  595.         bool load_detect_temp;
  596.         int dpms_mode;
  597. };
  598. extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
  599.                                        struct drm_display_mode *mode,
  600.                                        struct intel_load_detect_pipe *old);
  601. extern void intel_release_load_detect_pipe(struct drm_connector *connector,
  602.                                            struct intel_load_detect_pipe *old);
  603.  
  604. extern void intelfb_restore(void);
  605. extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  606.                                     u16 blue, int regno);
  607. extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  608.                                     u16 *blue, int regno);
  609. extern void intel_enable_clock_gating(struct drm_device *dev);
  610.  
  611. extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
  612.                                       struct drm_i915_gem_object *obj,
  613.                                       struct intel_ring_buffer *pipelined);
  614. extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
  615.  
  616. extern int intel_framebuffer_init(struct drm_device *dev,
  617.                                   struct intel_framebuffer *ifb,
  618.                                   struct drm_mode_fb_cmd2 *mode_cmd,
  619.                                   struct drm_i915_gem_object *obj);
  620. extern int intel_fbdev_init(struct drm_device *dev);
  621. extern void intel_fbdev_initial_config(struct drm_device *dev);
  622. extern void intel_fbdev_fini(struct drm_device *dev);
  623. extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
  624. extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
  625. extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
  626. extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
  627.  
  628. extern void intel_setup_overlay(struct drm_device *dev);
  629. extern void intel_cleanup_overlay(struct drm_device *dev);
  630. extern int intel_overlay_switch_off(struct intel_overlay *overlay);
  631. extern int intel_overlay_put_image(struct drm_device *dev, void *data,
  632.                                    struct drm_file *file_priv);
  633. extern int intel_overlay_attrs(struct drm_device *dev, void *data,
  634.                                struct drm_file *file_priv);
  635.  
  636. extern void intel_fb_output_poll_changed(struct drm_device *dev);
  637. extern void intel_fb_restore_mode(struct drm_device *dev);
  638.  
  639. extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  640.                         bool state);
  641. #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
  642. #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
  643.  
  644. extern void intel_init_clock_gating(struct drm_device *dev);
  645. extern void intel_write_eld(struct drm_encoder *encoder,
  646.                             struct drm_display_mode *mode);
  647. extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
  648. extern void intel_prepare_ddi(struct drm_device *dev);
  649. extern void hsw_fdi_link_train(struct drm_crtc *crtc);
  650. extern void intel_ddi_init(struct drm_device *dev, enum port port);
  651.  
  652. /* For use by IVB LP watermark workaround in intel_sprite.c */
  653. extern void intel_update_watermarks(struct drm_device *dev);
  654. extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
  655.                                            uint32_t sprite_width,
  656.                                            int pixel_size);
  657. extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
  658.                          struct drm_display_mode *mode);
  659.  
  660. extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  661.                                                     unsigned int tiling_mode,
  662.                                                       unsigned int bpp,
  663.                                                       unsigned int pitch);
  664.  
  665. extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  666.                                      struct drm_file *file_priv);
  667. extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
  668.                                      struct drm_file *file_priv);
  669.  
  670. extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
  671.  
  672. /* Power-related functions, located in intel_pm.c */
  673. extern void intel_init_pm(struct drm_device *dev);
  674. /* FBC */
  675. extern bool intel_fbc_enabled(struct drm_device *dev);
  676. extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
  677. extern void intel_update_fbc(struct drm_device *dev);
  678. /* IPS */
  679. extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
  680. extern void intel_gpu_ips_teardown(void);
  681.  
  682. extern void intel_init_power_well(struct drm_device *dev);
  683. extern void intel_set_power_well(struct drm_device *dev, bool enable);
  684. extern void intel_enable_gt_powersave(struct drm_device *dev);
  685. extern void intel_disable_gt_powersave(struct drm_device *dev);
  686. extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
  687. extern void ironlake_teardown_rc6(struct drm_device *dev);
  688.  
  689. extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
  690.                                    enum pipe *pipe);
  691. extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
  692. extern void intel_ddi_pll_init(struct drm_device *dev);
  693. extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
  694. extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
  695.                                               enum transcoder cpu_transcoder);
  696. extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
  697. extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
  698. extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
  699. extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
  700. extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
  701. extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
  702. extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
  703. extern bool
  704. intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
  705. extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
  706.  
  707. #endif /* __INTEL_DRV_H__ */
  708.