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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright (c) 2007-2008 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23.  * IN THE SOFTWARE.
  24.  */
  25. #ifndef __INTEL_DRV_H__
  26. #define __INTEL_DRV_H__
  27.  
  28. #include <linux/i2c.h>
  29. #include <drm/i915_drm.h>
  30. #include "i915_drv.h"
  31. #include <drm/drm_crtc.h>
  32. #include <drm/drm_crtc_helper.h>
  33. #include <drm/drm_fb_helper.h>
  34. #include <drm/drm_dp_helper.h>
  35.  
  36. #define cpu_relax()     asm volatile("rep; nop")
  37.  
  38. #define _wait_for(COND, MS, W) ({ \
  39.     unsigned long timeout__ = GetTimerTicks() + msecs_to_jiffies(MS);  \
  40.         int ret__ = 0;                                                  \
  41.         while (!(COND)) {                                               \
  42.         if (time_after(GetTimerTicks(), timeout__)) {          \
  43.                         ret__ = -ETIMEDOUT;                             \
  44.                         break;                                          \
  45.                 }                                                       \
  46.                 if (W )  {                              \
  47.          msleep(W); \
  48.                 } else {                                                \
  49.                         cpu_relax();                                    \
  50.                 }                                                       \
  51.         }                                                               \
  52.         ret__;                                                          \
  53. })
  54.  
  55. #define wait_for_atomic_us(COND, US) ({ \
  56.         unsigned long timeout__ = GetTimerTicks() + usecs_to_jiffies(US);       \
  57.         int ret__ = 0;                                                  \
  58.         while (!(COND)) {                                               \
  59.                 if (time_after(GetTimerTicks(), timeout__)) {                   \
  60.                         ret__ = -ETIMEDOUT;                             \
  61.                         break;                                          \
  62.                 }                                                       \
  63.                 cpu_relax();                                            \
  64.         }                                                               \
  65.         ret__;                                                          \
  66. })
  67.  
  68. #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  69. #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  70.  
  71. #define MSLEEP(x) do { \
  72.         if (in_dbg_master()) \
  73.                 mdelay(x); \
  74.         else \
  75.                 msleep(x); \
  76. } while(0)
  77.  
  78. #define KHz(x) (1000*x)
  79. #define MHz(x) KHz(1000*x)
  80.  
  81. /*
  82.  * Display related stuff
  83.  */
  84.  
  85. /* store information about an Ixxx DVO */
  86. /* The i830->i865 use multiple DVOs with multiple i2cs */
  87. /* the i915, i945 have a single sDVO i2c bus - which is different */
  88. #define MAX_OUTPUTS 6
  89. /* maximum connectors per crtcs in the mode set */
  90. #define INTELFB_CONN_LIMIT 4
  91.  
  92. #define INTEL_I2C_BUS_DVO 1
  93. #define INTEL_I2C_BUS_SDVO 2
  94.  
  95. /* these are outputs from the chip - integrated only
  96.    external chips are via DVO or SDVO output */
  97. #define INTEL_OUTPUT_UNUSED 0
  98. #define INTEL_OUTPUT_ANALOG 1
  99. #define INTEL_OUTPUT_DVO 2
  100. #define INTEL_OUTPUT_SDVO 3
  101. #define INTEL_OUTPUT_LVDS 4
  102. #define INTEL_OUTPUT_TVOUT 5
  103. #define INTEL_OUTPUT_HDMI 6
  104. #define INTEL_OUTPUT_DISPLAYPORT 7
  105. #define INTEL_OUTPUT_EDP 8
  106. #define INTEL_OUTPUT_UNKNOWN 9
  107.  
  108. #define INTEL_DVO_CHIP_NONE 0
  109. #define INTEL_DVO_CHIP_LVDS 1
  110. #define INTEL_DVO_CHIP_TMDS 2
  111. #define INTEL_DVO_CHIP_TVOUT 4
  112.  
  113. /* drm_display_mode->private_flags */
  114. #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
  115. #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
  116. #define INTEL_MODE_DP_FORCE_6BPC (0x10)
  117. /* This flag must be set by the encoder's mode_fixup if it changes the crtc
  118.  * timings in the mode to prevent the crtc fixup from overwriting them.
  119.  * Currently only lvds needs that. */
  120. #define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
  121.  
  122. static inline void
  123. intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
  124.                                 int multiplier)
  125. {
  126.         mode->clock *= multiplier;
  127.         mode->private_flags |= multiplier;
  128. }
  129.  
  130. static inline int
  131. intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
  132. {
  133.         return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
  134. }
  135.  
  136. struct intel_framebuffer {
  137.         struct drm_framebuffer base;
  138.         struct drm_i915_gem_object *obj;
  139. };
  140.  
  141. struct intel_fbdev {
  142.         struct drm_fb_helper helper;
  143.         struct intel_framebuffer ifb;
  144.         struct list_head fbdev_list;
  145.         struct drm_display_mode *our_mode;
  146. };
  147.  
  148. struct intel_encoder {
  149.         struct drm_encoder base;
  150.         /*
  151.          * The new crtc this encoder will be driven from. Only differs from
  152.          * base->crtc while a modeset is in progress.
  153.          */
  154.         struct intel_crtc *new_crtc;
  155.  
  156.         int type;
  157.         bool needs_tv_clock;
  158.         /*
  159.          * Intel hw has only one MUX where encoders could be clone, hence a
  160.          * simple flag is enough to compute the possible_clones mask.
  161.          */
  162.         bool cloneable;
  163.         bool connectors_active;
  164.         void (*hot_plug)(struct intel_encoder *);
  165.         void (*pre_enable)(struct intel_encoder *);
  166.         void (*enable)(struct intel_encoder *);
  167.         void (*disable)(struct intel_encoder *);
  168.         void (*post_disable)(struct intel_encoder *);
  169.         /* Read out the current hw state of this connector, returning true if
  170.          * the encoder is active. If the encoder is enabled it also set the pipe
  171.          * it is connected to in the pipe parameter. */
  172.         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
  173.         int crtc_mask;
  174. };
  175.  
  176. struct intel_panel {
  177.         struct drm_display_mode *fixed_mode;
  178.         int fitting_mode;
  179. };
  180.  
  181. struct intel_connector {
  182.         struct drm_connector base;
  183.         /*
  184.          * The fixed encoder this connector is connected to.
  185.          */
  186.         struct intel_encoder *encoder;
  187.  
  188.         /*
  189.          * The new encoder this connector will be driven. Only differs from
  190.          * encoder while a modeset is in progress.
  191.          */
  192.         struct intel_encoder *new_encoder;
  193.  
  194.         /* Reads out the current hw, returning true if the connector is enabled
  195.          * and active (i.e. dpms ON state). */
  196.         bool (*get_hw_state)(struct intel_connector *);
  197.  
  198.         /* Panel info for eDP and LVDS */
  199.         struct intel_panel panel;
  200.  
  201.         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
  202.         struct edid *edid;
  203. };
  204.  
  205. struct intel_crtc {
  206.         struct drm_crtc base;
  207.         enum pipe pipe;
  208.         enum plane plane;
  209.         enum transcoder cpu_transcoder;
  210.         u8 lut_r[256], lut_g[256], lut_b[256];
  211.         /*
  212.          * Whether the crtc and the connected output pipeline is active. Implies
  213.          * that crtc->enabled is set, i.e. the current mode configuration has
  214.          * some outputs connected to this crtc.
  215.          */
  216.         bool active;
  217.         bool primary_disabled; /* is the crtc obscured by a plane? */
  218.         bool lowfreq_avail;
  219.         struct intel_overlay *overlay;
  220.         struct intel_unpin_work *unpin_work;
  221.         int fdi_lanes;
  222.  
  223.         atomic_t unpin_work_count;
  224.  
  225.         /* Display surface base address adjustement for pageflips. Note that on
  226.          * gen4+ this only adjusts up to a tile, offsets within a tile are
  227.          * handled in the hw itself (with the TILEOFF register). */
  228.         unsigned long dspaddr_offset;
  229.  
  230.         struct drm_i915_gem_object *cursor_bo;
  231.         uint32_t cursor_addr;
  232.         int16_t cursor_x, cursor_y;
  233.         int16_t cursor_width, cursor_height;
  234.         bool cursor_visible;
  235.         unsigned int bpp;
  236.  
  237.         /* We can share PLLs across outputs if the timings match */
  238.         struct intel_pch_pll *pch_pll;
  239.         uint32_t ddi_pll_sel;
  240. };
  241.  
  242. struct intel_plane {
  243.         struct drm_plane base;
  244.         enum pipe pipe;
  245.         struct drm_i915_gem_object *obj;
  246.         bool can_scale;
  247.         int max_downscale;
  248.         u32 lut_r[1024], lut_g[1024], lut_b[1024];
  249.         void (*update_plane)(struct drm_plane *plane,
  250.                              struct drm_framebuffer *fb,
  251.                              struct drm_i915_gem_object *obj,
  252.                              int crtc_x, int crtc_y,
  253.                              unsigned int crtc_w, unsigned int crtc_h,
  254.                              uint32_t x, uint32_t y,
  255.                              uint32_t src_w, uint32_t src_h);
  256.         void (*disable_plane)(struct drm_plane *plane);
  257.         int (*update_colorkey)(struct drm_plane *plane,
  258.                                struct drm_intel_sprite_colorkey *key);
  259.         void (*get_colorkey)(struct drm_plane *plane,
  260.                              struct drm_intel_sprite_colorkey *key);
  261. };
  262.  
  263. struct intel_watermark_params {
  264.         unsigned long fifo_size;
  265.         unsigned long max_wm;
  266.         unsigned long default_wm;
  267.         unsigned long guard_size;
  268.         unsigned long cacheline_size;
  269. };
  270.  
  271. struct cxsr_latency {
  272.         int is_desktop;
  273.         int is_ddr3;
  274.         unsigned long fsb_freq;
  275.         unsigned long mem_freq;
  276.         unsigned long display_sr;
  277.         unsigned long display_hpll_disable;
  278.         unsigned long cursor_sr;
  279.         unsigned long cursor_hpll_disable;
  280. };
  281.  
  282. #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
  283. #define to_intel_connector(x) container_of(x, struct intel_connector, base)
  284. #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
  285. #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
  286. #define to_intel_plane(x) container_of(x, struct intel_plane, base)
  287.  
  288. #define DIP_HEADER_SIZE 5
  289.  
  290. #define DIP_TYPE_AVI    0x82
  291. #define DIP_VERSION_AVI 0x2
  292. #define DIP_LEN_AVI     13
  293. #define DIP_AVI_PR_1    0
  294. #define DIP_AVI_PR_2    1
  295.  
  296. #define DIP_TYPE_SPD    0x83
  297. #define DIP_VERSION_SPD 0x1
  298. #define DIP_LEN_SPD     25
  299. #define DIP_SPD_UNKNOWN 0
  300. #define DIP_SPD_DSTB    0x1
  301. #define DIP_SPD_DVDP    0x2
  302. #define DIP_SPD_DVHS    0x3
  303. #define DIP_SPD_HDDVR   0x4
  304. #define DIP_SPD_DVC     0x5
  305. #define DIP_SPD_DSC     0x6
  306. #define DIP_SPD_VCD     0x7
  307. #define DIP_SPD_GAME    0x8
  308. #define DIP_SPD_PC      0x9
  309. #define DIP_SPD_BD      0xa
  310. #define DIP_SPD_SCD     0xb
  311.  
  312. struct dip_infoframe {
  313.         uint8_t type;           /* HB0 */
  314.         uint8_t ver;            /* HB1 */
  315.         uint8_t len;            /* HB2 - body len, not including checksum */
  316.         uint8_t ecc;            /* Header ECC */
  317.         uint8_t checksum;       /* PB0 */
  318.         union {
  319.                 struct {
  320.                         /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
  321.                         uint8_t Y_A_B_S;
  322.                         /* PB2 - C 7:6, M 5:4, R 3:0 */
  323.                         uint8_t C_M_R;
  324.                         /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
  325.                         uint8_t ITC_EC_Q_SC;
  326.                         /* PB4 - VIC 6:0 */
  327.                         uint8_t VIC;
  328.                         /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
  329.                         uint8_t YQ_CN_PR;
  330.                         /* PB6 to PB13 */
  331.                         uint16_t top_bar_end;
  332.                         uint16_t bottom_bar_start;
  333.                         uint16_t left_bar_end;
  334.                         uint16_t right_bar_start;
  335.                 } __attribute__ ((packed)) avi;
  336.                 struct {
  337.                         uint8_t vn[8];
  338.                         uint8_t pd[16];
  339.                         uint8_t sdi;
  340.                 } __attribute__ ((packed)) spd;
  341.                 uint8_t payload[27];
  342.         } __attribute__ ((packed)) body;
  343. } __attribute__((packed));
  344.  
  345. struct intel_hdmi {
  346.         u32 sdvox_reg;
  347.         int ddc_bus;
  348.         uint32_t color_range;
  349.         bool has_hdmi_sink;
  350.         bool has_audio;
  351.         enum hdmi_force_audio force_audio;
  352.         void (*write_infoframe)(struct drm_encoder *encoder,
  353.                                 struct dip_infoframe *frame);
  354.         void (*set_infoframes)(struct drm_encoder *encoder,
  355.                                struct drm_display_mode *adjusted_mode);
  356. };
  357.  
  358. #define DP_MAX_DOWNSTREAM_PORTS         0x10
  359. #define DP_LINK_CONFIGURATION_SIZE      9
  360.  
  361. struct intel_dp {
  362.         uint32_t output_reg;
  363.         uint32_t DP;
  364.         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  365.         bool has_audio;
  366.         enum hdmi_force_audio force_audio;
  367.         uint32_t color_range;
  368.         uint8_t link_bw;
  369.         uint8_t lane_count;
  370.         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  371.         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
  372.         struct i2c_adapter adapter;
  373.         struct i2c_algo_dp_aux_data algo;
  374.         bool is_pch_edp;
  375.         uint8_t train_set[4];
  376.         int panel_power_up_delay;
  377.         int panel_power_down_delay;
  378.         int panel_power_cycle_delay;
  379.         int backlight_on_delay;
  380.         int backlight_off_delay;
  381.         struct delayed_work panel_vdd_work;
  382.         bool want_panel_vdd;
  383.         struct intel_connector *attached_connector;
  384. };
  385.  
  386. struct intel_digital_port {
  387.         struct intel_encoder base;
  388.         enum port port;
  389.         struct intel_dp dp;
  390.         struct intel_hdmi hdmi;
  391. };
  392.  
  393. static inline struct drm_crtc *
  394. intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
  395. {
  396.         struct drm_i915_private *dev_priv = dev->dev_private;
  397.         return dev_priv->pipe_to_crtc_mapping[pipe];
  398. }
  399.  
  400. static inline struct drm_crtc *
  401. intel_get_crtc_for_plane(struct drm_device *dev, int plane)
  402. {
  403.         struct drm_i915_private *dev_priv = dev->dev_private;
  404.         return dev_priv->plane_to_crtc_mapping[plane];
  405. }
  406.  
  407. struct intel_unpin_work {
  408.         struct work_struct work;
  409.         struct drm_crtc *crtc;
  410.         struct drm_i915_gem_object *old_fb_obj;
  411.         struct drm_i915_gem_object *pending_flip_obj;
  412.         struct drm_pending_vblank_event *event;
  413.         atomic_t pending;
  414. #define INTEL_FLIP_INACTIVE     0
  415. #define INTEL_FLIP_PENDING      1
  416. #define INTEL_FLIP_COMPLETE     2
  417.         bool enable_stall_check;
  418. };
  419.  
  420. struct intel_fbc_work {
  421.         struct delayed_work work;
  422.         struct drm_crtc *crtc;
  423.         struct drm_framebuffer *fb;
  424.         int interval;
  425. };
  426.  
  427. int intel_pch_rawclk(struct drm_device *dev);
  428.  
  429. int intel_connector_update_modes(struct drm_connector *connector,
  430.                                 struct edid *edid);
  431. int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
  432.  
  433. extern void intel_attach_force_audio_property(struct drm_connector *connector);
  434. extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
  435.  
  436. extern void intel_crt_init(struct drm_device *dev);
  437. extern void intel_hdmi_init(struct drm_device *dev,
  438.                             int sdvox_reg, enum port port);
  439. extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  440.                                       struct intel_connector *intel_connector);
  441. extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
  442. extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
  443.                                   const struct drm_display_mode *mode,
  444.                                   struct drm_display_mode *adjusted_mode);
  445. extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
  446. extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
  447.                             bool is_sdvob);
  448. extern void intel_dvo_init(struct drm_device *dev);
  449. extern void intel_tv_init(struct drm_device *dev);
  450. extern void intel_mark_busy(struct drm_device *dev);
  451. extern void intel_mark_idle(struct drm_device *dev);
  452. extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
  453. extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
  454. extern bool intel_lvds_init(struct drm_device *dev);
  455. extern void intel_dp_init(struct drm_device *dev, int output_reg,
  456.                           enum port port);
  457. extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  458.                                     struct intel_connector *intel_connector);
  459. void
  460. intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
  461.                  struct drm_display_mode *adjusted_mode);
  462. extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
  463. extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
  464. extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
  465. extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
  466. extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
  467. extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
  468. extern bool intel_dp_mode_fixup(struct drm_encoder *encoder,
  469.                                 const struct drm_display_mode *mode,
  470.                                 struct drm_display_mode *adjusted_mode);
  471. extern bool intel_dpd_is_edp(struct drm_device *dev);
  472. extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
  473. extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
  474. extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
  475. extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
  476. extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
  477. extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  478. extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
  479. extern int intel_edp_target_clock(struct intel_encoder *,
  480.                                   struct drm_display_mode *mode);
  481. extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
  482. extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
  483. extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  484.                                       enum plane plane);
  485.  
  486. /* intel_panel.c */
  487. extern int intel_panel_init(struct intel_panel *panel,
  488.                             struct drm_display_mode *fixed_mode);
  489. extern void intel_panel_fini(struct intel_panel *panel);
  490.  
  491. extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
  492.                                    struct drm_display_mode *adjusted_mode);
  493. extern void intel_pch_panel_fitting(struct drm_device *dev,
  494.                                     int fitting_mode,
  495.                                     const struct drm_display_mode *mode,
  496.                                     struct drm_display_mode *adjusted_mode);
  497. extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
  498. extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
  499. extern int intel_panel_setup_backlight(struct drm_connector *connector);
  500. extern void intel_panel_enable_backlight(struct drm_device *dev,
  501.                                          enum pipe pipe);
  502. extern void intel_panel_disable_backlight(struct drm_device *dev);
  503. extern void intel_panel_destroy_backlight(struct drm_device *dev);
  504. extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
  505.  
  506. struct intel_set_config {
  507.         struct drm_encoder **save_connector_encoders;
  508.         struct drm_crtc **save_encoder_crtcs;
  509.  
  510.         bool fb_changed;
  511.         bool mode_changed;
  512. };
  513.  
  514. extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  515.                            int x, int y, struct drm_framebuffer *old_fb);
  516. extern void intel_modeset_disable(struct drm_device *dev);
  517. extern void intel_crtc_load_lut(struct drm_crtc *crtc);
  518. extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
  519. extern void intel_encoder_noop(struct drm_encoder *encoder);
  520. extern void intel_encoder_destroy(struct drm_encoder *encoder);
  521. extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
  522. extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
  523. extern void intel_connector_dpms(struct drm_connector *, int mode);
  524. extern bool intel_connector_get_hw_state(struct intel_connector *connector);
  525. extern void intel_modeset_check_state(struct drm_device *dev);
  526.  
  527.  
  528. static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
  529. {
  530.         return to_intel_connector(connector)->encoder;
  531. }
  532.  
  533. static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  534. {
  535.         struct intel_digital_port *intel_dig_port =
  536.                 container_of(encoder, struct intel_digital_port, base.base);
  537.         return &intel_dig_port->dp;
  538. }
  539.  
  540. static inline struct intel_digital_port *
  541. enc_to_dig_port(struct drm_encoder *encoder)
  542. {
  543.         return container_of(encoder, struct intel_digital_port, base.base);
  544. }
  545.  
  546. static inline struct intel_digital_port *
  547. dp_to_dig_port(struct intel_dp *intel_dp)
  548. {
  549.         return container_of(intel_dp, struct intel_digital_port, dp);
  550. }
  551.  
  552. static inline struct intel_digital_port *
  553. hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
  554. {
  555.         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
  556. }
  557.  
  558. extern void intel_connector_attach_encoder(struct intel_connector *connector,
  559.                                            struct intel_encoder *encoder);
  560. extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
  561.  
  562. extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  563.                                                     struct drm_crtc *crtc);
  564. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  565.                                 struct drm_file *file_priv);
  566. extern enum transcoder
  567. intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  568.                              enum pipe pipe);
  569. extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
  570. extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
  571. extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
  572.  
  573. struct intel_load_detect_pipe {
  574.         struct drm_framebuffer *release_fb;
  575.         bool load_detect_temp;
  576.         int dpms_mode;
  577. };
  578. extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
  579.                                        struct drm_display_mode *mode,
  580.                                        struct intel_load_detect_pipe *old);
  581. extern void intel_release_load_detect_pipe(struct drm_connector *connector,
  582.                                            struct intel_load_detect_pipe *old);
  583.  
  584. extern void intelfb_restore(void);
  585. extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  586.                                     u16 blue, int regno);
  587. extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  588.                                     u16 *blue, int regno);
  589. extern void intel_enable_clock_gating(struct drm_device *dev);
  590.  
  591. extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
  592.                                       struct drm_i915_gem_object *obj,
  593.                                       struct intel_ring_buffer *pipelined);
  594. extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
  595.  
  596. extern int intel_framebuffer_init(struct drm_device *dev,
  597.                                   struct intel_framebuffer *ifb,
  598.                                   struct drm_mode_fb_cmd2 *mode_cmd,
  599.                                   struct drm_i915_gem_object *obj);
  600. extern int intel_fbdev_init(struct drm_device *dev);
  601. extern void intel_fbdev_fini(struct drm_device *dev);
  602. extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
  603. extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
  604. extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
  605. extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
  606.  
  607. extern void intel_setup_overlay(struct drm_device *dev);
  608. extern void intel_cleanup_overlay(struct drm_device *dev);
  609. extern int intel_overlay_switch_off(struct intel_overlay *overlay);
  610. extern int intel_overlay_put_image(struct drm_device *dev, void *data,
  611.                                    struct drm_file *file_priv);
  612. extern int intel_overlay_attrs(struct drm_device *dev, void *data,
  613.                                struct drm_file *file_priv);
  614.  
  615. extern void intel_fb_output_poll_changed(struct drm_device *dev);
  616. extern void intel_fb_restore_mode(struct drm_device *dev);
  617.  
  618. extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  619.                         bool state);
  620. #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
  621. #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
  622.  
  623. extern void intel_init_clock_gating(struct drm_device *dev);
  624. extern void intel_write_eld(struct drm_encoder *encoder,
  625.                             struct drm_display_mode *mode);
  626. extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
  627. extern void intel_prepare_ddi(struct drm_device *dev);
  628. extern void hsw_fdi_link_train(struct drm_crtc *crtc);
  629. extern void intel_ddi_init(struct drm_device *dev, enum port port);
  630.  
  631. /* For use by IVB LP watermark workaround in intel_sprite.c */
  632. extern void intel_update_watermarks(struct drm_device *dev);
  633. extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
  634.                                            uint32_t sprite_width,
  635.                                            int pixel_size);
  636. extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
  637.                          struct drm_display_mode *mode);
  638.  
  639. extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
  640.                                                       unsigned int bpp,
  641.                                                       unsigned int pitch);
  642.  
  643. extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  644.                                      struct drm_file *file_priv);
  645. extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
  646.                                      struct drm_file *file_priv);
  647.  
  648. extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
  649.  
  650. /* Power-related functions, located in intel_pm.c */
  651. extern void intel_init_pm(struct drm_device *dev);
  652. /* FBC */
  653. extern bool intel_fbc_enabled(struct drm_device *dev);
  654. extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
  655. extern void intel_update_fbc(struct drm_device *dev);
  656. /* IPS */
  657. extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
  658. extern void intel_gpu_ips_teardown(void);
  659.  
  660. extern void intel_init_power_wells(struct drm_device *dev);
  661. extern void intel_enable_gt_powersave(struct drm_device *dev);
  662. extern void intel_disable_gt_powersave(struct drm_device *dev);
  663. extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
  664. extern void ironlake_teardown_rc6(struct drm_device *dev);
  665.  
  666. extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
  667.                                    enum pipe *pipe);
  668. extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
  669. extern void intel_ddi_pll_init(struct drm_device *dev);
  670. extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
  671. extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
  672.                                               enum transcoder cpu_transcoder);
  673. extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
  674. extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
  675. extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
  676. extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
  677. extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
  678. extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
  679. extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
  680. extern bool
  681. intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
  682. extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
  683.  
  684. #endif /* __INTEL_DRV_H__ */
  685.