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  1. /*
  2.  * Copyright © 2006-2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *  Eric Anholt <eric@anholt.net>
  25.  */
  26.  
  27. //#include <linux/dmi.h>
  28. #include <linux/module.h>
  29. //#include <linux/input.h>
  30. #include <linux/i2c.h>
  31. #include <linux/kernel.h>
  32. #include <linux/slab.h>
  33. #include <linux/math64.h>
  34. #include <drm/drm_edid.h>
  35. #include <drm/drmP.h>
  36. #include "intel_drv.h"
  37. #include <drm/i915_drm.h>
  38. #include "i915_drv.h"
  39. #include "i915_trace.h"
  40. #include <drm/drm_dp_helper.h>
  41. #include <drm/drm_crtc_helper.h>
  42. //#include <linux/dma_remapping.h>
  43.  
  44. #define MAX_ERRNO       4095
  45. phys_addr_t get_bus_addr(void);
  46.  
  47. bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  48. static void intel_increase_pllclock(struct drm_crtc *crtc);
  49. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50.  
  51. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  52.                                 struct intel_crtc_config *pipe_config);
  53. static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  54.                                     struct intel_crtc_config *pipe_config);
  55.  
  56. static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  57.                           int x, int y, struct drm_framebuffer *old_fb);
  58.  
  59.  
  60. typedef struct {
  61.     int min, max;
  62. } intel_range_t;
  63.  
  64. typedef struct {
  65.     int dot_limit;
  66.     int p2_slow, p2_fast;
  67. } intel_p2_t;
  68.  
  69. typedef struct intel_limit intel_limit_t;
  70. struct intel_limit {
  71.     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  72.     intel_p2_t      p2;
  73. };
  74.  
  75. /* FDI */
  76. #define IRONLAKE_FDI_FREQ       2700000 /* in kHz for mode->clock */
  77.  
  78. int
  79. intel_pch_rawclk(struct drm_device *dev)
  80. {
  81.         struct drm_i915_private *dev_priv = dev->dev_private;
  82.  
  83.         WARN_ON(!HAS_PCH_SPLIT(dev));
  84.  
  85.         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  86. }
  87.  
  88. static inline u32 /* units of 100MHz */
  89. intel_fdi_link_freq(struct drm_device *dev)
  90. {
  91.         if (IS_GEN5(dev)) {
  92.                 struct drm_i915_private *dev_priv = dev->dev_private;
  93.                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  94.         } else
  95.                 return 27;
  96. }
  97.  
  98. static const intel_limit_t intel_limits_i8xx_dac = {
  99.         .dot = { .min = 25000, .max = 350000 },
  100.         .vco = { .min = 930000, .max = 1400000 },
  101.         .n = { .min = 3, .max = 16 },
  102.         .m = { .min = 96, .max = 140 },
  103.         .m1 = { .min = 18, .max = 26 },
  104.         .m2 = { .min = 6, .max = 16 },
  105.         .p = { .min = 4, .max = 128 },
  106.         .p1 = { .min = 2, .max = 33 },
  107.         .p2 = { .dot_limit = 165000,
  108.                 .p2_slow = 4, .p2_fast = 2 },
  109. };
  110.  
  111. static const intel_limit_t intel_limits_i8xx_dvo = {
  112.         .dot = { .min = 25000, .max = 350000 },
  113.         .vco = { .min = 930000, .max = 1400000 },
  114.         .n = { .min = 3, .max = 16 },
  115.         .m = { .min = 96, .max = 140 },
  116.         .m1 = { .min = 18, .max = 26 },
  117.         .m2 = { .min = 6, .max = 16 },
  118.         .p = { .min = 4, .max = 128 },
  119.         .p1 = { .min = 2, .max = 33 },
  120.         .p2 = { .dot_limit = 165000,
  121.                 .p2_slow = 4, .p2_fast = 4 },
  122. };
  123.  
  124. static const intel_limit_t intel_limits_i8xx_lvds = {
  125.         .dot = { .min = 25000, .max = 350000 },
  126.         .vco = { .min = 930000, .max = 1400000 },
  127.         .n = { .min = 3, .max = 16 },
  128.         .m = { .min = 96, .max = 140 },
  129.         .m1 = { .min = 18, .max = 26 },
  130.         .m2 = { .min = 6, .max = 16 },
  131.         .p = { .min = 4, .max = 128 },
  132.         .p1 = { .min = 1, .max = 6 },
  133.         .p2 = { .dot_limit = 165000,
  134.                 .p2_slow = 14, .p2_fast = 7 },
  135. };
  136.  
  137. static const intel_limit_t intel_limits_i9xx_sdvo = {
  138.         .dot = { .min = 20000, .max = 400000 },
  139.         .vco = { .min = 1400000, .max = 2800000 },
  140.         .n = { .min = 1, .max = 6 },
  141.         .m = { .min = 70, .max = 120 },
  142.         .m1 = { .min = 8, .max = 18 },
  143.         .m2 = { .min = 3, .max = 7 },
  144.         .p = { .min = 5, .max = 80 },
  145.         .p1 = { .min = 1, .max = 8 },
  146.         .p2 = { .dot_limit = 200000,
  147.                 .p2_slow = 10, .p2_fast = 5 },
  148. };
  149.  
  150. static const intel_limit_t intel_limits_i9xx_lvds = {
  151.         .dot = { .min = 20000, .max = 400000 },
  152.         .vco = { .min = 1400000, .max = 2800000 },
  153.         .n = { .min = 1, .max = 6 },
  154.         .m = { .min = 70, .max = 120 },
  155.         .m1 = { .min = 8, .max = 18 },
  156.         .m2 = { .min = 3, .max = 7 },
  157.         .p = { .min = 7, .max = 98 },
  158.         .p1 = { .min = 1, .max = 8 },
  159.         .p2 = { .dot_limit = 112000,
  160.                 .p2_slow = 14, .p2_fast = 7 },
  161. };
  162.  
  163.  
  164. static const intel_limit_t intel_limits_g4x_sdvo = {
  165.         .dot = { .min = 25000, .max = 270000 },
  166.         .vco = { .min = 1750000, .max = 3500000},
  167.         .n = { .min = 1, .max = 4 },
  168.         .m = { .min = 104, .max = 138 },
  169.         .m1 = { .min = 17, .max = 23 },
  170.         .m2 = { .min = 5, .max = 11 },
  171.         .p = { .min = 10, .max = 30 },
  172.         .p1 = { .min = 1, .max = 3},
  173.         .p2 = { .dot_limit = 270000,
  174.                 .p2_slow = 10,
  175.                 .p2_fast = 10
  176.         },
  177. };
  178.  
  179. static const intel_limit_t intel_limits_g4x_hdmi = {
  180.         .dot = { .min = 22000, .max = 400000 },
  181.         .vco = { .min = 1750000, .max = 3500000},
  182.         .n = { .min = 1, .max = 4 },
  183.         .m = { .min = 104, .max = 138 },
  184.         .m1 = { .min = 16, .max = 23 },
  185.         .m2 = { .min = 5, .max = 11 },
  186.         .p = { .min = 5, .max = 80 },
  187.         .p1 = { .min = 1, .max = 8},
  188.         .p2 = { .dot_limit = 165000,
  189.                 .p2_slow = 10, .p2_fast = 5 },
  190. };
  191.  
  192. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  193.         .dot = { .min = 20000, .max = 115000 },
  194.         .vco = { .min = 1750000, .max = 3500000 },
  195.         .n = { .min = 1, .max = 3 },
  196.         .m = { .min = 104, .max = 138 },
  197.         .m1 = { .min = 17, .max = 23 },
  198.         .m2 = { .min = 5, .max = 11 },
  199.         .p = { .min = 28, .max = 112 },
  200.         .p1 = { .min = 2, .max = 8 },
  201.         .p2 = { .dot_limit = 0,
  202.                 .p2_slow = 14, .p2_fast = 14
  203.         },
  204. };
  205.  
  206. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  207.         .dot = { .min = 80000, .max = 224000 },
  208.         .vco = { .min = 1750000, .max = 3500000 },
  209.         .n = { .min = 1, .max = 3 },
  210.         .m = { .min = 104, .max = 138 },
  211.         .m1 = { .min = 17, .max = 23 },
  212.         .m2 = { .min = 5, .max = 11 },
  213.         .p = { .min = 14, .max = 42 },
  214.         .p1 = { .min = 2, .max = 6 },
  215.         .p2 = { .dot_limit = 0,
  216.                 .p2_slow = 7, .p2_fast = 7
  217.         },
  218. };
  219.  
  220. static const intel_limit_t intel_limits_pineview_sdvo = {
  221.         .dot = { .min = 20000, .max = 400000},
  222.         .vco = { .min = 1700000, .max = 3500000 },
  223.         /* Pineview's Ncounter is a ring counter */
  224.         .n = { .min = 3, .max = 6 },
  225.         .m = { .min = 2, .max = 256 },
  226.         /* Pineview only has one combined m divider, which we treat as m2. */
  227.         .m1 = { .min = 0, .max = 0 },
  228.         .m2 = { .min = 0, .max = 254 },
  229.         .p = { .min = 5, .max = 80 },
  230.         .p1 = { .min = 1, .max = 8 },
  231.         .p2 = { .dot_limit = 200000,
  232.                 .p2_slow = 10, .p2_fast = 5 },
  233. };
  234.  
  235. static const intel_limit_t intel_limits_pineview_lvds = {
  236.         .dot = { .min = 20000, .max = 400000 },
  237.         .vco = { .min = 1700000, .max = 3500000 },
  238.         .n = { .min = 3, .max = 6 },
  239.         .m = { .min = 2, .max = 256 },
  240.         .m1 = { .min = 0, .max = 0 },
  241.         .m2 = { .min = 0, .max = 254 },
  242.         .p = { .min = 7, .max = 112 },
  243.         .p1 = { .min = 1, .max = 8 },
  244.         .p2 = { .dot_limit = 112000,
  245.                 .p2_slow = 14, .p2_fast = 14 },
  246. };
  247.  
  248. /* Ironlake / Sandybridge
  249.  *
  250.  * We calculate clock using (register_value + 2) for N/M1/M2, so here
  251.  * the range value for them is (actual_value - 2).
  252.  */
  253. static const intel_limit_t intel_limits_ironlake_dac = {
  254.         .dot = { .min = 25000, .max = 350000 },
  255.         .vco = { .min = 1760000, .max = 3510000 },
  256.         .n = { .min = 1, .max = 5 },
  257.         .m = { .min = 79, .max = 127 },
  258.         .m1 = { .min = 12, .max = 22 },
  259.         .m2 = { .min = 5, .max = 9 },
  260.         .p = { .min = 5, .max = 80 },
  261.         .p1 = { .min = 1, .max = 8 },
  262.         .p2 = { .dot_limit = 225000,
  263.                 .p2_slow = 10, .p2_fast = 5 },
  264. };
  265.  
  266. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  267.         .dot = { .min = 25000, .max = 350000 },
  268.         .vco = { .min = 1760000, .max = 3510000 },
  269.         .n = { .min = 1, .max = 3 },
  270.         .m = { .min = 79, .max = 118 },
  271.         .m1 = { .min = 12, .max = 22 },
  272.         .m2 = { .min = 5, .max = 9 },
  273.         .p = { .min = 28, .max = 112 },
  274.         .p1 = { .min = 2, .max = 8 },
  275.         .p2 = { .dot_limit = 225000,
  276.                 .p2_slow = 14, .p2_fast = 14 },
  277. };
  278.  
  279. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  280.         .dot = { .min = 25000, .max = 350000 },
  281.         .vco = { .min = 1760000, .max = 3510000 },
  282.         .n = { .min = 1, .max = 3 },
  283.         .m = { .min = 79, .max = 127 },
  284.         .m1 = { .min = 12, .max = 22 },
  285.         .m2 = { .min = 5, .max = 9 },
  286.         .p = { .min = 14, .max = 56 },
  287.         .p1 = { .min = 2, .max = 8 },
  288.         .p2 = { .dot_limit = 225000,
  289.                 .p2_slow = 7, .p2_fast = 7 },
  290. };
  291.  
  292. /* LVDS 100mhz refclk limits. */
  293. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  294.         .dot = { .min = 25000, .max = 350000 },
  295.         .vco = { .min = 1760000, .max = 3510000 },
  296.         .n = { .min = 1, .max = 2 },
  297.         .m = { .min = 79, .max = 126 },
  298.         .m1 = { .min = 12, .max = 22 },
  299.         .m2 = { .min = 5, .max = 9 },
  300.         .p = { .min = 28, .max = 112 },
  301.         .p1 = { .min = 2, .max = 8 },
  302.         .p2 = { .dot_limit = 225000,
  303.                 .p2_slow = 14, .p2_fast = 14 },
  304. };
  305.  
  306. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  307.         .dot = { .min = 25000, .max = 350000 },
  308.         .vco = { .min = 1760000, .max = 3510000 },
  309.         .n = { .min = 1, .max = 3 },
  310.         .m = { .min = 79, .max = 126 },
  311.         .m1 = { .min = 12, .max = 22 },
  312.         .m2 = { .min = 5, .max = 9 },
  313.         .p = { .min = 14, .max = 42 },
  314.         .p1 = { .min = 2, .max = 6 },
  315.         .p2 = { .dot_limit = 225000,
  316.                 .p2_slow = 7, .p2_fast = 7 },
  317. };
  318.  
  319. static const intel_limit_t intel_limits_vlv_dac = {
  320.         .dot = { .min = 25000, .max = 270000 },
  321.         .vco = { .min = 4000000, .max = 6000000 },
  322.         .n = { .min = 1, .max = 7 },
  323.         .m = { .min = 22, .max = 450 }, /* guess */
  324.         .m1 = { .min = 2, .max = 3 },
  325.         .m2 = { .min = 11, .max = 156 },
  326.         .p = { .min = 10, .max = 30 },
  327.         .p1 = { .min = 1, .max = 3 },
  328.         .p2 = { .dot_limit = 270000,
  329.                 .p2_slow = 2, .p2_fast = 20 },
  330. };
  331.  
  332. static const intel_limit_t intel_limits_vlv_hdmi = {
  333.         .dot = { .min = 25000, .max = 270000 },
  334.         .vco = { .min = 4000000, .max = 6000000 },
  335.         .n = { .min = 1, .max = 7 },
  336.         .m = { .min = 60, .max = 300 }, /* guess */
  337.         .m1 = { .min = 2, .max = 3 },
  338.         .m2 = { .min = 11, .max = 156 },
  339.         .p = { .min = 10, .max = 30 },
  340.         .p1 = { .min = 2, .max = 3 },
  341.         .p2 = { .dot_limit = 270000,
  342.                 .p2_slow = 2, .p2_fast = 20 },
  343. };
  344.  
  345. static const intel_limit_t intel_limits_vlv_dp = {
  346.         .dot = { .min = 25000, .max = 270000 },
  347.         .vco = { .min = 4000000, .max = 6000000 },
  348.         .n = { .min = 1, .max = 7 },
  349.         .m = { .min = 22, .max = 450 },
  350.         .m1 = { .min = 2, .max = 3 },
  351.         .m2 = { .min = 11, .max = 156 },
  352.         .p = { .min = 10, .max = 30 },
  353.         .p1 = { .min = 1, .max = 3 },
  354.         .p2 = { .dot_limit = 270000,
  355.                 .p2_slow = 2, .p2_fast = 20 },
  356. };
  357.  
  358. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  359.                                                 int refclk)
  360. {
  361.         struct drm_device *dev = crtc->dev;
  362.         const intel_limit_t *limit;
  363.  
  364.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  365.                 if (intel_is_dual_link_lvds(dev)) {
  366.                         if (refclk == 100000)
  367.                                 limit = &intel_limits_ironlake_dual_lvds_100m;
  368.                         else
  369.                                 limit = &intel_limits_ironlake_dual_lvds;
  370.                 } else {
  371.                         if (refclk == 100000)
  372.                                 limit = &intel_limits_ironlake_single_lvds_100m;
  373.                         else
  374.                                 limit = &intel_limits_ironlake_single_lvds;
  375.                 }
  376.         } else
  377.                 limit = &intel_limits_ironlake_dac;
  378.  
  379.         return limit;
  380. }
  381.  
  382. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  383. {
  384.         struct drm_device *dev = crtc->dev;
  385.         const intel_limit_t *limit;
  386.  
  387.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  388.                 if (intel_is_dual_link_lvds(dev))
  389.                         limit = &intel_limits_g4x_dual_channel_lvds;
  390.                 else
  391.                         limit = &intel_limits_g4x_single_channel_lvds;
  392.         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  393.                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  394.                 limit = &intel_limits_g4x_hdmi;
  395.         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  396.                 limit = &intel_limits_g4x_sdvo;
  397.         } else /* The option is for other outputs */
  398.                 limit = &intel_limits_i9xx_sdvo;
  399.  
  400.         return limit;
  401. }
  402.  
  403. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  404. {
  405.         struct drm_device *dev = crtc->dev;
  406.         const intel_limit_t *limit;
  407.  
  408.         if (HAS_PCH_SPLIT(dev))
  409.                 limit = intel_ironlake_limit(crtc, refclk);
  410.         else if (IS_G4X(dev)) {
  411.                 limit = intel_g4x_limit(crtc);
  412.         } else if (IS_PINEVIEW(dev)) {
  413.                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  414.                         limit = &intel_limits_pineview_lvds;
  415.                 else
  416.                         limit = &intel_limits_pineview_sdvo;
  417.         } else if (IS_VALLEYVIEW(dev)) {
  418.                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
  419.                         limit = &intel_limits_vlv_dac;
  420.                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  421.                         limit = &intel_limits_vlv_hdmi;
  422.                 else
  423.                         limit = &intel_limits_vlv_dp;
  424.         } else if (!IS_GEN2(dev)) {
  425.                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  426.                         limit = &intel_limits_i9xx_lvds;
  427.                 else
  428.                         limit = &intel_limits_i9xx_sdvo;
  429.         } else {
  430.                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  431.                         limit = &intel_limits_i8xx_lvds;
  432.                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
  433.                         limit = &intel_limits_i8xx_dvo;
  434.                 else
  435.                         limit = &intel_limits_i8xx_dac;
  436.         }
  437.         return limit;
  438. }
  439.  
  440. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  441. static void pineview_clock(int refclk, intel_clock_t *clock)
  442. {
  443.         clock->m = clock->m2 + 2;
  444.         clock->p = clock->p1 * clock->p2;
  445.         clock->vco = refclk * clock->m / clock->n;
  446.         clock->dot = clock->vco / clock->p;
  447. }
  448.  
  449. static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
  450. {
  451.         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
  452. }
  453.  
  454. static void i9xx_clock(int refclk, intel_clock_t *clock)
  455. {
  456.         clock->m = i9xx_dpll_compute_m(clock);
  457.         clock->p = clock->p1 * clock->p2;
  458.         clock->vco = refclk * clock->m / (clock->n + 2);
  459.         clock->dot = clock->vco / clock->p;
  460. }
  461.  
  462. /**
  463.  * Returns whether any output on the specified pipe is of the specified type
  464.  */
  465. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  466. {
  467.         struct drm_device *dev = crtc->dev;
  468.         struct intel_encoder *encoder;
  469.  
  470.         for_each_encoder_on_crtc(dev, crtc, encoder)
  471.                 if (encoder->type == type)
  472.                         return true;
  473.  
  474.         return false;
  475. }
  476.  
  477. #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
  478. /**
  479.  * Returns whether the given set of divisors are valid for a given refclk with
  480.  * the given connectors.
  481.  */
  482.  
  483. static bool intel_PLL_is_valid(struct drm_device *dev,
  484.                                const intel_limit_t *limit,
  485.                                const intel_clock_t *clock)
  486. {
  487.         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
  488.                 INTELPllInvalid("p1 out of range\n");
  489.         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
  490.                 INTELPllInvalid("p out of range\n");
  491.         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
  492.                 INTELPllInvalid("m2 out of range\n");
  493.         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
  494.                 INTELPllInvalid("m1 out of range\n");
  495.         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  496.                 INTELPllInvalid("m1 <= m2\n");
  497.         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
  498.                 INTELPllInvalid("m out of range\n");
  499.         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
  500.                 INTELPllInvalid("n out of range\n");
  501.         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  502.                 INTELPllInvalid("vco out of range\n");
  503.         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  504.          * connector, etc., rather than just a single range.
  505.          */
  506.         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  507.                 INTELPllInvalid("dot out of range\n");
  508.  
  509.         return true;
  510. }
  511.  
  512. static bool
  513. i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  514.                     int target, int refclk, intel_clock_t *match_clock,
  515.                     intel_clock_t *best_clock)
  516. {
  517.         struct drm_device *dev = crtc->dev;
  518.         intel_clock_t clock;
  519.         int err = target;
  520.  
  521.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  522.                 /*
  523.                  * For LVDS just rely on its current settings for dual-channel.
  524.                  * We haven't figured out how to reliably set up different
  525.                  * single/dual channel state, if we even can.
  526.                  */
  527.                 if (intel_is_dual_link_lvds(dev))
  528.                         clock.p2 = limit->p2.p2_fast;
  529.                 else
  530.                         clock.p2 = limit->p2.p2_slow;
  531.         } else {
  532.                 if (target < limit->p2.dot_limit)
  533.                         clock.p2 = limit->p2.p2_slow;
  534.                 else
  535.                         clock.p2 = limit->p2.p2_fast;
  536.         }
  537.  
  538.         memset(best_clock, 0, sizeof(*best_clock));
  539.  
  540.         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  541.              clock.m1++) {
  542.                 for (clock.m2 = limit->m2.min;
  543.                      clock.m2 <= limit->m2.max; clock.m2++) {
  544.                         if (clock.m2 >= clock.m1)
  545.                                 break;
  546.                         for (clock.n = limit->n.min;
  547.                              clock.n <= limit->n.max; clock.n++) {
  548.                                 for (clock.p1 = limit->p1.min;
  549.                                         clock.p1 <= limit->p1.max; clock.p1++) {
  550.                                         int this_err;
  551.  
  552.                                         i9xx_clock(refclk, &clock);
  553.                                         if (!intel_PLL_is_valid(dev, limit,
  554.                                                                 &clock))
  555.                                                 continue;
  556.                                         if (match_clock &&
  557.                                             clock.p != match_clock->p)
  558.                                                 continue;
  559.  
  560.                                         this_err = abs(clock.dot - target);
  561.                                         if (this_err < err) {
  562.                                                 *best_clock = clock;
  563.                                                 err = this_err;
  564.                                         }
  565.                                 }
  566.                         }
  567.                 }
  568.         }
  569.  
  570.         return (err != target);
  571. }
  572.  
  573. static bool
  574. pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  575.                    int target, int refclk, intel_clock_t *match_clock,
  576.                    intel_clock_t *best_clock)
  577. {
  578.         struct drm_device *dev = crtc->dev;
  579.         intel_clock_t clock;
  580.         int err = target;
  581.  
  582.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  583.                 /*
  584.                  * For LVDS just rely on its current settings for dual-channel.
  585.                  * We haven't figured out how to reliably set up different
  586.                  * single/dual channel state, if we even can.
  587.                  */
  588.                 if (intel_is_dual_link_lvds(dev))
  589.                         clock.p2 = limit->p2.p2_fast;
  590.                 else
  591.                         clock.p2 = limit->p2.p2_slow;
  592.         } else {
  593.                 if (target < limit->p2.dot_limit)
  594.                         clock.p2 = limit->p2.p2_slow;
  595.                 else
  596.                         clock.p2 = limit->p2.p2_fast;
  597.         }
  598.  
  599.         memset(best_clock, 0, sizeof(*best_clock));
  600.  
  601.         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  602.              clock.m1++) {
  603.                 for (clock.m2 = limit->m2.min;
  604.                      clock.m2 <= limit->m2.max; clock.m2++) {
  605.                         for (clock.n = limit->n.min;
  606.                              clock.n <= limit->n.max; clock.n++) {
  607.                                 for (clock.p1 = limit->p1.min;
  608.                                         clock.p1 <= limit->p1.max; clock.p1++) {
  609.                                         int this_err;
  610.  
  611.                                         pineview_clock(refclk, &clock);
  612.                                         if (!intel_PLL_is_valid(dev, limit,
  613.                                                                 &clock))
  614.                                                 continue;
  615.                                         if (match_clock &&
  616.                                             clock.p != match_clock->p)
  617.                                                 continue;
  618.  
  619.                                         this_err = abs(clock.dot - target);
  620.                                         if (this_err < err) {
  621.                                                 *best_clock = clock;
  622.                                                 err = this_err;
  623.                                         }
  624.                                 }
  625.                         }
  626.                 }
  627.         }
  628.  
  629.         return (err != target);
  630. }
  631.  
  632. static bool
  633. g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  634.                         int target, int refclk, intel_clock_t *match_clock,
  635.                         intel_clock_t *best_clock)
  636. {
  637.         struct drm_device *dev = crtc->dev;
  638.         intel_clock_t clock;
  639.         int max_n;
  640.         bool found;
  641.         /* approximately equals target * 0.00585 */
  642.         int err_most = (target >> 8) + (target >> 9);
  643.         found = false;
  644.  
  645.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  646.                 if (intel_is_dual_link_lvds(dev))
  647.                         clock.p2 = limit->p2.p2_fast;
  648.                 else
  649.                         clock.p2 = limit->p2.p2_slow;
  650.         } else {
  651.                 if (target < limit->p2.dot_limit)
  652.                         clock.p2 = limit->p2.p2_slow;
  653.                 else
  654.                         clock.p2 = limit->p2.p2_fast;
  655.         }
  656.  
  657.         memset(best_clock, 0, sizeof(*best_clock));
  658.         max_n = limit->n.max;
  659.         /* based on hardware requirement, prefer smaller n to precision */
  660.         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  661.                 /* based on hardware requirement, prefere larger m1,m2 */
  662.                 for (clock.m1 = limit->m1.max;
  663.                      clock.m1 >= limit->m1.min; clock.m1--) {
  664.                         for (clock.m2 = limit->m2.max;
  665.                              clock.m2 >= limit->m2.min; clock.m2--) {
  666.                                 for (clock.p1 = limit->p1.max;
  667.                                      clock.p1 >= limit->p1.min; clock.p1--) {
  668.                                         int this_err;
  669.  
  670.                                         i9xx_clock(refclk, &clock);
  671.                                         if (!intel_PLL_is_valid(dev, limit,
  672.                                                                 &clock))
  673.                                                 continue;
  674.  
  675.                                         this_err = abs(clock.dot - target);
  676.                                         if (this_err < err_most) {
  677.                                                 *best_clock = clock;
  678.                                                 err_most = this_err;
  679.                                                 max_n = clock.n;
  680.                                                 found = true;
  681.                                         }
  682.                                 }
  683.                         }
  684.                 }
  685.         }
  686.         return found;
  687. }
  688.  
  689. static bool
  690. vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  691.                         int target, int refclk, intel_clock_t *match_clock,
  692.                         intel_clock_t *best_clock)
  693. {
  694.         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
  695.         u32 m, n, fastclk;
  696.         u32 updrate, minupdate, p;
  697.         unsigned long bestppm, ppm, absppm;
  698.         int dotclk, flag;
  699.  
  700.         flag = 0;
  701.         dotclk = target * 1000;
  702.         bestppm = 1000000;
  703.         ppm = absppm = 0;
  704.         fastclk = dotclk / (2*100);
  705.         updrate = 0;
  706.         minupdate = 19200;
  707.         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
  708.         bestm1 = bestm2 = bestp1 = bestp2 = 0;
  709.  
  710.         /* based on hardware requirement, prefer smaller n to precision */
  711.         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
  712.                 updrate = refclk / n;
  713.                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
  714.                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
  715.                                 if (p2 > 10)
  716.                                         p2 = p2 - 1;
  717.                                 p = p1 * p2;
  718.                                 /* based on hardware requirement, prefer bigger m1,m2 values */
  719.                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
  720.                                         m2 = (((2*(fastclk * p * n / m1 )) +
  721.                                                refclk) / (2*refclk));
  722.                                         m = m1 * m2;
  723.                                         vco = updrate * m;
  724.                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
  725.                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
  726.                                                 absppm = (ppm > 0) ? ppm : (-ppm);
  727.                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
  728.                                                         bestppm = 0;
  729.                                                         flag = 1;
  730.                                                 }
  731.                                                 if (absppm < bestppm - 10) {
  732.                                                         bestppm = absppm;
  733.                                                         flag = 1;
  734.                                                 }
  735.                                                 if (flag) {
  736.                                                         bestn = n;
  737.                                                         bestm1 = m1;
  738.                                                         bestm2 = m2;
  739.                                                         bestp1 = p1;
  740.                                                         bestp2 = p2;
  741.                                                         flag = 0;
  742.                                                 }
  743.                                         }
  744.                                 }
  745.                         }
  746.                 }
  747.         }
  748.         best_clock->n = bestn;
  749.         best_clock->m1 = bestm1;
  750.         best_clock->m2 = bestm2;
  751.         best_clock->p1 = bestp1;
  752.         best_clock->p2 = bestp2;
  753.  
  754.         return true;
  755. }
  756.  
  757. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  758.                                              enum pipe pipe)
  759. {
  760.         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  761.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  762.  
  763.         return intel_crtc->config.cpu_transcoder;
  764. }
  765.  
  766. static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
  767. {
  768.         struct drm_i915_private *dev_priv = dev->dev_private;
  769.         u32 frame, frame_reg = PIPEFRAME(pipe);
  770.  
  771.         frame = I915_READ(frame_reg);
  772.  
  773.         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
  774.                 DRM_DEBUG_KMS("vblank wait timed out\n");
  775. }
  776.  
  777. /**
  778.  * intel_wait_for_vblank - wait for vblank on a given pipe
  779.  * @dev: drm device
  780.  * @pipe: pipe to wait for
  781.  *
  782.  * Wait for vblank to occur on a given pipe.  Needed for various bits of
  783.  * mode setting code.
  784.  */
  785. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  786. {
  787.         struct drm_i915_private *dev_priv = dev->dev_private;
  788.         int pipestat_reg = PIPESTAT(pipe);
  789.  
  790.         if (INTEL_INFO(dev)->gen >= 5) {
  791.                 ironlake_wait_for_vblank(dev, pipe);
  792.                 return;
  793.         }
  794.  
  795.         /* Clear existing vblank status. Note this will clear any other
  796.          * sticky status fields as well.
  797.          *
  798.          * This races with i915_driver_irq_handler() with the result
  799.          * that either function could miss a vblank event.  Here it is not
  800.          * fatal, as we will either wait upon the next vblank interrupt or
  801.          * timeout.  Generally speaking intel_wait_for_vblank() is only
  802.          * called during modeset at which time the GPU should be idle and
  803.          * should *not* be performing page flips and thus not waiting on
  804.          * vblanks...
  805.          * Currently, the result of us stealing a vblank from the irq
  806.          * handler is that a single frame will be skipped during swapbuffers.
  807.          */
  808.         I915_WRITE(pipestat_reg,
  809.                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  810.  
  811.         /* Wait for vblank interrupt bit to set */
  812.         if (wait_for(I915_READ(pipestat_reg) &
  813.                      PIPE_VBLANK_INTERRUPT_STATUS,
  814.                      50))
  815.                 DRM_DEBUG_KMS("vblank wait timed out\n");
  816. }
  817.  
  818. /*
  819.  * intel_wait_for_pipe_off - wait for pipe to turn off
  820.  * @dev: drm device
  821.  * @pipe: pipe to wait for
  822.  *
  823.  * After disabling a pipe, we can't wait for vblank in the usual way,
  824.  * spinning on the vblank interrupt status bit, since we won't actually
  825.  * see an interrupt when the pipe is disabled.
  826.  *
  827.  * On Gen4 and above:
  828.  *   wait for the pipe register state bit to turn off
  829.  *
  830.  * Otherwise:
  831.  *   wait for the display line value to settle (it usually
  832.  *   ends up stopping at the start of the next frame).
  833.  *
  834.  */
  835. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  836. {
  837.         struct drm_i915_private *dev_priv = dev->dev_private;
  838.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  839.                                                                       pipe);
  840.  
  841.         if (INTEL_INFO(dev)->gen >= 4) {
  842.                 int reg = PIPECONF(cpu_transcoder);
  843.  
  844.                 /* Wait for the Pipe State to go off */
  845.                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  846.                              100))
  847.                         WARN(1, "pipe_off wait timed out\n");
  848.         } else {
  849.                 u32 last_line, line_mask;
  850.                 int reg = PIPEDSL(pipe);
  851.                 unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100);
  852.  
  853.                 if (IS_GEN2(dev))
  854.                         line_mask = DSL_LINEMASK_GEN2;
  855.                 else
  856.                         line_mask = DSL_LINEMASK_GEN3;
  857.  
  858.                 /* Wait for the display line to settle */
  859.                 do {
  860.                         last_line = I915_READ(reg) & line_mask;
  861.                         mdelay(5);
  862.                 } while (((I915_READ(reg) & line_mask) != last_line) &&
  863.                          time_after(timeout, GetTimerTicks()));
  864.                 if (time_after(GetTimerTicks(), timeout))
  865.                         WARN(1, "pipe_off wait timed out\n");
  866.         }
  867. }
  868.  
  869. /*
  870.  * ibx_digital_port_connected - is the specified port connected?
  871.  * @dev_priv: i915 private structure
  872.  * @port: the port to test
  873.  *
  874.  * Returns true if @port is connected, false otherwise.
  875.  */
  876. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  877.                                 struct intel_digital_port *port)
  878. {
  879.         u32 bit;
  880.  
  881.         if (HAS_PCH_IBX(dev_priv->dev)) {
  882.                 switch(port->port) {
  883.                 case PORT_B:
  884.                         bit = SDE_PORTB_HOTPLUG;
  885.                         break;
  886.                 case PORT_C:
  887.                         bit = SDE_PORTC_HOTPLUG;
  888.                         break;
  889.                 case PORT_D:
  890.                         bit = SDE_PORTD_HOTPLUG;
  891.                         break;
  892.                 default:
  893.                         return true;
  894.                 }
  895.         } else {
  896.                 switch(port->port) {
  897.                 case PORT_B:
  898.                         bit = SDE_PORTB_HOTPLUG_CPT;
  899.                         break;
  900.                 case PORT_C:
  901.                         bit = SDE_PORTC_HOTPLUG_CPT;
  902.                         break;
  903.                 case PORT_D:
  904.                         bit = SDE_PORTD_HOTPLUG_CPT;
  905.                         break;
  906.                 default:
  907.                         return true;
  908.                 }
  909.         }
  910.  
  911.         return I915_READ(SDEISR) & bit;
  912. }
  913.  
  914. static const char *state_string(bool enabled)
  915. {
  916.         return enabled ? "on" : "off";
  917. }
  918.  
  919. /* Only for pre-ILK configs */
  920. void assert_pll(struct drm_i915_private *dev_priv,
  921.                        enum pipe pipe, bool state)
  922. {
  923.         int reg;
  924.         u32 val;
  925.         bool cur_state;
  926.  
  927.         reg = DPLL(pipe);
  928.         val = I915_READ(reg);
  929.         cur_state = !!(val & DPLL_VCO_ENABLE);
  930.         WARN(cur_state != state,
  931.              "PLL state assertion failure (expected %s, current %s)\n",
  932.              state_string(state), state_string(cur_state));
  933. }
  934.  
  935. struct intel_shared_dpll *
  936. intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
  937. {
  938.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  939.  
  940.         if (crtc->config.shared_dpll < 0)
  941.                 return NULL;
  942.  
  943.         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
  944. }
  945.  
  946. /* For ILK+ */
  947. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  948.                                struct intel_shared_dpll *pll,
  949.                            bool state)
  950. {
  951.         bool cur_state;
  952.         struct intel_dpll_hw_state hw_state;
  953.  
  954.         if (HAS_PCH_LPT(dev_priv->dev)) {
  955.                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
  956.                 return;
  957.         }
  958.  
  959.         if (WARN (!pll,
  960.                   "asserting DPLL %s with no DPLL\n", state_string(state)))
  961.                 return;
  962.  
  963.         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
  964.         WARN(cur_state != state,
  965.              "%s assertion failure (expected %s, current %s)\n",
  966.              pll->name, state_string(state), state_string(cur_state));
  967. }
  968.  
  969. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  970.                           enum pipe pipe, bool state)
  971. {
  972.         int reg;
  973.         u32 val;
  974.         bool cur_state;
  975.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  976.                                                                       pipe);
  977.  
  978.         if (HAS_DDI(dev_priv->dev)) {
  979.                 /* DDI does not have a specific FDI_TX register */
  980.                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
  981.                 val = I915_READ(reg);
  982.                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
  983.         } else {
  984.         reg = FDI_TX_CTL(pipe);
  985.         val = I915_READ(reg);
  986.         cur_state = !!(val & FDI_TX_ENABLE);
  987.         }
  988.         WARN(cur_state != state,
  989.              "FDI TX state assertion failure (expected %s, current %s)\n",
  990.              state_string(state), state_string(cur_state));
  991. }
  992. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  993. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  994.  
  995. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  996.                           enum pipe pipe, bool state)
  997. {
  998.         int reg;
  999.         u32 val;
  1000.         bool cur_state;
  1001.  
  1002.         reg = FDI_RX_CTL(pipe);
  1003.         val = I915_READ(reg);
  1004.         cur_state = !!(val & FDI_RX_ENABLE);
  1005.         WARN(cur_state != state,
  1006.              "FDI RX state assertion failure (expected %s, current %s)\n",
  1007.              state_string(state), state_string(cur_state));
  1008. }
  1009. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  1010. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  1011.  
  1012. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  1013.                                       enum pipe pipe)
  1014. {
  1015.         int reg;
  1016.         u32 val;
  1017.  
  1018.         /* ILK FDI PLL is always enabled */
  1019.         if (dev_priv->info->gen == 5)
  1020.                 return;
  1021.  
  1022.         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  1023.         if (HAS_DDI(dev_priv->dev))
  1024.                 return;
  1025.  
  1026.         reg = FDI_TX_CTL(pipe);
  1027.         val = I915_READ(reg);
  1028.         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  1029. }
  1030.  
  1031. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  1032.                        enum pipe pipe, bool state)
  1033. {
  1034.         int reg;
  1035.         u32 val;
  1036.         bool cur_state;
  1037.  
  1038.         reg = FDI_RX_CTL(pipe);
  1039.         val = I915_READ(reg);
  1040.         cur_state = !!(val & FDI_RX_PLL_ENABLE);
  1041.         WARN(cur_state != state,
  1042.              "FDI RX PLL assertion failure (expected %s, current %s)\n",
  1043.              state_string(state), state_string(cur_state));
  1044. }
  1045.  
  1046. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  1047.                                   enum pipe pipe)
  1048. {
  1049.         int pp_reg, lvds_reg;
  1050.         u32 val;
  1051.         enum pipe panel_pipe = PIPE_A;
  1052.         bool locked = true;
  1053.  
  1054.         if (HAS_PCH_SPLIT(dev_priv->dev)) {
  1055.                 pp_reg = PCH_PP_CONTROL;
  1056.                 lvds_reg = PCH_LVDS;
  1057.         } else {
  1058.                 pp_reg = PP_CONTROL;
  1059.                 lvds_reg = LVDS;
  1060.         }
  1061.  
  1062.         val = I915_READ(pp_reg);
  1063.         if (!(val & PANEL_POWER_ON) ||
  1064.             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  1065.                 locked = false;
  1066.  
  1067.         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  1068.                 panel_pipe = PIPE_B;
  1069.  
  1070.         WARN(panel_pipe == pipe && locked,
  1071.              "panel assertion failure, pipe %c regs locked\n",
  1072.              pipe_name(pipe));
  1073. }
  1074.  
  1075. void assert_pipe(struct drm_i915_private *dev_priv,
  1076.                         enum pipe pipe, bool state)
  1077. {
  1078.         int reg;
  1079.         u32 val;
  1080.         bool cur_state;
  1081.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1082.                                                                       pipe);
  1083.  
  1084.         /* if we need the pipe A quirk it must be always on */
  1085.         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  1086.                 state = true;
  1087.  
  1088.         if (!intel_display_power_enabled(dev_priv->dev,
  1089.                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
  1090.                 cur_state = false;
  1091.         } else {
  1092.         reg = PIPECONF(cpu_transcoder);
  1093.         val = I915_READ(reg);
  1094.         cur_state = !!(val & PIPECONF_ENABLE);
  1095.         }
  1096.  
  1097.         WARN(cur_state != state,
  1098.              "pipe %c assertion failure (expected %s, current %s)\n",
  1099.              pipe_name(pipe), state_string(state), state_string(cur_state));
  1100. }
  1101.  
  1102. static void assert_plane(struct drm_i915_private *dev_priv,
  1103.                          enum plane plane, bool state)
  1104. {
  1105.         int reg;
  1106.         u32 val;
  1107.         bool cur_state;
  1108.  
  1109.         reg = DSPCNTR(plane);
  1110.         val = I915_READ(reg);
  1111.         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  1112.         WARN(cur_state != state,
  1113.              "plane %c assertion failure (expected %s, current %s)\n",
  1114.              plane_name(plane), state_string(state), state_string(cur_state));
  1115. }
  1116.  
  1117. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  1118. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  1119.  
  1120. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  1121.                                    enum pipe pipe)
  1122. {
  1123.         struct drm_device *dev = dev_priv->dev;
  1124.         int reg, i;
  1125.         u32 val;
  1126.         int cur_pipe;
  1127.  
  1128.         /* Primary planes are fixed to pipes on gen4+ */
  1129.         if (INTEL_INFO(dev)->gen >= 4) {
  1130.                 reg = DSPCNTR(pipe);
  1131.                 val = I915_READ(reg);
  1132.                 WARN((val & DISPLAY_PLANE_ENABLE),
  1133.                      "plane %c assertion failure, should be disabled but not\n",
  1134.                      plane_name(pipe));
  1135.                 return;
  1136.         }
  1137.  
  1138.         /* Need to check both planes against the pipe */
  1139.         for_each_pipe(i) {
  1140.                 reg = DSPCNTR(i);
  1141.                 val = I915_READ(reg);
  1142.                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1143.                         DISPPLANE_SEL_PIPE_SHIFT;
  1144.                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1145.                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1146.                      plane_name(i), pipe_name(pipe));
  1147.         }
  1148. }
  1149.  
  1150. static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
  1151.                                     enum pipe pipe)
  1152. {
  1153.         struct drm_device *dev = dev_priv->dev;
  1154.         int reg, i;
  1155.         u32 val;
  1156.  
  1157.         if (IS_VALLEYVIEW(dev)) {
  1158.         for (i = 0; i < dev_priv->num_plane; i++) {
  1159.                 reg = SPCNTR(pipe, i);
  1160.                 val = I915_READ(reg);
  1161.                 WARN((val & SP_ENABLE),
  1162.                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1163.                              sprite_name(pipe, i), pipe_name(pipe));
  1164.                 }
  1165.         } else if (INTEL_INFO(dev)->gen >= 7) {
  1166.                 reg = SPRCTL(pipe);
  1167.                 val = I915_READ(reg);
  1168.                 WARN((val & SPRITE_ENABLE),
  1169.                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1170.                      plane_name(pipe), pipe_name(pipe));
  1171.         } else if (INTEL_INFO(dev)->gen >= 5) {
  1172.                 reg = DVSCNTR(pipe);
  1173.                 val = I915_READ(reg);
  1174.                 WARN((val & DVS_ENABLE),
  1175.                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1176.                      plane_name(pipe), pipe_name(pipe));
  1177.         }
  1178. }
  1179.  
  1180. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  1181. {
  1182.         u32 val;
  1183.         bool enabled;
  1184.  
  1185.         if (HAS_PCH_LPT(dev_priv->dev)) {
  1186.                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
  1187.                 return;
  1188.         }
  1189.  
  1190.         val = I915_READ(PCH_DREF_CONTROL);
  1191.         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  1192.                             DREF_SUPERSPREAD_SOURCE_MASK));
  1193.         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  1194. }
  1195.  
  1196. static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
  1197.                                        enum pipe pipe)
  1198. {
  1199.         int reg;
  1200.         u32 val;
  1201.         bool enabled;
  1202.  
  1203.         reg = PCH_TRANSCONF(pipe);
  1204.         val = I915_READ(reg);
  1205.         enabled = !!(val & TRANS_ENABLE);
  1206.         WARN(enabled,
  1207.              "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1208.              pipe_name(pipe));
  1209. }
  1210.  
  1211. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1212.                             enum pipe pipe, u32 port_sel, u32 val)
  1213. {
  1214.         if ((val & DP_PORT_EN) == 0)
  1215.                 return false;
  1216.  
  1217.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1218.                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  1219.                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  1220.                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1221.                         return false;
  1222.         } else {
  1223.                 if ((val & DP_PIPE_MASK) != (pipe << 30))
  1224.                         return false;
  1225.         }
  1226.         return true;
  1227. }
  1228.  
  1229. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1230.                               enum pipe pipe, u32 val)
  1231. {
  1232.         if ((val & SDVO_ENABLE) == 0)
  1233.                 return false;
  1234.  
  1235.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1236.                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
  1237.                         return false;
  1238.         } else {
  1239.                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
  1240.                         return false;
  1241.         }
  1242.         return true;
  1243. }
  1244.  
  1245. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1246.                               enum pipe pipe, u32 val)
  1247. {
  1248.         if ((val & LVDS_PORT_EN) == 0)
  1249.                 return false;
  1250.  
  1251.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1252.                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1253.                         return false;
  1254.         } else {
  1255.                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1256.                         return false;
  1257.         }
  1258.         return true;
  1259. }
  1260.  
  1261. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1262.                               enum pipe pipe, u32 val)
  1263. {
  1264.         if ((val & ADPA_DAC_ENABLE) == 0)
  1265.                 return false;
  1266.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1267.                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1268.                         return false;
  1269.         } else {
  1270.                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1271.                         return false;
  1272.         }
  1273.         return true;
  1274. }
  1275.  
  1276. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1277.                                    enum pipe pipe, int reg, u32 port_sel)
  1278. {
  1279.         u32 val = I915_READ(reg);
  1280.         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1281.              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1282.              reg, pipe_name(pipe));
  1283.  
  1284.         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
  1285.              && (val & DP_PIPEB_SELECT),
  1286.              "IBX PCH dp port still using transcoder B\n");
  1287. }
  1288.  
  1289. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1290.                                      enum pipe pipe, int reg)
  1291. {
  1292.         u32 val = I915_READ(reg);
  1293.         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1294.              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1295.              reg, pipe_name(pipe));
  1296.  
  1297.         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
  1298.              && (val & SDVO_PIPE_B_SELECT),
  1299.              "IBX PCH hdmi port still using transcoder B\n");
  1300. }
  1301.  
  1302. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1303.                                       enum pipe pipe)
  1304. {
  1305.         int reg;
  1306.         u32 val;
  1307.  
  1308.         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1309.         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1310.         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1311.  
  1312.         reg = PCH_ADPA;
  1313.         val = I915_READ(reg);
  1314.         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1315.              "PCH VGA enabled on transcoder %c, should be disabled\n",
  1316.              pipe_name(pipe));
  1317.  
  1318.         reg = PCH_LVDS;
  1319.         val = I915_READ(reg);
  1320.         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1321.              "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1322.              pipe_name(pipe));
  1323.  
  1324.         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
  1325.         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
  1326.         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
  1327. }
  1328.  
  1329. static void vlv_enable_pll(struct intel_crtc *crtc)
  1330. {
  1331.         struct drm_device *dev = crtc->base.dev;
  1332.         struct drm_i915_private *dev_priv = dev->dev_private;
  1333.         int reg = DPLL(crtc->pipe);
  1334.         u32 dpll = crtc->config.dpll_hw_state.dpll;
  1335.  
  1336.         assert_pipe_disabled(dev_priv, crtc->pipe);
  1337.  
  1338.     /* No really, not for ILK+ */
  1339.         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
  1340.  
  1341.     /* PLL is protected by panel, make sure we can write it */
  1342.     if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  1343.                 assert_panel_unlocked(dev_priv, crtc->pipe);
  1344.  
  1345.         I915_WRITE(reg, dpll);
  1346.         POSTING_READ(reg);
  1347.         udelay(150);
  1348.  
  1349.         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  1350.                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
  1351.  
  1352.         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
  1353.         POSTING_READ(DPLL_MD(crtc->pipe));
  1354.  
  1355.         /* We do this three times for luck */
  1356.         I915_WRITE(reg, dpll);
  1357.         POSTING_READ(reg);
  1358.         udelay(150); /* wait for warmup */
  1359.         I915_WRITE(reg, dpll);
  1360.         POSTING_READ(reg);
  1361.         udelay(150); /* wait for warmup */
  1362.         I915_WRITE(reg, dpll);
  1363.         POSTING_READ(reg);
  1364.         udelay(150); /* wait for warmup */
  1365. }
  1366.  
  1367. static void i9xx_enable_pll(struct intel_crtc *crtc)
  1368. {
  1369.         struct drm_device *dev = crtc->base.dev;
  1370.         struct drm_i915_private *dev_priv = dev->dev_private;
  1371.         int reg = DPLL(crtc->pipe);
  1372.         u32 dpll = crtc->config.dpll_hw_state.dpll;
  1373.  
  1374.         assert_pipe_disabled(dev_priv, crtc->pipe);
  1375.  
  1376.         /* No really, not for ILK+ */
  1377.         BUG_ON(dev_priv->info->gen >= 5);
  1378.  
  1379.         /* PLL is protected by panel, make sure we can write it */
  1380.         if (IS_MOBILE(dev) && !IS_I830(dev))
  1381.                 assert_panel_unlocked(dev_priv, crtc->pipe);
  1382.  
  1383.         I915_WRITE(reg, dpll);
  1384.  
  1385.         /* Wait for the clocks to stabilize. */
  1386.         POSTING_READ(reg);
  1387.         udelay(150);
  1388.  
  1389.         if (INTEL_INFO(dev)->gen >= 4) {
  1390.                 I915_WRITE(DPLL_MD(crtc->pipe),
  1391.                            crtc->config.dpll_hw_state.dpll_md);
  1392.         } else {
  1393.                 /* The pixel multiplier can only be updated once the
  1394.                  * DPLL is enabled and the clocks are stable.
  1395.                  *
  1396.                  * So write it again.
  1397.                  */
  1398.                 I915_WRITE(reg, dpll);
  1399.         }
  1400.  
  1401.     /* We do this three times for luck */
  1402.         I915_WRITE(reg, dpll);
  1403.     POSTING_READ(reg);
  1404.     udelay(150); /* wait for warmup */
  1405.         I915_WRITE(reg, dpll);
  1406.     POSTING_READ(reg);
  1407.     udelay(150); /* wait for warmup */
  1408.         I915_WRITE(reg, dpll);
  1409.     POSTING_READ(reg);
  1410.     udelay(150); /* wait for warmup */
  1411. }
  1412.  
  1413. /**
  1414.  * i9xx_disable_pll - disable a PLL
  1415.  * @dev_priv: i915 private structure
  1416.  * @pipe: pipe PLL to disable
  1417.  *
  1418.  * Disable the PLL for @pipe, making sure the pipe is off first.
  1419.  *
  1420.  * Note!  This is for pre-ILK only.
  1421.  */
  1422. static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1423. {
  1424.         /* Don't disable pipe A or pipe A PLLs if needed */
  1425.         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1426.                 return;
  1427.  
  1428.         /* Make sure the pipe isn't still relying on us */
  1429.         assert_pipe_disabled(dev_priv, pipe);
  1430.  
  1431.         I915_WRITE(DPLL(pipe), 0);
  1432.         POSTING_READ(DPLL(pipe));
  1433. }
  1434.  
  1435. void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
  1436. {
  1437.         u32 port_mask;
  1438.  
  1439.         if (!port)
  1440.                 port_mask = DPLL_PORTB_READY_MASK;
  1441.         else
  1442.                 port_mask = DPLL_PORTC_READY_MASK;
  1443.  
  1444.         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
  1445.                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
  1446.                      'B' + port, I915_READ(DPLL(0)));
  1447. }
  1448.  
  1449. /**
  1450.  * ironlake_enable_shared_dpll - enable PCH PLL
  1451.  * @dev_priv: i915 private structure
  1452.  * @pipe: pipe PLL to enable
  1453.  *
  1454.  * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1455.  * drives the transcoder clock.
  1456.  */
  1457. static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
  1458. {
  1459.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1460.         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1461.  
  1462.         /* PCH PLLs only available on ILK, SNB and IVB */
  1463.         BUG_ON(dev_priv->info->gen < 5);
  1464.         if (WARN_ON(pll == NULL))
  1465.                 return;
  1466.  
  1467.         if (WARN_ON(pll->refcount == 0))
  1468.                 return;
  1469.  
  1470.         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
  1471.                       pll->name, pll->active, pll->on,
  1472.                       crtc->base.base.id);
  1473.  
  1474.         if (pll->active++) {
  1475.                 WARN_ON(!pll->on);
  1476.                 assert_shared_dpll_enabled(dev_priv, pll);
  1477.                 return;
  1478.         }
  1479.         WARN_ON(pll->on);
  1480.  
  1481.         DRM_DEBUG_KMS("enabling %s\n", pll->name);
  1482.         pll->enable(dev_priv, pll);
  1483.         pll->on = true;
  1484. }
  1485.  
  1486. static void intel_disable_shared_dpll(struct intel_crtc *crtc)
  1487. {
  1488.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1489.         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1490.  
  1491.         /* PCH only available on ILK+ */
  1492.         BUG_ON(dev_priv->info->gen < 5);
  1493.         if (WARN_ON(pll == NULL))
  1494.                return;
  1495.  
  1496.         if (WARN_ON(pll->refcount == 0))
  1497.                 return;
  1498.  
  1499.         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
  1500.                       pll->name, pll->active, pll->on,
  1501.                       crtc->base.base.id);
  1502.  
  1503.         if (WARN_ON(pll->active == 0)) {
  1504.                 assert_shared_dpll_disabled(dev_priv, pll);
  1505.                 return;
  1506.         }
  1507.  
  1508.         assert_shared_dpll_enabled(dev_priv, pll);
  1509.         WARN_ON(!pll->on);
  1510.         if (--pll->active)
  1511.                 return;
  1512.  
  1513.         DRM_DEBUG_KMS("disabling %s\n", pll->name);
  1514.         pll->disable(dev_priv, pll);
  1515.         pll->on = false;
  1516. }
  1517.  
  1518. static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1519.                                     enum pipe pipe)
  1520. {
  1521.         struct drm_device *dev = dev_priv->dev;
  1522.         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1523.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1524.         uint32_t reg, val, pipeconf_val;
  1525.  
  1526.         /* PCH only available on ILK+ */
  1527.         BUG_ON(dev_priv->info->gen < 5);
  1528.  
  1529.         /* Make sure PCH DPLL is enabled */
  1530.         assert_shared_dpll_enabled(dev_priv,
  1531.                                    intel_crtc_to_shared_dpll(intel_crtc));
  1532.  
  1533.         /* FDI must be feeding us bits for PCH ports */
  1534.         assert_fdi_tx_enabled(dev_priv, pipe);
  1535.         assert_fdi_rx_enabled(dev_priv, pipe);
  1536.  
  1537.         if (HAS_PCH_CPT(dev)) {
  1538.                 /* Workaround: Set the timing override bit before enabling the
  1539.                  * pch transcoder. */
  1540.                 reg = TRANS_CHICKEN2(pipe);
  1541.                 val = I915_READ(reg);
  1542.                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1543.                 I915_WRITE(reg, val);
  1544.         }
  1545.  
  1546.         reg = PCH_TRANSCONF(pipe);
  1547.         val = I915_READ(reg);
  1548.         pipeconf_val = I915_READ(PIPECONF(pipe));
  1549.  
  1550.         if (HAS_PCH_IBX(dev_priv->dev)) {
  1551.                 /*
  1552.                  * make the BPC in transcoder be consistent with
  1553.                  * that in pipeconf reg.
  1554.                  */
  1555.                 val &= ~PIPECONF_BPC_MASK;
  1556.                 val |= pipeconf_val & PIPECONF_BPC_MASK;
  1557.         }
  1558.  
  1559.         val &= ~TRANS_INTERLACE_MASK;
  1560.         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1561.                 if (HAS_PCH_IBX(dev_priv->dev) &&
  1562.                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
  1563.                         val |= TRANS_LEGACY_INTERLACED_ILK;
  1564.                 else
  1565.                         val |= TRANS_INTERLACED;
  1566.         else
  1567.                 val |= TRANS_PROGRESSIVE;
  1568.  
  1569.         I915_WRITE(reg, val | TRANS_ENABLE);
  1570.         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1571.                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
  1572. }
  1573.  
  1574. static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1575.                                       enum transcoder cpu_transcoder)
  1576. {
  1577.         u32 val, pipeconf_val;
  1578.  
  1579.         /* PCH only available on ILK+ */
  1580.         BUG_ON(dev_priv->info->gen < 5);
  1581.  
  1582.         /* FDI must be feeding us bits for PCH ports */
  1583.         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
  1584.         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
  1585.  
  1586.         /* Workaround: set timing override bit. */
  1587.         val = I915_READ(_TRANSA_CHICKEN2);
  1588.         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1589.         I915_WRITE(_TRANSA_CHICKEN2, val);
  1590.  
  1591.         val = TRANS_ENABLE;
  1592.         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
  1593.  
  1594.         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
  1595.             PIPECONF_INTERLACED_ILK)
  1596.                 val |= TRANS_INTERLACED;
  1597.         else
  1598.                 val |= TRANS_PROGRESSIVE;
  1599.  
  1600.         I915_WRITE(LPT_TRANSCONF, val);
  1601.         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
  1602.                 DRM_ERROR("Failed to enable PCH transcoder\n");
  1603. }
  1604.  
  1605. static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
  1606.                                      enum pipe pipe)
  1607. {
  1608.         struct drm_device *dev = dev_priv->dev;
  1609.         uint32_t reg, val;
  1610.  
  1611.         /* FDI relies on the transcoder */
  1612.         assert_fdi_tx_disabled(dev_priv, pipe);
  1613.         assert_fdi_rx_disabled(dev_priv, pipe);
  1614.  
  1615.         /* Ports must be off as well */
  1616.         assert_pch_ports_disabled(dev_priv, pipe);
  1617.  
  1618.         reg = PCH_TRANSCONF(pipe);
  1619.         val = I915_READ(reg);
  1620.         val &= ~TRANS_ENABLE;
  1621.         I915_WRITE(reg, val);
  1622.         /* wait for PCH transcoder off, transcoder state */
  1623.         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1624.                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
  1625.  
  1626.         if (!HAS_PCH_IBX(dev)) {
  1627.                 /* Workaround: Clear the timing override chicken bit again. */
  1628.                 reg = TRANS_CHICKEN2(pipe);
  1629.                 val = I915_READ(reg);
  1630.                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1631.                 I915_WRITE(reg, val);
  1632.         }
  1633. }
  1634.  
  1635. static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
  1636. {
  1637.         u32 val;
  1638.  
  1639.         val = I915_READ(LPT_TRANSCONF);
  1640.         val &= ~TRANS_ENABLE;
  1641.         I915_WRITE(LPT_TRANSCONF, val);
  1642.         /* wait for PCH transcoder off, transcoder state */
  1643.         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
  1644.                 DRM_ERROR("Failed to disable PCH transcoder\n");
  1645.  
  1646.         /* Workaround: clear timing override bit. */
  1647.         val = I915_READ(_TRANSA_CHICKEN2);
  1648.         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1649.         I915_WRITE(_TRANSA_CHICKEN2, val);
  1650. }
  1651.  
  1652. /**
  1653.  * intel_enable_pipe - enable a pipe, asserting requirements
  1654.  * @dev_priv: i915 private structure
  1655.  * @pipe: pipe to enable
  1656.  * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1657.  *
  1658.  * Enable @pipe, making sure that various hardware specific requirements
  1659.  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1660.  *
  1661.  * @pipe should be %PIPE_A or %PIPE_B.
  1662.  *
  1663.  * Will wait until the pipe is actually running (i.e. first vblank) before
  1664.  * returning.
  1665.  */
  1666. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1667.                               bool pch_port)
  1668. {
  1669.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1670.                                                                       pipe);
  1671.         enum pipe pch_transcoder;
  1672.         int reg;
  1673.         u32 val;
  1674.  
  1675.         assert_planes_disabled(dev_priv, pipe);
  1676.         assert_sprites_disabled(dev_priv, pipe);
  1677.  
  1678.         if (HAS_PCH_LPT(dev_priv->dev))
  1679.                 pch_transcoder = TRANSCODER_A;
  1680.         else
  1681.                 pch_transcoder = pipe;
  1682.  
  1683.         /*
  1684.          * A pipe without a PLL won't actually be able to drive bits from
  1685.          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
  1686.          * need the check.
  1687.          */
  1688.         if (!HAS_PCH_SPLIT(dev_priv->dev))
  1689.                 assert_pll_enabled(dev_priv, pipe);
  1690.         else {
  1691.                 if (pch_port) {
  1692.                         /* if driving the PCH, we need FDI enabled */
  1693.                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
  1694.                         assert_fdi_tx_pll_enabled(dev_priv,
  1695.                                                   (enum pipe) cpu_transcoder);
  1696.                 }
  1697.                 /* FIXME: assert CPU port conditions for SNB+ */
  1698.         }
  1699.  
  1700.         reg = PIPECONF(cpu_transcoder);
  1701.         val = I915_READ(reg);
  1702.         if (val & PIPECONF_ENABLE)
  1703.                 return;
  1704.  
  1705.         I915_WRITE(reg, val | PIPECONF_ENABLE);
  1706.         intel_wait_for_vblank(dev_priv->dev, pipe);
  1707. }
  1708.  
  1709. /**
  1710.  * intel_disable_pipe - disable a pipe, asserting requirements
  1711.  * @dev_priv: i915 private structure
  1712.  * @pipe: pipe to disable
  1713.  *
  1714.  * Disable @pipe, making sure that various hardware specific requirements
  1715.  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1716.  *
  1717.  * @pipe should be %PIPE_A or %PIPE_B.
  1718.  *
  1719.  * Will wait until the pipe has shut down before returning.
  1720.  */
  1721. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1722.                                enum pipe pipe)
  1723. {
  1724.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1725.                                                                       pipe);
  1726.         int reg;
  1727.         u32 val;
  1728.  
  1729.     /*
  1730.          * Make sure planes won't keep trying to pump pixels to us,
  1731.          * or we might hang the display.
  1732.          */
  1733.         assert_planes_disabled(dev_priv, pipe);
  1734.         assert_sprites_disabled(dev_priv, pipe);
  1735.  
  1736.         /* Don't disable pipe A or pipe A PLLs if needed */
  1737.         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1738.                 return;
  1739.  
  1740.         reg = PIPECONF(cpu_transcoder);
  1741.         val = I915_READ(reg);
  1742.         if ((val & PIPECONF_ENABLE) == 0)
  1743.                 return;
  1744.  
  1745.         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1746.         intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1747. }
  1748.  
  1749. /*
  1750.  * Plane regs are double buffered, going from enabled->disabled needs a
  1751.  * trigger in order to latch.  The display address reg provides this.
  1752.  */
  1753. void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1754.                                       enum plane plane)
  1755. {
  1756.         if (dev_priv->info->gen >= 4)
  1757.                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
  1758.         else
  1759.         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
  1760. }
  1761.  
  1762. /**
  1763.  * intel_enable_plane - enable a display plane on a given pipe
  1764.  * @dev_priv: i915 private structure
  1765.  * @plane: plane to enable
  1766.  * @pipe: pipe being fed
  1767.  *
  1768.  * Enable @plane on @pipe, making sure that @pipe is running first.
  1769.  */
  1770. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1771.                                enum plane plane, enum pipe pipe)
  1772. {
  1773.         int reg;
  1774.         u32 val;
  1775.  
  1776.         /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1777.         assert_pipe_enabled(dev_priv, pipe);
  1778.  
  1779.         reg = DSPCNTR(plane);
  1780.         val = I915_READ(reg);
  1781.         if (val & DISPLAY_PLANE_ENABLE)
  1782.                 return;
  1783.  
  1784.         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1785.         intel_flush_display_plane(dev_priv, plane);
  1786.         intel_wait_for_vblank(dev_priv->dev, pipe);
  1787. }
  1788.  
  1789. /**
  1790.  * intel_disable_plane - disable a display plane
  1791.  * @dev_priv: i915 private structure
  1792.  * @plane: plane to disable
  1793.  * @pipe: pipe consuming the data
  1794.  *
  1795.  * Disable @plane; should be an independent operation.
  1796.  */
  1797. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1798.                                 enum plane plane, enum pipe pipe)
  1799. {
  1800.         int reg;
  1801.         u32 val;
  1802.  
  1803.         reg = DSPCNTR(plane);
  1804.         val = I915_READ(reg);
  1805.         if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1806.                 return;
  1807.  
  1808.         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1809.         intel_flush_display_plane(dev_priv, plane);
  1810.     intel_wait_for_vblank(dev_priv->dev, pipe);
  1811. }
  1812.  
  1813. static bool need_vtd_wa(struct drm_device *dev)
  1814. {
  1815. #ifdef CONFIG_INTEL_IOMMU
  1816.         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
  1817.                 return true;
  1818. #endif
  1819.         return false;
  1820. }
  1821.  
  1822. int
  1823. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1824.                            struct drm_i915_gem_object *obj,
  1825.                            struct intel_ring_buffer *pipelined)
  1826. {
  1827.         struct drm_i915_private *dev_priv = dev->dev_private;
  1828.         u32 alignment;
  1829.         int ret;
  1830.  
  1831.         switch (obj->tiling_mode) {
  1832.         case I915_TILING_NONE:
  1833.                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1834.                         alignment = 128 * 1024;
  1835.                 else if (INTEL_INFO(dev)->gen >= 4)
  1836.                         alignment = 4 * 1024;
  1837.                 else
  1838.                         alignment = 64 * 1024;
  1839.                 break;
  1840.         case I915_TILING_X:
  1841.                 /* pin() will align the object as required by fence */
  1842.                 alignment = 0;
  1843.                 break;
  1844.         case I915_TILING_Y:
  1845.                 /* Despite that we check this in framebuffer_init userspace can
  1846.                  * screw us over and change the tiling after the fact. Only
  1847.                  * pinned buffers can't change their tiling. */
  1848.                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
  1849.                 return -EINVAL;
  1850.         default:
  1851.                 BUG();
  1852.         }
  1853.  
  1854.         /* Note that the w/a also requires 64 PTE of padding following the
  1855.          * bo. We currently fill all unused PTE with the shadow page and so
  1856.          * we should always have valid PTE following the scanout preventing
  1857.          * the VT-d warning.
  1858.          */
  1859.         if (need_vtd_wa(dev) && alignment < 256 * 1024)
  1860.                 alignment = 256 * 1024;
  1861.  
  1862.         dev_priv->mm.interruptible = false;
  1863.         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1864.         if (ret)
  1865.                 goto err_interruptible;
  1866.  
  1867.         /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1868.          * fence, whereas 965+ only requires a fence if using
  1869.          * framebuffer compression.  For simplicity, we always install
  1870.          * a fence as the cost is not that onerous.
  1871.          */
  1872.         ret = i915_gem_object_get_fence(obj);
  1873.         if (ret)
  1874.                 goto err_unpin;
  1875.  
  1876.         i915_gem_object_pin_fence(obj);
  1877.  
  1878.         dev_priv->mm.interruptible = true;
  1879.         return 0;
  1880.  
  1881. err_unpin:
  1882.         i915_gem_object_unpin_from_display_plane(obj);
  1883. err_interruptible:
  1884.         dev_priv->mm.interruptible = true;
  1885.         return ret;
  1886. }
  1887.  
  1888. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
  1889. {
  1890. //      i915_gem_object_unpin_fence(obj);
  1891. //      i915_gem_object_unpin(obj);
  1892. }
  1893.  
  1894. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  1895.  * is assumed to be a power-of-two. */
  1896. unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  1897.                                              unsigned int tiling_mode,
  1898.                                              unsigned int cpp,
  1899.                                                         unsigned int pitch)
  1900. {
  1901.         if (tiling_mode != I915_TILING_NONE) {
  1902.                 unsigned int tile_rows, tiles;
  1903.  
  1904.         tile_rows = *y / 8;
  1905.         *y %= 8;
  1906.  
  1907.                 tiles = *x / (512/cpp);
  1908.                 *x %= 512/cpp;
  1909.  
  1910.         return tile_rows * pitch * 8 + tiles * 4096;
  1911.         } else {
  1912.                 unsigned int offset;
  1913.  
  1914.                 offset = *y * pitch + *x * cpp;
  1915.                 *y = 0;
  1916.                 *x = (offset & 4095) / cpp;
  1917.                 return offset & -4096;
  1918.         }
  1919. }
  1920.  
  1921. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1922.                  int x, int y)
  1923. {
  1924.     struct drm_device *dev = crtc->dev;
  1925.     struct drm_i915_private *dev_priv = dev->dev_private;
  1926.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1927.     struct intel_framebuffer *intel_fb;
  1928.     struct drm_i915_gem_object *obj;
  1929.     int plane = intel_crtc->plane;
  1930.         unsigned long linear_offset;
  1931.     u32 dspcntr;
  1932.     u32 reg;
  1933.  
  1934.     switch (plane) {
  1935.     case 0:
  1936.     case 1:
  1937.         break;
  1938.     default:
  1939.                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1940.         return -EINVAL;
  1941.     }
  1942.  
  1943.     intel_fb = to_intel_framebuffer(fb);
  1944.     obj = intel_fb->obj;
  1945.  
  1946.     reg = DSPCNTR(plane);
  1947.     dspcntr = I915_READ(reg);
  1948.     /* Mask out pixel format bits in case we change it */
  1949.     dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1950.         switch (fb->pixel_format) {
  1951.         case DRM_FORMAT_C8:
  1952.         dspcntr |= DISPPLANE_8BPP;
  1953.         break;
  1954.         case DRM_FORMAT_XRGB1555:
  1955.         case DRM_FORMAT_ARGB1555:
  1956.                 dspcntr |= DISPPLANE_BGRX555;
  1957.                 break;
  1958.         case DRM_FORMAT_RGB565:
  1959.                 dspcntr |= DISPPLANE_BGRX565;
  1960.                 break;
  1961.         case DRM_FORMAT_XRGB8888:
  1962.         case DRM_FORMAT_ARGB8888:
  1963.                 dspcntr |= DISPPLANE_BGRX888;
  1964.                 break;
  1965.         case DRM_FORMAT_XBGR8888:
  1966.         case DRM_FORMAT_ABGR8888:
  1967.                 dspcntr |= DISPPLANE_RGBX888;
  1968.                 break;
  1969.         case DRM_FORMAT_XRGB2101010:
  1970.         case DRM_FORMAT_ARGB2101010:
  1971.                 dspcntr |= DISPPLANE_BGRX101010;
  1972.         break;
  1973.         case DRM_FORMAT_XBGR2101010:
  1974.         case DRM_FORMAT_ABGR2101010:
  1975.                 dspcntr |= DISPPLANE_RGBX101010;
  1976.         break;
  1977.     default:
  1978.                 BUG();
  1979.     }
  1980.  
  1981.     if (INTEL_INFO(dev)->gen >= 4) {
  1982.         if (obj->tiling_mode != I915_TILING_NONE)
  1983.             dspcntr |= DISPPLANE_TILED;
  1984.         else
  1985.             dspcntr &= ~DISPPLANE_TILED;
  1986.     }
  1987.  
  1988.         if (IS_G4X(dev))
  1989.                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1990.  
  1991.     I915_WRITE(reg, dspcntr);
  1992.  
  1993.         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1994.  
  1995.         if (INTEL_INFO(dev)->gen >= 4) {
  1996.                 intel_crtc->dspaddr_offset =
  1997.                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1998.                                                            fb->bits_per_pixel / 8,
  1999.                                                            fb->pitches[0]);
  2000.                 linear_offset -= intel_crtc->dspaddr_offset;
  2001.         } else {
  2002.                 intel_crtc->dspaddr_offset = linear_offset;
  2003.         }
  2004.  
  2005.         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  2006.                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  2007.                       fb->pitches[0]);
  2008.         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  2009.     if (INTEL_INFO(dev)->gen >= 4) {
  2010.                 I915_MODIFY_DISPBASE(DSPSURF(plane),
  2011.                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  2012.         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  2013.                 I915_WRITE(DSPLINOFF(plane), linear_offset);
  2014.     } else
  2015.                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
  2016.     POSTING_READ(reg);
  2017.  
  2018.     return 0;
  2019. }
  2020.  
  2021. static int ironlake_update_plane(struct drm_crtc *crtc,
  2022.                  struct drm_framebuffer *fb, int x, int y)
  2023. {
  2024.     struct drm_device *dev = crtc->dev;
  2025.     struct drm_i915_private *dev_priv = dev->dev_private;
  2026.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2027.     struct intel_framebuffer *intel_fb;
  2028.     struct drm_i915_gem_object *obj;
  2029.     int plane = intel_crtc->plane;
  2030.         unsigned long linear_offset;
  2031.     u32 dspcntr;
  2032.     u32 reg;
  2033.  
  2034.     switch (plane) {
  2035.     case 0:
  2036.     case 1:
  2037.         case 2:
  2038.         break;
  2039.     default:
  2040.                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  2041.         return -EINVAL;
  2042.     }
  2043.  
  2044.     intel_fb = to_intel_framebuffer(fb);
  2045.     obj = intel_fb->obj;
  2046.  
  2047.     reg = DSPCNTR(plane);
  2048.     dspcntr = I915_READ(reg);
  2049.     /* Mask out pixel format bits in case we change it */
  2050.     dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  2051.         switch (fb->pixel_format) {
  2052.         case DRM_FORMAT_C8:
  2053.         dspcntr |= DISPPLANE_8BPP;
  2054.         break;
  2055.         case DRM_FORMAT_RGB565:
  2056.                 dspcntr |= DISPPLANE_BGRX565;
  2057.         break;
  2058.         case DRM_FORMAT_XRGB8888:
  2059.         case DRM_FORMAT_ARGB8888:
  2060.                 dspcntr |= DISPPLANE_BGRX888;
  2061.                 break;
  2062.         case DRM_FORMAT_XBGR8888:
  2063.         case DRM_FORMAT_ABGR8888:
  2064.                 dspcntr |= DISPPLANE_RGBX888;
  2065.                 break;
  2066.         case DRM_FORMAT_XRGB2101010:
  2067.         case DRM_FORMAT_ARGB2101010:
  2068.                 dspcntr |= DISPPLANE_BGRX101010;
  2069.                 break;
  2070.         case DRM_FORMAT_XBGR2101010:
  2071.         case DRM_FORMAT_ABGR2101010:
  2072.                 dspcntr |= DISPPLANE_RGBX101010;
  2073.         break;
  2074.     default:
  2075.                 BUG();
  2076.     }
  2077.  
  2078.         if (obj->tiling_mode != I915_TILING_NONE)
  2079.                 dspcntr |= DISPPLANE_TILED;
  2080.         else
  2081.         dspcntr &= ~DISPPLANE_TILED;
  2082.  
  2083.         if (IS_HASWELL(dev))
  2084.                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
  2085.         else
  2086.     dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  2087.  
  2088.     I915_WRITE(reg, dspcntr);
  2089.  
  2090.         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  2091.         intel_crtc->dspaddr_offset =
  2092.                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  2093.                                                    fb->bits_per_pixel / 8,
  2094.                                                    fb->pitches[0]);
  2095.         linear_offset -= intel_crtc->dspaddr_offset;
  2096.  
  2097.         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  2098.                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  2099.                       fb->pitches[0]);
  2100.         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  2101.         I915_MODIFY_DISPBASE(DSPSURF(plane),
  2102.                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  2103.         if (IS_HASWELL(dev)) {
  2104.                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
  2105.         } else {
  2106.         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  2107.         I915_WRITE(DSPLINOFF(plane), linear_offset);
  2108.         }
  2109.         POSTING_READ(reg);
  2110.  
  2111.     return 0;
  2112. }
  2113.  
  2114. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  2115. static int
  2116. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  2117.                            int x, int y, enum mode_set_atomic state)
  2118. {
  2119.         struct drm_device *dev = crtc->dev;
  2120.         struct drm_i915_private *dev_priv = dev->dev_private;
  2121.  
  2122.         if (dev_priv->display.disable_fbc)
  2123.                 dev_priv->display.disable_fbc(dev);
  2124.         intel_increase_pllclock(crtc);
  2125.  
  2126.         return dev_priv->display.update_plane(crtc, fb, x, y);
  2127. }
  2128.  
  2129. #if 0
  2130. void intel_display_handle_reset(struct drm_device *dev)
  2131. {
  2132.         struct drm_i915_private *dev_priv = dev->dev_private;
  2133.         struct drm_crtc *crtc;
  2134.  
  2135.         /*
  2136.          * Flips in the rings have been nuked by the reset,
  2137.          * so complete all pending flips so that user space
  2138.          * will get its events and not get stuck.
  2139.          *
  2140.          * Also update the base address of all primary
  2141.          * planes to the the last fb to make sure we're
  2142.          * showing the correct fb after a reset.
  2143.          *
  2144.          * Need to make two loops over the crtcs so that we
  2145.          * don't try to grab a crtc mutex before the
  2146.          * pending_flip_queue really got woken up.
  2147.          */
  2148.  
  2149.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2150.                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2151.                 enum plane plane = intel_crtc->plane;
  2152.  
  2153.                 intel_prepare_page_flip(dev, plane);
  2154.                 intel_finish_page_flip_plane(dev, plane);
  2155.         }
  2156.  
  2157.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2158.                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2159.  
  2160.                 mutex_lock(&crtc->mutex);
  2161.                 if (intel_crtc->active)
  2162.                         dev_priv->display.update_plane(crtc, crtc->fb,
  2163.                                                        crtc->x, crtc->y);
  2164.                 mutex_unlock(&crtc->mutex);
  2165.         }
  2166. }
  2167.  
  2168. static int
  2169. intel_finish_fb(struct drm_framebuffer *old_fb)
  2170. {
  2171.         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  2172.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  2173.         bool was_interruptible = dev_priv->mm.interruptible;
  2174.         int ret;
  2175.  
  2176.         /* Big Hammer, we also need to ensure that any pending
  2177.          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  2178.          * current scanout is retired before unpinning the old
  2179.          * framebuffer.
  2180.          *
  2181.          * This should only fail upon a hung GPU, in which case we
  2182.          * can safely continue.
  2183.          */
  2184.         dev_priv->mm.interruptible = false;
  2185.         ret = i915_gem_object_finish_gpu(obj);
  2186.         dev_priv->mm.interruptible = was_interruptible;
  2187.  
  2188.         return ret;
  2189. }
  2190.  
  2191. static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
  2192. {
  2193.         struct drm_device *dev = crtc->dev;
  2194.         struct drm_i915_master_private *master_priv;
  2195.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2196.  
  2197.         if (!dev->primary->master)
  2198.                 return;
  2199.  
  2200.         master_priv = dev->primary->master->driver_priv;
  2201.         if (!master_priv->sarea_priv)
  2202.                 return;
  2203.  
  2204.         switch (intel_crtc->pipe) {
  2205.         case 0:
  2206.                 master_priv->sarea_priv->pipeA_x = x;
  2207.                 master_priv->sarea_priv->pipeA_y = y;
  2208.                 break;
  2209.         case 1:
  2210.                 master_priv->sarea_priv->pipeB_x = x;
  2211.                 master_priv->sarea_priv->pipeB_y = y;
  2212.                 break;
  2213.         default:
  2214.                 break;
  2215.         }
  2216. }
  2217. #endif
  2218.  
  2219. static int
  2220. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  2221.                     struct drm_framebuffer *fb)
  2222. {
  2223.         struct drm_device *dev = crtc->dev;
  2224.         struct drm_i915_private *dev_priv = dev->dev_private;
  2225.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2226.         struct drm_framebuffer *old_fb;
  2227.         int ret;
  2228.  
  2229.         /* no fb bound */
  2230.         if (!fb) {
  2231.                 DRM_ERROR("No FB bound\n");
  2232.                 return 0;
  2233.         }
  2234.  
  2235.         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
  2236.                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
  2237.                           plane_name(intel_crtc->plane),
  2238.                                 INTEL_INFO(dev)->num_pipes);
  2239.                 return -EINVAL;
  2240.         }
  2241.  
  2242.         mutex_lock(&dev->struct_mutex);
  2243.     ret = intel_pin_and_fence_fb_obj(dev,
  2244.                     to_intel_framebuffer(fb)->obj,
  2245.                     NULL);
  2246.     if (ret != 0) {
  2247.        mutex_unlock(&dev->struct_mutex);
  2248.        DRM_ERROR("pin & fence failed\n");
  2249.        return ret;
  2250.     }
  2251.  
  2252.         /* Update pipe size and adjust fitter if needed */
  2253.         if (i915_fastboot) {
  2254.                 I915_WRITE(PIPESRC(intel_crtc->pipe),
  2255.                            ((crtc->mode.hdisplay - 1) << 16) |
  2256.                            (crtc->mode.vdisplay - 1));
  2257.                 if (!intel_crtc->config.pch_pfit.enabled &&
  2258.                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
  2259.                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2260.                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
  2261.                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
  2262.                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
  2263.                 }
  2264.         }
  2265.  
  2266.         ret = dev_priv->display.update_plane(crtc, fb, x, y);
  2267.         if (ret) {
  2268.                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
  2269.                 mutex_unlock(&dev->struct_mutex);
  2270.                 DRM_ERROR("failed to update base address\n");
  2271.         return ret;
  2272.         }
  2273.  
  2274.         old_fb = crtc->fb;
  2275.         crtc->fb = fb;
  2276.         crtc->x = x;
  2277.         crtc->y = y;
  2278.  
  2279.         if (old_fb) {
  2280.                 if (intel_crtc->active && old_fb != fb)
  2281.                 intel_wait_for_vblank(dev, intel_crtc->pipe);
  2282.                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
  2283.         }
  2284.  
  2285.         intel_update_fbc(dev);
  2286.         intel_edp_psr_update(dev);
  2287.         mutex_unlock(&dev->struct_mutex);
  2288.  
  2289.     return 0;
  2290. }
  2291.  
  2292. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  2293. {
  2294.         struct drm_device *dev = crtc->dev;
  2295.         struct drm_i915_private *dev_priv = dev->dev_private;
  2296.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2297.         int pipe = intel_crtc->pipe;
  2298.         u32 reg, temp;
  2299.  
  2300.         /* enable normal train */
  2301.         reg = FDI_TX_CTL(pipe);
  2302.         temp = I915_READ(reg);
  2303.         if (IS_IVYBRIDGE(dev)) {
  2304.                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2305.                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2306.         } else {
  2307.                 temp &= ~FDI_LINK_TRAIN_NONE;
  2308.                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2309.         }
  2310.         I915_WRITE(reg, temp);
  2311.  
  2312.         reg = FDI_RX_CTL(pipe);
  2313.         temp = I915_READ(reg);
  2314.         if (HAS_PCH_CPT(dev)) {
  2315.                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2316.                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2317.         } else {
  2318.                 temp &= ~FDI_LINK_TRAIN_NONE;
  2319.                 temp |= FDI_LINK_TRAIN_NONE;
  2320.         }
  2321.         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2322.  
  2323.         /* wait one idle pattern time */
  2324.         POSTING_READ(reg);
  2325.         udelay(1000);
  2326.  
  2327.         /* IVB wants error correction enabled */
  2328.         if (IS_IVYBRIDGE(dev))
  2329.                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2330.                            FDI_FE_ERRC_ENABLE);
  2331. }
  2332.  
  2333. static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
  2334. {
  2335.         return crtc->base.enabled && crtc->active &&
  2336.                 crtc->config.has_pch_encoder;
  2337. }
  2338.  
  2339. static void ivb_modeset_global_resources(struct drm_device *dev)
  2340. {
  2341.         struct drm_i915_private *dev_priv = dev->dev_private;
  2342.         struct intel_crtc *pipe_B_crtc =
  2343.                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  2344.         struct intel_crtc *pipe_C_crtc =
  2345.                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
  2346.         uint32_t temp;
  2347.  
  2348.         /*
  2349.          * When everything is off disable fdi C so that we could enable fdi B
  2350.          * with all lanes. Note that we don't care about enabled pipes without
  2351.          * an enabled pch encoder.
  2352.          */
  2353.         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
  2354.             !pipe_has_enabled_pch(pipe_C_crtc)) {
  2355.                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  2356.                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  2357.  
  2358.                 temp = I915_READ(SOUTH_CHICKEN1);
  2359.                 temp &= ~FDI_BC_BIFURCATION_SELECT;
  2360.                 DRM_DEBUG_KMS("disabling fdi C rx\n");
  2361.                 I915_WRITE(SOUTH_CHICKEN1, temp);
  2362.         }
  2363. }
  2364.  
  2365. /* The FDI link training functions for ILK/Ibexpeak. */
  2366. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2367. {
  2368.     struct drm_device *dev = crtc->dev;
  2369.     struct drm_i915_private *dev_priv = dev->dev_private;
  2370.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2371.     int pipe = intel_crtc->pipe;
  2372.     int plane = intel_crtc->plane;
  2373.     u32 reg, temp, tries;
  2374.  
  2375.     /* FDI needs bits from pipe & plane first */
  2376.     assert_pipe_enabled(dev_priv, pipe);
  2377.     assert_plane_enabled(dev_priv, plane);
  2378.  
  2379.     /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2380.        for train result */
  2381.     reg = FDI_RX_IMR(pipe);
  2382.     temp = I915_READ(reg);
  2383.     temp &= ~FDI_RX_SYMBOL_LOCK;
  2384.     temp &= ~FDI_RX_BIT_LOCK;
  2385.     I915_WRITE(reg, temp);
  2386.     I915_READ(reg);
  2387.     udelay(150);
  2388.  
  2389.     /* enable CPU FDI TX and PCH FDI RX */
  2390.     reg = FDI_TX_CTL(pipe);
  2391.     temp = I915_READ(reg);
  2392.         temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2393.         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2394.     temp &= ~FDI_LINK_TRAIN_NONE;
  2395.     temp |= FDI_LINK_TRAIN_PATTERN_1;
  2396.     I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2397.  
  2398.     reg = FDI_RX_CTL(pipe);
  2399.     temp = I915_READ(reg);
  2400.     temp &= ~FDI_LINK_TRAIN_NONE;
  2401.     temp |= FDI_LINK_TRAIN_PATTERN_1;
  2402.     I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2403.  
  2404.     POSTING_READ(reg);
  2405.     udelay(150);
  2406.  
  2407.     /* Ironlake workaround, enable clock pointer after FDI enable*/
  2408.         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2409.         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2410.                FDI_RX_PHASE_SYNC_POINTER_EN);
  2411.  
  2412.     reg = FDI_RX_IIR(pipe);
  2413.     for (tries = 0; tries < 5; tries++) {
  2414.         temp = I915_READ(reg);
  2415.         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2416.  
  2417.         if ((temp & FDI_RX_BIT_LOCK)) {
  2418.             DRM_DEBUG_KMS("FDI train 1 done.\n");
  2419.             I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2420.             break;
  2421.         }
  2422.     }
  2423.     if (tries == 5)
  2424.         DRM_ERROR("FDI train 1 fail!\n");
  2425.  
  2426.     /* Train 2 */
  2427.     reg = FDI_TX_CTL(pipe);
  2428.     temp = I915_READ(reg);
  2429.     temp &= ~FDI_LINK_TRAIN_NONE;
  2430.     temp |= FDI_LINK_TRAIN_PATTERN_2;
  2431.     I915_WRITE(reg, temp);
  2432.  
  2433.     reg = FDI_RX_CTL(pipe);
  2434.     temp = I915_READ(reg);
  2435.     temp &= ~FDI_LINK_TRAIN_NONE;
  2436.     temp |= FDI_LINK_TRAIN_PATTERN_2;
  2437.     I915_WRITE(reg, temp);
  2438.  
  2439.     POSTING_READ(reg);
  2440.     udelay(150);
  2441.  
  2442.     reg = FDI_RX_IIR(pipe);
  2443.     for (tries = 0; tries < 5; tries++) {
  2444.         temp = I915_READ(reg);
  2445.         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2446.  
  2447.         if (temp & FDI_RX_SYMBOL_LOCK) {
  2448.             I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2449.             DRM_DEBUG_KMS("FDI train 2 done.\n");
  2450.             break;
  2451.         }
  2452.     }
  2453.     if (tries == 5)
  2454.         DRM_ERROR("FDI train 2 fail!\n");
  2455.  
  2456.     DRM_DEBUG_KMS("FDI train done\n");
  2457.  
  2458. }
  2459.  
  2460. static const int snb_b_fdi_train_param[] = {
  2461.     FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2462.     FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2463.     FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2464.     FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2465. };
  2466.  
  2467. /* The FDI link training functions for SNB/Cougarpoint. */
  2468. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2469. {
  2470.     struct drm_device *dev = crtc->dev;
  2471.     struct drm_i915_private *dev_priv = dev->dev_private;
  2472.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2473.     int pipe = intel_crtc->pipe;
  2474.         u32 reg, temp, i, retry;
  2475.  
  2476.     /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2477.        for train result */
  2478.     reg = FDI_RX_IMR(pipe);
  2479.     temp = I915_READ(reg);
  2480.     temp &= ~FDI_RX_SYMBOL_LOCK;
  2481.     temp &= ~FDI_RX_BIT_LOCK;
  2482.     I915_WRITE(reg, temp);
  2483.  
  2484.     POSTING_READ(reg);
  2485.     udelay(150);
  2486.  
  2487.     /* enable CPU FDI TX and PCH FDI RX */
  2488.     reg = FDI_TX_CTL(pipe);
  2489.     temp = I915_READ(reg);
  2490.         temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2491.         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2492.     temp &= ~FDI_LINK_TRAIN_NONE;
  2493.     temp |= FDI_LINK_TRAIN_PATTERN_1;
  2494.     temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2495.     /* SNB-B */
  2496.     temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2497.     I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2498.  
  2499.         I915_WRITE(FDI_RX_MISC(pipe),
  2500.                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2501.  
  2502.     reg = FDI_RX_CTL(pipe);
  2503.     temp = I915_READ(reg);
  2504.     if (HAS_PCH_CPT(dev)) {
  2505.         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2506.         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2507.     } else {
  2508.         temp &= ~FDI_LINK_TRAIN_NONE;
  2509.         temp |= FDI_LINK_TRAIN_PATTERN_1;
  2510.     }
  2511.     I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2512.  
  2513.     POSTING_READ(reg);
  2514.     udelay(150);
  2515.  
  2516.         for (i = 0; i < 4; i++) {
  2517.         reg = FDI_TX_CTL(pipe);
  2518.         temp = I915_READ(reg);
  2519.         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2520.         temp |= snb_b_fdi_train_param[i];
  2521.         I915_WRITE(reg, temp);
  2522.  
  2523.         POSTING_READ(reg);
  2524.         udelay(500);
  2525.  
  2526.                 for (retry = 0; retry < 5; retry++) {
  2527.         reg = FDI_RX_IIR(pipe);
  2528.         temp = I915_READ(reg);
  2529.         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2530.         if (temp & FDI_RX_BIT_LOCK) {
  2531.             I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2532.             DRM_DEBUG_KMS("FDI train 1 done.\n");
  2533.             break;
  2534.         }
  2535.                         udelay(50);
  2536.                 }
  2537.                 if (retry < 5)
  2538.                         break;
  2539.     }
  2540.     if (i == 4)
  2541.         DRM_ERROR("FDI train 1 fail!\n");
  2542.  
  2543.     /* Train 2 */
  2544.     reg = FDI_TX_CTL(pipe);
  2545.     temp = I915_READ(reg);
  2546.     temp &= ~FDI_LINK_TRAIN_NONE;
  2547.     temp |= FDI_LINK_TRAIN_PATTERN_2;
  2548.     if (IS_GEN6(dev)) {
  2549.         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2550.         /* SNB-B */
  2551.         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2552.     }
  2553.     I915_WRITE(reg, temp);
  2554.  
  2555.     reg = FDI_RX_CTL(pipe);
  2556.     temp = I915_READ(reg);
  2557.     if (HAS_PCH_CPT(dev)) {
  2558.         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2559.         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2560.     } else {
  2561.         temp &= ~FDI_LINK_TRAIN_NONE;
  2562.         temp |= FDI_LINK_TRAIN_PATTERN_2;
  2563.     }
  2564.     I915_WRITE(reg, temp);
  2565.  
  2566.     POSTING_READ(reg);
  2567.     udelay(150);
  2568.  
  2569.         for (i = 0; i < 4; i++) {
  2570.         reg = FDI_TX_CTL(pipe);
  2571.         temp = I915_READ(reg);
  2572.         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2573.         temp |= snb_b_fdi_train_param[i];
  2574.         I915_WRITE(reg, temp);
  2575.  
  2576.         POSTING_READ(reg);
  2577.         udelay(500);
  2578.  
  2579.                 for (retry = 0; retry < 5; retry++) {
  2580.         reg = FDI_RX_IIR(pipe);
  2581.         temp = I915_READ(reg);
  2582.         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2583.         if (temp & FDI_RX_SYMBOL_LOCK) {
  2584.             I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2585.             DRM_DEBUG_KMS("FDI train 2 done.\n");
  2586.             break;
  2587.         }
  2588.                         udelay(50);
  2589.                 }
  2590.                 if (retry < 5)
  2591.                         break;
  2592.     }
  2593.     if (i == 4)
  2594.         DRM_ERROR("FDI train 2 fail!\n");
  2595.  
  2596.     DRM_DEBUG_KMS("FDI train done.\n");
  2597. }
  2598.  
  2599. /* Manual link training for Ivy Bridge A0 parts */
  2600. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2601. {
  2602.     struct drm_device *dev = crtc->dev;
  2603.     struct drm_i915_private *dev_priv = dev->dev_private;
  2604.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2605.     int pipe = intel_crtc->pipe;
  2606.         u32 reg, temp, i, j;
  2607.  
  2608.     /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2609.        for train result */
  2610.     reg = FDI_RX_IMR(pipe);
  2611.     temp = I915_READ(reg);
  2612.     temp &= ~FDI_RX_SYMBOL_LOCK;
  2613.     temp &= ~FDI_RX_BIT_LOCK;
  2614.     I915_WRITE(reg, temp);
  2615.  
  2616.     POSTING_READ(reg);
  2617.     udelay(150);
  2618.  
  2619.         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
  2620.                       I915_READ(FDI_RX_IIR(pipe)));
  2621.  
  2622.         /* Try each vswing and preemphasis setting twice before moving on */
  2623.         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
  2624.                 /* disable first in case we need to retry */
  2625.                 reg = FDI_TX_CTL(pipe);
  2626.                 temp = I915_READ(reg);
  2627.                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2628.                 temp &= ~FDI_TX_ENABLE;
  2629.                 I915_WRITE(reg, temp);
  2630.  
  2631.                 reg = FDI_RX_CTL(pipe);
  2632.                 temp = I915_READ(reg);
  2633.                 temp &= ~FDI_LINK_TRAIN_AUTO;
  2634.                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2635.                 temp &= ~FDI_RX_ENABLE;
  2636.                 I915_WRITE(reg, temp)