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  1. /*
  2.  * Copyright © 2006-2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *  Eric Anholt <eric@anholt.net>
  25.  */
  26.  
  27. //#include <linux/dmi.h>
  28. #include <linux/module.h>
  29. //#include <linux/input.h>
  30. #include <linux/i2c.h>
  31. #include <linux/kernel.h>
  32. #include <linux/slab.h>
  33. #include <linux/math64.h>
  34. #include <drm/drm_edid.h>
  35. #include <drm/drmP.h>
  36. #include "intel_drv.h"
  37. #include <drm/i915_drm.h>
  38. #include "i915_drv.h"
  39. #include "i915_trace.h"
  40. #include <drm/drm_dp_helper.h>
  41. #include <drm/drm_crtc_helper.h>
  42. //#include <linux/dma_remapping.h>
  43.  
  44. #define MAX_ERRNO       4095
  45. phys_addr_t get_bus_addr(void);
  46.  
  47. bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  48. static void intel_increase_pllclock(struct drm_crtc *crtc);
  49. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50.  
  51. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  52.                                 struct intel_crtc_config *pipe_config);
  53. static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  54.                                     struct intel_crtc_config *pipe_config);
  55.  
  56. static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  57.                           int x, int y, struct drm_framebuffer *old_fb);
  58.  
  59.  
  60. typedef struct {
  61.     int min, max;
  62. } intel_range_t;
  63.  
  64. typedef struct {
  65.     int dot_limit;
  66.     int p2_slow, p2_fast;
  67. } intel_p2_t;
  68.  
  69. typedef struct intel_limit intel_limit_t;
  70. struct intel_limit {
  71.     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  72.     intel_p2_t      p2;
  73. };
  74.  
  75. /* FDI */
  76. #define IRONLAKE_FDI_FREQ       2700000 /* in kHz for mode->clock */
  77.  
  78. int
  79. intel_pch_rawclk(struct drm_device *dev)
  80. {
  81.         struct drm_i915_private *dev_priv = dev->dev_private;
  82.  
  83.         WARN_ON(!HAS_PCH_SPLIT(dev));
  84.  
  85.         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  86. }
  87.  
  88. static inline u32 /* units of 100MHz */
  89. intel_fdi_link_freq(struct drm_device *dev)
  90. {
  91.         if (IS_GEN5(dev)) {
  92.                 struct drm_i915_private *dev_priv = dev->dev_private;
  93.                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  94.         } else
  95.                 return 27;
  96. }
  97.  
  98. static const intel_limit_t intel_limits_i8xx_dac = {
  99.         .dot = { .min = 25000, .max = 350000 },
  100.         .vco = { .min = 930000, .max = 1400000 },
  101.         .n = { .min = 3, .max = 16 },
  102.         .m = { .min = 96, .max = 140 },
  103.         .m1 = { .min = 18, .max = 26 },
  104.         .m2 = { .min = 6, .max = 16 },
  105.         .p = { .min = 4, .max = 128 },
  106.         .p1 = { .min = 2, .max = 33 },
  107.         .p2 = { .dot_limit = 165000,
  108.                 .p2_slow = 4, .p2_fast = 2 },
  109. };
  110.  
  111. static const intel_limit_t intel_limits_i8xx_dvo = {
  112.         .dot = { .min = 25000, .max = 350000 },
  113.         .vco = { .min = 930000, .max = 1400000 },
  114.         .n = { .min = 3, .max = 16 },
  115.         .m = { .min = 96, .max = 140 },
  116.         .m1 = { .min = 18, .max = 26 },
  117.         .m2 = { .min = 6, .max = 16 },
  118.         .p = { .min = 4, .max = 128 },
  119.         .p1 = { .min = 2, .max = 33 },
  120.         .p2 = { .dot_limit = 165000,
  121.                 .p2_slow = 4, .p2_fast = 4 },
  122. };
  123.  
  124. static const intel_limit_t intel_limits_i8xx_lvds = {
  125.         .dot = { .min = 25000, .max = 350000 },
  126.         .vco = { .min = 930000, .max = 1400000 },
  127.         .n = { .min = 3, .max = 16 },
  128.         .m = { .min = 96, .max = 140 },
  129.         .m1 = { .min = 18, .max = 26 },
  130.         .m2 = { .min = 6, .max = 16 },
  131.         .p = { .min = 4, .max = 128 },
  132.         .p1 = { .min = 1, .max = 6 },
  133.         .p2 = { .dot_limit = 165000,
  134.                 .p2_slow = 14, .p2_fast = 7 },
  135. };
  136.  
  137. static const intel_limit_t intel_limits_i9xx_sdvo = {
  138.         .dot = { .min = 20000, .max = 400000 },
  139.         .vco = { .min = 1400000, .max = 2800000 },
  140.         .n = { .min = 1, .max = 6 },
  141.         .m = { .min = 70, .max = 120 },
  142.         .m1 = { .min = 8, .max = 18 },
  143.         .m2 = { .min = 3, .max = 7 },
  144.         .p = { .min = 5, .max = 80 },
  145.         .p1 = { .min = 1, .max = 8 },
  146.         .p2 = { .dot_limit = 200000,
  147.                 .p2_slow = 10, .p2_fast = 5 },
  148. };
  149.  
  150. static const intel_limit_t intel_limits_i9xx_lvds = {
  151.         .dot = { .min = 20000, .max = 400000 },
  152.         .vco = { .min = 1400000, .max = 2800000 },
  153.         .n = { .min = 1, .max = 6 },
  154.         .m = { .min = 70, .max = 120 },
  155.         .m1 = { .min = 8, .max = 18 },
  156.         .m2 = { .min = 3, .max = 7 },
  157.         .p = { .min = 7, .max = 98 },
  158.         .p1 = { .min = 1, .max = 8 },
  159.         .p2 = { .dot_limit = 112000,
  160.                 .p2_slow = 14, .p2_fast = 7 },
  161. };
  162.  
  163.  
  164. static const intel_limit_t intel_limits_g4x_sdvo = {
  165.         .dot = { .min = 25000, .max = 270000 },
  166.         .vco = { .min = 1750000, .max = 3500000},
  167.         .n = { .min = 1, .max = 4 },
  168.         .m = { .min = 104, .max = 138 },
  169.         .m1 = { .min = 17, .max = 23 },
  170.         .m2 = { .min = 5, .max = 11 },
  171.         .p = { .min = 10, .max = 30 },
  172.         .p1 = { .min = 1, .max = 3},
  173.         .p2 = { .dot_limit = 270000,
  174.                 .p2_slow = 10,
  175.                 .p2_fast = 10
  176.         },
  177. };
  178.  
  179. static const intel_limit_t intel_limits_g4x_hdmi = {
  180.         .dot = { .min = 22000, .max = 400000 },
  181.         .vco = { .min = 1750000, .max = 3500000},
  182.         .n = { .min = 1, .max = 4 },
  183.         .m = { .min = 104, .max = 138 },
  184.         .m1 = { .min = 16, .max = 23 },
  185.         .m2 = { .min = 5, .max = 11 },
  186.         .p = { .min = 5, .max = 80 },
  187.         .p1 = { .min = 1, .max = 8},
  188.         .p2 = { .dot_limit = 165000,
  189.                 .p2_slow = 10, .p2_fast = 5 },
  190. };
  191.  
  192. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  193.         .dot = { .min = 20000, .max = 115000 },
  194.         .vco = { .min = 1750000, .max = 3500000 },
  195.         .n = { .min = 1, .max = 3 },
  196.         .m = { .min = 104, .max = 138 },
  197.         .m1 = { .min = 17, .max = 23 },
  198.         .m2 = { .min = 5, .max = 11 },
  199.         .p = { .min = 28, .max = 112 },
  200.         .p1 = { .min = 2, .max = 8 },
  201.         .p2 = { .dot_limit = 0,
  202.                 .p2_slow = 14, .p2_fast = 14
  203.         },
  204. };
  205.  
  206. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  207.         .dot = { .min = 80000, .max = 224000 },
  208.         .vco = { .min = 1750000, .max = 3500000 },
  209.         .n = { .min = 1, .max = 3 },
  210.         .m = { .min = 104, .max = 138 },
  211.         .m1 = { .min = 17, .max = 23 },
  212.         .m2 = { .min = 5, .max = 11 },
  213.         .p = { .min = 14, .max = 42 },
  214.         .p1 = { .min = 2, .max = 6 },
  215.         .p2 = { .dot_limit = 0,
  216.                 .p2_slow = 7, .p2_fast = 7
  217.         },
  218. };
  219.  
  220. static const intel_limit_t intel_limits_pineview_sdvo = {
  221.         .dot = { .min = 20000, .max = 400000},
  222.         .vco = { .min = 1700000, .max = 3500000 },
  223.         /* Pineview's Ncounter is a ring counter */
  224.         .n = { .min = 3, .max = 6 },
  225.         .m = { .min = 2, .max = 256 },
  226.         /* Pineview only has one combined m divider, which we treat as m2. */
  227.         .m1 = { .min = 0, .max = 0 },
  228.         .m2 = { .min = 0, .max = 254 },
  229.         .p = { .min = 5, .max = 80 },
  230.         .p1 = { .min = 1, .max = 8 },
  231.         .p2 = { .dot_limit = 200000,
  232.                 .p2_slow = 10, .p2_fast = 5 },
  233. };
  234.  
  235. static const intel_limit_t intel_limits_pineview_lvds = {
  236.         .dot = { .min = 20000, .max = 400000 },
  237.         .vco = { .min = 1700000, .max = 3500000 },
  238.         .n = { .min = 3, .max = 6 },
  239.         .m = { .min = 2, .max = 256 },
  240.         .m1 = { .min = 0, .max = 0 },
  241.         .m2 = { .min = 0, .max = 254 },
  242.         .p = { .min = 7, .max = 112 },
  243.         .p1 = { .min = 1, .max = 8 },
  244.         .p2 = { .dot_limit = 112000,
  245.                 .p2_slow = 14, .p2_fast = 14 },
  246. };
  247.  
  248. /* Ironlake / Sandybridge
  249.  *
  250.  * We calculate clock using (register_value + 2) for N/M1/M2, so here
  251.  * the range value for them is (actual_value - 2).
  252.  */
  253. static const intel_limit_t intel_limits_ironlake_dac = {
  254.         .dot = { .min = 25000, .max = 350000 },
  255.         .vco = { .min = 1760000, .max = 3510000 },
  256.         .n = { .min = 1, .max = 5 },
  257.         .m = { .min = 79, .max = 127 },
  258.         .m1 = { .min = 12, .max = 22 },
  259.         .m2 = { .min = 5, .max = 9 },
  260.         .p = { .min = 5, .max = 80 },
  261.         .p1 = { .min = 1, .max = 8 },
  262.         .p2 = { .dot_limit = 225000,
  263.                 .p2_slow = 10, .p2_fast = 5 },
  264. };
  265.  
  266. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  267.         .dot = { .min = 25000, .max = 350000 },
  268.         .vco = { .min = 1760000, .max = 3510000 },
  269.         .n = { .min = 1, .max = 3 },
  270.         .m = { .min = 79, .max = 118 },
  271.         .m1 = { .min = 12, .max = 22 },
  272.         .m2 = { .min = 5, .max = 9 },
  273.         .p = { .min = 28, .max = 112 },
  274.         .p1 = { .min = 2, .max = 8 },
  275.         .p2 = { .dot_limit = 225000,
  276.                 .p2_slow = 14, .p2_fast = 14 },
  277. };
  278.  
  279. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  280.         .dot = { .min = 25000, .max = 350000 },
  281.         .vco = { .min = 1760000, .max = 3510000 },
  282.         .n = { .min = 1, .max = 3 },
  283.         .m = { .min = 79, .max = 127 },
  284.         .m1 = { .min = 12, .max = 22 },
  285.         .m2 = { .min = 5, .max = 9 },
  286.         .p = { .min = 14, .max = 56 },
  287.         .p1 = { .min = 2, .max = 8 },
  288.         .p2 = { .dot_limit = 225000,
  289.                 .p2_slow = 7, .p2_fast = 7 },
  290. };
  291.  
  292. /* LVDS 100mhz refclk limits. */
  293. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  294.         .dot = { .min = 25000, .max = 350000 },
  295.         .vco = { .min = 1760000, .max = 3510000 },
  296.         .n = { .min = 1, .max = 2 },
  297.         .m = { .min = 79, .max = 126 },
  298.         .m1 = { .min = 12, .max = 22 },
  299.         .m2 = { .min = 5, .max = 9 },
  300.         .p = { .min = 28, .max = 112 },
  301.         .p1 = { .min = 2, .max = 8 },
  302.         .p2 = { .dot_limit = 225000,
  303.                 .p2_slow = 14, .p2_fast = 14 },
  304. };
  305.  
  306. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  307.         .dot = { .min = 25000, .max = 350000 },
  308.         .vco = { .min = 1760000, .max = 3510000 },
  309.         .n = { .min = 1, .max = 3 },
  310.         .m = { .min = 79, .max = 126 },
  311.         .m1 = { .min = 12, .max = 22 },
  312.         .m2 = { .min = 5, .max = 9 },
  313.         .p = { .min = 14, .max = 42 },
  314.         .p1 = { .min = 2, .max = 6 },
  315.         .p2 = { .dot_limit = 225000,
  316.                 .p2_slow = 7, .p2_fast = 7 },
  317. };
  318.  
  319. static const intel_limit_t intel_limits_vlv_dac = {
  320.         .dot = { .min = 25000, .max = 270000 },
  321.         .vco = { .min = 4000000, .max = 6000000 },
  322.         .n = { .min = 1, .max = 7 },
  323.         .m = { .min = 22, .max = 450 }, /* guess */
  324.         .m1 = { .min = 2, .max = 3 },
  325.         .m2 = { .min = 11, .max = 156 },
  326.         .p = { .min = 10, .max = 30 },
  327.         .p1 = { .min = 1, .max = 3 },
  328.         .p2 = { .dot_limit = 270000,
  329.                 .p2_slow = 2, .p2_fast = 20 },
  330. };
  331.  
  332. static const intel_limit_t intel_limits_vlv_hdmi = {
  333.         .dot = { .min = 25000, .max = 270000 },
  334.         .vco = { .min = 4000000, .max = 6000000 },
  335.         .n = { .min = 1, .max = 7 },
  336.         .m = { .min = 60, .max = 300 }, /* guess */
  337.         .m1 = { .min = 2, .max = 3 },
  338.         .m2 = { .min = 11, .max = 156 },
  339.         .p = { .min = 10, .max = 30 },
  340.         .p1 = { .min = 2, .max = 3 },
  341.         .p2 = { .dot_limit = 270000,
  342.                 .p2_slow = 2, .p2_fast = 20 },
  343. };
  344.  
  345. static const intel_limit_t intel_limits_vlv_dp = {
  346.         .dot = { .min = 25000, .max = 270000 },
  347.         .vco = { .min = 4000000, .max = 6000000 },
  348.         .n = { .min = 1, .max = 7 },
  349.         .m = { .min = 22, .max = 450 },
  350.         .m1 = { .min = 2, .max = 3 },
  351.         .m2 = { .min = 11, .max = 156 },
  352.         .p = { .min = 10, .max = 30 },
  353.         .p1 = { .min = 1, .max = 3 },
  354.         .p2 = { .dot_limit = 270000,
  355.                 .p2_slow = 2, .p2_fast = 20 },
  356. };
  357.  
  358. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  359.                                                 int refclk)
  360. {
  361.         struct drm_device *dev = crtc->dev;
  362.         const intel_limit_t *limit;
  363.  
  364.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  365.                 if (intel_is_dual_link_lvds(dev)) {
  366.                         if (refclk == 100000)
  367.                                 limit = &intel_limits_ironlake_dual_lvds_100m;
  368.                         else
  369.                                 limit = &intel_limits_ironlake_dual_lvds;
  370.                 } else {
  371.                         if (refclk == 100000)
  372.                                 limit = &intel_limits_ironlake_single_lvds_100m;
  373.                         else
  374.                                 limit = &intel_limits_ironlake_single_lvds;
  375.                 }
  376.         } else
  377.                 limit = &intel_limits_ironlake_dac;
  378.  
  379.         return limit;
  380. }
  381.  
  382. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  383. {
  384.         struct drm_device *dev = crtc->dev;
  385.         const intel_limit_t *limit;
  386.  
  387.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  388.                 if (intel_is_dual_link_lvds(dev))
  389.                         limit = &intel_limits_g4x_dual_channel_lvds;
  390.                 else
  391.                         limit = &intel_limits_g4x_single_channel_lvds;
  392.         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  393.                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  394.                 limit = &intel_limits_g4x_hdmi;
  395.         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  396.                 limit = &intel_limits_g4x_sdvo;
  397.         } else /* The option is for other outputs */
  398.                 limit = &intel_limits_i9xx_sdvo;
  399.  
  400.         return limit;
  401. }
  402.  
  403. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  404. {
  405.         struct drm_device *dev = crtc->dev;
  406.         const intel_limit_t *limit;
  407.  
  408.         if (HAS_PCH_SPLIT(dev))
  409.                 limit = intel_ironlake_limit(crtc, refclk);
  410.         else if (IS_G4X(dev)) {
  411.                 limit = intel_g4x_limit(crtc);
  412.         } else if (IS_PINEVIEW(dev)) {
  413.                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  414.                         limit = &intel_limits_pineview_lvds;
  415.                 else
  416.                         limit = &intel_limits_pineview_sdvo;
  417.         } else if (IS_VALLEYVIEW(dev)) {
  418.                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
  419.                         limit = &intel_limits_vlv_dac;
  420.                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  421.                         limit = &intel_limits_vlv_hdmi;
  422.                 else
  423.                         limit = &intel_limits_vlv_dp;
  424.         } else if (!IS_GEN2(dev)) {
  425.                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  426.                         limit = &intel_limits_i9xx_lvds;
  427.                 else
  428.                         limit = &intel_limits_i9xx_sdvo;
  429.         } else {
  430.                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  431.                         limit = &intel_limits_i8xx_lvds;
  432.                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
  433.                         limit = &intel_limits_i8xx_dvo;
  434.                 else
  435.                         limit = &intel_limits_i8xx_dac;
  436.         }
  437.         return limit;
  438. }
  439.  
  440. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  441. static void pineview_clock(int refclk, intel_clock_t *clock)
  442. {
  443.         clock->m = clock->m2 + 2;
  444.         clock->p = clock->p1 * clock->p2;
  445.         clock->vco = refclk * clock->m / clock->n;
  446.         clock->dot = clock->vco / clock->p;
  447. }
  448.  
  449. static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
  450. {
  451.         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
  452. }
  453.  
  454. static void i9xx_clock(int refclk, intel_clock_t *clock)
  455. {
  456.         clock->m = i9xx_dpll_compute_m(clock);
  457.         clock->p = clock->p1 * clock->p2;
  458.         clock->vco = refclk * clock->m / (clock->n + 2);
  459.         clock->dot = clock->vco / clock->p;
  460. }
  461.  
  462. /**
  463.  * Returns whether any output on the specified pipe is of the specified type
  464.  */
  465. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  466. {
  467.         struct drm_device *dev = crtc->dev;
  468.         struct intel_encoder *encoder;
  469.  
  470.         for_each_encoder_on_crtc(dev, crtc, encoder)
  471.                 if (encoder->type == type)
  472.                         return true;
  473.  
  474.         return false;
  475. }
  476.  
  477. #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
  478. /**
  479.  * Returns whether the given set of divisors are valid for a given refclk with
  480.  * the given connectors.
  481.  */
  482.  
  483. static bool intel_PLL_is_valid(struct drm_device *dev,
  484.                                const intel_limit_t *limit,
  485.                                const intel_clock_t *clock)
  486. {
  487.         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
  488.                 INTELPllInvalid("p1 out of range\n");
  489.         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
  490.                 INTELPllInvalid("p out of range\n");
  491.         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
  492.                 INTELPllInvalid("m2 out of range\n");
  493.         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
  494.                 INTELPllInvalid("m1 out of range\n");
  495.         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  496.                 INTELPllInvalid("m1 <= m2\n");
  497.         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
  498.                 INTELPllInvalid("m out of range\n");
  499.         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
  500.                 INTELPllInvalid("n out of range\n");
  501.         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  502.                 INTELPllInvalid("vco out of range\n");
  503.         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  504.          * connector, etc., rather than just a single range.
  505.          */
  506.         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  507.                 INTELPllInvalid("dot out of range\n");
  508.  
  509.         return true;
  510. }
  511.  
  512. static bool
  513. i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  514.                     int target, int refclk, intel_clock_t *match_clock,
  515.                     intel_clock_t *best_clock)
  516. {
  517.         struct drm_device *dev = crtc->dev;
  518.         intel_clock_t clock;
  519.         int err = target;
  520.  
  521.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  522.                 /*
  523.                  * For LVDS just rely on its current settings for dual-channel.
  524.                  * We haven't figured out how to reliably set up different
  525.                  * single/dual channel state, if we even can.
  526.                  */
  527.                 if (intel_is_dual_link_lvds(dev))
  528.                         clock.p2 = limit->p2.p2_fast;
  529.                 else
  530.                         clock.p2 = limit->p2.p2_slow;
  531.         } else {
  532.                 if (target < limit->p2.dot_limit)
  533.                         clock.p2 = limit->p2.p2_slow;
  534.                 else
  535.                         clock.p2 = limit->p2.p2_fast;
  536.         }
  537.  
  538.         memset(best_clock, 0, sizeof(*best_clock));
  539.  
  540.         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  541.              clock.m1++) {
  542.                 for (clock.m2 = limit->m2.min;
  543.                      clock.m2 <= limit->m2.max; clock.m2++) {
  544.                         if (clock.m2 >= clock.m1)
  545.                                 break;
  546.                         for (clock.n = limit->n.min;
  547.                              clock.n <= limit->n.max; clock.n++) {
  548.                                 for (clock.p1 = limit->p1.min;
  549.                                         clock.p1 <= limit->p1.max; clock.p1++) {
  550.                                         int this_err;
  551.  
  552.                                         i9xx_clock(refclk, &clock);
  553.                                         if (!intel_PLL_is_valid(dev, limit,
  554.                                                                 &clock))
  555.                                                 continue;
  556.                                         if (match_clock &&
  557.                                             clock.p != match_clock->p)
  558.                                                 continue;
  559.  
  560.                                         this_err = abs(clock.dot - target);
  561.                                         if (this_err < err) {
  562.                                                 *best_clock = clock;
  563.                                                 err = this_err;
  564.                                         }
  565.                                 }
  566.                         }
  567.                 }
  568.         }
  569.  
  570.         return (err != target);
  571. }
  572.  
  573. static bool
  574. pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  575.                    int target, int refclk, intel_clock_t *match_clock,
  576.                    intel_clock_t *best_clock)
  577. {
  578.         struct drm_device *dev = crtc->dev;
  579.         intel_clock_t clock;
  580.         int err = target;
  581.  
  582.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  583.                 /*
  584.                  * For LVDS just rely on its current settings for dual-channel.
  585.                  * We haven't figured out how to reliably set up different
  586.                  * single/dual channel state, if we even can.
  587.                  */
  588.                 if (intel_is_dual_link_lvds(dev))
  589.                         clock.p2 = limit->p2.p2_fast;
  590.                 else
  591.                         clock.p2 = limit->p2.p2_slow;
  592.         } else {
  593.                 if (target < limit->p2.dot_limit)
  594.                         clock.p2 = limit->p2.p2_slow;
  595.                 else
  596.                         clock.p2 = limit->p2.p2_fast;
  597.         }
  598.  
  599.         memset(best_clock, 0, sizeof(*best_clock));
  600.  
  601.         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  602.              clock.m1++) {
  603.                 for (clock.m2 = limit->m2.min;
  604.                      clock.m2 <= limit->m2.max; clock.m2++) {
  605.                         for (clock.n = limit->n.min;
  606.                              clock.n <= limit->n.max; clock.n++) {
  607.                                 for (clock.p1 = limit->p1.min;
  608.                                         clock.p1 <= limit->p1.max; clock.p1++) {
  609.                                         int this_err;
  610.  
  611.                                         pineview_clock(refclk, &clock);
  612.                                         if (!intel_PLL_is_valid(dev, limit,
  613.                                                                 &clock))
  614.                                                 continue;
  615.                                         if (match_clock &&
  616.                                             clock.p != match_clock->p)
  617.                                                 continue;
  618.  
  619.                                         this_err = abs(clock.dot - target);
  620.                                         if (this_err < err) {
  621.                                                 *best_clock = clock;
  622.                                                 err = this_err;
  623.                                         }
  624.                                 }
  625.                         }
  626.                 }
  627.         }
  628.  
  629.         return (err != target);
  630. }
  631.  
  632. static bool
  633. g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  634.                         int target, int refclk, intel_clock_t *match_clock,
  635.                         intel_clock_t *best_clock)
  636. {
  637.         struct drm_device *dev = crtc->dev;
  638.         intel_clock_t clock;
  639.         int max_n;
  640.         bool found;
  641.         /* approximately equals target * 0.00585 */
  642.         int err_most = (target >> 8) + (target >> 9);
  643.         found = false;
  644.  
  645.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  646.                 if (intel_is_dual_link_lvds(dev))
  647.                         clock.p2 = limit->p2.p2_fast;
  648.                 else
  649.                         clock.p2 = limit->p2.p2_slow;
  650.         } else {
  651.                 if (target < limit->p2.dot_limit)
  652.                         clock.p2 = limit->p2.p2_slow;
  653.                 else
  654.                         clock.p2 = limit->p2.p2_fast;
  655.         }
  656.  
  657.         memset(best_clock, 0, sizeof(*best_clock));
  658.         max_n = limit->n.max;
  659.         /* based on hardware requirement, prefer smaller n to precision */
  660.         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  661.                 /* based on hardware requirement, prefere larger m1,m2 */
  662.                 for (clock.m1 = limit->m1.max;
  663.                      clock.m1 >= limit->m1.min; clock.m1--) {
  664.                         for (clock.m2 = limit->m2.max;
  665.                              clock.m2 >= limit->m2.min; clock.m2--) {
  666.                                 for (clock.p1 = limit->p1.max;
  667.                                      clock.p1 >= limit->p1.min; clock.p1--) {
  668.                                         int this_err;
  669.  
  670.                                         i9xx_clock(refclk, &clock);
  671.                                         if (!intel_PLL_is_valid(dev, limit,
  672.                                                                 &clock))
  673.                                                 continue;
  674.  
  675.                                         this_err = abs(clock.dot - target);
  676.                                         if (this_err < err_most) {
  677.                                                 *best_clock = clock;
  678.                                                 err_most = this_err;
  679.                                                 max_n = clock.n;
  680.                                                 found = true;
  681.                                         }
  682.                                 }
  683.                         }
  684.                 }
  685.         }
  686.         return found;
  687. }
  688.  
  689. static bool
  690. vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  691.                         int target, int refclk, intel_clock_t *match_clock,
  692.                         intel_clock_t *best_clock)
  693. {
  694.         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
  695.         u32 m, n, fastclk;
  696.         u32 updrate, minupdate, p;
  697.         unsigned long bestppm, ppm, absppm;
  698.         int dotclk, flag;
  699.  
  700.         flag = 0;
  701.         dotclk = target * 1000;
  702.         bestppm = 1000000;
  703.         ppm = absppm = 0;
  704.         fastclk = dotclk / (2*100);
  705.         updrate = 0;
  706.         minupdate = 19200;
  707.         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
  708.         bestm1 = bestm2 = bestp1 = bestp2 = 0;
  709.  
  710.         /* based on hardware requirement, prefer smaller n to precision */
  711.         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
  712.                 updrate = refclk / n;
  713.                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
  714.                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
  715.                                 if (p2 > 10)
  716.                                         p2 = p2 - 1;
  717.                                 p = p1 * p2;
  718.                                 /* based on hardware requirement, prefer bigger m1,m2 values */
  719.                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
  720.                                         m2 = (((2*(fastclk * p * n / m1 )) +
  721.                                                refclk) / (2*refclk));
  722.                                         m = m1 * m2;
  723.                                         vco = updrate * m;
  724.                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
  725.                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
  726.                                                 absppm = (ppm > 0) ? ppm : (-ppm);
  727.                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
  728.                                                         bestppm = 0;
  729.                                                         flag = 1;
  730.                                                 }
  731.                                                 if (absppm < bestppm - 10) {
  732.                                                         bestppm = absppm;
  733.                                                         flag = 1;
  734.                                                 }
  735.                                                 if (flag) {
  736.                                                         bestn = n;
  737.                                                         bestm1 = m1;
  738.                                                         bestm2 = m2;
  739.                                                         bestp1 = p1;
  740.                                                         bestp2 = p2;
  741.                                                         flag = 0;
  742.                                                 }
  743.                                         }
  744.                                 }
  745.                         }
  746.                 }
  747.         }
  748.         best_clock->n = bestn;
  749.         best_clock->m1 = bestm1;
  750.         best_clock->m2 = bestm2;
  751.         best_clock->p1 = bestp1;
  752.         best_clock->p2 = bestp2;
  753.  
  754.         return true;
  755. }
  756.  
  757. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  758.                                              enum pipe pipe)
  759. {
  760.         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  761.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  762.  
  763.         return intel_crtc->config.cpu_transcoder;
  764. }
  765.  
  766. static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
  767. {
  768.         struct drm_i915_private *dev_priv = dev->dev_private;
  769.         u32 frame, frame_reg = PIPEFRAME(pipe);
  770.  
  771.         frame = I915_READ(frame_reg);
  772.  
  773.         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
  774.                 DRM_DEBUG_KMS("vblank wait timed out\n");
  775. }
  776.  
  777. /**
  778.  * intel_wait_for_vblank - wait for vblank on a given pipe
  779.  * @dev: drm device
  780.  * @pipe: pipe to wait for
  781.  *
  782.  * Wait for vblank to occur on a given pipe.  Needed for various bits of
  783.  * mode setting code.
  784.  */
  785. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  786. {
  787.         struct drm_i915_private *dev_priv = dev->dev_private;
  788.         int pipestat_reg = PIPESTAT(pipe);
  789.  
  790.         if (INTEL_INFO(dev)->gen >= 5) {
  791.                 ironlake_wait_for_vblank(dev, pipe);
  792.                 return;
  793.         }
  794.  
  795.         /* Clear existing vblank status. Note this will clear any other
  796.          * sticky status fields as well.
  797.          *
  798.          * This races with i915_driver_irq_handler() with the result
  799.          * that either function could miss a vblank event.  Here it is not
  800.          * fatal, as we will either wait upon the next vblank interrupt or
  801.          * timeout.  Generally speaking intel_wait_for_vblank() is only
  802.          * called during modeset at which time the GPU should be idle and
  803.          * should *not* be performing page flips and thus not waiting on
  804.          * vblanks...
  805.          * Currently, the result of us stealing a vblank from the irq
  806.          * handler is that a single frame will be skipped during swapbuffers.
  807.          */
  808.         I915_WRITE(pipestat_reg,
  809.                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  810.  
  811.         /* Wait for vblank interrupt bit to set */
  812.         if (wait_for(I915_READ(pipestat_reg) &
  813.                      PIPE_VBLANK_INTERRUPT_STATUS,
  814.                      50))
  815.                 DRM_DEBUG_KMS("vblank wait timed out\n");
  816. }
  817.  
  818. /*
  819.  * intel_wait_for_pipe_off - wait for pipe to turn off
  820.  * @dev: drm device
  821.  * @pipe: pipe to wait for
  822.  *
  823.  * After disabling a pipe, we can't wait for vblank in the usual way,
  824.  * spinning on the vblank interrupt status bit, since we won't actually
  825.  * see an interrupt when the pipe is disabled.
  826.  *
  827.  * On Gen4 and above:
  828.  *   wait for the pipe register state bit to turn off
  829.  *
  830.  * Otherwise:
  831.  *   wait for the display line value to settle (it usually
  832.  *   ends up stopping at the start of the next frame).
  833.  *
  834.  */
  835. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  836. {
  837.         struct drm_i915_private *dev_priv = dev->dev_private;
  838.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  839.                                                                       pipe);
  840.  
  841.         if (INTEL_INFO(dev)->gen >= 4) {
  842.                 int reg = PIPECONF(cpu_transcoder);
  843.  
  844.                 /* Wait for the Pipe State to go off */
  845.                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  846.                              100))
  847.                         WARN(1, "pipe_off wait timed out\n");
  848.         } else {
  849.                 u32 last_line, line_mask;
  850.                 int reg = PIPEDSL(pipe);
  851.                 unsigned long timeout = GetTimerTicks() + msecs_to_jiffies(100);
  852.  
  853.                 if (IS_GEN2(dev))
  854.                         line_mask = DSL_LINEMASK_GEN2;
  855.                 else
  856.                         line_mask = DSL_LINEMASK_GEN3;
  857.  
  858.                 /* Wait for the display line to settle */
  859.                 do {
  860.                         last_line = I915_READ(reg) & line_mask;
  861.                         mdelay(5);
  862.                 } while (((I915_READ(reg) & line_mask) != last_line) &&
  863.                          time_after(timeout, GetTimerTicks()));
  864.                 if (time_after(GetTimerTicks(), timeout))
  865.                         WARN(1, "pipe_off wait timed out\n");
  866.         }
  867. }
  868.  
  869. /*
  870.  * ibx_digital_port_connected - is the specified port connected?
  871.  * @dev_priv: i915 private structure
  872.  * @port: the port to test
  873.  *
  874.  * Returns true if @port is connected, false otherwise.
  875.  */
  876. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  877.                                 struct intel_digital_port *port)
  878. {
  879.         u32 bit;
  880.  
  881.         if (HAS_PCH_IBX(dev_priv->dev)) {
  882.                 switch(port->port) {
  883.                 case PORT_B:
  884.                         bit = SDE_PORTB_HOTPLUG;
  885.                         break;
  886.                 case PORT_C:
  887.                         bit = SDE_PORTC_HOTPLUG;
  888.                         break;
  889.                 case PORT_D:
  890.                         bit = SDE_PORTD_HOTPLUG;
  891.                         break;
  892.                 default:
  893.                         return true;
  894.                 }
  895.         } else {
  896.                 switch(port->port) {
  897.                 case PORT_B:
  898.                         bit = SDE_PORTB_HOTPLUG_CPT;
  899.                         break;
  900.                 case PORT_C:
  901.                         bit = SDE_PORTC_HOTPLUG_CPT;
  902.                         break;
  903.                 case PORT_D:
  904.                         bit = SDE_PORTD_HOTPLUG_CPT;
  905.                         break;
  906.                 default:
  907.                         return true;
  908.                 }
  909.         }
  910.  
  911.         return I915_READ(SDEISR) & bit;
  912. }
  913.  
  914. static const char *state_string(bool enabled)
  915. {
  916.         return enabled ? "on" : "off";
  917. }
  918.  
  919. /* Only for pre-ILK configs */
  920. void assert_pll(struct drm_i915_private *dev_priv,
  921.                        enum pipe pipe, bool state)
  922. {
  923.         int reg;
  924.         u32 val;
  925.         bool cur_state;
  926.  
  927.         reg = DPLL(pipe);
  928.         val = I915_READ(reg);
  929.         cur_state = !!(val & DPLL_VCO_ENABLE);
  930.         WARN(cur_state != state,
  931.              "PLL state assertion failure (expected %s, current %s)\n",
  932.              state_string(state), state_string(cur_state));
  933. }
  934.  
  935. struct intel_shared_dpll *
  936. intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
  937. {
  938.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  939.  
  940.         if (crtc->config.shared_dpll < 0)
  941.                 return NULL;
  942.  
  943.         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
  944. }
  945.  
  946. /* For ILK+ */
  947. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  948.                                struct intel_shared_dpll *pll,
  949.                            bool state)
  950. {
  951.         bool cur_state;
  952.         struct intel_dpll_hw_state hw_state;
  953.  
  954.         if (HAS_PCH_LPT(dev_priv->dev)) {
  955.                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
  956.                 return;
  957.         }
  958.  
  959.         if (WARN (!pll,
  960.                   "asserting DPLL %s with no DPLL\n", state_string(state)))
  961.                 return;
  962.  
  963.         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
  964.         WARN(cur_state != state,
  965.              "%s assertion failure (expected %s, current %s)\n",
  966.              pll->name, state_string(state), state_string(cur_state));
  967. }
  968.  
  969. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  970.                           enum pipe pipe, bool state)
  971. {
  972.         int reg;
  973.         u32 val;
  974.         bool cur_state;
  975.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  976.                                                                       pipe);
  977.  
  978.         if (HAS_DDI(dev_priv->dev)) {
  979.                 /* DDI does not have a specific FDI_TX register */
  980.                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
  981.                 val = I915_READ(reg);
  982.                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
  983.         } else {
  984.         reg = FDI_TX_CTL(pipe);
  985.         val = I915_READ(reg);
  986.         cur_state = !!(val & FDI_TX_ENABLE);
  987.         }
  988.         WARN(cur_state != state,
  989.              "FDI TX state assertion failure (expected %s, current %s)\n",
  990.              state_string(state), state_string(cur_state));
  991. }
  992. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  993. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  994.  
  995. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  996.                           enum pipe pipe, bool state)
  997. {
  998.         int reg;
  999.         u32 val;
  1000.         bool cur_state;
  1001.  
  1002.         reg = FDI_RX_CTL(pipe);
  1003.         val = I915_READ(reg);
  1004.         cur_state = !!(val & FDI_RX_ENABLE);
  1005.         WARN(cur_state != state,
  1006.              "FDI RX state assertion failure (expected %s, current %s)\n",
  1007.              state_string(state), state_string(cur_state));
  1008. }
  1009. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  1010. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  1011.  
  1012. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  1013.                                       enum pipe pipe)
  1014. {
  1015.         int reg;
  1016.         u32 val;
  1017.  
  1018.         /* ILK FDI PLL is always enabled */
  1019.         if (dev_priv->info->gen == 5)
  1020.                 return;
  1021.  
  1022.         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  1023.         if (HAS_DDI(dev_priv->dev))
  1024.                 return;
  1025.  
  1026.         reg = FDI_TX_CTL(pipe);
  1027.         val = I915_READ(reg);
  1028.         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  1029. }
  1030.  
  1031. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  1032.                        enum pipe pipe, bool state)
  1033. {
  1034.         int reg;
  1035.         u32 val;
  1036.         bool cur_state;
  1037.  
  1038.         reg = FDI_RX_CTL(pipe);
  1039.         val = I915_READ(reg);
  1040.         cur_state = !!(val & FDI_RX_PLL_ENABLE);
  1041.         WARN(cur_state != state,
  1042.              "FDI RX PLL assertion failure (expected %s, current %s)\n",
  1043.              state_string(state), state_string(cur_state));
  1044. }
  1045.  
  1046. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  1047.                                   enum pipe pipe)
  1048. {
  1049.         int pp_reg, lvds_reg;
  1050.         u32 val;
  1051.         enum pipe panel_pipe = PIPE_A;
  1052.         bool locked = true;
  1053.  
  1054.         if (HAS_PCH_SPLIT(dev_priv->dev)) {
  1055.                 pp_reg = PCH_PP_CONTROL;
  1056.                 lvds_reg = PCH_LVDS;
  1057.         } else {
  1058.                 pp_reg = PP_CONTROL;
  1059.                 lvds_reg = LVDS;
  1060.         }
  1061.  
  1062.         val = I915_READ(pp_reg);
  1063.         if (!(val & PANEL_POWER_ON) ||
  1064.             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  1065.                 locked = false;
  1066.  
  1067.         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  1068.                 panel_pipe = PIPE_B;
  1069.  
  1070.         WARN(panel_pipe == pipe && locked,
  1071.              "panel assertion failure, pipe %c regs locked\n",
  1072.              pipe_name(pipe));
  1073. }
  1074.  
  1075. void assert_pipe(struct drm_i915_private *dev_priv,
  1076.                         enum pipe pipe, bool state)
  1077. {
  1078.         int reg;
  1079.         u32 val;
  1080.         bool cur_state;
  1081.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1082.                                                                       pipe);
  1083.  
  1084.         /* if we need the pipe A quirk it must be always on */
  1085.         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  1086.                 state = true;
  1087.  
  1088.         if (!intel_display_power_enabled(dev_priv->dev,
  1089.                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
  1090.                 cur_state = false;
  1091.         } else {
  1092.         reg = PIPECONF(cpu_transcoder);
  1093.         val = I915_READ(reg);
  1094.         cur_state = !!(val & PIPECONF_ENABLE);
  1095.         }
  1096.  
  1097.         WARN(cur_state != state,
  1098.              "pipe %c assertion failure (expected %s, current %s)\n",
  1099.              pipe_name(pipe), state_string(state), state_string(cur_state));
  1100. }
  1101.  
  1102. static void assert_plane(struct drm_i915_private *dev_priv,
  1103.                          enum plane plane, bool state)
  1104. {
  1105.         int reg;
  1106.         u32 val;
  1107.         bool cur_state;
  1108.  
  1109.         reg = DSPCNTR(plane);
  1110.         val = I915_READ(reg);
  1111.         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  1112.         WARN(cur_state != state,
  1113.              "plane %c assertion failure (expected %s, current %s)\n",
  1114.              plane_name(plane), state_string(state), state_string(cur_state));
  1115. }
  1116.  
  1117. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  1118. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  1119.  
  1120. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  1121.                                    enum pipe pipe)
  1122. {
  1123.         struct drm_device *dev = dev_priv->dev;
  1124.         int reg, i;
  1125.         u32 val;
  1126.         int cur_pipe;
  1127.  
  1128.         /* Primary planes are fixed to pipes on gen4+ */
  1129.         if (INTEL_INFO(dev)->gen >= 4) {
  1130.                 reg = DSPCNTR(pipe);
  1131.                 val = I915_READ(reg);
  1132.                 WARN((val & DISPLAY_PLANE_ENABLE),
  1133.                      "plane %c assertion failure, should be disabled but not\n",
  1134.                      plane_name(pipe));
  1135.                 return;
  1136.         }
  1137.  
  1138.         /* Need to check both planes against the pipe */
  1139.         for_each_pipe(i) {
  1140.                 reg = DSPCNTR(i);
  1141.                 val = I915_READ(reg);
  1142.                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1143.                         DISPPLANE_SEL_PIPE_SHIFT;
  1144.                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1145.                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1146.                      plane_name(i), pipe_name(pipe));
  1147.         }
  1148. }
  1149.  
  1150. static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
  1151.                                     enum pipe pipe)
  1152. {
  1153.         struct drm_device *dev = dev_priv->dev;
  1154.         int reg, i;
  1155.         u32 val;
  1156.  
  1157.         if (IS_VALLEYVIEW(dev)) {
  1158.         for (i = 0; i < dev_priv->num_plane; i++) {
  1159.                 reg = SPCNTR(pipe, i);
  1160.                 val = I915_READ(reg);
  1161.                 WARN((val & SP_ENABLE),
  1162.                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1163.                              sprite_name(pipe, i), pipe_name(pipe));
  1164.                 }
  1165.         } else if (INTEL_INFO(dev)->gen >= 7) {
  1166.                 reg = SPRCTL(pipe);
  1167.                 val = I915_READ(reg);
  1168.                 WARN((val & SPRITE_ENABLE),
  1169.                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1170.                      plane_name(pipe), pipe_name(pipe));
  1171.         } else if (INTEL_INFO(dev)->gen >= 5) {
  1172.                 reg = DVSCNTR(pipe);
  1173.                 val = I915_READ(reg);
  1174.                 WARN((val & DVS_ENABLE),
  1175.                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1176.                      plane_name(pipe), pipe_name(pipe));
  1177.         }
  1178. }
  1179.  
  1180. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  1181. {
  1182.         u32 val;
  1183.         bool enabled;
  1184.  
  1185.         if (HAS_PCH_LPT(dev_priv->dev)) {
  1186.                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
  1187.                 return;
  1188.         }
  1189.  
  1190.         val = I915_READ(PCH_DREF_CONTROL);
  1191.         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  1192.                             DREF_SUPERSPREAD_SOURCE_MASK));
  1193.         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  1194. }
  1195.  
  1196. static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
  1197.                                        enum pipe pipe)
  1198. {
  1199.         int reg;
  1200.         u32 val;
  1201.         bool enabled;
  1202.  
  1203.         reg = PCH_TRANSCONF(pipe);
  1204.         val = I915_READ(reg);
  1205.         enabled = !!(val & TRANS_ENABLE);
  1206.         WARN(enabled,
  1207.              "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1208.              pipe_name(pipe));
  1209. }
  1210.  
  1211. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1212.                             enum pipe pipe, u32 port_sel, u32 val)
  1213. {
  1214.         if ((val & DP_PORT_EN) == 0)
  1215.                 return false;
  1216.  
  1217.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1218.                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  1219.                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  1220.                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1221.                         return false;
  1222.         } else {
  1223.                 if ((val & DP_PIPE_MASK) != (pipe << 30))
  1224.                         return false;
  1225.         }
  1226.         return true;
  1227. }
  1228.  
  1229. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1230.                               enum pipe pipe, u32 val)
  1231. {
  1232.         if ((val & SDVO_ENABLE) == 0)
  1233.                 return false;
  1234.  
  1235.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1236.                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
  1237.                         return false;
  1238.         } else {
  1239.                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
  1240.                         return false;
  1241.         }
  1242.         return true;
  1243. }
  1244.  
  1245. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1246.                               enum pipe pipe, u32 val)
  1247. {
  1248.         if ((val & LVDS_PORT_EN) == 0)
  1249.                 return false;
  1250.  
  1251.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1252.                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1253.                         return false;
  1254.         } else {
  1255.                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1256.                         return false;
  1257.         }
  1258.         return true;
  1259. }
  1260.  
  1261. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1262.                               enum pipe pipe, u32 val)
  1263. {
  1264.         if ((val & ADPA_DAC_ENABLE) == 0)
  1265.                 return false;
  1266.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1267.                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1268.                         return false;
  1269.         } else {
  1270.                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1271.                         return false;
  1272.         }
  1273.         return true;
  1274. }
  1275.  
  1276. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1277.                                    enum pipe pipe, int reg, u32 port_sel)
  1278. {
  1279.         u32 val = I915_READ(reg);
  1280.         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1281.              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1282.              reg, pipe_name(pipe));
  1283.  
  1284.         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
  1285.              && (val & DP_PIPEB_SELECT),
  1286.              "IBX PCH dp port still using transcoder B\n");
  1287. }
  1288.  
  1289. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1290.                                      enum pipe pipe, int reg)
  1291. {
  1292.         u32 val = I915_READ(reg);
  1293.         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1294.              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1295.              reg, pipe_name(pipe));
  1296.  
  1297.         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
  1298.              && (val & SDVO_PIPE_B_SELECT),
  1299.              "IBX PCH hdmi port still using transcoder B\n");
  1300. }
  1301.  
  1302. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1303.                                       enum pipe pipe)
  1304. {
  1305.         int reg;
  1306.         u32 val;
  1307.  
  1308.         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1309.         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1310.         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1311.  
  1312.         reg = PCH_ADPA;
  1313.         val = I915_READ(reg);
  1314.         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1315.              "PCH VGA enabled on transcoder %c, should be disabled\n",
  1316.              pipe_name(pipe));
  1317.  
  1318.         reg = PCH_LVDS;
  1319.         val = I915_READ(reg);
  1320.         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1321.              "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1322.              pipe_name(pipe));
  1323.  
  1324.         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
  1325.         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
  1326.         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
  1327. }
  1328.  
  1329. static void vlv_enable_pll(struct intel_crtc *crtc)
  1330. {
  1331.         struct drm_device *dev = crtc->base.dev;
  1332.         struct drm_i915_private *dev_priv = dev->dev_private;
  1333.         int reg = DPLL(crtc->pipe);
  1334.         u32 dpll = crtc->config.dpll_hw_state.dpll;
  1335.  
  1336.         assert_pipe_disabled(dev_priv, crtc->pipe);
  1337.  
  1338.     /* No really, not for ILK+ */
  1339.         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
  1340.  
  1341.     /* PLL is protected by panel, make sure we can write it */
  1342.     if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  1343.                 assert_panel_unlocked(dev_priv, crtc->pipe);
  1344.  
  1345.         I915_WRITE(reg, dpll);
  1346.         POSTING_READ(reg);
  1347.         udelay(150);
  1348.  
  1349.         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  1350.                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
  1351.  
  1352.         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
  1353.         POSTING_READ(DPLL_MD(crtc->pipe));
  1354.  
  1355.         /* We do this three times for luck */
  1356.         I915_WRITE(reg, dpll);
  1357.         POSTING_READ(reg);
  1358.         udelay(150); /* wait for warmup */
  1359.         I915_WRITE(reg, dpll);
  1360.         POSTING_READ(reg);
  1361.         udelay(150); /* wait for warmup */
  1362.         I915_WRITE(reg, dpll);
  1363.         POSTING_READ(reg);
  1364.         udelay(150); /* wait for warmup */
  1365. }
  1366.  
  1367. static void i9xx_enable_pll(struct intel_crtc *crtc)
  1368. {
  1369.         struct drm_device *dev = crtc->base.dev;
  1370.         struct drm_i915_private *dev_priv = dev->dev_private;
  1371.         int reg = DPLL(crtc->pipe);
  1372.         u32 dpll = crtc->config.dpll_hw_state.dpll;
  1373.  
  1374.         assert_pipe_disabled(dev_priv, crtc->pipe);
  1375.  
  1376.         /* No really, not for ILK+ */
  1377.         BUG_ON(dev_priv->info->gen >= 5);
  1378.  
  1379.         /* PLL is protected by panel, make sure we can write it */
  1380.         if (IS_MOBILE(dev) && !IS_I830(dev))
  1381.                 assert_panel_unlocked(dev_priv, crtc->pipe);
  1382.  
  1383.         I915_WRITE(reg, dpll);
  1384.  
  1385.         /* Wait for the clocks to stabilize. */
  1386.         POSTING_READ(reg);
  1387.         udelay(150);
  1388.  
  1389.         if (INTEL_INFO(dev)->gen >= 4) {
  1390.                 I915_WRITE(DPLL_MD(crtc->pipe),
  1391.                            crtc->config.dpll_hw_state.dpll_md);
  1392.         } else {
  1393.                 /* The pixel multiplier can only be updated once the
  1394.                  * DPLL is enabled and the clocks are stable.
  1395.                  *
  1396.                  * So write it again.
  1397.                  */
  1398.                 I915_WRITE(reg, dpll);
  1399.         }
  1400.  
  1401.     /* We do this three times for luck */
  1402.         I915_WRITE(reg, dpll);
  1403.     POSTING_READ(reg);
  1404.     udelay(150); /* wait for warmup */
  1405.         I915_WRITE(reg, dpll);
  1406.     POSTING_READ(reg);
  1407.     udelay(150); /* wait for warmup */
  1408.         I915_WRITE(reg, dpll);
  1409.     POSTING_READ(reg);
  1410.     udelay(150); /* wait for warmup */
  1411. }
  1412.  
  1413. /**
  1414.  * i9xx_disable_pll - disable a PLL
  1415.  * @dev_priv: i915 private structure
  1416.  * @pipe: pipe PLL to disable
  1417.  *
  1418.  * Disable the PLL for @pipe, making sure the pipe is off first.
  1419.  *
  1420.  * Note!  This is for pre-ILK only.
  1421.  */
  1422. static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1423. {
  1424.         /* Don't disable pipe A or pipe A PLLs if needed */
  1425.         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1426.                 return;
  1427.  
  1428.         /* Make sure the pipe isn't still relying on us */
  1429.         assert_pipe_disabled(dev_priv, pipe);
  1430.  
  1431.         I915_WRITE(DPLL(pipe), 0);
  1432.         POSTING_READ(DPLL(pipe));
  1433. }
  1434.  
  1435. void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
  1436. {
  1437.         u32 port_mask;
  1438.  
  1439.         if (!port)
  1440.                 port_mask = DPLL_PORTB_READY_MASK;
  1441.         else
  1442.                 port_mask = DPLL_PORTC_READY_MASK;
  1443.  
  1444.         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
  1445.                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
  1446.                      'B' + port, I915_READ(DPLL(0)));
  1447. }
  1448.  
  1449. /**
  1450.  * ironlake_enable_shared_dpll - enable PCH PLL
  1451.  * @dev_priv: i915 private structure
  1452.  * @pipe: pipe PLL to enable
  1453.  *
  1454.  * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1455.  * drives the transcoder clock.
  1456.  */
  1457. static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
  1458. {
  1459.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1460.         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1461.  
  1462.         /* PCH PLLs only available on ILK, SNB and IVB */
  1463.         BUG_ON(dev_priv->info->gen < 5);
  1464.         if (WARN_ON(pll == NULL))
  1465.                 return;
  1466.  
  1467.         if (WARN_ON(pll->refcount == 0))
  1468.                 return;
  1469.  
  1470.         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
  1471.                       pll->name, pll->active, pll->on,
  1472.                       crtc->base.base.id);
  1473.  
  1474.         if (pll->active++) {
  1475.                 WARN_ON(!pll->on);
  1476.                 assert_shared_dpll_enabled(dev_priv, pll);
  1477.                 return;
  1478.         }
  1479.         WARN_ON(pll->on);
  1480.  
  1481.         DRM_DEBUG_KMS("enabling %s\n", pll->name);
  1482.         pll->enable(dev_priv, pll);
  1483.         pll->on = true;
  1484. }
  1485.  
  1486. static void intel_disable_shared_dpll(struct intel_crtc *crtc)
  1487. {
  1488.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1489.         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1490.  
  1491.         /* PCH only available on ILK+ */
  1492.         BUG_ON(dev_priv->info->gen < 5);
  1493.         if (WARN_ON(pll == NULL))
  1494.                return;
  1495.  
  1496.         if (WARN_ON(pll->refcount == 0))
  1497.                 return;
  1498.  
  1499.         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
  1500.                       pll->name, pll->active, pll->on,
  1501.                       crtc->base.base.id);
  1502.  
  1503.         if (WARN_ON(pll->active == 0)) {
  1504.                 assert_shared_dpll_disabled(dev_priv, pll);
  1505.                 return;
  1506.         }
  1507.  
  1508.         assert_shared_dpll_enabled(dev_priv, pll);
  1509.         WARN_ON(!pll->on);
  1510.         if (--pll->active)
  1511.                 return;
  1512.  
  1513.         DRM_DEBUG_KMS("disabling %s\n", pll->name);
  1514.         pll->disable(dev_priv, pll);
  1515.         pll->on = false;
  1516. }
  1517.  
  1518. static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1519.                                     enum pipe pipe)
  1520. {
  1521.         struct drm_device *dev = dev_priv->dev;
  1522.         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1523.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1524.         uint32_t reg, val, pipeconf_val;
  1525.  
  1526.         /* PCH only available on ILK+ */
  1527.         BUG_ON(dev_priv->info->gen < 5);
  1528.  
  1529.         /* Make sure PCH DPLL is enabled */
  1530.         assert_shared_dpll_enabled(dev_priv,
  1531.                                    intel_crtc_to_shared_dpll(intel_crtc));
  1532.  
  1533.         /* FDI must be feeding us bits for PCH ports */
  1534.         assert_fdi_tx_enabled(dev_priv, pipe);
  1535.         assert_fdi_rx_enabled(dev_priv, pipe);
  1536.  
  1537.         if (HAS_PCH_CPT(dev)) {
  1538.                 /* Workaround: Set the timing override bit before enabling the
  1539.                  * pch transcoder. */
  1540.                 reg = TRANS_CHICKEN2(pipe);
  1541.                 val = I915_READ(reg);
  1542.                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1543.                 I915_WRITE(reg, val);
  1544.         }
  1545.  
  1546.         reg = PCH_TRANSCONF(pipe);
  1547.         val = I915_READ(reg);
  1548.         pipeconf_val = I915_READ(PIPECONF(pipe));
  1549.  
  1550.         if (HAS_PCH_IBX(dev_priv->dev)) {
  1551.                 /*
  1552.                  * make the BPC in transcoder be consistent with
  1553.                  * that in pipeconf reg.
  1554.                  */
  1555.                 val &= ~PIPECONF_BPC_MASK;
  1556.                 val |= pipeconf_val & PIPECONF_BPC_MASK;
  1557.         }
  1558.  
  1559.         val &= ~TRANS_INTERLACE_MASK;
  1560.         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1561.                 if (HAS_PCH_IBX(dev_priv->dev) &&
  1562.                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
  1563.                         val |= TRANS_LEGACY_INTERLACED_ILK;
  1564.                 else
  1565.                         val |= TRANS_INTERLACED;
  1566.         else
  1567.                 val |= TRANS_PROGRESSIVE;
  1568.  
  1569.         I915_WRITE(reg, val | TRANS_ENABLE);
  1570.         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1571.                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
  1572. }
  1573.  
  1574. static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1575.                                       enum transcoder cpu_transcoder)
  1576. {
  1577.         u32 val, pipeconf_val;
  1578.  
  1579.         /* PCH only available on ILK+ */
  1580.         BUG_ON(dev_priv->info->gen < 5);
  1581.  
  1582.         /* FDI must be feeding us bits for PCH ports */
  1583.         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
  1584.         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
  1585.  
  1586.         /* Workaround: set timing override bit. */
  1587.         val = I915_READ(_TRANSA_CHICKEN2);
  1588.         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1589.         I915_WRITE(_TRANSA_CHICKEN2, val);
  1590.  
  1591.         val = TRANS_ENABLE;
  1592.         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
  1593.  
  1594.         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
  1595.             PIPECONF_INTERLACED_ILK)
  1596.                 val |= TRANS_INTERLACED;
  1597.         else
  1598.                 val |= TRANS_PROGRESSIVE;
  1599.  
  1600.         I915_WRITE(LPT_TRANSCONF, val);
  1601.         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
  1602.                 DRM_ERROR("Failed to enable PCH transcoder\n");
  1603. }
  1604.  
  1605. static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
  1606.                                      enum pipe pipe)
  1607. {
  1608.         struct drm_device *dev = dev_priv->dev;
  1609.         uint32_t reg, val;
  1610.  
  1611.         /* FDI relies on the transcoder */
  1612.         assert_fdi_tx_disabled(dev_priv, pipe);
  1613.         assert_fdi_rx_disabled(dev_priv, pipe);
  1614.  
  1615.         /* Ports must be off as well */
  1616.         assert_pch_ports_disabled(dev_priv, pipe);
  1617.  
  1618.         reg = PCH_TRANSCONF(pipe);
  1619.         val = I915_READ(reg);
  1620.         val &= ~TRANS_ENABLE;
  1621.         I915_WRITE(reg, val);
  1622.         /* wait for PCH transcoder off, transcoder state */
  1623.         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1624.                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
  1625.  
  1626.         if (!HAS_PCH_IBX(dev)) {
  1627.                 /* Workaround: Clear the timing override chicken bit again. */
  1628.                 reg = TRANS_CHICKEN2(pipe);
  1629.                 val = I915_READ(reg);
  1630.                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1631.                 I915_WRITE(reg, val);
  1632.         }
  1633. }
  1634.  
  1635. static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
  1636. {
  1637.         u32 val;
  1638.  
  1639.         val = I915_READ(LPT_TRANSCONF);
  1640.         val &= ~TRANS_ENABLE;
  1641.         I915_WRITE(LPT_TRANSCONF, val);
  1642.         /* wait for PCH transcoder off, transcoder state */
  1643.         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
  1644.                 DRM_ERROR("Failed to disable PCH transcoder\n");
  1645.  
  1646.         /* Workaround: clear timing override bit. */
  1647.         val = I915_READ(_TRANSA_CHICKEN2);
  1648.         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1649.         I915_WRITE(_TRANSA_CHICKEN2, val);
  1650. }
  1651.  
  1652. /**
  1653.  * intel_enable_pipe - enable a pipe, asserting requirements
  1654.  * @dev_priv: i915 private structure
  1655.  * @pipe: pipe to enable
  1656.  * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1657.  *
  1658.  * Enable @pipe, making sure that various hardware specific requirements
  1659.  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1660.  *
  1661.  * @pipe should be %PIPE_A or %PIPE_B.
  1662.  *
  1663.  * Will wait until the pipe is actually running (i.e. first vblank) before
  1664.  * returning.
  1665.  */
  1666. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1667.                               bool pch_port)
  1668. {
  1669.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1670.                                                                       pipe);
  1671.         enum pipe pch_transcoder;
  1672.         int reg;
  1673.         u32 val;
  1674.  
  1675.         assert_planes_disabled(dev_priv, pipe);
  1676.         assert_sprites_disabled(dev_priv, pipe);
  1677.  
  1678.         if (HAS_PCH_LPT(dev_priv->dev))
  1679.                 pch_transcoder = TRANSCODER_A;
  1680.         else
  1681.                 pch_transcoder = pipe;
  1682.  
  1683.         /*
  1684.          * A pipe without a PLL won't actually be able to drive bits from
  1685.          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
  1686.          * need the check.
  1687.          */
  1688.         if (!HAS_PCH_SPLIT(dev_priv->dev))
  1689.                 assert_pll_enabled(dev_priv, pipe);
  1690.         else {
  1691.                 if (pch_port) {
  1692.                         /* if driving the PCH, we need FDI enabled */
  1693.                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
  1694.                         assert_fdi_tx_pll_enabled(dev_priv,
  1695.                                                   (enum pipe) cpu_transcoder);
  1696.                 }
  1697.                 /* FIXME: assert CPU port conditions for SNB+ */
  1698.         }
  1699.  
  1700.         reg = PIPECONF(cpu_transcoder);
  1701.         val = I915_READ(reg);
  1702.         if (val & PIPECONF_ENABLE)
  1703.                 return;
  1704.  
  1705.         I915_WRITE(reg, val | PIPECONF_ENABLE);
  1706.         intel_wait_for_vblank(dev_priv->dev, pipe);
  1707. }
  1708.  
  1709. /**
  1710.  * intel_disable_pipe - disable a pipe, asserting requirements
  1711.  * @dev_priv: i915 private structure
  1712.  * @pipe: pipe to disable
  1713.  *
  1714.  * Disable @pipe, making sure that various hardware specific requirements
  1715.  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1716.  *
  1717.  * @pipe should be %PIPE_A or %PIPE_B.
  1718.  *
  1719.  * Will wait until the pipe has shut down before returning.
  1720.  */
  1721. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1722.                                enum pipe pipe)
  1723. {
  1724.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1725.                                                                       pipe);
  1726.         int reg;
  1727.         u32 val;
  1728.  
  1729.     /*
  1730.          * Make sure planes won't keep trying to pump pixels to us,
  1731.          * or we might hang the display.
  1732.          */
  1733.         assert_planes_disabled(dev_priv, pipe);
  1734.         assert_sprites_disabled(dev_priv, pipe);
  1735.  
  1736.         /* Don't disable pipe A or pipe A PLLs if needed */
  1737.         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1738.                 return;
  1739.  
  1740.         reg = PIPECONF(cpu_transcoder);
  1741.         val = I915_READ(reg);
  1742.         if ((val & PIPECONF_ENABLE) == 0)
  1743.                 return;
  1744.  
  1745.         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1746.         intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1747. }
  1748.  
  1749. /*
  1750.  * Plane regs are double buffered, going from enabled->disabled needs a
  1751.  * trigger in order to latch.  The display address reg provides this.
  1752.  */
  1753. void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1754.                                       enum plane plane)
  1755. {
  1756.         if (dev_priv->info->gen >= 4)
  1757.                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
  1758.         else
  1759.         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
  1760. }
  1761.  
  1762. /**
  1763.  * intel_enable_plane - enable a display plane on a given pipe
  1764.  * @dev_priv: i915 private structure
  1765.  * @plane: plane to enable
  1766.  * @pipe: pipe being fed
  1767.  *
  1768.  * Enable @plane on @pipe, making sure that @pipe is running first.
  1769.  */
  1770. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1771.                                enum plane plane, enum pipe pipe)
  1772. {
  1773.         int reg;
  1774.         u32 val;
  1775.  
  1776.         /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1777.         assert_pipe_enabled(dev_priv, pipe);
  1778.  
  1779.         reg = DSPCNTR(plane);
  1780.         val = I915_READ(reg);
  1781.         if (val & DISPLAY_PLANE_ENABLE)
  1782.                 return;
  1783.  
  1784.         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1785.         intel_flush_display_plane(dev_priv, plane);
  1786.         intel_wait_for_vblank(dev_priv->dev, pipe);
  1787. }
  1788.  
  1789. /**
  1790.  * intel_disable_plane - disable a display plane
  1791.  * @dev_priv: i915 private structure
  1792.  * @plane: plane to disable
  1793.  * @pipe: pipe consuming the data
  1794.  *
  1795.  * Disable @plane; should be an independent operation.
  1796.  */
  1797. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1798.                                 enum plane plane, enum pipe pipe)
  1799. {
  1800.         int reg;
  1801.         u32 val;
  1802.  
  1803.         reg = DSPCNTR(plane);
  1804.         val = I915_READ(reg);
  1805.         if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1806.                 return;
  1807.  
  1808.         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1809.         intel_flush_display_plane(dev_priv, plane);
  1810.     intel_wait_for_vblank(dev_priv->dev, pipe);
  1811. }
  1812.  
  1813. static bool need_vtd_wa(struct drm_device *dev)
  1814. {
  1815. #ifdef CONFIG_INTEL_IOMMU
  1816.         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
  1817.                 return true;
  1818. #endif
  1819.         return false;
  1820. }
  1821.  
  1822. int
  1823. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1824.                            struct drm_i915_gem_object *obj,
  1825.                            struct intel_ring_buffer *pipelined)
  1826. {
  1827.         struct drm_i915_private *dev_priv = dev->dev_private;
  1828.         u32 alignment;
  1829.         int ret;
  1830.  
  1831.         switch (obj->tiling_mode) {
  1832.         case I915_TILING_NONE:
  1833.                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1834.                         alignment = 128 * 1024;
  1835.                 else if (INTEL_INFO(dev)->gen >= 4)
  1836.                         alignment = 4 * 1024;
  1837.                 else
  1838.                         alignment = 64 * 1024;
  1839.                 break;
  1840.         case I915_TILING_X:
  1841.                 /* pin() will align the object as required by fence */
  1842.                 alignment = 0;
  1843.                 break;
  1844.         case I915_TILING_Y:
  1845.                 /* Despite that we check this in framebuffer_init userspace can
  1846.                  * screw us over and change the tiling after the fact. Only
  1847.                  * pinned buffers can't change their tiling. */
  1848.                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
  1849.                 return -EINVAL;
  1850.         default:
  1851.                 BUG();
  1852.         }
  1853.  
  1854.         /* Note that the w/a also requires 64 PTE of padding following the
  1855.          * bo. We currently fill all unused PTE with the shadow page and so
  1856.          * we should always have valid PTE following the scanout preventing
  1857.          * the VT-d warning.
  1858.          */
  1859.         if (need_vtd_wa(dev) && alignment < 256 * 1024)
  1860.                 alignment = 256 * 1024;
  1861.  
  1862.         dev_priv->mm.interruptible = false;
  1863.         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1864.         if (ret)
  1865.                 goto err_interruptible;
  1866.  
  1867.         /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1868.          * fence, whereas 965+ only requires a fence if using
  1869.          * framebuffer compression.  For simplicity, we always install
  1870.          * a fence as the cost is not that onerous.
  1871.          */
  1872.         ret = i915_gem_object_get_fence(obj);
  1873.         if (ret)
  1874.                 goto err_unpin;
  1875.  
  1876.         i915_gem_object_pin_fence(obj);
  1877.  
  1878.         dev_priv->mm.interruptible = true;
  1879.  
  1880.         return 0;
  1881.  
  1882. err_unpin:
  1883.         i915_gem_object_unpin_from_display_plane(obj);
  1884. err_interruptible:
  1885.         dev_priv->mm.interruptible = true;
  1886.         return ret;
  1887. }
  1888.  
  1889. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
  1890. {
  1891. //      i915_gem_object_unpin_fence(obj);
  1892. //      i915_gem_object_unpin(obj);
  1893. }
  1894.  
  1895. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  1896.  * is assumed to be a power-of-two. */
  1897. unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  1898.                                              unsigned int tiling_mode,
  1899.                                              unsigned int cpp,
  1900.                                                         unsigned int pitch)
  1901. {
  1902.         if (tiling_mode != I915_TILING_NONE) {
  1903.                 unsigned int tile_rows, tiles;
  1904.  
  1905.         tile_rows = *y / 8;
  1906.         *y %= 8;
  1907.  
  1908.                 tiles = *x / (512/cpp);
  1909.                 *x %= 512/cpp;
  1910.  
  1911.         return tile_rows * pitch * 8 + tiles * 4096;
  1912.         } else {
  1913.                 unsigned int offset;
  1914.  
  1915.                 offset = *y * pitch + *x * cpp;
  1916.                 *y = 0;
  1917.                 *x = (offset & 4095) / cpp;
  1918.                 return offset & -4096;
  1919.         }
  1920. }
  1921.  
  1922. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1923.                  int x, int y)
  1924. {
  1925.     struct drm_device *dev = crtc->dev;
  1926.     struct drm_i915_private *dev_priv = dev->dev_private;
  1927.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1928.     struct intel_framebuffer *intel_fb;
  1929.     struct drm_i915_gem_object *obj;
  1930.     int plane = intel_crtc->plane;
  1931.         unsigned long linear_offset;
  1932.     u32 dspcntr;
  1933.     u32 reg;
  1934.  
  1935.     switch (plane) {
  1936.     case 0:
  1937.     case 1:
  1938.         break;
  1939.     default:
  1940.                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1941.         return -EINVAL;
  1942.     }
  1943.  
  1944.     intel_fb = to_intel_framebuffer(fb);
  1945.     obj = intel_fb->obj;
  1946.  
  1947.     reg = DSPCNTR(plane);
  1948.     dspcntr = I915_READ(reg);
  1949.     /* Mask out pixel format bits in case we change it */
  1950.     dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1951.         switch (fb->pixel_format) {
  1952.         case DRM_FORMAT_C8:
  1953.         dspcntr |= DISPPLANE_8BPP;
  1954.         break;
  1955.         case DRM_FORMAT_XRGB1555:
  1956.         case DRM_FORMAT_ARGB1555:
  1957.                 dspcntr |= DISPPLANE_BGRX555;
  1958.                 break;
  1959.         case DRM_FORMAT_RGB565:
  1960.                 dspcntr |= DISPPLANE_BGRX565;
  1961.                 break;
  1962.         case DRM_FORMAT_XRGB8888:
  1963.         case DRM_FORMAT_ARGB8888:
  1964.                 dspcntr |= DISPPLANE_BGRX888;
  1965.                 break;
  1966.         case DRM_FORMAT_XBGR8888:
  1967.         case DRM_FORMAT_ABGR8888:
  1968.                 dspcntr |= DISPPLANE_RGBX888;
  1969.                 break;
  1970.         case DRM_FORMAT_XRGB2101010:
  1971.         case DRM_FORMAT_ARGB2101010:
  1972.                 dspcntr |= DISPPLANE_BGRX101010;
  1973.         break;
  1974.         case DRM_FORMAT_XBGR2101010:
  1975.         case DRM_FORMAT_ABGR2101010:
  1976.                 dspcntr |= DISPPLANE_RGBX101010;
  1977.         break;
  1978.     default:
  1979.                 BUG();
  1980.     }
  1981.  
  1982.     if (INTEL_INFO(dev)->gen >= 4) {
  1983.         if (obj->tiling_mode != I915_TILING_NONE)
  1984.             dspcntr |= DISPPLANE_TILED;
  1985.         else
  1986.             dspcntr &= ~DISPPLANE_TILED;
  1987.     }
  1988.  
  1989.         if (IS_G4X(dev))
  1990.                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1991.  
  1992.     I915_WRITE(reg, dspcntr);
  1993.  
  1994.         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1995.  
  1996.         if (INTEL_INFO(dev)->gen >= 4) {
  1997.                 intel_crtc->dspaddr_offset =
  1998.                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1999.                                                            fb->bits_per_pixel / 8,
  2000.                                                            fb->pitches[0]);
  2001.                 linear_offset -= intel_crtc->dspaddr_offset;
  2002.         } else {
  2003.                 intel_crtc->dspaddr_offset = linear_offset;
  2004.         }
  2005.  
  2006.         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  2007.                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  2008.                       fb->pitches[0]);
  2009.         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  2010.     if (INTEL_INFO(dev)->gen >= 4) {
  2011.                 I915_MODIFY_DISPBASE(DSPSURF(plane),
  2012.                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  2013.         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  2014.                 I915_WRITE(DSPLINOFF(plane), linear_offset);
  2015.     } else
  2016.                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
  2017.     POSTING_READ(reg);
  2018.  
  2019.     return 0;
  2020. }
  2021.  
  2022. static int ironlake_update_plane(struct drm_crtc *crtc,
  2023.                  struct drm_framebuffer *fb, int x, int y)
  2024. {
  2025.     struct drm_device *dev = crtc->dev;
  2026.     struct drm_i915_private *dev_priv = dev->dev_private;
  2027.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2028.     struct intel_framebuffer *intel_fb;
  2029.     struct drm_i915_gem_object *obj;
  2030.     int plane = intel_crtc->plane;
  2031.         unsigned long linear_offset;
  2032.     u32 dspcntr;
  2033.     u32 reg;
  2034.  
  2035.     switch (plane) {
  2036.     case 0:
  2037.     case 1:
  2038.         case 2:
  2039.         break;
  2040.     default:
  2041.                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  2042.         return -EINVAL;
  2043.     }
  2044.  
  2045.     intel_fb = to_intel_framebuffer(fb);
  2046.     obj = intel_fb->obj;
  2047.  
  2048.     reg = DSPCNTR(plane);
  2049.     dspcntr = I915_READ(reg);
  2050.     /* Mask out pixel format bits in case we change it */
  2051.     dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  2052.         switch (fb->pixel_format) {
  2053.         case DRM_FORMAT_C8:
  2054.         dspcntr |= DISPPLANE_8BPP;
  2055.         break;
  2056.         case DRM_FORMAT_RGB565:
  2057.                 dspcntr |= DISPPLANE_BGRX565;
  2058.         break;
  2059.         case DRM_FORMAT_XRGB8888:
  2060.         case DRM_FORMAT_ARGB8888:
  2061.                 dspcntr |= DISPPLANE_BGRX888;
  2062.                 break;
  2063.         case DRM_FORMAT_XBGR8888:
  2064.         case DRM_FORMAT_ABGR8888:
  2065.                 dspcntr |= DISPPLANE_RGBX888;
  2066.                 break;
  2067.         case DRM_FORMAT_XRGB2101010:
  2068.         case DRM_FORMAT_ARGB2101010:
  2069.                 dspcntr |= DISPPLANE_BGRX101010;
  2070.                 break;
  2071.         case DRM_FORMAT_XBGR2101010:
  2072.         case DRM_FORMAT_ABGR2101010:
  2073.                 dspcntr |= DISPPLANE_RGBX101010;
  2074.         break;
  2075.     default:
  2076.                 BUG();
  2077.     }
  2078.  
  2079.         if (obj->tiling_mode != I915_TILING_NONE)
  2080.                 dspcntr |= DISPPLANE_TILED;
  2081.         else
  2082.         dspcntr &= ~DISPPLANE_TILED;
  2083.  
  2084.         if (IS_HASWELL(dev))
  2085.                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
  2086.         else
  2087.     dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  2088.  
  2089.     I915_WRITE(reg, dspcntr);
  2090.  
  2091.         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  2092.         intel_crtc->dspaddr_offset =
  2093.                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  2094.                                                    fb->bits_per_pixel / 8,
  2095.                                                    fb->pitches[0]);
  2096.         linear_offset -= intel_crtc->dspaddr_offset;
  2097.  
  2098.         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  2099.                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  2100.                       fb->pitches[0]);
  2101.         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  2102.         I915_MODIFY_DISPBASE(DSPSURF(plane),
  2103.                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  2104.         if (IS_HASWELL(dev)) {
  2105.                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
  2106.         } else {
  2107.         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  2108.         I915_WRITE(DSPLINOFF(plane), linear_offset);
  2109.         }
  2110.         POSTING_READ(reg);
  2111.  
  2112.     return 0;
  2113. }
  2114.  
  2115. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  2116. static int
  2117. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  2118.                            int x, int y, enum mode_set_atomic state)
  2119. {
  2120.         struct drm_device *dev = crtc->dev;
  2121.         struct drm_i915_private *dev_priv = dev->dev_private;
  2122.  
  2123.         if (dev_priv->display.disable_fbc)
  2124.                 dev_priv->display.disable_fbc(dev);
  2125.         intel_increase_pllclock(crtc);
  2126.  
  2127.         return dev_priv->display.update_plane(crtc, fb, x, y);
  2128. }
  2129.  
  2130. #if 0
  2131. void intel_display_handle_reset(struct drm_device *dev)
  2132. {
  2133.         struct drm_i915_private *dev_priv = dev->dev_private;
  2134.         struct drm_crtc *crtc;
  2135.  
  2136.         /*
  2137.          * Flips in the rings have been nuked by the reset,
  2138.          * so complete all pending flips so that user space
  2139.          * will get its events and not get stuck.
  2140.          *
  2141.          * Also update the base address of all primary
  2142.          * planes to the the last fb to make sure we're
  2143.          * showing the correct fb after a reset.
  2144.          *
  2145.          * Need to make two loops over the crtcs so that we
  2146.          * don't try to grab a crtc mutex before the
  2147.          * pending_flip_queue really got woken up.
  2148.          */
  2149.  
  2150.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2151.                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2152.                 enum plane plane = intel_crtc->plane;
  2153.  
  2154.                 intel_prepare_page_flip(dev, plane);
  2155.                 intel_finish_page_flip_plane(dev, plane);
  2156.         }
  2157.  
  2158.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2159.                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2160.  
  2161.                 mutex_lock(&crtc->mutex);
  2162.                 if (intel_crtc->active)
  2163.                         dev_priv->display.update_plane(crtc, crtc->fb,
  2164.                                                        crtc->x, crtc->y);
  2165.                 mutex_unlock(&crtc->mutex);
  2166.         }
  2167. }
  2168.  
  2169. static int
  2170. intel_finish_fb(struct drm_framebuffer *old_fb)
  2171. {
  2172.         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  2173.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  2174.         bool was_interruptible = dev_priv->mm.interruptible;
  2175.         int ret;
  2176.  
  2177.         /* Big Hammer, we also need to ensure that any pending
  2178.          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  2179.          * current scanout is retired before unpinning the old
  2180.          * framebuffer.
  2181.          *
  2182.          * This should only fail upon a hung GPU, in which case we
  2183.          * can safely continue.
  2184.          */
  2185.         dev_priv->mm.interruptible = false;
  2186.         ret = i915_gem_object_finish_gpu(obj);
  2187.         dev_priv->mm.interruptible = was_interruptible;
  2188.  
  2189.         return ret;
  2190. }
  2191.  
  2192. static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
  2193. {
  2194.         struct drm_device *dev = crtc->dev;
  2195.         struct drm_i915_master_private *master_priv;
  2196.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2197.  
  2198.         if (!dev->primary->master)
  2199.                 return;
  2200.  
  2201.         master_priv = dev->primary->master->driver_priv;
  2202.         if (!master_priv->sarea_priv)
  2203.                 return;
  2204.  
  2205.         switch (intel_crtc->pipe) {
  2206.         case 0:
  2207.                 master_priv->sarea_priv->pipeA_x = x;
  2208.                 master_priv->sarea_priv->pipeA_y = y;
  2209.                 break;
  2210.         case 1:
  2211.                 master_priv->sarea_priv->pipeB_x = x;
  2212.                 master_priv->sarea_priv->pipeB_y = y;
  2213.                 break;
  2214.         default:
  2215.                 break;
  2216.         }
  2217. }
  2218. #endif
  2219.  
  2220. static int
  2221. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  2222.                     struct drm_framebuffer *fb)
  2223. {
  2224.         struct drm_device *dev = crtc->dev;
  2225.         struct drm_i915_private *dev_priv = dev->dev_private;
  2226.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2227.         struct drm_framebuffer *old_fb;
  2228.         int ret;
  2229.  
  2230.         /* no fb bound */
  2231.         if (!fb) {
  2232.                 DRM_ERROR("No FB bound\n");
  2233.                 return 0;
  2234.         }
  2235.  
  2236.         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
  2237.                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
  2238.                           plane_name(intel_crtc->plane),
  2239.                                 INTEL_INFO(dev)->num_pipes);
  2240.                 return -EINVAL;
  2241.         }
  2242.  
  2243.         mutex_lock(&dev->struct_mutex);
  2244.     ret = intel_pin_and_fence_fb_obj(dev,
  2245.                     to_intel_framebuffer(fb)->obj,
  2246.                     NULL);
  2247.     if (ret != 0) {
  2248.        mutex_unlock(&dev->struct_mutex);
  2249.        DRM_ERROR("pin & fence failed\n");
  2250.        return ret;
  2251.     }
  2252.  
  2253.         /* Update pipe size and adjust fitter if needed */
  2254.         if (i915_fastboot) {
  2255.                 I915_WRITE(PIPESRC(intel_crtc->pipe),
  2256.                            ((crtc->mode.hdisplay - 1) << 16) |
  2257.                            (crtc->mode.vdisplay - 1));
  2258.                 if (!intel_crtc->config.pch_pfit.enabled &&
  2259.                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
  2260.                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2261.                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
  2262.                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
  2263.                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
  2264.                 }
  2265.         }
  2266.  
  2267.         ret = dev_priv->display.update_plane(crtc, fb, x, y);
  2268.         if (ret) {
  2269.                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
  2270.                 mutex_unlock(&dev->struct_mutex);
  2271.                 DRM_ERROR("failed to update base address\n");
  2272.         return ret;
  2273.         }
  2274.  
  2275.         old_fb = crtc->fb;
  2276.         crtc->fb = fb;
  2277.         crtc->x = x;
  2278.         crtc->y = y;
  2279.  
  2280.         if (old_fb) {
  2281.                 if (intel_crtc->active && old_fb != fb)
  2282.                 intel_wait_for_vblank(dev, intel_crtc->pipe);
  2283.                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
  2284.         }
  2285.  
  2286.         intel_update_fbc(dev);
  2287.         intel_edp_psr_update(dev);
  2288.         mutex_unlock(&dev->struct_mutex);
  2289.  
  2290.     return 0;
  2291. }
  2292.  
  2293. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  2294. {
  2295.         struct drm_device *dev = crtc->dev;
  2296.         struct drm_i915_private *dev_priv = dev->dev_private;
  2297.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2298.         int pipe = intel_crtc->pipe;
  2299.         u32 reg, temp;
  2300.  
  2301.         /* enable normal train */
  2302.         reg = FDI_TX_CTL(pipe);
  2303.         temp = I915_READ(reg);
  2304.         if (IS_IVYBRIDGE(dev)) {
  2305.                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2306.                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2307.         } else {
  2308.                 temp &= ~FDI_LINK_TRAIN_NONE;
  2309.                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2310.         }
  2311.         I915_WRITE(reg, temp);
  2312.  
  2313.         reg = FDI_RX_CTL(pipe);
  2314.         temp = I915_READ(reg);
  2315.         if (HAS_PCH_CPT(dev)) {
  2316.                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2317.                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2318.         } else {
  2319.                 temp &= ~FDI_LINK_TRAIN_NONE;
  2320.                 temp |= FDI_LINK_TRAIN_NONE;
  2321.         }
  2322.         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2323.  
  2324.         /* wait one idle pattern time */
  2325.         POSTING_READ(reg);
  2326.         udelay(1000);
  2327.  
  2328.         /* IVB wants error correction enabled */
  2329.         if (IS_IVYBRIDGE(dev))
  2330.                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2331.                            FDI_FE_ERRC_ENABLE);
  2332. }
  2333.  
  2334. static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
  2335. {
  2336.         return crtc->base.enabled && crtc->active &&
  2337.                 crtc->config.has_pch_encoder;
  2338. }
  2339.  
  2340. static void ivb_modeset_global_resources(struct drm_device *dev)
  2341. {
  2342.         struct drm_i915_private *dev_priv = dev->dev_private;
  2343.         struct intel_crtc *pipe_B_crtc =
  2344.                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  2345.         struct intel_crtc *pipe_C_crtc =
  2346.                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
  2347.         uint32_t temp;
  2348.  
  2349.         /*
  2350.          * When everything is off disable fdi C so that we could enable fdi B
  2351.          * with all lanes. Note that we don't care about enabled pipes without
  2352.          * an enabled pch encoder.
  2353.          */
  2354.         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
  2355.             !pipe_has_enabled_pch(pipe_C_crtc)) {
  2356.                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  2357.                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  2358.  
  2359.                 temp = I915_READ(SOUTH_CHICKEN1);
  2360.                 temp &= ~FDI_BC_BIFURCATION_SELECT;
  2361.                 DRM_DEBUG_KMS("disabling fdi C rx\n");
  2362.                 I915_WRITE(SOUTH_CHICKEN1, temp);
  2363.         }
  2364. }
  2365.  
  2366. /* The FDI link training functions for ILK/Ibexpeak. */
  2367. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2368. {
  2369.     struct drm_device *dev = crtc->dev;
  2370.     struct drm_i915_private *dev_priv = dev->dev_private;
  2371.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2372.     int pipe = intel_crtc->pipe;
  2373.     int plane = intel_crtc->plane;
  2374.     u32 reg, temp, tries;
  2375.  
  2376.     /* FDI needs bits from pipe & plane first */
  2377.     assert_pipe_enabled(dev_priv, pipe);
  2378.     assert_plane_enabled(dev_priv, plane);
  2379.  
  2380.     /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2381.        for train result */
  2382.     reg = FDI_RX_IMR(pipe);
  2383.     temp = I915_READ(reg);
  2384.     temp &= ~FDI_RX_SYMBOL_LOCK;
  2385.     temp &= ~FDI_RX_BIT_LOCK;
  2386.     I915_WRITE(reg, temp);
  2387.     I915_READ(reg);
  2388.     udelay(150);
  2389.  
  2390.     /* enable CPU FDI TX and PCH FDI RX */
  2391.     reg = FDI_TX_CTL(pipe);
  2392.     temp = I915_READ(reg);
  2393.         temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2394.         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2395.     temp &= ~FDI_LINK_TRAIN_NONE;
  2396.     temp |= FDI_LINK_TRAIN_PATTERN_1;
  2397.     I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2398.  
  2399.     reg = FDI_RX_CTL(pipe);
  2400.     temp = I915_READ(reg);
  2401.     temp &= ~FDI_LINK_TRAIN_NONE;
  2402.     temp |= FDI_LINK_TRAIN_PATTERN_1;
  2403.     I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2404.  
  2405.     POSTING_READ(reg);
  2406.     udelay(150);
  2407.  
  2408.     /* Ironlake workaround, enable clock pointer after FDI enable*/
  2409.         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2410.         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2411.                FDI_RX_PHASE_SYNC_POINTER_EN);
  2412.  
  2413.     reg = FDI_RX_IIR(pipe);
  2414.     for (tries = 0; tries < 5; tries++) {
  2415.         temp = I915_READ(reg);
  2416.         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2417.  
  2418.         if ((temp & FDI_RX_BIT_LOCK)) {
  2419.             DRM_DEBUG_KMS("FDI train 1 done.\n");
  2420.             I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2421.             break;
  2422.         }
  2423.     }
  2424.     if (tries == 5)
  2425.         DRM_ERROR("FDI train 1 fail!\n");
  2426.  
  2427.     /* Train 2 */
  2428.     reg = FDI_TX_CTL(pipe);
  2429.     temp = I915_READ(reg);
  2430.     temp &= ~FDI_LINK_TRAIN_NONE;
  2431.     temp |= FDI_LINK_TRAIN_PATTERN_2;
  2432.     I915_WRITE(reg, temp);
  2433.  
  2434.     reg = FDI_RX_CTL(pipe);
  2435.     temp = I915_READ(reg);
  2436.     temp &= ~FDI_LINK_TRAIN_NONE;
  2437.     temp |= FDI_LINK_TRAIN_PATTERN_2;
  2438.     I915_WRITE(reg, temp);
  2439.  
  2440.     POSTING_READ(reg);
  2441.     udelay(150);
  2442.  
  2443.     reg = FDI_RX_IIR(pipe);
  2444.     for (tries = 0; tries < 5; tries++) {
  2445.         temp = I915_READ(reg);
  2446.         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2447.  
  2448.         if (temp & FDI_RX_SYMBOL_LOCK) {
  2449.             I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2450.             DRM_DEBUG_KMS("FDI train 2 done.\n");
  2451.             break;
  2452.         }
  2453.     }
  2454.     if (tries == 5)
  2455.         DRM_ERROR("FDI train 2 fail!\n");
  2456.  
  2457.     DRM_DEBUG_KMS("FDI train done\n");
  2458.  
  2459. }
  2460.  
  2461. static const int snb_b_fdi_train_param[] = {
  2462.     FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2463.     FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2464.     FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2465.     FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2466. };
  2467.  
  2468. /* The FDI link training functions for SNB/Cougarpoint. */
  2469. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2470. {
  2471.     struct drm_device *dev = crtc->dev;
  2472.     struct drm_i915_private *dev_priv = dev->dev_private;
  2473.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2474.     int pipe = intel_crtc->pipe;
  2475.         u32 reg, temp, i, retry;
  2476.  
  2477.     /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2478.        for train result */
  2479.     reg = FDI_RX_IMR(pipe);
  2480.     temp = I915_READ(reg);
  2481.     temp &= ~FDI_RX_SYMBOL_LOCK;
  2482.     temp &= ~FDI_RX_BIT_LOCK;
  2483.     I915_WRITE(reg, temp);
  2484.  
  2485.     POSTING_READ(reg);
  2486.     udelay(150);
  2487.  
  2488.     /* enable CPU FDI TX and PCH FDI RX */
  2489.     reg = FDI_TX_CTL(pipe);
  2490.     temp = I915_READ(reg);
  2491.         temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2492.         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2493.     temp &= ~FDI_LINK_TRAIN_NONE;
  2494.     temp |= FDI_LINK_TRAIN_PATTERN_1;
  2495.     temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2496.     /* SNB-B */
  2497.     temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2498.     I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2499.  
  2500.         I915_WRITE(FDI_RX_MISC(pipe),
  2501.                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2502.  
  2503.     reg = FDI_RX_CTL(pipe);
  2504.     temp = I915_READ(reg);
  2505.     if (HAS_PCH_CPT(dev)) {
  2506.         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2507.         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2508.     } else {
  2509.         temp &= ~FDI_LINK_TRAIN_NONE;
  2510.         temp |= FDI_LINK_TRAIN_PATTERN_1;
  2511.     }
  2512.     I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2513.  
  2514.     POSTING_READ(reg);
  2515.     udelay(150);
  2516.  
  2517.         for (i = 0; i < 4; i++) {
  2518.         reg = FDI_TX_CTL(pipe);
  2519.         temp = I915_READ(reg);
  2520.         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2521.         temp |= snb_b_fdi_train_param[i];
  2522.         I915_WRITE(reg, temp);
  2523.  
  2524.         POSTING_READ(reg);
  2525.         udelay(500);
  2526.  
  2527.                 for (retry = 0; retry < 5; retry++) {
  2528.         reg = FDI_RX_IIR(pipe);
  2529.         temp = I915_READ(reg);
  2530.         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2531.         if (temp & FDI_RX_BIT_LOCK) {
  2532.             I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2533.             DRM_DEBUG_KMS("FDI train 1 done.\n");
  2534.             break;
  2535.         }
  2536.                         udelay(50);
  2537.                 }
  2538.                 if (retry < 5)
  2539.                         break;
  2540.     }
  2541.     if (i == 4)
  2542.         DRM_ERROR("FDI train 1 fail!\n");
  2543.  
  2544.     /* Train 2 */
  2545.     reg = FDI_TX_CTL(pipe);
  2546.     temp = I915_READ(reg);
  2547.     temp &= ~FDI_LINK_TRAIN_NONE;
  2548.     temp |= FDI_LINK_TRAIN_PATTERN_2;
  2549.     if (IS_GEN6(dev)) {
  2550.         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2551.         /* SNB-B */
  2552.         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2553.     }
  2554.     I915_WRITE(reg, temp);
  2555.  
  2556.     reg = FDI_RX_CTL(pipe);
  2557.     temp = I915_READ(reg);
  2558.     if (HAS_PCH_CPT(dev)) {
  2559.         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2560.         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2561.     } else {
  2562.         temp &= ~FDI_LINK_TRAIN_NONE;
  2563.         temp |= FDI_LINK_TRAIN_PATTERN_2;
  2564.     }
  2565.     I915_WRITE(reg, temp);
  2566.  
  2567.     POSTING_READ(reg);
  2568.     udelay(150);
  2569.  
  2570.         for (i = 0; i < 4; i++) {
  2571.         reg = FDI_TX_CTL(pipe);
  2572.         temp = I915_READ(reg);
  2573.         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2574.         temp |= snb_b_fdi_train_param[i];
  2575.         I915_WRITE(reg, temp);
  2576.  
  2577.         POSTING_READ(reg);
  2578.         udelay(500);
  2579.  
  2580.                 for (retry = 0; retry < 5; retry++) {
  2581.         reg = FDI_RX_IIR(pipe);
  2582.         temp = I915_READ(reg);
  2583.         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2584.         if (temp & FDI_RX_SYMBOL_LOCK) {
  2585.             I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2586.             DRM_DEBUG_KMS("FDI train 2 done.\n");
  2587.             break;
  2588.         }
  2589.                         udelay(50);
  2590.                 }
  2591.                 if (retry < 5)
  2592.                         break;
  2593.     }
  2594.     if (i == 4)
  2595.         DRM_ERROR("FDI train 2 fail!\n");
  2596.  
  2597.     DRM_DEBUG_KMS("FDI train done.\n");
  2598. }
  2599.  
  2600. /* Manual link training for Ivy Bridge A0 parts */
  2601. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2602. {
  2603.     struct drm_device *dev = crtc->dev;
  2604.     struct drm_i915_private *dev_priv = dev->dev_private;
  2605.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2606.     int pipe = intel_crtc->pipe;
  2607.         u32 reg, temp, i, j;
  2608.  
  2609.     /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2610.        for train result */
  2611.     reg = FDI_RX_IMR(pipe);
  2612.     temp = I915_READ(reg);
  2613.     temp &= ~FDI_RX_SYMBOL_LOCK;
  2614.     temp &= ~FDI_RX_BIT_LOCK;
  2615.     I915_WRITE(reg, temp);
  2616.  
  2617.     POSTING_READ(reg);
  2618.     udelay(150);
  2619.  
  2620.         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
  2621.                       I915_READ(FDI_RX_IIR(pipe)));
  2622.  
  2623.         /* Try each vswing and preemphasis setting twice before moving on */
  2624.         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
  2625.                 /* disable first in case we need to retry */
  2626.                 reg = FDI_TX_CTL(pipe);
  2627.                 temp = I915_READ(reg);
  2628.                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2629.                 temp &= ~FDI_TX_ENABLE;
  2630.                 I915_WRITE(reg, temp);
  2631.  
  2632.                 reg = FDI_RX_CTL(pipe);
  2633.                 temp = I915_READ(reg);
  2634.                 temp &= ~FDI_LINK_TRAIN_AUTO;
  2635.                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2636.                 temp &= ~FDI_RX_ENABLE;
  2637.                 I915_WRITE(reg, temp);
  2638.  
  2639.     /* enable CPU FDI TX and PCH FDI RX */
  2640.     reg = FDI_TX_CTL(pipe);
  2641.     temp = I915_READ(reg);
  2642.         temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2643.         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2644.     temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2645.     temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2646.                 temp |= snb_b_fdi_train_param[j/2];
  2647.         temp |= FDI_COMPOSITE_SYNC;
  2648.     I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2649.  
  2650.         I915_WRITE(FDI_RX_MISC(pipe),
  2651.                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2652.  
  2653.     reg = FDI_RX_CTL(pipe);
  2654.     temp = I915_READ(reg);
  2655.     temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2656.         temp |= FDI_COMPOSITE_SYNC;
  2657.     I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2658.  
  2659.     POSTING_READ(reg);
  2660.                 udelay(1); /* should be 0.5us */
  2661.  
  2662.         for (i = 0; i < 4; i++) {
  2663.         reg = FDI_RX_IIR(pipe);
  2664.         temp = I915_READ(reg);
  2665.         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2666.  
  2667.         if (temp & FDI_RX_BIT_LOCK ||
  2668.             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2669.             I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2670.                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
  2671.                                               i);
  2672.             break;
  2673.         }
  2674.                         udelay(1); /* should be 0.5us */
  2675.                 }
  2676.                 if (i == 4) {
  2677.                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
  2678.                         continue;
  2679.     }
  2680.  
  2681.     /* Train 2 */
  2682.     reg = FDI_TX_CTL(pipe);
  2683.     temp = I915_READ(reg);
  2684.     temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2685.     temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2686.     I915_WRITE(reg, temp);
  2687.  
  2688.     reg = FDI_RX_CTL(pipe);
  2689.     temp = I915_READ(reg);
  2690.     temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2691.     temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2692.     I915_WRITE(reg, temp);
  2693.  
  2694.     POSTING_READ(reg);
  2695.                 udelay(2); /* should be 1.5us */
  2696.  
  2697.         for (i = 0; i < 4; i++) {
  2698.         reg = FDI_RX_IIR(pipe);
  2699.         temp = I915_READ(reg);
  2700.         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2701.  
  2702.                         if (temp & FDI_RX_SYMBOL_LOCK ||
  2703.                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
  2704.             I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2705.                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
  2706.                                               i);
  2707.                                 goto train_done;
  2708.         }
  2709.                         udelay(2); /* should be 1.5us */
  2710.     }
  2711.     if (i == 4)
  2712.                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
  2713.         }
  2714.  
  2715. train_done:
  2716.     DRM_DEBUG_KMS("FDI train done.\n");
  2717. }
  2718.  
  2719. static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
  2720. {
  2721.         struct drm_device *dev = intel_crtc->base.dev;
  2722.         struct drm_i915_private *dev_priv = dev->dev_private;
  2723.         int pipe = intel_crtc->pipe;
  2724.         u32 reg, temp;
  2725.  
  2726.  
  2727.         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2728.         reg = FDI_RX_CTL(pipe);
  2729.         temp = I915_READ(reg);
  2730.         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
  2731.         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2732.         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2733.         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2734.  
  2735.         POSTING_READ(reg);
  2736.         udelay(200);
  2737.  
  2738.         /* Switch from Rawclk to PCDclk */
  2739.         temp = I915_READ(reg);
  2740.         I915_WRITE(reg, temp | FDI_PCDCLK);
  2741.  
  2742.         POSTING_READ(reg);
  2743.         udelay(200);
  2744.  
  2745.         /* Enable CPU FDI TX PLL, always on for Ironlake */
  2746.         reg = FDI_TX_CTL(pipe);
  2747.         temp = I915_READ(reg);
  2748.         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2749.                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2750.  
  2751.                 POSTING_READ(reg);
  2752.                 udelay(100);
  2753.         }
  2754. }
  2755.  
  2756. static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
  2757. {
  2758.         struct drm_device *dev = intel_crtc->base.dev;
  2759.         struct drm_i915_private *dev_priv = dev->dev_private;
  2760.         int pipe = intel_crtc->pipe;
  2761.         u32 reg, temp;
  2762.  
  2763.         /* Switch from PCDclk to Rawclk */
  2764.         reg = FDI_RX_CTL(pipe);
  2765.         temp = I915_READ(reg);
  2766.         I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2767.  
  2768.         /* Disable CPU FDI TX PLL */
  2769.         reg = FDI_TX_CTL(pipe);
  2770.         temp = I915_READ(reg);
  2771.         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2772.  
  2773.         POSTING_READ(reg);
  2774.         udelay(100);
  2775.  
  2776.         reg = FDI_RX_CTL(pipe);
  2777.         temp = I915_READ(reg);
  2778.         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2779.  
  2780.         /* Wait for the clocks to turn off. */
  2781.         POSTING_READ(reg);
  2782.         udelay(100);
  2783. }
  2784.  
  2785. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2786. {
  2787.         struct drm_device *dev = crtc->dev;
  2788.         struct drm_i915_private *dev_priv = dev->dev_private;
  2789.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2790.         int pipe = intel_crtc->pipe;
  2791.         u32 reg, temp;
  2792.  
  2793.         /* disable CPU FDI tx and PCH FDI rx */
  2794.         reg = FDI_TX_CTL(pipe);
  2795.         temp = I915_READ(reg);
  2796.         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2797.         POSTING_READ(reg);
  2798.  
  2799.         reg = FDI_RX_CTL(pipe);
  2800.         temp = I915_READ(reg);
  2801.         temp &= ~(0x7 << 16);
  2802.         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2803.         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2804.  
  2805.         POSTING_READ(reg);
  2806.         udelay(100);
  2807.  
  2808.         /* Ironlake workaround, disable clock pointer after downing FDI */
  2809.         if (HAS_PCH_IBX(dev)) {
  2810.                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2811.         }
  2812.  
  2813.         /* still set train pattern 1 */
  2814.         reg = FDI_TX_CTL(pipe);
  2815.         temp = I915_READ(reg);
  2816.         temp &= ~FDI_LINK_TRAIN_NONE;
  2817.         temp |= FDI_LINK_TRAIN_PATTERN_1;
  2818.         I915_WRITE(reg, temp);
  2819.  
  2820.         reg = FDI_RX_CTL(pipe);
  2821.         temp = I915_READ(reg);
  2822.         if (HAS_PCH_CPT(dev)) {
  2823.                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2824.                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2825.         } else {
  2826.                 temp &= ~FDI_LINK_TRAIN_NONE;
  2827.                 temp |= FDI_LINK_TRAIN_PATTERN_1;
  2828.         }
  2829.         /* BPC in FDI rx is consistent with that in PIPECONF */
  2830.         temp &= ~(0x07 << 16);
  2831.         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2832.         I915_WRITE(reg, temp);
  2833.  
  2834.         POSTING_READ(reg);
  2835.         udelay(100);
  2836. }
  2837.  
  2838. static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
  2839. {
  2840.         struct drm_device *dev = crtc->dev;
  2841.         struct drm_i915_private *dev_priv = dev->dev_private;
  2842.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2843.         unsigned long flags;
  2844.         bool pending;
  2845.  
  2846.         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
  2847.             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
  2848.                 return false;
  2849.  
  2850.         spin_lock_irqsave(&dev->event_lock, flags);
  2851.         pending = to_intel_crtc(crtc)->unpin_work != NULL;
  2852.         spin_unlock_irqrestore(&dev->event_lock, flags);
  2853.  
  2854.         return pending;
  2855. }
  2856.  
  2857. #if 0
  2858. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2859. {
  2860.         struct drm_device *dev = crtc->dev;
  2861.         struct drm_i915_private *dev_priv = dev->dev_private;
  2862.  
  2863.         if (crtc->fb == NULL)
  2864.                 return;
  2865.  
  2866.         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
  2867.  
  2868.         wait_event(dev_priv->pending_flip_queue,
  2869.                    !intel_crtc_has_pending_flip(crtc));
  2870.  
  2871.         mutex_lock(&dev->struct_mutex);
  2872.         intel_finish_fb(crtc->fb);
  2873.         mutex_unlock(&dev->struct_mutex);
  2874. }
  2875. #endif
  2876.  
  2877. /* Program iCLKIP clock to the desired frequency */
  2878. static void lpt_program_iclkip(struct drm_crtc *crtc)
  2879. {
  2880.         struct drm_device *dev = crtc->dev;
  2881.         struct drm_i915_private *dev_priv = dev->dev_private;
  2882.         u32 divsel, phaseinc, auxdiv, phasedir = 0;
  2883.         u32 temp;
  2884.  
  2885.         mutex_lock(&dev_priv->dpio_lock);
  2886.  
  2887.         /* It is necessary to ungate the pixclk gate prior to programming
  2888.          * the divisors, and gate it back when it is done.
  2889.          */
  2890.         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
  2891.  
  2892.         /* Disable SSCCTL */
  2893.         intel_sbi_write(dev_priv, SBI_SSCCTL6,
  2894.                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
  2895.                                 SBI_SSCCTL_DISABLE,
  2896.                         SBI_ICLK);
  2897.  
  2898.         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
  2899.         if (crtc->mode.clock == 20000) {
  2900.                 auxdiv = 1;
  2901.                 divsel = 0x41;
  2902.                 phaseinc = 0x20;
  2903.         } else {
  2904.                 /* The iCLK virtual clock root frequency is in MHz,
  2905.                  * but the crtc->mode.clock in in KHz. To get the divisors,
  2906.                  * it is necessary to divide one by another, so we
  2907.                  * convert the virtual clock precision to KHz here for higher
  2908.                  * precision.
  2909.                  */
  2910.                 u32 iclk_virtual_root_freq = 172800 * 1000;
  2911.                 u32 iclk_pi_range = 64;
  2912.                 u32 desired_divisor, msb_divisor_value, pi_value;
  2913.  
  2914.                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
  2915.                 msb_divisor_value = desired_divisor / iclk_pi_range;
  2916.                 pi_value = desired_divisor % iclk_pi_range;
  2917.  
  2918.                 auxdiv = 0;
  2919.                 divsel = msb_divisor_value - 2;
  2920.                 phaseinc = pi_value;
  2921.         }
  2922.  
  2923.         /* This should not happen with any sane values */
  2924.         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
  2925.                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
  2926.         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
  2927.                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
  2928.  
  2929.         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
  2930.                         crtc->mode.clock,
  2931.                         auxdiv,
  2932.                         divsel,
  2933.                         phasedir,
  2934.                         phaseinc);
  2935.  
  2936.         /* Program SSCDIVINTPHASE6 */
  2937.         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
  2938.         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
  2939.         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
  2940.         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
  2941.         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
  2942.         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
  2943.         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
  2944.         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
  2945.  
  2946.         /* Program SSCAUXDIV */
  2947.         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
  2948.         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
  2949.         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
  2950.         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
  2951.  
  2952.         /* Enable modulator and associated divider */
  2953.         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
  2954.         temp &= ~SBI_SSCCTL_DISABLE;
  2955.         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
  2956.  
  2957.         /* Wait for initialization time */
  2958.         udelay(24);
  2959.  
  2960.         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
  2961.  
  2962.         mutex_unlock(&dev_priv->dpio_lock);
  2963. }
  2964.  
  2965. static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
  2966.                                                 enum pipe pch_transcoder)
  2967. {
  2968.         struct drm_device *dev = crtc->base.dev;
  2969.         struct drm_i915_private *dev_priv = dev->dev_private;
  2970.         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
  2971.  
  2972.         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
  2973.                    I915_READ(HTOTAL(cpu_transcoder)));
  2974.         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
  2975.                    I915_READ(HBLANK(cpu_transcoder)));
  2976.         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
  2977.                    I915_READ(HSYNC(cpu_transcoder)));
  2978.  
  2979.         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
  2980.                    I915_READ(VTOTAL(cpu_transcoder)));
  2981.         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
  2982.                    I915_READ(VBLANK(cpu_transcoder)));
  2983.         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
  2984.                    I915_READ(VSYNC(cpu_transcoder)));
  2985.         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
  2986.                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
  2987. }
  2988.  
  2989. static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
  2990. {
  2991.         struct drm_i915_private *dev_priv = dev->dev_private;
  2992.         uint32_t temp;
  2993.  
  2994.         temp = I915_READ(SOUTH_CHICKEN1);
  2995.         if (temp & FDI_BC_BIFURCATION_SELECT)
  2996.                 return;
  2997.  
  2998.         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  2999.         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  3000.  
  3001.         temp |= FDI_BC_BIFURCATION_SELECT;
  3002.         DRM_DEBUG_KMS("enabling fdi C rx\n");
  3003.         I915_WRITE(SOUTH_CHICKEN1, temp);
  3004.         POSTING_READ(SOUTH_CHICKEN1);
  3005. }
  3006.  
  3007. static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
  3008. {
  3009.         struct drm_device *dev = intel_crtc->base.dev;
  3010.         struct drm_i915_private *dev_priv = dev->dev_private;
  3011.  
  3012.         switch (intel_crtc->pipe) {
  3013.         case PIPE_A:
  3014.                 break;
  3015.         case PIPE_B:
  3016.                 if (intel_crtc->config.fdi_lanes > 2)
  3017.                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
  3018.                 else
  3019.                         cpt_enable_fdi_bc_bifurcation(dev);
  3020.  
  3021.                 break;
  3022.         case PIPE_C:
  3023.                 cpt_enable_fdi_bc_bifurcation(dev);
  3024.  
  3025.                 break;
  3026.         default:
  3027.                 BUG();
  3028.         }
  3029. }
  3030.  
  3031. /*
  3032.  * Enable PCH resources required for PCH ports:
  3033.  *   - PCH PLLs
  3034.  *   - FDI training & RX/TX
  3035.  *   - update transcoder timings
  3036.  *   - DP transcoding bits
  3037.  *   - transcoder
  3038.  */
  3039. static void ironlake_pch_enable(struct drm_crtc *crtc)
  3040. {
  3041.         struct drm_device *dev = crtc->dev;
  3042.         struct drm_i915_private *dev_priv = dev->dev_private;
  3043.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3044.         int pipe = intel_crtc->pipe;
  3045.         u32 reg, temp;
  3046.  
  3047.         assert_pch_transcoder_disabled(dev_priv, pipe);
  3048.  
  3049.         if (IS_IVYBRIDGE(dev))
  3050.                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
  3051.  
  3052.         /* Write the TU size bits before fdi link training, so that error
  3053.          * detection works. */
  3054.         I915_WRITE(FDI_RX_TUSIZE1(pipe),
  3055.                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  3056.  
  3057.         /* For PCH output, training FDI link */
  3058.         dev_priv->display.fdi_link_train(crtc);
  3059.  
  3060.         /* We need to program the right clock selection before writing the pixel
  3061.          * mutliplier into the DPLL. */
  3062.         if (HAS_PCH_CPT(dev)) {
  3063.                 u32 sel;
  3064.  
  3065.                 temp = I915_READ(PCH_DPLL_SEL);
  3066.                 temp |= TRANS_DPLL_ENABLE(pipe);
  3067.                 sel = TRANS_DPLLB_SEL(pipe);
  3068.                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
  3069.                         temp |= sel;
  3070.                 else
  3071.                         temp &= ~sel;
  3072.                 I915_WRITE(PCH_DPLL_SEL, temp);
  3073.         }
  3074.  
  3075.         /* XXX: pch pll's can be enabled any time before we enable the PCH
  3076.          * transcoder, and we actually should do this to not upset any PCH
  3077.          * transcoder that already use the clock when we share it.
  3078.          *
  3079.          * Note that enable_shared_dpll tries to do the right thing, but
  3080.          * get_shared_dpll unconditionally resets the pll - we need that to have
  3081.          * the right LVDS enable sequence. */
  3082.         ironlake_enable_shared_dpll(intel_crtc);
  3083.  
  3084.         /* set transcoder timing, panel must allow it */
  3085.         assert_panel_unlocked(dev_priv, pipe);
  3086.         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
  3087.  
  3088.         intel_fdi_normal_train(crtc);
  3089.  
  3090.         /* For PCH DP, enable TRANS_DP_CTL */
  3091.         if (HAS_PCH_CPT(dev) &&
  3092.             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  3093.              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  3094.                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
  3095.                 reg = TRANS_DP_CTL(pipe);
  3096.                 temp = I915_READ(reg);
  3097.                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
  3098.                           TRANS_DP_SYNC_MASK |
  3099.                           TRANS_DP_BPC_MASK);
  3100.                 temp |= (TRANS_DP_OUTPUT_ENABLE |
  3101.                          TRANS_DP_ENH_FRAMING);
  3102.                 temp |= bpc << 9; /* same format but at 11:9 */
  3103.  
  3104.                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  3105.                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  3106.                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  3107.                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  3108.  
  3109.                 switch (intel_trans_dp_port_sel(crtc)) {
  3110.                 case PCH_DP_B:
  3111.                         temp |= TRANS_DP_PORT_SEL_B;
  3112.                         break;
  3113.                 case PCH_DP_C:
  3114.                         temp |= TRANS_DP_PORT_SEL_C;
  3115.                         break;
  3116.                 case PCH_DP_D:
  3117.                         temp |= TRANS_DP_PORT_SEL_D;
  3118.                         break;
  3119.                 default:
  3120.                         BUG();
  3121.                 }
  3122.  
  3123.                 I915_WRITE(reg, temp);
  3124.         }
  3125.  
  3126.         ironlake_enable_pch_transcoder(dev_priv, pipe);
  3127. }
  3128.  
  3129. static void lpt_pch_enable(struct drm_crtc *crtc)
  3130. {
  3131.         struct drm_device *dev = crtc->dev;
  3132.         struct drm_i915_private *dev_priv = dev->dev_private;
  3133.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3134.         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  3135.  
  3136.         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
  3137.  
  3138.         lpt_program_iclkip(crtc);
  3139.  
  3140.         /* Set transcoder timing. */
  3141.         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
  3142.  
  3143.         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
  3144. }
  3145.  
  3146. static void intel_put_shared_dpll(struct intel_crtc *crtc)
  3147. {
  3148.         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  3149.  
  3150.         if (pll == NULL)
  3151.                 return;
  3152.  
  3153.         if (pll->refcount == 0) {
  3154.                 WARN(1, "bad %s refcount\n", pll->name);
  3155.                 return;
  3156.         }
  3157.  
  3158.         if (--pll->refcount == 0) {
  3159.                 WARN_ON(pll->on);
  3160.                 WARN_ON(pll->active);
  3161.         }
  3162.  
  3163.         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
  3164. }
  3165.  
  3166. static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
  3167. {
  3168.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  3169.         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  3170.         enum intel_dpll_id i;
  3171.  
  3172.         if (pll) {
  3173.                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
  3174.                               crtc->base.base.id, pll->name);
  3175.                 intel_put_shared_dpll(crtc);
  3176.         }
  3177.  
  3178.         if (HAS_PCH_IBX(dev_priv->dev)) {
  3179.                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
  3180.                 i = (enum intel_dpll_id) crtc->pipe;
  3181.                 pll = &dev_priv->shared_dplls[i];
  3182.  
  3183.                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
  3184.                               crtc->base.base.id, pll->name);
  3185.  
  3186.                 goto found;
  3187.         }
  3188.  
  3189.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  3190.                 pll = &dev_priv->shared_dplls[i];
  3191.  
  3192.                 /* Only want to check enabled timings first */
  3193.                 if (pll->refcount == 0)
  3194.                         continue;
  3195.  
  3196.                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
  3197.                            sizeof(pll->hw_state)) == 0) {
  3198.                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
  3199.                                       crtc->base.base.id,
  3200.                                       pll->name, pll->refcount, pll->active);
  3201.  
  3202.                         goto found;
  3203.                 }
  3204.         }
  3205.  
  3206.         /* Ok no matching timings, maybe there's a free one? */
  3207.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  3208.                 pll = &dev_priv->shared_dplls[i];
  3209.                 if (pll->refcount == 0) {
  3210.                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
  3211.                                       crtc->base.base.id, pll->name);
  3212.                         goto found;
  3213.                 }
  3214.         }
  3215.  
  3216.         return NULL;
  3217.  
  3218. found:
  3219.         crtc->config.shared_dpll = i;
  3220.         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
  3221.                          pipe_name(crtc->pipe));
  3222.  
  3223.         if (pll->active == 0) {
  3224.                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
  3225.                        sizeof(pll->hw_state));
  3226.  
  3227.                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
  3228.                 WARN_ON(pll->on);
  3229.                 assert_shared_dpll_disabled(dev_priv, pll);
  3230.  
  3231.                 pll->mode_set(dev_priv, pll);
  3232.         }
  3233.         pll->refcount++;
  3234.  
  3235.         return pll;
  3236. }
  3237.  
  3238. static void cpt_verify_modeset(struct drm_device *dev, int pipe)
  3239. {
  3240.         struct drm_i915_private *dev_priv = dev->dev_private;
  3241.         int dslreg = PIPEDSL(pipe);
  3242.         u32 temp;
  3243.  
  3244.         temp = I915_READ(dslreg);
  3245.         udelay(500);
  3246.         if (wait_for(I915_READ(dslreg) != temp, 5)) {
  3247.                 if (wait_for(I915_READ(dslreg) != temp, 5))
  3248.                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
  3249.         }
  3250. }
  3251.  
  3252. static void ironlake_pfit_enable(struct intel_crtc *crtc)
  3253. {
  3254.         struct drm_device *dev = crtc->base.dev;
  3255.         struct drm_i915_private *dev_priv = dev->dev_private;
  3256.         int pipe = crtc->pipe;
  3257.  
  3258.         if (crtc->config.pch_pfit.enabled) {
  3259.                 /* Force use of hard-coded filter coefficients
  3260.                  * as some pre-programmed values are broken,
  3261.                  * e.g. x201.
  3262.                  */
  3263.                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  3264.                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
  3265.                                                  PF_PIPE_SEL_IVB(pipe));
  3266.                 else
  3267.                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  3268.                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
  3269.                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
  3270.         }
  3271. }
  3272.  
  3273. static void intel_enable_planes(struct drm_crtc *crtc)
  3274. {
  3275.         struct drm_device *dev = crtc->dev;
  3276.         enum pipe pipe = to_intel_crtc(crtc)->pipe;
  3277.         struct intel_plane *intel_plane;
  3278.  
  3279.         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
  3280.                 if (intel_plane->pipe == pipe)
  3281.                         intel_plane_restore(&intel_plane->base);
  3282. }
  3283.  
  3284. static void intel_disable_planes(struct drm_crtc *crtc)
  3285. {
  3286.         struct drm_device *dev = crtc->dev;
  3287.         enum pipe pipe = to_intel_crtc(crtc)->pipe;
  3288.         struct intel_plane *intel_plane;
  3289.  
  3290.         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
  3291.                 if (intel_plane->pipe == pipe)
  3292.                         intel_plane_disable(&intel_plane->base);
  3293. }
  3294.  
  3295. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  3296. {
  3297.     struct drm_device *dev = crtc->dev;
  3298.     struct drm_i915_private *dev_priv = dev->dev_private;
  3299.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3300.         struct intel_encoder *encoder;
  3301.     int pipe = intel_crtc->pipe;
  3302.     int plane = intel_crtc->plane;
  3303.  
  3304.         WARN_ON(!crtc->enabled);
  3305.  
  3306.     if (intel_crtc->active)
  3307.         return;
  3308.  
  3309.     intel_crtc->active = true;
  3310.  
  3311.         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  3312.         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  3313.  
  3314.     intel_update_watermarks(dev);
  3315.  
  3316.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3317.                 if (encoder->pre_enable)
  3318.                         encoder->pre_enable(encoder);
  3319.  
  3320.         if (intel_crtc->config.has_pch_encoder) {
  3321.                 /* Note: FDI PLL enabling _must_ be done before we enable the
  3322.                  * cpu pipes, hence this is separate from all the other fdi/pch
  3323.                  * enabling. */
  3324.                 ironlake_fdi_pll_enable(intel_crtc);
  3325.         } else {
  3326.                 assert_fdi_tx_disabled(dev_priv, pipe);
  3327.                 assert_fdi_rx_disabled(dev_priv, pipe);
  3328.         }
  3329.  
  3330.         ironlake_pfit_enable(intel_crtc);
  3331.  
  3332.     /*
  3333.      * On ILK+ LUT must be loaded before the pipe is running but with
  3334.      * clocks enabled
  3335.      */
  3336.     intel_crtc_load_lut(crtc);
  3337.  
  3338.         intel_enable_pipe(dev_priv, pipe,
  3339.                           intel_crtc->config.has_pch_encoder);
  3340.     intel_enable_plane(dev_priv, plane, pipe);
  3341.         intel_enable_planes(crtc);
  3342. //      intel_crtc_update_cursor(crtc, true);
  3343.  
  3344.         if (intel_crtc->config.has_pch_encoder)
  3345.         ironlake_pch_enable(crtc);
  3346.  
  3347.     mutex_lock(&dev->struct_mutex);
  3348.     intel_update_fbc(dev);
  3349.     mutex_unlock(&dev->struct_mutex);
  3350.  
  3351.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3352.                 encoder->enable(encoder);
  3353.  
  3354.         if (HAS_PCH_CPT(dev))
  3355.                 cpt_verify_modeset(dev, intel_crtc->pipe);
  3356.  
  3357.         /*
  3358.          * There seems to be a race in PCH platform hw (at least on some
  3359.          * outputs) where an enabled pipe still completes any pageflip right
  3360.          * away (as if the pipe is off) instead of waiting for vblank. As soon
  3361.          * as the first vblank happend, everything works as expected. Hence just
  3362.          * wait for one vblank before returning to avoid strange things
  3363.          * happening.
  3364.          */
  3365.         intel_wait_for_vblank(dev, intel_crtc->pipe);
  3366. }
  3367.  
  3368. /* IPS only exists on ULT machines and is tied to pipe A. */
  3369. static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
  3370. {
  3371.         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
  3372. }
  3373.  
  3374. static void hsw_enable_ips(struct intel_crtc *crtc)
  3375. {
  3376.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  3377.  
  3378.         if (!crtc->config.ips_enabled)
  3379.                 return;
  3380.  
  3381.         /* We can only enable IPS after we enable a plane and wait for a vblank.
  3382.          * We guarantee that the plane is enabled by calling intel_enable_ips
  3383.          * only after intel_enable_plane. And intel_enable_plane already waits
  3384.          * for a vblank, so all we need to do here is to enable the IPS bit. */
  3385.         assert_plane_enabled(dev_priv, crtc->plane);
  3386.         I915_WRITE(IPS_CTL, IPS_ENABLE);
  3387. }
  3388.  
  3389. static void hsw_disable_ips(struct intel_crtc *crtc)
  3390. {
  3391.         struct drm_device *dev = crtc->base.dev;
  3392.         struct drm_i915_private *dev_priv = dev->dev_private;
  3393.  
  3394.         if (!crtc->config.ips_enabled)
  3395.                 return;
  3396.  
  3397.         assert_plane_enabled(dev_priv, crtc->plane);
  3398.         I915_WRITE(IPS_CTL, 0);
  3399.  
  3400.         /* We need to wait for a vblank before we can disable the plane. */
  3401.         intel_wait_for_vblank(dev, crtc->pipe);
  3402. }
  3403.  
  3404. static void haswell_crtc_enable(struct drm_crtc *crtc)
  3405. {
  3406.         struct drm_device *dev = crtc->dev;
  3407.         struct drm_i915_private *dev_priv = dev->dev_private;
  3408.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3409.         struct intel_encoder *encoder;
  3410.         int pipe = intel_crtc->pipe;
  3411.         int plane = intel_crtc->plane;
  3412.  
  3413.         WARN_ON(!crtc->enabled);
  3414.  
  3415.         if (intel_crtc->active)
  3416.                 return;
  3417.  
  3418.         intel_crtc->active = true;
  3419.  
  3420.         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  3421.         if (intel_crtc->config.has_pch_encoder)
  3422.                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  3423.  
  3424.         intel_update_watermarks(dev);
  3425.  
  3426.         if (intel_crtc->config.has_pch_encoder)
  3427.                 dev_priv->display.fdi_link_train(crtc);
  3428.  
  3429.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3430.                 if (encoder->pre_enable)
  3431.                         encoder->pre_enable(encoder);
  3432.  
  3433.         intel_ddi_enable_pipe_clock(intel_crtc);
  3434.  
  3435.         ironlake_pfit_enable(intel_crtc);
  3436.  
  3437.         /*
  3438.          * On ILK+ LUT must be loaded before the pipe is running but with
  3439.          * clocks enabled
  3440.          */
  3441.         intel_crtc_load_lut(crtc);
  3442.  
  3443.         intel_ddi_set_pipe_settings(crtc);
  3444.         intel_ddi_enable_transcoder_func(crtc);
  3445.  
  3446.         intel_enable_pipe(dev_priv, pipe,
  3447.                           intel_crtc->config.has_pch_encoder);
  3448.         intel_enable_plane(dev_priv, plane, pipe);
  3449.         intel_enable_planes(crtc);
  3450. //      intel_crtc_update_cursor(crtc, true);
  3451.  
  3452.         hsw_enable_ips(intel_crtc);
  3453.  
  3454.         if (intel_crtc->config.has_pch_encoder)
  3455.                 lpt_pch_enable(crtc);
  3456.  
  3457.         mutex_lock(&dev->struct_mutex);
  3458.         intel_update_fbc(dev);
  3459.         mutex_unlock(&dev->struct_mutex);
  3460.  
  3461.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3462.                 encoder->enable(encoder);
  3463.  
  3464.         /*
  3465.          * There seems to be a race in PCH platform hw (at least on some
  3466.          * outputs) where an enabled pipe still completes any pageflip right
  3467.          * away (as if the pipe is off) instead of waiting for vblank. As soon
  3468.          * as the first vblank happend, everything works as expected. Hence just
  3469.          * wait for one vblank before returning to avoid strange things
  3470.          * happening.
  3471.          */
  3472.         intel_wait_for_vblank(dev, intel_crtc->pipe);
  3473. }
  3474.  
  3475. static void ironlake_pfit_disable(struct intel_crtc *crtc)
  3476. {
  3477.         struct drm_device *dev = crtc->base.dev;
  3478.         struct drm_i915_private *dev_priv = dev->dev_private;
  3479.         int pipe = crtc->pipe;
  3480.  
  3481.         /* To avoid upsetting the power well on haswell only disable the pfit if
  3482.          * it's in use. The hw state code will make sure we get this right. */
  3483.         if (crtc->config.pch_pfit.enabled) {
  3484.                 I915_WRITE(PF_CTL(pipe), 0);
  3485.                 I915_WRITE(PF_WIN_POS(pipe), 0);
  3486.                 I915_WRITE(PF_WIN_SZ(pipe), 0);
  3487.         }
  3488. }
  3489.  
  3490. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  3491. {
  3492.     struct drm_device *dev = crtc->dev;
  3493.     struct drm_i915_private *dev_priv = dev->dev_private;
  3494.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3495.         struct intel_encoder *encoder;
  3496.     int pipe = intel_crtc->pipe;
  3497.     int plane = intel_crtc->plane;
  3498.     u32 reg, temp;
  3499.  
  3500.  
  3501.     if (!intel_crtc->active)
  3502.         return;
  3503.  
  3504.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3505.                 encoder->disable(encoder);
  3506.  
  3507. //    intel_crtc_wait_for_pending_flips(crtc);
  3508. //    drm_vblank_off(dev, pipe);
  3509.  
  3510.         if (dev_priv->fbc.plane == plane)
  3511.                 intel_disable_fbc(dev);
  3512.  
  3513. //      intel_crtc_update_cursor(crtc, false);
  3514.         intel_disable_planes(crtc);
  3515.     intel_disable_plane(dev_priv, plane, pipe);
  3516.  
  3517.         if (intel_crtc->config.has_pch_encoder)
  3518.                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
  3519.  
  3520.     intel_disable_pipe(dev_priv, pipe);
  3521.  
  3522.         ironlake_pfit_disable(intel_crtc);
  3523.  
  3524.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3525.                 if (encoder->post_disable)
  3526.                         encoder->post_disable(encoder);
  3527.  
  3528.         if (intel_crtc->config.has_pch_encoder) {
  3529.     ironlake_fdi_disable(crtc);
  3530.  
  3531.         ironlake_disable_pch_transcoder(dev_priv, pipe);
  3532.                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  3533.  
  3534.     if (HAS_PCH_CPT(dev)) {
  3535.         /* disable TRANS_DP_CTL */
  3536.         reg = TRANS_DP_CTL(pipe);
  3537.         temp = I915_READ(reg);
  3538.                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
  3539.                                   TRANS_DP_PORT_SEL_MASK);
  3540.         temp |= TRANS_DP_PORT_SEL_NONE;
  3541.         I915_WRITE(reg, temp);
  3542.  
  3543.         /* disable DPLL_SEL */
  3544.         temp = I915_READ(PCH_DPLL_SEL);
  3545.                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
  3546.         I915_WRITE(PCH_DPLL_SEL, temp);
  3547.     }
  3548.  
  3549.     /* disable PCH DPLL */
  3550.                 intel_disable_shared_dpll(intel_crtc);
  3551.  
  3552.         ironlake_fdi_pll_disable(intel_crtc);
  3553.         }
  3554.  
  3555.     intel_crtc->active = false;
  3556.     intel_update_watermarks(dev);
  3557.  
  3558.     mutex_lock(&dev->struct_mutex);
  3559.     intel_update_fbc(dev);
  3560.     mutex_unlock(&dev->struct_mutex);
  3561. }
  3562.  
  3563. static void haswell_crtc_disable(struct drm_crtc *crtc)
  3564. {
  3565.         struct drm_device *dev = crtc->dev;
  3566.         struct drm_i915_private *dev_priv = dev->dev_private;
  3567.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3568.         struct intel_encoder *encoder;
  3569.         int pipe = intel_crtc->pipe;
  3570.         int plane = intel_crtc->plane;
  3571.         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  3572.  
  3573.         if (!intel_crtc->active)
  3574.                 return;
  3575.  
  3576.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3577.                 encoder->disable(encoder);
  3578.  
  3579.  
  3580.         /* FBC must be disabled before disabling the plane on HSW. */
  3581.         if (dev_priv->fbc.plane == plane)
  3582.                 intel_disable_fbc(dev);
  3583.  
  3584.         hsw_disable_ips(intel_crtc);
  3585.  
  3586. //      intel_crtc_update_cursor(crtc, false);
  3587.         intel_disable_planes(crtc);
  3588.         intel_disable_plane(dev_priv, plane, pipe);
  3589.  
  3590.         if (intel_crtc->config.has_pch_encoder)
  3591.                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
  3592.         intel_disable_pipe(dev_priv, pipe);
  3593.  
  3594.         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
  3595.  
  3596.         ironlake_pfit_disable(intel_crtc);
  3597.  
  3598.         intel_ddi_disable_pipe_clock(intel_crtc);
  3599.  
  3600.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3601.                 if (encoder->post_disable)
  3602.                         encoder->post_disable(encoder);
  3603.  
  3604.         if (intel_crtc->config.has_pch_encoder) {
  3605.                 lpt_disable_pch_transcoder(dev_priv);
  3606.                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  3607.                 intel_ddi_fdi_disable(crtc);
  3608.         }
  3609.  
  3610.         intel_crtc->active = false;
  3611.         intel_update_watermarks(dev);
  3612.  
  3613.         mutex_lock(&dev->struct_mutex);
  3614.         intel_update_fbc(dev);
  3615.         mutex_unlock(&dev->struct_mutex);
  3616. }
  3617.  
  3618. static void ironlake_crtc_off(struct drm_crtc *crtc)
  3619. {
  3620.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3621.         intel_put_shared_dpll(intel_crtc);
  3622. }
  3623.  
  3624. static void haswell_crtc_off(struct drm_crtc *crtc)
  3625. {
  3626.         intel_ddi_put_crtc_pll(crtc);
  3627. }
  3628.  
  3629. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  3630. {
  3631.         if (!enable && intel_crtc->overlay) {
  3632.                 struct drm_device *dev = intel_crtc->base.dev;
  3633.                 struct drm_i915_private *dev_priv = dev->dev_private;
  3634.  
  3635.                 mutex_lock(&dev->struct_mutex);
  3636.                 dev_priv->mm.interruptible = false;
  3637. //       (void) intel_overlay_switch_off(intel_crtc->overlay);
  3638.                 dev_priv->mm.interruptible = true;
  3639.                 mutex_unlock(&dev->struct_mutex);
  3640.         }
  3641.  
  3642.         /* Let userspace switch the overlay on again. In most cases userspace
  3643.          * has to recompute where to put it anyway.
  3644.          */
  3645. }
  3646.  
  3647. /**
  3648.  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
  3649.  * cursor plane briefly if not already running after enabling the display
  3650.  * plane.
  3651.  * This workaround avoids occasional blank screens when self refresh is
  3652.  * enabled.
  3653.  */
  3654. static void
  3655. g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
  3656. {
  3657.         u32 cntl = I915_READ(CURCNTR(pipe));
  3658.  
  3659.         if ((cntl & CURSOR_MODE) == 0) {
  3660.                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
  3661.  
  3662.                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
  3663.                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
  3664.                 intel_wait_for_vblank(dev_priv->dev, pipe);
  3665.                 I915_WRITE(CURCNTR(pipe), cntl);
  3666.                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
  3667.                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
  3668.         }
  3669. }
  3670.  
  3671. static void i9xx_pfit_enable(struct intel_crtc *crtc)
  3672. {
  3673.         struct drm_device *dev = crtc->base.dev;
  3674.         struct drm_i915_private *dev_priv = dev->dev_private;
  3675.         struct intel_crtc_config *pipe_config = &crtc->config;
  3676.  
  3677.         if (!crtc->config.gmch_pfit.control)
  3678.                 return;
  3679.  
  3680.         /*
  3681.          * The panel fitter should only be adjusted whilst the pipe is disabled,
  3682.          * according to register description and PRM.
  3683.          */
  3684.         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
  3685.         assert_pipe_disabled(dev_priv, crtc->pipe);
  3686.  
  3687.         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
  3688.         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
  3689.  
  3690.         /* Border color in case we don't scale up to the full screen. Black by
  3691.          * default, change to something else for debugging. */
  3692.         I915_WRITE(BCLRPAT(crtc->pipe), 0);
  3693. }
  3694.  
  3695. static void valleyview_crtc_enable(struct drm_crtc *crtc)
  3696. {
  3697.         struct drm_device *dev = crtc->dev;
  3698.         struct drm_i915_private *dev_priv = dev->dev_private;
  3699.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3700.         struct intel_encoder *encoder;
  3701.         int pipe = intel_crtc->pipe;
  3702.         int plane = intel_crtc->plane;
  3703.  
  3704.         WARN_ON(!crtc->enabled);
  3705.  
  3706.         if (intel_crtc->active)
  3707.                 return;
  3708.  
  3709.         intel_crtc->active = true;
  3710.         intel_update_watermarks(dev);
  3711.  
  3712.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3713.                 if (encoder->pre_pll_enable)
  3714.                         encoder->pre_pll_enable(encoder);
  3715.  
  3716.         vlv_enable_pll(intel_crtc);
  3717.  
  3718.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3719.                 if (encoder->pre_enable)
  3720.                         encoder->pre_enable(encoder);
  3721.  
  3722.         i9xx_pfit_enable(intel_crtc);
  3723.  
  3724.         intel_crtc_load_lut(crtc);
  3725.  
  3726.         intel_enable_pipe(dev_priv, pipe, false);
  3727.         intel_enable_plane(dev_priv, plane, pipe);
  3728.         intel_enable_planes(crtc);
  3729. //      intel_crtc_update_cursor(crtc, true);
  3730.  
  3731.         intel_update_fbc(dev);
  3732.  
  3733.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3734.                 encoder->enable(encoder);
  3735. }
  3736.  
  3737. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  3738. {
  3739.     struct drm_device *dev = crtc->dev;
  3740.     struct drm_i915_private *dev_priv = dev->dev_private;
  3741.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3742.         struct intel_encoder *encoder;
  3743.     int pipe = intel_crtc->pipe;
  3744.     int plane = intel_crtc->plane;
  3745.  
  3746.         WARN_ON(!crtc->enabled);
  3747.  
  3748.     if (intel_crtc->active)
  3749.         return;
  3750.  
  3751.     intel_crtc->active = true;
  3752.     intel_update_watermarks(dev);
  3753.  
  3754.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3755.                 if (encoder->pre_enable)
  3756.                         encoder->pre_enable(encoder);
  3757.  
  3758.         i9xx_enable_pll(intel_crtc);
  3759.  
  3760.         i9xx_pfit_enable(intel_crtc);
  3761.  
  3762.         intel_crtc_load_lut(crtc);
  3763.  
  3764.     intel_enable_pipe(dev_priv, pipe, false);
  3765.     intel_enable_plane(dev_priv, plane, pipe);
  3766.         intel_enable_planes(crtc);
  3767.         /* The fixup needs to happen before cursor is enabled */
  3768.         if (IS_G4X(dev))
  3769.                 g4x_fixup_plane(dev_priv, pipe);
  3770. //      intel_crtc_update_cursor(crtc, true);
  3771.  
  3772.     /* Give the overlay scaler a chance to enable if it's on this pipe */
  3773.     intel_crtc_dpms_overlay(intel_crtc, true);
  3774.  
  3775.         intel_update_fbc(dev);
  3776.  
  3777.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3778.                 encoder->enable(encoder);
  3779. }
  3780.  
  3781. static void i9xx_pfit_disable(struct intel_crtc *crtc)
  3782. {
  3783.         struct drm_device *dev = crtc->base.dev;
  3784.         struct drm_i915_private *dev_priv = dev->dev_private;
  3785.  
  3786.         if (!crtc->config.gmch_pfit.control)
  3787.                 return;
  3788.  
  3789.         assert_pipe_disabled(dev_priv, crtc->pipe);
  3790.  
  3791.         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
  3792.                          I915_READ(PFIT_CONTROL));
  3793.                 I915_WRITE(PFIT_CONTROL, 0);
  3794. }
  3795.  
  3796. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  3797. {
  3798.     struct drm_device *dev = crtc->dev;
  3799.     struct drm_i915_private *dev_priv = dev->dev_private;
  3800.     struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3801.         struct intel_encoder *encoder;
  3802.     int pipe = intel_crtc->pipe;
  3803.     int plane = intel_crtc->plane;
  3804.  
  3805.     if (!intel_crtc->active)
  3806.         return;
  3807.  
  3808.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3809.                 encoder->disable(encoder);
  3810.  
  3811.     /* Give the overlay scaler a chance to disable if it's on this pipe */
  3812. //    intel_crtc_wait_for_pending_flips(crtc);
  3813. //    drm_vblank_off(dev, pipe);
  3814.  
  3815.         if (dev_priv->fbc.plane == plane)
  3816.         intel_disable_fbc(dev);
  3817.  
  3818.         intel_crtc_dpms_overlay(intel_crtc, false);
  3819. //      intel_crtc_update_cursor(crtc, false);
  3820.         intel_disable_planes(crtc);
  3821.     intel_disable_plane(dev_priv, plane, pipe);
  3822.  
  3823.     intel_disable_pipe(dev_priv, pipe);
  3824.  
  3825.         i9xx_pfit_disable(intel_crtc);
  3826.  
  3827.         for_each_encoder_on_crtc(dev, crtc, encoder)
  3828.                 if (encoder->post_disable)
  3829.                         encoder->post_disable(encoder);
  3830.  
  3831.         i9xx_disable_pll(dev_priv, pipe);
  3832.  
  3833.     intel_crtc->active = false;
  3834.     intel_update_fbc(dev);
  3835.     intel_update_watermarks(dev);
  3836. }
  3837.  
  3838. static void i9xx_crtc_off(struct drm_crtc *crtc)
  3839. {
  3840. }
  3841.  
  3842. static void intel_crtc_update_sarea(struct drm_crtc *crtc,
  3843.                                     bool enabled)
  3844. {
  3845.         struct drm_device *dev = crtc->dev;
  3846.         struct drm_i915_master_private *master_priv;
  3847.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3848.         int pipe = intel_crtc->pipe;
  3849.  
  3850.  
  3851. #if 0
  3852.         if (!dev->primary->master)
  3853.                 return;
  3854.  
  3855.         master_priv = dev->primary->master->driver_priv;
  3856.         if (!master_priv->sarea_priv)
  3857.                 return;
  3858.  
  3859.         switch (pipe) {
  3860.         case 0:
  3861.                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  3862.                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  3863.                 break;
  3864.         case 1:
  3865.                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  3866.                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  3867.                 break;
  3868.         default:
  3869.                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  3870.                 break;
  3871.         }
  3872. #endif
  3873.  
  3874. }
  3875.  
  3876. /**
  3877.  * Sets the power management mode of the pipe and plane.
  3878.  */
  3879. void intel_crtc_update_dpms(struct drm_crtc *crtc)
  3880. {
  3881.         struct drm_device *dev = crtc->dev;
  3882.         struct drm_i915_private *dev_priv = dev->dev_private;
  3883.         struct intel_encoder *intel_encoder;
  3884.         bool enable = false;
  3885.  
  3886.         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
  3887.                 enable |= intel_encoder->connectors_active;
  3888.  
  3889.         if (enable)
  3890.                 dev_priv->display.crtc_enable(crtc);
  3891.         else
  3892.                 dev_priv->display.crtc_disable(crtc);
  3893.  
  3894.         intel_crtc_update_sarea(crtc, enable);
  3895. }
  3896.  
  3897. static void intel_crtc_disable(struct drm_crtc *crtc)
  3898. {
  3899.         struct drm_device *dev = crtc->dev;
  3900.         struct drm_connector *connector;
  3901.         struct drm_i915_private *dev_priv = dev->dev_private;
  3902.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3903.  
  3904.         /* crtc should still be enabled when we disable it. */
  3905.         WARN_ON(!crtc->enabled);
  3906.  
  3907.         dev_priv->display.crtc_disable(crtc);
  3908.         intel_crtc->eld_vld = false;
  3909.         intel_crtc_update_sarea(crtc, false);
  3910.         dev_priv->display.off(crtc);
  3911.  
  3912.         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
  3913.         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
  3914.  
  3915.         if (crtc->fb) {
  3916.                 mutex_lock(&dev->struct_mutex);
  3917.                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  3918.                 mutex_unlock(&dev->struct_mutex);
  3919.                 crtc->fb = NULL;
  3920.         }
  3921.  
  3922.         /* Update computed state. */
  3923.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3924.                 if (!connector->encoder || !connector->encoder->crtc)
  3925.                         continue;
  3926.  
  3927.                 if (connector->encoder->crtc != crtc)
  3928.                         continue;
  3929.  
  3930.                 connector->dpms = DRM_MODE_DPMS_OFF;
  3931.                 to_intel_encoder(connector->encoder)->connectors_active = false;
  3932.         }
  3933. }
  3934.  
  3935. void intel_encoder_destroy(struct drm_encoder *encoder)
  3936. {
  3937.         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  3938.  
  3939.         drm_encoder_cleanup(encoder);
  3940.         kfree(intel_encoder);
  3941. }
  3942.  
  3943. /* Simple dpms helper for encoders with just one connector, no cloning and only
  3944.  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
  3945.  * state of the entire output pipe. */
  3946. static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
  3947. {
  3948.         if (mode == DRM_MODE_DPMS_ON) {
  3949.                 encoder->connectors_active = true;
  3950.  
  3951.                 intel_crtc_update_dpms(encoder->base.crtc);
  3952.         } else {
  3953.                 encoder->connectors_active = false;
  3954.  
  3955.                 intel_crtc_update_dpms(encoder->base.crtc);
  3956.         }
  3957. }
  3958.  
  3959. /* Cross check the actual hw state with our own modeset state tracking (and it's
  3960.  * internal consistency). */
  3961. static void intel_connector_check_state(struct intel_connector *connector)
  3962. {
  3963.         if (connector->get_hw_state(connector)) {
  3964.                 struct intel_encoder *encoder = connector->encoder;
  3965.                 struct drm_crtc *crtc;
  3966.                 bool encoder_enabled;
  3967.                 enum pipe pipe;
  3968.  
  3969.                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  3970.                               connector->base.base.id,
  3971.                               drm_get_connector_name(&connector->base));
  3972.  
  3973.                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
  3974.                      "wrong connector dpms state\n");
  3975.                 WARN(connector->base.encoder != &encoder->base,
  3976.                      "active connector not linked to encoder\n");
  3977.                 WARN(!encoder->connectors_active,
  3978.                      "encoder->connectors_active not set\n");
  3979.  
  3980.                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
  3981.                 WARN(!encoder_enabled, "encoder not enabled\n");
  3982.                 if (WARN_ON(!encoder->base.crtc))
  3983.                         return;
  3984.  
  3985.                 crtc = encoder->base.crtc;
  3986.  
  3987.                 WARN(!crtc->enabled, "crtc not enabled\n");
  3988.                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
  3989.                 WARN(pipe != to_intel_crtc(crtc)->pipe,
  3990.                      "encoder active on the wrong pipe\n");
  3991.         }
  3992. }
  3993.  
  3994. /* Even simpler default implementation, if there's really no special case to
  3995.  * consider. */
  3996. void intel_connector_dpms(struct drm_connector *connector, int mode)
  3997. {
  3998.         /* All the simple cases only support two dpms states. */
  3999.         if (mode != DRM_MODE_DPMS_ON)
  4000.                 mode = DRM_MODE_DPMS_OFF;
  4001.  
  4002.         if (mode == connector->dpms)
  4003.                 return;
  4004.  
  4005.         connector->dpms = mode;
  4006.  
  4007.         /* Only need to change hw state when actually enabled */
  4008.         if (connector->encoder)
  4009.                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
  4010.  
  4011.         intel_modeset_check_state(connector->dev);
  4012. }
  4013.  
  4014. /* Simple connector->get_hw_state implementation for encoders that support only
  4015.  * one connector and no cloning and hence the encoder state determines the state
  4016.  * of the connector. */
  4017. bool intel_connector_get_hw_state(struct intel_connector *connector)
  4018. {
  4019.         enum pipe pipe = 0;
  4020.         struct intel_encoder *encoder = connector->encoder;
  4021.  
  4022.         return encoder->get_hw_state(encoder, &pipe);
  4023. }
  4024.  
  4025. static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
  4026.                                      struct intel_crtc_config *pipe_config)
  4027. {
  4028.         struct drm_i915_private *dev_priv = dev->dev_private;
  4029.         struct intel_crtc *pipe_B_crtc =
  4030.                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  4031.  
  4032.         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
  4033.                       pipe_name(pipe), pipe_config->fdi_lanes);
  4034.         if (pipe_config->fdi_lanes > 4) {
  4035.                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
  4036.                               pipe_name(pipe), pipe_config->fdi_lanes);
  4037.                 return false;
  4038.         }
  4039.  
  4040.         if (IS_HASWELL(dev)) {
  4041.                 if (pipe_config->fdi_lanes > 2) {
  4042.                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
  4043.                                       pipe_config->fdi_lanes);
  4044.                         return false;
  4045.                 } else {
  4046.                         return true;
  4047.                 }
  4048.         }
  4049.  
  4050.         if (INTEL_INFO(dev)->num_pipes == 2)
  4051.                 return true;
  4052.  
  4053.         /* Ivybridge 3 pipe is really complicated */
  4054.         switch (pipe) {
  4055.         case PIPE_A:
  4056.                 return true;
  4057.         case PIPE_B:
  4058.                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
  4059.                     pipe_config->fdi_lanes > 2) {
  4060.                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  4061.                                       pipe_name(pipe), pipe_config->fdi_lanes);
  4062.                         return false;
  4063.                 }
  4064.                 return true;
  4065.         case PIPE_C:
  4066.                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
  4067.                     pipe_B_crtc->config.fdi_lanes <= 2) {
  4068.                         if (pipe_config->fdi_lanes > 2) {
  4069.                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  4070.                                               pipe_name(pipe), pipe_config->fdi_lanes);
  4071.                                 return false;
  4072.                         }
  4073.                 } else {
  4074.                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
  4075.                         return false;
  4076.                 }
  4077.                 return true;
  4078.         default:
  4079.                 BUG();
  4080.         }
  4081. }
  4082.  
  4083. #define RETRY 1
  4084. static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
  4085.                                       struct intel_crtc_config *pipe_config)
  4086. {
  4087.         struct drm_device *dev = intel_crtc->base.dev;
  4088.         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  4089.         int lane, link_bw, fdi_dotclock;
  4090.         bool setup_ok, needs_recompute = false;
  4091.  
  4092. retry:
  4093.         /* FDI is a binary signal running at ~2.7GHz, encoding
  4094.          * each output octet as 10 bits. The actual frequency
  4095.          * is stored as a divider into a 100MHz clock, and the
  4096.          * mode pixel clock is stored in units of 1KHz.
  4097.          * Hence the bw of each lane in terms of the mode signal
  4098.          * is:
  4099.          */
  4100.         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  4101.  
  4102.         fdi_dotclock = adjusted_mode->clock;
  4103.         fdi_dotclock /= pipe_config->pixel_multiplier;
  4104.  
  4105.         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
  4106.                                            pipe_config->pipe_bpp);
  4107.  
  4108.         pipe_config->fdi_lanes = lane;
  4109.  
  4110.         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
  4111.                                link_bw, &pipe_config->fdi_m_n);
  4112.  
  4113.         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
  4114.                                             intel_crtc->pipe, pipe_config);
  4115.         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
  4116.                 pipe_config->pipe_bpp -= 2*3;
  4117.                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
  4118.                               pipe_config->pipe_bpp);
  4119.                 needs_recompute = true;
  4120.                 pipe_config->bw_constrained = true;
  4121.  
  4122.                 goto retry;
  4123.         }
  4124.  
  4125.         if (needs_recompute)
  4126.                 return RETRY;
  4127.  
  4128.         return setup_ok ? 0 : -EINVAL;
  4129. }
  4130.  
  4131. static void hsw_compute_ips_config(struct intel_crtc *crtc,
  4132.                                    struct intel_crtc_config *pipe_config)
  4133. {
  4134.         pipe_config->ips_enabled = i915_enable_ips &&
  4135.                                    hsw_crtc_supports_ips(crtc) &&
  4136.                                    pipe_config->pipe_bpp <= 24;
  4137. }
  4138.  
  4139. static int intel_crtc_compute_config(struct intel_crtc *crtc,
  4140.                                      struct intel_crtc_config *pipe_config)
  4141. {
  4142.         struct drm_device *dev = crtc->base.dev;
  4143.         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  4144.  
  4145.         if (HAS_PCH_SPLIT(dev)) {
  4146.                 /* FDI link clock is fixed at 2.7G */
  4147.                 if (pipe_config->requested_mode.clock * 3
  4148.                     > IRONLAKE_FDI_FREQ * 4)
  4149.                         return -EINVAL;
  4150.         }
  4151.  
  4152.         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
  4153.          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
  4154.          */
  4155.         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
  4156.                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
  4157.                 return -EINVAL;
  4158.  
  4159.         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
  4160.                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
  4161.         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
  4162.                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
  4163.                  * for lvds. */
  4164.                 pipe_config->pipe_bpp = 8*3;
  4165.         }
  4166.  
  4167.         if (HAS_IPS(dev))
  4168.                 hsw_compute_ips_config(crtc, pipe_config);
  4169.  
  4170.         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
  4171.          * clock survives for now. */
  4172.         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  4173.                 pipe_config->shared_dpll = crtc->config.shared_dpll;
  4174.  
  4175.         if (pipe_config->has_pch_encoder)
  4176.                 return ironlake_fdi_compute_config(crtc, pipe_config);
  4177.  
  4178.         return 0;
  4179. }
  4180.  
  4181. static int valleyview_get_display_clock_speed(struct drm_device *dev)
  4182. {
  4183.         return 400000; /* FIXME */
  4184. }
  4185.  
  4186. static int i945_get_display_clock_speed(struct drm_device *dev)
  4187. {
  4188.         return 400000;
  4189. }
  4190.  
  4191. static int i915_get_display_clock_speed(struct drm_device *dev)
  4192. {
  4193.         return 333000;
  4194. }
  4195.  
  4196. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  4197. {
  4198.         return 200000;
  4199. }
  4200.  
  4201. static int pnv_get_display_clock_speed(struct drm_device *dev)
  4202. {
  4203.         u16 gcfgc = 0;
  4204.  
  4205.         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  4206.  
  4207.         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  4208.         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
  4209.                 return 267000;
  4210.         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
  4211.                 return 333000;
  4212.         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
  4213.                 return 444000;
  4214.         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
  4215.                 return 200000;
  4216.         default:
  4217.                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
  4218.         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
  4219.                 return 133000;
  4220.         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
  4221.                 return 167000;
  4222.         }
  4223. }
  4224.  
  4225. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  4226. {
  4227.         u16 gcfgc = 0;
  4228.  
  4229.         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  4230.  
  4231.         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  4232.                 return 133000;
  4233.         else {
  4234.                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  4235.                 case GC_DISPLAY_CLOCK_333_MHZ:
  4236.                         return 333000;
  4237.                 default:
  4238.                 case GC_DISPLAY_CLOCK_190_200_MHZ:
  4239.                         return 190000;
  4240.                 }
  4241.         }
  4242. }
  4243.  
  4244. static int i865_get_display_clock_speed(struct drm_device *dev)
  4245. {
  4246.         return 266000;
  4247. }
  4248.  
  4249. static int i855_get_display_clock_speed(struct drm_device *dev)
  4250. {
  4251.         u16 hpllcc = 0;
  4252.         /* Assume that the hardware is in the high speed state.  This
  4253.          * should be the default.
  4254.          */
  4255.         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  4256.         case GC_CLOCK_133_200:
  4257.         case GC_CLOCK_100_200:
  4258.                 return 200000;
  4259.         case GC_CLOCK_166_250:
  4260.                 return 250000;
  4261.         case GC_CLOCK_100_133:
  4262.                 return 133000;
  4263.         }
  4264.  
  4265.         /* Shouldn't happen */
  4266.         return 0;
  4267. }
  4268.  
  4269. static int i830_get_display_clock_speed(struct drm_device *dev)
  4270. {
  4271.         return 133000;
  4272. }
  4273.  
  4274. static void
  4275. intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
  4276. {
  4277.         while (*num > DATA_LINK_M_N_MASK ||
  4278.                *den > DATA_LINK_M_N_MASK) {
  4279.                 *num >>= 1;
  4280.                 *den >>= 1;
  4281.         }
  4282. }
  4283.  
  4284. static void compute_m_n(unsigned int m, unsigned int n,
  4285.                         uint32_t *ret_m, uint32_t *ret_n)
  4286. {
  4287.         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
  4288.         *ret_m = div_u64((uint64_t) m * *ret_n, n);
  4289.         intel_reduce_m_n_ratio(ret_m, ret_n);
  4290. }
  4291.  
  4292. void
  4293. intel_link_compute_m_n(int bits_per_pixel, int nlanes,
  4294.                        int pixel_clock, int link_clock,
  4295.                        struct intel_link_m_n *m_n)
  4296. {
  4297.         m_n->tu = 64;
  4298.  
  4299.         compute_m_n(bits_per_pixel * pixel_clock,
  4300.                     link_clock * nlanes * 8,
  4301.                     &m_n->gmch_m, &m_n->gmch_n);
  4302.  
  4303.         compute_m_n(pixel_clock, link_clock,
  4304.                     &m_n->link_m, &m_n->link_n);
  4305. }
  4306.  
  4307. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  4308. {
  4309.         if (i915_panel_use_ssc >= 0)
  4310.                 return i915_panel_use_ssc != 0;
  4311.         return dev_priv->vbt.lvds_use_ssc
  4312.                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  4313. }
  4314.  
  4315. static int vlv_get_refclk(struct drm_crtc *crtc)
  4316. {
  4317.         struct drm_device *dev = crtc->dev;
  4318.         struct drm_i915_private *dev_priv = dev->dev_private;
  4319.         int refclk = 27000; /* for DP & HDMI */
  4320.  
  4321.         return 100000; /* only one validated so far */
  4322.  
  4323.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  4324.                 refclk = 96000;
  4325.         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  4326.                 if (intel_panel_use_ssc(dev_priv))
  4327.                         refclk = 100000;
  4328.                 else
  4329.                         refclk = 96000;
  4330.         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
  4331.                 refclk = 100000;
  4332.         }
  4333.  
  4334.         return refclk;
  4335. }
  4336.  
  4337. static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
  4338. {
  4339.         struct drm_device *dev = crtc->dev;
  4340.         struct drm_i915_private *dev_priv = dev->dev_private;
  4341.         int refclk;
  4342.  
  4343.         if (IS_VALLEYVIEW(dev)) {
  4344.                 refclk = vlv_get_refclk(crtc);
  4345.         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  4346.             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4347.                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
  4348.                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4349.                               refclk / 1000);
  4350.         } else if (!IS_GEN2(dev)) {
  4351.                 refclk = 96000;
  4352.         } else {
  4353.                 refclk = 48000;
  4354.         }
  4355.  
  4356.         return refclk;
  4357. }
  4358.  
  4359. static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
  4360. {
  4361.         return (1 << dpll->n) << 16 | dpll->m2;
  4362. }
  4363.  
  4364. static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
  4365. {
  4366.         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
  4367. }
  4368.  
  4369. static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
  4370.                                      intel_clock_t *reduced_clock)
  4371. {
  4372.         struct drm_device *dev = crtc->base.dev;
  4373.         struct drm_i915_private *dev_priv = dev->dev_private;
  4374.         int pipe = crtc->pipe;
  4375.         u32 fp, fp2 = 0;
  4376.  
  4377.         if (IS_PINEVIEW(dev)) {
  4378.                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
  4379.                 if (reduced_clock)
  4380.                         fp2 = pnv_dpll_compute_fp(reduced_clock);
  4381.         } else {
  4382.                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
  4383.                 if (reduced_clock)
  4384.                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
  4385.         }
  4386.  
  4387.         I915_WRITE(FP0(pipe), fp);
  4388.         crtc->config.dpll_hw_state.fp0 = fp;
  4389.  
  4390.         crtc->lowfreq_avail = false;
  4391.         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  4392.             reduced_clock && i915_powersave) {
  4393.                 I915_WRITE(FP1(pipe), fp2);
  4394.                 crtc->config.dpll_hw_state.fp1 = fp2;
  4395.                 crtc->lowfreq_avail = true;
  4396.         } else {
  4397.                 I915_WRITE(FP1(pipe), fp);
  4398.                 crtc->config.dpll_hw_state.fp1 = fp;
  4399.         }
  4400. }
  4401.  
  4402. static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
  4403. {
  4404.         u32 reg_val;
  4405.  
  4406.         /*
  4407.          * PLLB opamp always calibrates to max value of 0x3f, force enable it
  4408.          * and set it to a reasonable value instead.
  4409.          */
  4410.         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
  4411.         reg_val &= 0xffffff00;
  4412.         reg_val |= 0x00000030;
  4413.         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
  4414.  
  4415.         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
  4416.         reg_val &= 0x8cffffff;
  4417.         reg_val = 0x8c000000;
  4418.         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
  4419.  
  4420.         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
  4421.         reg_val &= 0xffffff00;
  4422.         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
  4423.  
  4424.         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
  4425.         reg_val &= 0x00ffffff;
  4426.         reg_val |= 0xb0000000;
  4427.         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
  4428. }
  4429.  
  4430. static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
  4431.                                          struct intel_link_m_n *m_n)
  4432. {
  4433.         struct drm_device *dev = crtc->base.dev;
  4434.         struct drm_i915_private *dev_priv = dev->dev_private;
  4435.         int pipe = crtc->pipe;
  4436.  
  4437.         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  4438.         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
  4439.         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
  4440.         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
  4441. }
  4442.  
  4443. static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  4444.                                          struct intel_link_m_n *m_n)
  4445. {
  4446.         struct drm_device *dev = crtc->base.dev;
  4447.         struct drm_i915_private *dev_priv = dev->dev_private;
  4448.         int pipe = crtc->pipe;
  4449.         enum transcoder transcoder = crtc->config.cpu_transcoder;
  4450.  
  4451.         if (INTEL_INFO(dev)->gen >= 5) {
  4452.                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
  4453.                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
  4454.                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
  4455.                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
  4456.         } else {
  4457.                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  4458.                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
  4459.                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
  4460.                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
  4461.         }
  4462. }
  4463.  
  4464. static void intel_dp_set_m_n(struct intel_crtc *crtc)
  4465. {
  4466.         if (crtc->config.has_pch_encoder)
  4467.                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  4468.         else
  4469.                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  4470. }
  4471.  
  4472. static void vlv_update_pll(struct intel_crtc *crtc)
  4473. {
  4474.         struct drm_device *dev = crtc->base.dev;
  4475.         struct drm_i915_private *dev_priv = dev->dev_private;
  4476.         int pipe = crtc->pipe;
  4477.         u32 dpll, mdiv;
  4478.         u32 bestn, bestm1, bestm2, bestp1, bestp2;
  4479.         u32 coreclk, reg_val, dpll_md;
  4480.  
  4481.         mutex_lock(&dev_priv->dpio_lock);
  4482.  
  4483.         bestn = crtc->config.dpll.n;
  4484.         bestm1 = crtc->config.dpll.m1;
  4485.         bestm2 = crtc->config.dpll.m2;
  4486.         bestp1 = crtc->config.dpll.p1;
  4487.         bestp2 = crtc->config.dpll.p2;
  4488.  
  4489.         /* See eDP HDMI DPIO driver vbios notes doc */
  4490.  
  4491.         /* PLL B needs special handling */
  4492.         if (pipe)
  4493.                 vlv_pllb_recal_opamp(dev_priv);
  4494.  
  4495.         /* Set up Tx target for periodic Rcomp update */
  4496.         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
  4497.  
  4498.         /* Disable target IRef on PLL */
  4499.         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
  4500.         reg_val &= 0x00ffffff;
  4501.         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
  4502.  
  4503.         /* Disable fast lock */
  4504.         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
  4505.  
  4506.         /* Set idtafcrecal before PLL is enabled */
  4507.         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
  4508.         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
  4509.         mdiv |= ((bestn << DPIO_N_SHIFT));
  4510.         mdiv |= (1 << DPIO_K_SHIFT);
  4511.  
  4512.         /*
  4513.          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
  4514.          * but we don't support that).
  4515.          * Note: don't use the DAC post divider as it seems unstable.
  4516.          */
  4517.         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
  4518.         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
  4519.  
  4520.         mdiv |= DPIO_ENABLE_CALIBRATION;
  4521.         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
  4522.  
  4523.         /* Set HBR and RBR LPF coefficients */
  4524.         if (crtc->config.port_clock == 162000 ||
  4525.             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
  4526.             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
  4527.                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
  4528.                                  0x009f0003);
  4529.         else
  4530.                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
  4531.                                  0x00d0000f);
  4532.  
  4533.         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
  4534.             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
  4535.                 /* Use SSC source */
  4536.                 if (!pipe)
  4537.                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  4538.                                          0x0df40000);
  4539.                 else
  4540.                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  4541.                                          0x0df70000);
  4542.         } else { /* HDMI or VGA */
  4543.                 /* Use bend source */
  4544.                 if (!pipe)
  4545.                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  4546.                                          0x0df70000);
  4547.                 else
  4548.                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  4549.                                          0x0df40000);
  4550.         }
  4551.  
  4552.         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
  4553.         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
  4554.         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
  4555.             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
  4556.                 coreclk |= 0x01000000;
  4557.         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
  4558.  
  4559.         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
  4560.  
  4561.         /* Enable DPIO clock input */
  4562.         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
  4563.                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
  4564.         if (pipe)
  4565.                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
  4566.  
  4567.         dpll |= DPLL_VCO_ENABLE;
  4568.         crtc->config.dpll_hw_state.dpll = dpll;
  4569.  
  4570.         dpll_md = (crtc->config.pixel_multiplier - 1)
  4571.                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  4572.         crtc->config.dpll_hw_state.dpll_md = dpll_md;
  4573.  
  4574.         if (crtc->config.has_dp_encoder)
  4575.                 intel_dp_set_m_n(crtc);
  4576.  
  4577.         mutex_unlock(&dev_priv->dpio_lock);
  4578. }
  4579.  
  4580. static void i9xx_update_pll(struct intel_crtc *crtc,
  4581.                             intel_clock_t *reduced_clock,
  4582.                             int num_connectors)
  4583. {
  4584.         struct drm_device *dev = crtc->base.dev;
  4585.         struct drm_i915_private *dev_priv = dev->dev_private;
  4586.         u32 dpll;
  4587.         bool is_sdvo;
  4588.         struct dpll *clock = &crtc->config.dpll;
  4589.  
  4590.         i9xx_update_pll_dividers(crtc, reduced_clock);
  4591.  
  4592.         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
  4593.                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
  4594.  
  4595.         dpll = DPLL_VGA_MODE_DIS;
  4596.  
  4597.         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
  4598.                 dpll |= DPLLB_MODE_LVDS;
  4599.         else
  4600.                 dpll |= DPLLB_MODE_DAC_SERIAL;
  4601.  
  4602.         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  4603.                         dpll |= (crtc->config.pixel_multiplier - 1)
  4604.                                 << SDVO_MULTIPLIER_SHIFT_HIRES;
  4605.                 }
  4606.  
  4607.         if (is_sdvo)
  4608.                 dpll |= DPLL_SDVO_HIGH_SPEED;
  4609.  
  4610.         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
  4611.                 dpll |= DPLL_SDVO_HIGH_SPEED;
  4612.  
  4613.         /* compute bitmask from p1 value */
  4614.         if (IS_PINEVIEW(dev))
  4615.                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  4616.         else {
  4617.                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4618.                 if (IS_G4X(dev) && reduced_clock)
  4619.                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4620.         }
  4621.         switch (clock->p2) {
  4622.         case 5:
  4623.                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4624.                 break;
  4625.         case 7:
  4626.                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4627.                 break;
  4628.         case 10:
  4629.                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4630.                 break;
  4631.         case 14:
  4632.                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4633.                 break;
  4634.         }
  4635.         if (INTEL_INFO(dev)->gen >= 4)
  4636.                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  4637.  
  4638.         if (crtc->config.sdvo_tv_clock)
  4639.                 dpll |= PLL_REF_INPUT_TVCLKINBC;
  4640.         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  4641.                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4642.                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4643.         else
  4644.                 dpll |= PLL_REF_INPUT_DREFCLK;
  4645.  
  4646.         dpll |= DPLL_VCO_ENABLE;
  4647.         crtc->config.dpll_hw_state.dpll = dpll;
  4648.  
  4649.         if (INTEL_INFO(dev)->gen >= 4) {
  4650.                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
  4651.                                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  4652.                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
  4653.         }
  4654.  
  4655.         if (crtc->config.has_dp_encoder)
  4656.                 intel_dp_set_m_n(crtc);
  4657. }
  4658.  
  4659. static void i8xx_update_pll(struct intel_crtc *crtc,
  4660.                             intel_clock_t *reduced_clock,
  4661.                             int num_connectors)
  4662. {
  4663.         struct drm_device *dev = crtc->base.dev;
  4664.         struct drm_i915_private *dev_priv = dev->dev_private;
  4665.         u32 dpll;
  4666.         struct dpll *clock = &crtc->config.dpll;
  4667.  
  4668.         i9xx_update_pll_dividers(crtc, reduced_clock);
  4669.  
  4670.         dpll = DPLL_VGA_MODE_DIS;
  4671.  
  4672.         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
  4673.                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4674.         } else {
  4675.                 if (clock->p1 == 2)
  4676.                         dpll |= PLL_P1_DIVIDE_BY_TWO;
  4677.                 else
  4678.                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4679.                 if (clock->p2 == 4)
  4680.                         dpll |= PLL_P2_DIVIDE_BY_4;
  4681.         }
  4682.  
  4683.         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
  4684.                 dpll |= DPLL_DVO_2X_MODE;
  4685.  
  4686.         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  4687.                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4688.                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4689.         else
  4690.                 dpll |= PLL_REF_INPUT_DREFCLK;
  4691.  
  4692.         dpll |= DPLL_VCO_ENABLE;
  4693.         crtc->config.dpll_hw_state.dpll = dpll;
  4694. }
  4695.  
  4696. static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
  4697. {
  4698.         struct drm_device *dev = intel_crtc->base.dev;
  4699.         struct drm_i915_private *dev_priv = dev->dev_private;
  4700.         enum pipe pipe = intel_crtc->pipe;
  4701.         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  4702.         struct drm_display_mode *adjusted_mode =
  4703.                 &intel_crtc->config.adjusted_mode;
  4704.         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  4705.         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
  4706.  
  4707.         /* We need to be careful not to changed the adjusted mode, for otherwise
  4708.          * the hw state checker will get angry at the mismatch. */
  4709.         crtc_vtotal = adjusted_mode->crtc_vtotal;
  4710.         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
  4711.  
  4712.         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  4713.                 /* the chip adds 2 halflines automatically */
  4714.                 crtc_vtotal -= 1;
  4715.                 crtc_vblank_end -= 1;
  4716.                 vsyncshift = adjusted_mode->crtc_hsync_start
  4717.                              - adjusted_mode->crtc_htotal / 2;
  4718.         } else {
  4719.                 vsyncshift = 0;
  4720.         }
  4721.  
  4722.         if (INTEL_INFO(dev)->gen > 3)
  4723.                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
  4724.  
  4725.         I915_WRITE(HTOTAL(cpu_transcoder),
  4726.                    (adjusted_mode->crtc_hdisplay - 1) |
  4727.                    ((adjusted_mode->crtc_htotal - 1) << 16));
  4728.         I915_WRITE(HBLANK(cpu_transcoder),
  4729.                    (adjusted_mode->crtc_hblank_start - 1) |
  4730.                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
  4731.         I915_WRITE(HSYNC(cpu_transcoder),
  4732.                    (adjusted_mode->crtc_hsync_start - 1) |
  4733.                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
  4734.  
  4735.         I915_WRITE(VTOTAL(cpu_transcoder),
  4736.                    (adjusted_mode->crtc_vdisplay - 1) |
  4737.                    ((crtc_vtotal - 1) << 16));
  4738.         I915_WRITE(VBLANK(cpu_transcoder),
  4739.                    (adjusted_mode->crtc_vblank_start - 1) |
  4740.                    ((crtc_vblank_end - 1) << 16));
  4741.         I915_WRITE(VSYNC(cpu_transcoder),
  4742.                    (adjusted_mode->crtc_vsync_start - 1) |
  4743.                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
  4744.  
  4745.         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
  4746.          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
  4747.          * documented on the DDI_FUNC_CTL register description, EDP Input Select
  4748.          * bits. */
  4749.         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
  4750.             (pipe == PIPE_B || pipe == PIPE_C))
  4751.                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
  4752.  
  4753.         /* pipesrc controls the size that is scaled from, which should
  4754.          * always be the user's requested size.
  4755.          */
  4756.         I915_WRITE(PIPESRC(pipe),
  4757.                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  4758. }
  4759.  
  4760. static void intel_get_pipe_timings(struct intel_crtc *crtc,
  4761.                                    struct intel_crtc_config *pipe_config)
  4762. {
  4763.         struct drm_device *dev = crtc->base.dev;
  4764.         struct drm_i915_private *dev_priv = dev->dev_private;
  4765.         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
  4766.         uint32_t tmp;
  4767.  
  4768.         tmp = I915_READ(HTOTAL(cpu_transcoder));
  4769.         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
  4770.         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
  4771.         tmp = I915_READ(HBLANK(cpu_transcoder));
  4772.         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
  4773.         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
  4774.         tmp = I915_READ(HSYNC(cpu_transcoder));
  4775.         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
  4776.         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
  4777.  
  4778.         tmp = I915_READ(VTOTAL(cpu_transcoder));
  4779.         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
  4780.         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
  4781.         tmp = I915_READ(VBLANK(cpu_transcoder));
  4782.         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
  4783.         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
  4784.         tmp = I915_READ(VSYNC(cpu_transcoder));
  4785.         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
  4786.         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
  4787.  
  4788.         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
  4789.                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
  4790.                 pipe_config->adjusted_mode.crtc_vtotal += 1;
  4791.                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
  4792.         }
  4793.  
  4794.         tmp = I915_READ(PIPESRC(crtc->pipe));
  4795.         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
  4796.         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
  4797. }
  4798.  
  4799. static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
  4800.                                              struct intel_crtc_config *pipe_config)
  4801. {
  4802.         struct drm_crtc *crtc = &intel_crtc->base;
  4803.  
  4804.         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
  4805.         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
  4806.         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
  4807.         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
  4808.  
  4809.         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
  4810.         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
  4811.         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
  4812.         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
  4813.  
  4814.         crtc->mode.flags = pipe_config->adjusted_mode.flags;
  4815.  
  4816.         crtc->mode.clock = pipe_config->adjusted_mode.clock;
  4817.         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
  4818. }
  4819.  
  4820. static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
  4821. {
  4822.         struct drm_device *dev = intel_crtc->base.dev;
  4823.         struct drm_i915_private *dev_priv = dev->dev_private;
  4824.         uint32_t pipeconf;
  4825.  
  4826.         pipeconf = 0;
  4827.  
  4828.         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  4829.             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
  4830.                 pipeconf |= PIPECONF_ENABLE;
  4831.  
  4832.         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
  4833.                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
  4834.                  * core speed.
  4835.                  *
  4836.                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  4837.                  * pipe == 0 check?
  4838.                  */
  4839.                 if (intel_crtc->config.requested_mode.clock >
  4840.                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  4841.                         pipeconf |= PIPECONF_DOUBLE_WIDE;
  4842.         }
  4843.  
  4844.         /* only g4x and later have fancy bpc/dither controls */
  4845.         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  4846.                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
  4847.                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
  4848.                         pipeconf |= PIPECONF_DITHER_EN |
  4849.                                     PIPECONF_DITHER_TYPE_SP;
  4850.  
  4851.                 switch (intel_crtc->config.pipe_bpp) {
  4852.                 case 18:
  4853.                         pipeconf |= PIPECONF_6BPC;
  4854.                         break;
  4855.                 case 24:
  4856.                         pipeconf |= PIPECONF_8BPC;
  4857.                         break;
  4858.                 case 30:
  4859.                         pipeconf |= PIPECONF_10BPC;
  4860.                         break;
  4861.                 default:
  4862.                         /* Case prevented by intel_choose_pipe_bpp_dither. */
  4863.                         BUG();
  4864.                 }
  4865.         }
  4866.  
  4867.         if (HAS_PIPE_CXSR(dev)) {
  4868.                 if (intel_crtc->lowfreq_avail) {
  4869.                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4870.                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4871.                 } else {
  4872.                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4873.                 }
  4874.         }
  4875.  
  4876.         if (!IS_GEN2(dev) &&
  4877.             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4878.                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4879.         else
  4880.                 pipeconf |= PIPECONF_PROGRESSIVE;
  4881.  
  4882.         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
  4883.                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
  4884.  
  4885.         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
  4886.         POSTING_READ(PIPECONF(intel_crtc->pipe));
  4887. }
  4888.  
  4889. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  4890.                               int x, int y,
  4891.                               struct drm_framebuffer *fb)
  4892. {
  4893.         struct drm_device *dev = crtc->dev;
  4894.         struct drm_i915_private *dev_priv = dev->dev_private;
  4895.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4896.         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  4897.         int pipe = intel_crtc->pipe;
  4898.         int plane = intel_crtc->plane;
  4899.         int refclk, num_connectors = 0;
  4900.         intel_clock_t clock, reduced_clock;
  4901.         u32 dspcntr;
  4902.         bool ok, has_reduced_clock = false;
  4903.         bool is_lvds = false;
  4904.         struct intel_encoder *encoder;
  4905.         const intel_limit_t *limit;
  4906.         int ret;
  4907.  
  4908.         for_each_encoder_on_crtc(dev, crtc, encoder) {
  4909.                 switch (encoder->type) {
  4910.                 case INTEL_OUTPUT_LVDS:
  4911.                         is_lvds = true;
  4912.                         break;
  4913.                 }
  4914.  
  4915.                 num_connectors++;
  4916.         }
  4917.  
  4918.         refclk = i9xx_get_refclk(crtc, num_connectors);
  4919.  
  4920.         /*
  4921.          * Returns a set of divisors for the desired target clock with the given
  4922.          * refclk, or FALSE.  The returned values represent the clock equation:
  4923.          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4924.          */
  4925.         limit = intel_limit(crtc, refclk);
  4926.         ok = dev_priv->display.find_dpll(limit, crtc,
  4927.                                          intel_crtc->config.port_clock,
  4928.                                          refclk, NULL, &clock);
  4929.         if (!ok && !intel_crtc->config.clock_set) {
  4930.                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4931.                 return -EINVAL;
  4932.         }
  4933.  
  4934.         if (is_lvds && dev_priv->lvds_downclock_avail) {
  4935.                 /*
  4936.                  * Ensure we match the reduced clock's P to the target clock.
  4937.                  * If the clocks don't match, we can't switch the display clock
  4938.                  * by using the FP0/FP1. In such case we will disable the LVDS
  4939.                  * downclock feature.
  4940.                 */
  4941.                 has_reduced_clock =
  4942.                         dev_priv->display.find_dpll(limit, crtc,
  4943.                                                     dev_priv->lvds_downclock,
  4944.                                                     refclk, &clock,
  4945.                                                     &reduced_clock);
  4946.         }
  4947.         /* Compat-code for transition, will disappear. */
  4948.         if (!intel_crtc->config.clock_set) {
  4949.                 intel_crtc->config.dpll.n = clock.n;
  4950.                 intel_crtc->config.dpll.m1 = clock.m1;
  4951.                 intel_crtc->config.dpll.m2 = clock.m2;
  4952.                 intel_crtc->config.dpll.p1 = clock.p1;
  4953.                 intel_crtc->config.dpll.p2 = clock.p2;
  4954.         }
  4955.  
  4956.         if (IS_GEN2(dev))
  4957.                 i8xx_update_pll(intel_crtc,
  4958.                                 has_reduced_clock ? &reduced_clock : NULL,
  4959.                                 num_connectors);
  4960.         else if (IS_VALLEYVIEW(dev))
  4961.                 vlv_update_pll(intel_crtc);
  4962.         else
  4963.                 i9xx_update_pll(intel_crtc,
  4964.                                 has_reduced_clock ? &reduced_clock : NULL,
  4965.                                 num_connectors);
  4966.  
  4967.         /* Set up the display plane register */
  4968.         dspcntr = DISPPLANE_GAMMA_ENABLE;
  4969.  
  4970.         if (!IS_VALLEYVIEW(dev)) {
  4971.         if (pipe == 0)
  4972.                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  4973.         else
  4974.                 dspcntr |= DISPPLANE_SEL_PIPE_B;
  4975.         }
  4976.  
  4977.         intel_set_pipe_timings(intel_crtc);
  4978.  
  4979.         /* pipesrc and dspsize control the size that is scaled from,
  4980.          * which should always be the user's requested size.
  4981.          */
  4982.         I915_WRITE(DSPSIZE(plane),
  4983.                    ((mode->vdisplay - 1) << 16) |
  4984.                    (mode->hdisplay - 1));
  4985.         I915_WRITE(DSPPOS(plane), 0);
  4986.  
  4987.         i9xx_set_pipeconf(intel_crtc);
  4988.  
  4989.         I915_WRITE(DSPCNTR(plane), dspcntr);
  4990.         POSTING_READ(DSPCNTR(plane));
  4991.  
  4992.         ret = intel_pipe_set_base(crtc, x, y, fb);
  4993.  
  4994.         intel_update_watermarks(dev);
  4995.  
  4996.     return ret;
  4997. }
  4998.  
  4999. static void i9xx_get_pfit_config(struct intel_crtc *crtc,
  5000.                                  struct intel_crtc_config *pipe_config)
  5001. {
  5002.         struct drm_device *dev = crtc->base.dev;
  5003.         struct drm_i915_private *dev_priv = dev->dev_private;
  5004.         uint32_t tmp;
  5005.  
  5006.         tmp = I915_READ(PFIT_CONTROL);
  5007.         if (!(tmp & PFIT_ENABLE))
  5008.                 return;
  5009.  
  5010.         /* Check whether the pfit is attached to our pipe. */
  5011.         if (INTEL_INFO(dev)->gen < 4) {
  5012.                 if (crtc->pipe != PIPE_B)
  5013.                         return;
  5014.         } else {
  5015.                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
  5016.                         return;
  5017.         }
  5018.  
  5019.         pipe_config->gmch_pfit.control = tmp;
  5020.         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
  5021.         if (INTEL_INFO(dev)->gen < 5)
  5022.                 pipe_config->gmch_pfit.lvds_border_bits =
  5023.                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
  5024. }
  5025.  
  5026. static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
  5027.                                  struct intel_crtc_config *pipe_config)
  5028. {
  5029.         struct drm_device *dev = crtc->base.dev;
  5030.         struct drm_i915_private *dev_priv = dev->dev_private;
  5031.         uint32_t tmp;
  5032.  
  5033.         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  5034.         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  5035.  
  5036.         tmp = I915_READ(PIPECONF(crtc->pipe));
  5037.         if (!(tmp & PIPECONF_ENABLE))
  5038.                 return false;
  5039.  
  5040.         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  5041.                 switch (tmp & PIPECONF_BPC_MASK) {
  5042.                 case PIPECONF_6BPC:
  5043.                         pipe_config->pipe_bpp = 18;
  5044.                         break;
  5045.                 case PIPECONF_8BPC:
  5046.                         pipe_config->pipe_bpp = 24;
  5047.                         break;
  5048.                 case PIPECONF_10BPC:
  5049.                         pipe_config->pipe_bpp = 30;
  5050.                         break;
  5051.                 default:
  5052.                         break;
  5053.                 }
  5054.         }
  5055.  
  5056.         intel_get_pipe_timings(crtc, pipe_config);
  5057.  
  5058.         i9xx_get_pfit_config(crtc, pipe_config);
  5059.  
  5060.         if (INTEL_INFO(dev)->gen >= 4) {
  5061.                 tmp = I915_READ(DPLL_MD(crtc->pipe));
  5062.                 pipe_config->pixel_multiplier =
  5063.                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
  5064.                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
  5065.                 pipe_config->dpll_hw_state.dpll_md = tmp;
  5066.         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  5067.                 tmp = I915_READ(DPLL(crtc->pipe));
  5068.                 pipe_config->pixel_multiplier =
  5069.                         ((tmp & SDVO_MULTIPLIER_MASK)
  5070.                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
  5071.         } else {
  5072.                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
  5073.                  * port and will be fixed up in the encoder->get_config
  5074.                  * function. */
  5075.                 pipe_config->pixel_multiplier = 1;
  5076.         }
  5077.         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
  5078.         if (!IS_VALLEYVIEW(dev)) {
  5079.                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
  5080.                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
  5081.         } else {
  5082.                 /* Mask out read-only status bits. */
  5083.                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
  5084.                                                      DPLL_PORTC_READY_MASK |
  5085.                                                      DPLL_PORTB_READY_MASK);
  5086.         }
  5087.  
  5088.         return true;
  5089. }
  5090.  
  5091. static void ironlake_init_pch_refclk(struct drm_device *dev)
  5092. {
  5093.         struct drm_i915_private *dev_priv = dev->dev_private;
  5094.         struct drm_mode_config *mode_config = &dev->mode_config;
  5095.         struct intel_encoder *encoder;
  5096.         u32 val, final;
  5097.         bool has_lvds = false;
  5098.         bool has_cpu_edp = false;
  5099.         bool has_panel = false;
  5100.         bool has_ck505 = false;
  5101.         bool can_ssc = false;
  5102.  
  5103.         /* We need to take the global config into account */
  5104.                 list_for_each_entry(encoder, &mode_config->encoder_list,
  5105.                                     base.head) {
  5106.                         switch (encoder->type) {
  5107.                         case INTEL_OUTPUT_LVDS:
  5108.                         has_panel = true;
  5109.                                 has_lvds = true;
  5110.                         break;
  5111.                         case INTEL_OUTPUT_EDP:
  5112.                         has_panel = true;
  5113.                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
  5114.                                 has_cpu_edp = true;
  5115.                                 break;
  5116.                         }
  5117.                 }
  5118.  
  5119.         if (HAS_PCH_IBX(dev)) {
  5120.                 has_ck505 = dev_priv->vbt.display_clock_mode;
  5121.                 can_ssc = has_ck505;
  5122.         } else {
  5123.                 has_ck505 = false;
  5124.                 can_ssc = true;
  5125.         }
  5126.  
  5127.         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
  5128.                       has_panel, has_lvds, has_ck505);
  5129.  
  5130.         /* Ironlake: try to setup display ref clock before DPLL
  5131.          * enabling. This is only under driver's control after
  5132.          * PCH B stepping, previous chipset stepping should be
  5133.          * ignoring this setting.
  5134.          */
  5135.         val = I915_READ(PCH_DREF_CONTROL);
  5136.  
  5137.         /* As we must carefully and slowly disable/enable each source in turn,
  5138.          * compute the final state we want first and check if we need to
  5139.          * make any changes at all.
  5140.          */
  5141.         final = val;
  5142.         final &= ~DREF_NONSPREAD_SOURCE_MASK;
  5143.         if (has_ck505)
  5144.                 final |= DREF_NONSPREAD_CK505_ENABLE;
  5145.         else
  5146.                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
  5147.  
  5148.         final &= ~DREF_SSC_SOURCE_MASK;
  5149.         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  5150.         final &= ~DREF_SSC1_ENABLE;
  5151.  
  5152.         if (has_panel) {
  5153.                 final |= DREF_SSC_SOURCE_ENABLE;
  5154.  
  5155.                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
  5156.                         final |= DREF_SSC1_ENABLE;
  5157.  
  5158.                 if (has_cpu_edp) {
  5159.                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
  5160.                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  5161.                         else
  5162.                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  5163.                 } else
  5164.                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  5165.         } else {
  5166.                 final |= DREF_SSC_SOURCE_DISABLE;
  5167.                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  5168.         }
  5169.  
  5170.         if (final == val)
  5171.                 return;
  5172.  
  5173.         /* Always enable nonspread source */
  5174.         val &= ~DREF_NONSPREAD_SOURCE_MASK;
  5175.  
  5176.         if (has_ck505)
  5177.                 val |= DREF_NONSPREAD_CK505_ENABLE;
  5178.         else
  5179.                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
  5180.  
  5181.         if (has_panel) {
  5182.                 val &= ~DREF_SSC_SOURCE_MASK;
  5183.                 val |= DREF_SSC_SOURCE_ENABLE;
  5184.  
  5185.                 /* SSC must be turned on before enabling the CPU output  */
  5186.                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  5187.                         DRM_DEBUG_KMS("Using SSC on panel\n");
  5188.                         val |= DREF_SSC1_ENABLE;
  5189.                 } else
  5190.                         val &= ~DREF_SSC1_ENABLE;
  5191.  
  5192.                 /* Get SSC going before enabling the outputs */
  5193.                 I915_WRITE(PCH_DREF_CONTROL, val);
  5194.                         POSTING_READ(PCH_DREF_CONTROL);
  5195.                         udelay(200);
  5196.  
  5197.                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  5198.  
  5199.                 /* Enable CPU source on CPU attached eDP */
  5200.                 if (has_cpu_edp) {
  5201.                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  5202.                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
  5203.                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  5204.                         }
  5205.                         else
  5206.                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  5207.                 } else
  5208.                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  5209.  
  5210.                 I915_WRITE(PCH_DREF_CONTROL, val);
  5211.                 POSTING_READ(PCH_DREF_CONTROL);
  5212.                 udelay(200);
  5213.                 } else {
  5214.                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
  5215.  
  5216.                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  5217.  
  5218.                 /* Turn off CPU output */
  5219.                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  5220.  
  5221.                 I915_WRITE(PCH_DREF_CONTROL, val);
  5222.                 POSTING_READ(PCH_DREF_CONTROL);
  5223.                 udelay(200);
  5224.  
  5225.                 /* Turn off the SSC source */
  5226.                 val &= ~DREF_SSC_SOURCE_MASK;
  5227.                 val |= DREF_SSC_SOURCE_DISABLE;
  5228.  
  5229.                 /* Turn off SSC1 */
  5230.                 val &= ~DREF_SSC1_ENABLE;
  5231.  
  5232.                 I915_WRITE(PCH_DREF_CONTROL, val);
  5233.                 POSTING_READ(PCH_DREF_CONTROL);
  5234.                 udelay(200);
  5235.         }
  5236.  
  5237.         BUG_ON(val != final);
  5238. }
  5239.  
  5240. static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
  5241. {
  5242.         uint32_t tmp;
  5243.  
  5244.                 tmp = I915_READ(SOUTH_CHICKEN2);
  5245.                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
  5246.                 I915_WRITE(SOUTH_CHICKEN2, tmp);
  5247.  
  5248.                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
  5249.                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
  5250.                         DRM_ERROR("FDI mPHY reset assert timeout\n");
  5251.  
  5252.                 tmp = I915_READ(SOUTH_CHICKEN2);
  5253.                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
  5254.                 I915_WRITE(SOUTH_CHICKEN2, tmp);
  5255.  
  5256.                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
  5257.                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
  5258.                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
  5259.         }
  5260.  
  5261. /* WaMPhyProgramming:hsw */
  5262. static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
  5263. {
  5264.         uint32_t tmp;
  5265.  
  5266.         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
  5267.         tmp &= ~(0xFF << 24);
  5268.         tmp |= (0x12 << 24);
  5269.         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
  5270.  
  5271.         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
  5272.         tmp |= (1 << 11);
  5273.         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
  5274.  
  5275.         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
  5276.         tmp |= (1 << 11);
  5277.         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
  5278.  
  5279.         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
  5280.         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  5281.         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
  5282.  
  5283.         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
  5284.         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  5285.         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
  5286.  
  5287.                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
  5288.                 tmp &= ~(7 << 13);
  5289.                 tmp |= (5 << 13);
  5290.                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
  5291.  
  5292.                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
  5293.                 tmp &= ~(7 << 13);
  5294.                 tmp |= (5 << 13);
  5295.                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
  5296.  
  5297.         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
  5298.         tmp &= ~0xFF;
  5299.         tmp |= 0x1C;
  5300.         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
  5301.  
  5302.         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
  5303.         tmp &= ~0xFF;
  5304.         tmp |= 0x1C;
  5305.         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
  5306.  
  5307.         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
  5308.         tmp &= ~(0xFF << 16);
  5309.         tmp |= (0x1C << 16);
  5310.         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
  5311.  
  5312.         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
  5313.         tmp &= ~(0xFF << 16);
  5314.         tmp |= (0x1C << 16);
  5315.         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
  5316.  
  5317.                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
  5318.                 tmp |= (1 << 27);
  5319.                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
  5320.  
  5321.                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
  5322.                 tmp |= (1 << 27);
  5323.                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
  5324.  
  5325.                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
  5326.                 tmp &= ~(0xF << 28);
  5327.                 tmp |= (4 << 28);
  5328.                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
  5329.  
  5330.                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
  5331.                 tmp &= ~(0xF << 28);
  5332.                 tmp |= (4 << 28);
  5333.                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
  5334.         }
  5335.  
  5336. /* Implements 3 different sequences from BSpec chapter "Display iCLK
  5337.  * Programming" based on the parameters passed:
  5338.  * - Sequence to enable CLKOUT_DP
  5339.  * - Sequence to enable CLKOUT_DP without spread
  5340.  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
  5341.  */
  5342. static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
  5343.                                  bool with_fdi)
  5344. {
  5345.         struct drm_i915_private *dev_priv = dev->dev_private;
  5346.         uint32_t reg, tmp;
  5347.  
  5348.         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
  5349.                 with_spread = true;
  5350.         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
  5351.                  with_fdi, "LP PCH doesn't have FDI\n"))
  5352.                 with_fdi = false;
  5353.  
  5354.         mutex_lock(&dev_priv->dpio_lock);
  5355.  
  5356.         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  5357.         tmp &= ~SBI_SSCCTL_DISABLE;
  5358.         tmp |= SBI_SSCCTL_PATHALT;
  5359.         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  5360.  
  5361.         udelay(24);
  5362.  
  5363.         if (with_spread) {
  5364.                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  5365.                 tmp &= ~SBI_SSCCTL_PATHALT;
  5366.                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  5367.  
  5368.                 if (with_fdi) {
  5369.                         lpt_reset_fdi_mphy(dev_priv);
  5370.                         lpt_program_fdi_mphy(dev_priv);
  5371.                 }
  5372.         }
  5373.  
  5374.         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
  5375.                SBI_GEN0 : SBI_DBUFF0;
  5376.         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  5377.         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  5378.         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  5379.  
  5380.         mutex_unlock(&dev_priv->dpio_lock);
  5381. }
  5382.  
  5383. /* Sequence to disable CLKOUT_DP */
  5384. static void lpt_disable_clkout_dp(struct drm_device *dev)
  5385. {
  5386.         struct drm_i915_private *dev_priv = dev->dev_private;
  5387.         uint32_t reg, tmp;
  5388.  
  5389.         mutex_lock(&dev_priv->dpio_lock);
  5390.  
  5391.         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
  5392.                SBI_GEN0 : SBI_DBUFF0;
  5393.         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  5394.         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  5395.         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  5396.  
  5397.         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  5398.         if (!(tmp & SBI_SSCCTL_DISABLE)) {
  5399.                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
  5400.                         tmp |= SBI_SSCCTL_PATHALT;
  5401.                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  5402.                         udelay(32);
  5403.                 }
  5404.                 tmp |= SBI_SSCCTL_DISABLE;
  5405.                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  5406.         }
  5407.  
  5408.         mutex_unlock(&dev_priv->dpio_lock);
  5409. }
  5410.  
  5411. static void lpt_init_pch_refclk(struct drm_device *dev)
  5412. {
  5413.         struct drm_mode_config *mode_config = &dev->mode_config;
  5414.         struct intel_encoder *encoder;
  5415.         bool has_vga = false;
  5416.  
  5417.         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  5418.                 switch (encoder->type) {
  5419.                 case INTEL_OUTPUT_ANALOG:
  5420.                         has_vga = true;
  5421.                         break;
  5422.                 }
  5423.         }
  5424.  
  5425.         if (has_vga)
  5426.                 lpt_enable_clkout_dp(dev, true, true);
  5427.         else
  5428.                 lpt_disable_clkout_dp(dev);
  5429. }
  5430.  
  5431. /*
  5432.  * Initialize reference clocks when the driver loads
  5433.  */
  5434. void intel_init_pch_refclk(struct drm_device *dev)
  5435. {
  5436.         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  5437.                 ironlake_init_pch_refclk(dev);
  5438.         else if (HAS_PCH_LPT(dev))
  5439.                 lpt_init_pch_refclk(dev);
  5440. }
  5441.  
  5442. static int ironlake_get_refclk(struct drm_crtc *crtc)
  5443. {
  5444.         struct drm_device *dev = crtc->dev;
  5445.         struct drm_i915_private *dev_priv = dev->dev_private;
  5446.         struct intel_encoder *encoder;
  5447.         int num_connectors = 0;
  5448.         bool is_lvds = false;
  5449.  
  5450.         for_each_encoder_on_crtc(dev, crtc, encoder) {
  5451.                 switch (encoder->type) {
  5452.                 case INTEL_OUTPUT_LVDS:
  5453.                         is_lvds = true;
  5454.                         break;
  5455.                 }
  5456.                 num_connectors++;
  5457.         }
  5458.  
  5459.         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  5460.                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  5461.                               dev_priv->vbt.lvds_ssc_freq);
  5462.                 return dev_priv->vbt.lvds_ssc_freq * 1000;
  5463.         }
  5464.  
  5465.         return 120000;
  5466. }
  5467.  
  5468. static void ironlake_set_pipeconf(struct drm_crtc *crtc)
  5469. {
  5470.         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  5471.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5472.         int pipe = intel_crtc->pipe;
  5473.         uint32_t val;
  5474.  
  5475.         val = 0;
  5476.  
  5477.         switch (intel_crtc->config.pipe_bpp) {
  5478.         case 18:
  5479.                 val |= PIPECONF_6BPC;
  5480.                 break;
  5481.         case 24:
  5482.                 val |= PIPECONF_8BPC;
  5483.                 break;
  5484.         case 30:
  5485.                 val |= PIPECONF_10BPC;
  5486.                 break;
  5487.         case 36:
  5488.                 val |= PIPECONF_12BPC;
  5489.                 break;
  5490.         default:
  5491.                 /* Case prevented by intel_choose_pipe_bpp_dither. */
  5492.                 BUG();
  5493.         }
  5494.  
  5495.         if (intel_crtc->config.dither)
  5496.                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  5497.  
  5498.         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  5499.                 val |= PIPECONF_INTERLACED_ILK;
  5500.         else
  5501.                 val |= PIPECONF_PROGRESSIVE;
  5502.  
  5503.         if (intel_crtc->config.limited_color_range)
  5504.                 val |= PIPECONF_COLOR_RANGE_SELECT;
  5505.  
  5506.         I915_WRITE(PIPECONF(pipe), val);
  5507.         POSTING_READ(PIPECONF(pipe));
  5508. }
  5509.  
  5510. /*
  5511.  * Set up the pipe CSC unit.
  5512.  *
  5513.  * Currently only full range RGB to limited range RGB conversion
  5514.  * is supported, but eventually this should handle various
  5515.  * RGB<->YCbCr scenarios as well.
  5516.  */
  5517. static void intel_set_pipe_csc(struct drm_crtc *crtc)
  5518. {
  5519.         struct drm_device *dev = crtc->dev;
  5520.         struct drm_i915_private *dev_priv = dev->dev_private;
  5521.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5522.         int pipe = intel_crtc->pipe;
  5523.         uint16_t coeff = 0x7800; /* 1.0 */
  5524.  
  5525.         /*
  5526.          * TODO: Check what kind of values actually come out of the pipe
  5527.          * with these coeff/postoff values and adjust to get the best
  5528.          * accuracy. Perhaps we even need to take the bpc value into
  5529.          * consideration.
  5530.          */
  5531.  
  5532.         if (intel_crtc->config.limited_color_range)
  5533.                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
  5534.  
  5535.         /*
  5536.          * GY/GU and RY/RU should be the other way around according
  5537.          * to BSpec, but reality doesn't agree. Just set them up in
  5538.          * a way that results in the correct picture.
  5539.          */
  5540.         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
  5541.         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
  5542.  
  5543.         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
  5544.         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
  5545.  
  5546.         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
  5547.         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
  5548.  
  5549.         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
  5550.         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
  5551.         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
  5552.  
  5553.         if (INTEL_INFO(dev)->gen > 6) {
  5554.                 uint16_t postoff = 0;
  5555.  
  5556.                 if (intel_crtc->config.limited_color_range)
  5557.                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
  5558.  
  5559.                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
  5560.                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
  5561.                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
  5562.  
  5563.                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
  5564.         } else {
  5565.                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
  5566.  
  5567.                 if (intel_crtc->config.limited_color_range)
  5568.                         mode |= CSC_BLACK_SCREEN_OFFSET;
  5569.  
  5570.                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
  5571.         }
  5572. }
  5573.  
  5574. static void haswell_set_pipeconf(struct drm_crtc *crtc)
  5575. {
  5576.         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  5577.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5578.         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  5579.         uint32_t val;
  5580.  
  5581.         val = 0;
  5582.  
  5583.         if (intel_crtc->config.dither)
  5584.                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  5585.  
  5586.         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  5587.                 val |= PIPECONF_INTERLACED_ILK;
  5588.         else
  5589.                 val |= PIPECONF_PROGRESSIVE;
  5590.  
  5591.         I915_WRITE(PIPECONF(cpu_transcoder), val);
  5592.         POSTING_READ(PIPECONF(cpu_transcoder));
  5593.  
  5594.         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
  5595.         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
  5596. }
  5597.  
  5598. static bool ironlake_compute_clocks(struct drm_crtc *crtc,
  5599.                                     intel_clock_t *clock,
  5600.                                     bool *has_reduced_clock,
  5601.                                     intel_clock_t *reduced_clock)
  5602. {
  5603.         struct drm_device *dev = crtc->dev;
  5604.         struct drm_i915_private *dev_priv = dev->dev_private;
  5605.         struct intel_encoder *intel_encoder;
  5606.         int refclk;
  5607.         const intel_limit_t *limit;
  5608.         bool ret, is_lvds = false;
  5609.  
  5610.         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  5611.                 switch (intel_encoder->type) {
  5612.                 case INTEL_OUTPUT_LVDS:
  5613.                         is_lvds = true;
  5614.                         break;
  5615.                 }
  5616.         }
  5617.  
  5618.         refclk = ironlake_get_refclk(crtc);
  5619.  
  5620.         /*
  5621.          * Returns a set of divisors for the desired target clock with the given
  5622.          * refclk, or FALSE.  The returned values represent the clock equation:
  5623.          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  5624.          */
  5625.         limit = intel_limit(crtc, refclk);
  5626.         ret = dev_priv->display.find_dpll(limit, crtc,
  5627.                                           to_intel_crtc(crtc)->config.port_clock,
  5628.                                           refclk, NULL, clock);
  5629.         if (!ret)
  5630.                 return false;
  5631.  
  5632.         if (is_lvds && dev_priv->lvds_downclock_avail) {
  5633.                 /*
  5634.                  * Ensure we match the reduced clock's P to the target clock.
  5635.                  * If the clocks don't match, we can't switch the display clock
  5636.                  * by using the FP0/FP1. In such case we will disable the LVDS
  5637.                  * downclock feature.
  5638.                 */
  5639.                 *has_reduced_clock =
  5640.                         dev_priv->display.find_dpll(limit, crtc,
  5641.                                                      dev_priv->lvds_downclock,
  5642.                                                     refclk, clock,
  5643.                                                      reduced_clock);
  5644.         }
  5645.  
  5646.         return true;
  5647. }
  5648.  
  5649. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
  5650. {
  5651.         /*
  5652.          * Account for spread spectrum to avoid
  5653.          * oversubscribing the link. Max center spread
  5654.          * is 2.5%; use 5% for safety's sake.
  5655.          */
  5656.         u32 bps = target_clock * bpp * 21 / 20;
  5657.         return bps / (link_bw * 8) + 1;
  5658. }
  5659.  
  5660. static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
  5661. {
  5662.         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
  5663. }
  5664.  
  5665. static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
  5666.                                       u32 *fp,
  5667.                                       intel_clock_t *reduced_clock, u32 *fp2)
  5668. {
  5669.         struct drm_crtc *crtc = &intel_crtc->base;
  5670.         struct drm_device *dev = crtc->dev;
  5671.         struct drm_i915_private *dev_priv = dev->dev_private;
  5672.         struct intel_encoder *intel_encoder;
  5673.         uint32_t dpll;
  5674.         int factor, num_connectors = 0;
  5675.         bool is_lvds = false, is_sdvo = false;
  5676.  
  5677.         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  5678.                 switch (intel_encoder->type) {
  5679.                 case INTEL_OUTPUT_LVDS:
  5680.                         is_lvds = true;
  5681.                         break;
  5682.                 case INTEL_OUTPUT_SDVO:
  5683.                 case INTEL_OUTPUT_HDMI:
  5684.                         is_sdvo = true;
  5685.                         break;
  5686.                 }
  5687.  
  5688.                 num_connectors++;
  5689.         }
  5690.  
  5691.     /* Enable autotuning of the PLL clock (if permissible) */
  5692.     factor = 21;
  5693.     if (is_lvds) {
  5694.         if ((intel_panel_use_ssc(dev_priv) &&
  5695.                      dev_priv->vbt.lvds_ssc_freq == 100) ||
  5696.                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
  5697.             factor = 25;
  5698.         } else if (intel_crtc->config.sdvo_tv_clock)
  5699.         factor = 20;
  5700.  
  5701.         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
  5702.                 *fp |= FP_CB_TUNE;
  5703.  
  5704.         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
  5705.                 *fp2 |= FP_CB_TUNE;
  5706.  
  5707.     dpll = 0;
  5708.  
  5709.     if (is_lvds)
  5710.         dpll |= DPLLB_MODE_LVDS;
  5711.     else
  5712.         dpll |= DPLLB_MODE_DAC_SERIAL;
  5713.  
  5714.                         dpll |= (intel_crtc->config.pixel_multiplier - 1)
  5715.                                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  5716.  
  5717.         if (is_sdvo)
  5718.                 dpll |= DPLL_SDVO_HIGH_SPEED;
  5719.         if (intel_crtc->config.has_dp_encoder)
  5720.                 dpll |= DPLL_SDVO_HIGH_SPEED;
  5721.  
  5722.     /* compute bitmask from p1 value */
  5723.         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  5724.     /* also FPA1 */
  5725.         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  5726.  
  5727.         switch (intel_crtc->config.dpll.p2) {
  5728.     case 5:
  5729.         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  5730.         break;
  5731.     case 7:
  5732.         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  5733.         break;
  5734.     case 10:
  5735.         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  5736.         break;
  5737.     case 14:
  5738.         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  5739.         break;
  5740.     }
  5741.  
  5742.         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  5743.         dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  5744.     else
  5745.         dpll |= PLL_REF_INPUT_DREFCLK;
  5746.  
  5747.         return dpll | DPLL_VCO_ENABLE;
  5748. }
  5749.  
  5750. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  5751.                                   int x, int y,
  5752.                                   struct drm_framebuffer *fb)
  5753. {
  5754.         struct drm_device *dev = crtc->dev;
  5755.         struct drm_i915_private *dev_priv = dev->dev_private;
  5756.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5757.         int pipe = intel_crtc->pipe;
  5758.         int plane = intel_crtc->plane;
  5759.         int num_connectors = 0;
  5760.         intel_clock_t clock, reduced_clock;
  5761.         u32 dpll = 0, fp = 0, fp2 = 0;
  5762.         bool ok, has_reduced_clock = false;
  5763.         bool is_lvds = false;
  5764.         struct intel_encoder *encoder;
  5765.         struct intel_shared_dpll *pll;
  5766.         int ret;
  5767.  
  5768.         for_each_encoder_on_crtc(dev, crtc, encoder) {
  5769.                 switch (encoder->type) {
  5770.                 case INTEL_OUTPUT_LVDS:
  5771.                         is_lvds = true;
  5772.                         break;
  5773.                 }
  5774.  
  5775.                 num_connectors++;
  5776.         }
  5777.  
  5778.         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
  5779.              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
  5780.  
  5781.         ok = ironlake_compute_clocks(crtc, &clock,
  5782.                                      &has_reduced_clock, &reduced_clock);
  5783.         if (!ok && !intel_crtc->config.clock_set) {
  5784.                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
  5785.                 return -EINVAL;
  5786.         }
  5787.         /* Compat-code for transition, will disappear. */
  5788.         if (!intel_crtc->config.clock_set) {
  5789.                 intel_crtc->config.dpll.n = clock.n;
  5790.                 intel_crtc->config.dpll.m1 = clock.m1;
  5791.                 intel_crtc->config.dpll.m2 = clock.m2;
  5792.                 intel_crtc->config.dpll.p1 = clock.p1;
  5793.                 intel_crtc->config.dpll.p2 = clock.p2;
  5794.         }
  5795.  
  5796.         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
  5797.         if (intel_crtc->config.has_pch_encoder) {
  5798.                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
  5799.         if (has_reduced_clock)
  5800.                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
  5801.  
  5802.                 dpll = ironlake_compute_dpll(intel_crtc,
  5803.                                              &fp, &reduced_clock,
  5804.                                      has_reduced_clock ? &fp2 : NULL);
  5805.  
  5806.                 intel_crtc->config.dpll_hw_state.dpll = dpll;
  5807.                 intel_crtc->config.dpll_hw_state.fp0 = fp;
  5808.                 if (has_reduced_clock)
  5809.                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
  5810.                 else
  5811.                         intel_crtc->config.dpll_hw_state.fp1 = fp;
  5812.  
  5813.                 pll = intel_get_shared_dpll(intel_crtc);
  5814.                 if (pll == NULL) {
  5815.                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
  5816.                                          pipe_name(pipe));
  5817.                         return -EINVAL;
  5818.         }
  5819.         } else
  5820.                 intel_put_shared_dpll(intel_crtc);
  5821.  
  5822.         if (intel_crtc->config.has_dp_encoder)
  5823.                 intel_dp_set_m_n(intel_crtc);
  5824.  
  5825.         if (is_lvds && has_reduced_clock && i915_powersave)
  5826.                 intel_crtc->lowfreq_avail = true;
  5827.         else
  5828.                 intel_crtc->lowfreq_avail = false;
  5829.  
  5830.         if (intel_crtc->config.has_pch_encoder) {
  5831.                 pll = intel_crtc_to_shared_dpll(intel_crtc);
  5832.  
  5833.         }
  5834.  
  5835.         intel_set_pipe_timings(intel_crtc);
  5836.  
  5837.         if (intel_crtc->config.has_pch_encoder) {
  5838.                 intel_cpu_transcoder_set_m_n(intel_crtc,
  5839.                                              &intel_crtc->config.fdi_m_n);
  5840.         }
  5841.  
  5842.         ironlake_set_pipeconf(crtc);
  5843.  
  5844.         /* Set up the display plane register */
  5845.         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
  5846.         POSTING_READ(DSPCNTR(plane));
  5847.  
  5848.         ret = intel_pipe_set_base(crtc, x, y, fb);
  5849.  
  5850.         intel_update_watermarks(dev);
  5851.  
  5852.         return ret;
  5853. }
  5854.  
  5855. static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
  5856.                                         struct intel_crtc_config *pipe_config)
  5857. {
  5858.         struct drm_device *dev = crtc->base.dev;
  5859.         struct drm_i915_private *dev_priv = dev->dev_private;
  5860.         enum transcoder transcoder = pipe_config->cpu_transcoder;
  5861.  
  5862.         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
  5863.         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
  5864.         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
  5865.                                         & ~TU_SIZE_MASK;
  5866.         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
  5867.         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
  5868.                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  5869. }
  5870.  
  5871. static void ironlake_get_pfit_config(struct intel_crtc *crtc,
  5872.                                      struct intel_crtc_config *pipe_config)
  5873. {
  5874.         struct drm_device *dev = crtc->base.dev;
  5875.         struct drm_i915_private *dev_priv = dev->dev_private;
  5876.         uint32_t tmp;
  5877.  
  5878.         tmp = I915_READ(PF_CTL(crtc->pipe));
  5879.  
  5880.         if (tmp & PF_ENABLE) {
  5881.                 pipe_config->pch_pfit.enabled = true;
  5882.                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
  5883.                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
  5884.  
  5885.                 /* We currently do not free assignements of panel fitters on
  5886.                  * ivb/hsw (since we don't use the higher upscaling modes which
  5887.                  * differentiates them) so just WARN about this case for now. */
  5888.                 if (IS_GEN7(dev)) {
  5889.                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
  5890.                                 PF_PIPE_SEL_IVB(crtc->pipe));
  5891.                 }
  5892.         }
  5893. }
  5894.  
  5895. static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
  5896.                                      struct intel_crtc_config *pipe_config)
  5897. {
  5898.         struct drm_device *dev = crtc->base.dev;
  5899.         struct drm_i915_private *dev_priv = dev->dev_private;
  5900.         uint32_t tmp;
  5901.  
  5902.         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  5903.         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  5904.  
  5905.         tmp = I915_READ(PIPECONF(crtc->pipe));
  5906.         if (!(tmp & PIPECONF_ENABLE))
  5907.                 return false;
  5908.  
  5909.         switch (tmp & PIPECONF_BPC_MASK) {
  5910.         case PIPECONF_6BPC:
  5911.                 pipe_config->pipe_bpp = 18;
  5912.                 break;
  5913.         case PIPECONF_8BPC:
  5914.                 pipe_config->pipe_bpp = 24;
  5915.                 break;
  5916.         case PIPECONF_10BPC:
  5917.                 pipe_config->pipe_bpp = 30;
  5918.                 break;
  5919.         case PIPECONF_12BPC:
  5920.                 pipe_config->pipe_bpp = 36;
  5921.                 break;
  5922.         default:
  5923.                 break;
  5924.         }
  5925.  
  5926.         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
  5927.                 struct intel_shared_dpll *pll;
  5928.  
  5929.                 pipe_config->has_pch_encoder = true;
  5930.  
  5931.                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
  5932.                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  5933.                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
  5934.  
  5935.                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
  5936.  
  5937.                 if (HAS_PCH_IBX(dev_priv->dev)) {
  5938.                         pipe_config->shared_dpll =
  5939.                                 (enum intel_dpll_id) crtc->pipe;
  5940.                 } else {
  5941.                         tmp = I915_READ(PCH_DPLL_SEL);
  5942.                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
  5943.                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
  5944.                         else
  5945.                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
  5946.                 }
  5947.  
  5948.                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
  5949.  
  5950.                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
  5951.                                            &pipe_config->dpll_hw_state));
  5952.  
  5953.                 tmp = pipe_config->dpll_hw_state.dpll;
  5954.                 pipe_config->pixel_multiplier =
  5955.                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
  5956.                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
  5957.         } else {
  5958.                 pipe_config->pixel_multiplier = 1;
  5959.         }
  5960.  
  5961.         intel_get_pipe_timings(crtc, pipe_config);
  5962.  
  5963.         ironlake_get_pfit_config(crtc, pipe_config);
  5964.  
  5965.         return true;
  5966. }
  5967.  
  5968. static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
  5969. {
  5970.         struct drm_device *dev = dev_priv->dev;
  5971.         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
  5972.         struct intel_crtc *crtc;
  5973.         unsigned long irqflags;
  5974.         uint32_t val;
  5975.  
  5976.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
  5977.                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
  5978.                      pipe_name(crtc->pipe));
  5979.  
  5980.         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
  5981.         WARN(plls->spll_refcount, "SPLL enabled\n");
  5982.         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
  5983.         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
  5984.         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
  5985.         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
  5986.              "CPU PWM1 enabled\n");
  5987.         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
  5988.              "CPU PWM2 enabled\n");
  5989.         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
  5990.              "PCH PWM1 enabled\n");
  5991.         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
  5992.              "Utility pin enabled\n");
  5993.         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
  5994.  
  5995.         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  5996.         val = I915_READ(DEIMR);
  5997.         WARN((val & ~DE_PCH_EVENT_IVB) != val,
  5998.              "Unexpected DEIMR bits enabled: 0x%x\n", val);
  5999.         val = I915_READ(SDEIMR);
  6000.         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
  6001.              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
  6002.         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  6003. }
  6004.  
  6005. /*
  6006.  * This function implements pieces of two sequences from BSpec:
  6007.  * - Sequence for display software to disable LCPLL
  6008.  * - Sequence for display software to allow package C8+
  6009.  * The steps implemented here are just the steps that actually touch the LCPLL
  6010.  * register. Callers should take care of disabling all the display engine
  6011.  * functions, doing the mode unset, fixing interrupts, etc.
  6012.  */
  6013. void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
  6014.                        bool switch_to_fclk, bool allow_power_down)
  6015. {
  6016.         uint32_t val;
  6017.  
  6018.         assert_can_disable_lcpll(dev_priv);
  6019.  
  6020.         val = I915_READ(LCPLL_CTL);
  6021.  
  6022.         if (switch_to_fclk) {
  6023.                 val |= LCPLL_CD_SOURCE_FCLK;
  6024.                 I915_WRITE(LCPLL_CTL, val);
  6025.  
  6026.                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
  6027.                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
  6028.                         DRM_ERROR("Switching to FCLK failed\n");
  6029.  
  6030.                 val = I915_READ(LCPLL_CTL);
  6031.         }
  6032.  
  6033.         val |= LCPLL_PLL_DISABLE;
  6034.         I915_WRITE(LCPLL_CTL, val);
  6035.         POSTING_READ(LCPLL_CTL);
  6036.  
  6037.         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
  6038.                 DRM_ERROR("LCPLL still locked\n");
  6039.  
  6040.         val = I915_READ(D_COMP);
  6041.         val |= D_COMP_COMP_DISABLE;
  6042.         I915_WRITE(D_COMP, val);
  6043.         POSTING_READ(D_COMP);
  6044.     udelay(100);
  6045.  
  6046.         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
  6047.                 DRM_ERROR("D_COMP RCOMP still in progress\n");
  6048.  
  6049.         if (allow_power_down) {
  6050.                 val = I915_READ(LCPLL_CTL);
  6051.                 val |= LCPLL_POWER_DOWN_ALLOW;
  6052.                 I915_WRITE(LCPLL_CTL, val);
  6053.                 POSTING_READ(LCPLL_CTL);
  6054.         }
  6055. }
  6056.  
  6057. /*
  6058.  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
  6059.  * source.
  6060.  */
  6061. void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
  6062. {
  6063.         uint32_t val;
  6064.  
  6065.         val = I915_READ(LCPLL_CTL);
  6066.  
  6067.         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
  6068.                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
  6069.                 return;
  6070.  
  6071.         /* Make sure we're not on PC8 state before disabling PC8, otherwise
  6072.          * we'll hang the machine! */
  6073.         dev_priv->uncore.funcs.force_wake_get(dev_priv);
  6074.  
  6075.         if (val & LCPLL_POWER_DOWN_ALLOW) {
  6076.                 val &= ~LCPLL_POWER_DOWN_ALLOW;
  6077.                 I915_WRITE(LCPLL_CTL, val);
  6078.                 POSTING_READ(LCPLL_CTL);
  6079.         }
  6080.  
  6081.         val = I915_READ(D_COMP);
  6082.         val |= D_COMP_COMP_FORCE;
  6083.         val &= ~D_COMP_COMP_DISABLE;
  6084.         I915_WRITE(D_COMP, val);
  6085.         POSTING_READ(D_COMP);
  6086.  
  6087.         val = I915_READ(LCPLL_CTL);
  6088.         val &= ~LCPLL_PLL_DISABLE;
  6089.         I915_WRITE(LCPLL_CTL, val);
  6090.  
  6091.         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
  6092.                 DRM_ERROR("LCPLL not locked yet\n");
  6093.  
  6094.         if (val & LCPLL_CD_SOURCE_FCLK) {
  6095.                 val = I915_READ(LCPLL_CTL);
  6096.                 val &= ~LCPLL_CD_SOURCE_FCLK;
  6097.                 I915_WRITE(LCPLL_CTL, val);
  6098.  
  6099.                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
  6100.                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
  6101.                         DRM_ERROR("Switching back to LCPLL failed\n");
  6102.         }
  6103.  
  6104.         dev_priv->uncore.funcs.force_wake_put(dev_priv);
  6105. }
  6106.  
  6107. void hsw_enable_pc8_work(struct work_struct *__work)
  6108. {
  6109.         struct drm_i915_private *dev_priv =
  6110.                 container_of(to_delayed_work(__work), struct drm_i915_private,
  6111.                              pc8.enable_work);
  6112.         struct drm_device *dev = dev_priv->dev;
  6113.         uint32_t val;
  6114.  
  6115.         if (dev_priv->pc8.enabled)
  6116.                 return;
  6117.  
  6118.         DRM_DEBUG_KMS("Enabling package C8+\n");
  6119.  
  6120.         dev_priv->pc8.enabled = true;
  6121.  
  6122.         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  6123.                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
  6124.                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
  6125.                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  6126.         }
  6127.  
  6128.         lpt_disable_clkout_dp(dev);
  6129.         hsw_pc8_disable_interrupts(dev);
  6130.         hsw_disable_lcpll(dev_priv, true, true);
  6131. }
  6132.  
  6133. static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
  6134. {
  6135.         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
  6136.         WARN(dev_priv->pc8.disable_count < 1,
  6137.              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
  6138.  
  6139.         dev_priv->pc8.disable_count--;
  6140.         if (dev_priv->pc8.disable_count != 0)
  6141.                 return;
  6142.  
  6143.         schedule_delayed_work(&dev_priv->pc8.enable_work,
  6144.                               msecs_to_jiffies(i915_pc8_timeout));
  6145. }
  6146.  
  6147. static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
  6148. {
  6149.         struct drm_device *dev = dev_priv->dev;
  6150.         uint32_t val;
  6151.  
  6152.         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
  6153.         WARN(dev_priv->pc8.disable_count < 0,
  6154.              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
  6155.  
  6156.         dev_priv->pc8.disable_count++;
  6157.         if (dev_priv->pc8.disable_count != 1)
  6158.                 return;
  6159.  
  6160.         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
  6161.         if (!dev_priv->pc8.enabled)
  6162.                 return;
  6163.  
  6164.         DRM_DEBUG_KMS("Disabling package C8+\n");
  6165.  
  6166.         hsw_restore_lcpll(dev_priv);
  6167.         hsw_pc8_restore_interrupts(dev);
  6168.         lpt_init_pch_refclk(dev);
  6169.  
  6170.         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  6171.                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
  6172.                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
  6173.                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  6174.         }
  6175.  
  6176.         intel_prepare_ddi(dev);
  6177.         i915_gem_init_swizzling(dev);
  6178.         mutex_lock(&dev_priv->rps.hw_lock);
  6179.         gen6_update_ring_freq(dev);
  6180.         mutex_unlock(&dev_priv->rps.hw_lock);
  6181.         dev_priv->pc8.enabled = false;
  6182. }
  6183.  
  6184. void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
  6185. {
  6186.         mutex_lock(&dev_priv->pc8.lock);
  6187.         __hsw_enable_package_c8(dev_priv);
  6188.         mutex_unlock(&dev_priv->pc8.lock);
  6189. }
  6190.  
  6191. void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
  6192. {
  6193.         mutex_lock(&dev_priv->pc8.lock);
  6194.         __hsw_disable_package_c8(dev_priv);
  6195.         mutex_unlock(&dev_priv->pc8.lock);
  6196. }
  6197.  
  6198. static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
  6199. {
  6200.         struct drm_device *dev = dev_priv->dev;
  6201.         struct intel_crtc *crtc;
  6202.         uint32_t val;
  6203.  
  6204.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
  6205.                 if (crtc->base.enabled)
  6206.                         return false;
  6207.  
  6208.         /* This case is still possible since we have the i915.disable_power_well
  6209.          * parameter and also the KVMr or something else might be requesting the
  6210.          * power well. */
  6211.         val = I915_READ(HSW_PWR_WELL_DRIVER);
  6212.         if (val != 0) {
  6213.                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
  6214.                 return false;
  6215.         }
  6216.  
  6217.         return true;
  6218. }
  6219.  
  6220. /* Since we're called from modeset_global_resources there's no way to
  6221.  * symmetrically increase and decrease the refcount, so we use
  6222.  * dev_priv->pc8.requirements_met to track whether we already have the refcount
  6223.  * or not.
  6224.  */
  6225. static void hsw_update_package_c8(struct drm_device *dev)
  6226. {
  6227.         struct drm_i915_private *dev_priv = dev->dev_private;
  6228.         bool allow;
  6229.  
  6230.         if (!i915_enable_pc8)
  6231.                 return;
  6232.  
  6233.         mutex_lock(&dev_priv->pc8.lock);
  6234.  
  6235.         allow = hsw_can_enable_package_c8(dev_priv);
  6236.  
  6237.         if (allow == dev_priv->pc8.requirements_met)
  6238.                 goto done;
  6239.  
  6240.         dev_priv->pc8.requirements_met = allow;
  6241.  
  6242.         if (allow)
  6243.                 __hsw_enable_package_c8(dev_priv);
  6244.         else
  6245.                 __hsw_disable_package_c8(dev_priv);
  6246.  
  6247. done:
  6248.         mutex_unlock(&dev_priv->pc8.lock);
  6249. }
  6250.  
  6251. static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
  6252. {
  6253.         if (!dev_priv->pc8.gpu_idle) {
  6254.                 dev_priv->pc8.gpu_idle = true;
  6255.                 hsw_enable_package_c8(dev_priv);
  6256.         }
  6257. }
  6258.  
  6259. static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
  6260. {
  6261.         if (dev_priv->pc8.gpu_idle) {
  6262.                 dev_priv->pc8.gpu_idle = false;
  6263.                 hsw_disable_package_c8(dev_priv);
  6264.         }
  6265. }
  6266.  
  6267. static void haswell_modeset_global_resources(struct drm_device *dev)
  6268. {
  6269.         bool enable = false;
  6270.         struct intel_crtc *crtc;
  6271.  
  6272.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  6273.                 if (!crtc->base.enabled)
  6274.                         continue;
  6275.  
  6276.                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
  6277.                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
  6278.                         enable = true;
  6279.         }
  6280.  
  6281.         intel_set_power_well(dev, enable);
  6282.  
  6283.         hsw_update_package_c8(dev);
  6284. }
  6285.  
  6286. static int haswell_crtc_mode_set(struct drm_crtc *crtc,
  6287.                                  int x, int y,
  6288.                                  struct drm_framebuffer *fb)
  6289. {
  6290.         struct drm_device *dev = crtc->dev;
  6291.         struct drm_i915_private *dev_priv = dev->dev_private;
  6292.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6293.         int plane = intel_crtc->plane;
  6294.         int ret;
  6295.  
  6296.         if (!intel_ddi_pll_mode_set(crtc))
  6297.                 return -EINVAL;
  6298.  
  6299.         if (intel_crtc->config.has_dp_encoder)
  6300.                 intel_dp_set_m_n(intel_crtc);
  6301.  
  6302.         intel_crtc->lowfreq_avail = false;
  6303.  
  6304.         intel_set_pipe_timings(intel_crtc);
  6305.  
  6306.         if (intel_crtc->config.has_pch_encoder) {
  6307.                 intel_cpu_transcoder_set_m_n(intel_crtc,
  6308.                                              &intel_crtc->config.fdi_m_n);
  6309.         }
  6310.  
  6311.         haswell_set_pipeconf(crtc);
  6312.  
  6313.         intel_set_pipe_csc(crtc);
  6314.  
  6315.         /* Set up the display plane register */
  6316.         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
  6317.     POSTING_READ(DSPCNTR(plane));
  6318.  
  6319.         ret = intel_pipe_set_base(crtc, x, y, fb);
  6320.  
  6321.     intel_update_watermarks(dev);
  6322.  
  6323.     return ret;
  6324. }
  6325.  
  6326. static bool haswell_get_pipe_config(struct intel_crtc *crtc,
  6327.                                     struct intel_crtc_config *pipe_config)
  6328. {
  6329.         struct drm_device *dev = crtc->base.dev;
  6330.         struct drm_i915_private *dev_priv = dev->dev_private;
  6331.         enum intel_display_power_domain pfit_domain;
  6332.         uint32_t tmp;
  6333.  
  6334.         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  6335.         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  6336.  
  6337.         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
  6338.         if (tmp & TRANS_DDI_FUNC_ENABLE) {
  6339.                 enum pipe trans_edp_pipe;
  6340.                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
  6341.                 default:
  6342.                         WARN(1, "unknown pipe linked to edp transcoder\n");
  6343.                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
  6344.                 case TRANS_DDI_EDP_INPUT_A_ON:
  6345.                         trans_edp_pipe = PIPE_A;
  6346.                         break;
  6347.                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
  6348.                         trans_edp_pipe = PIPE_B;
  6349.                         break;
  6350.                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
  6351.                         trans_edp_pipe = PIPE_C;
  6352.                         break;
  6353.                 }
  6354.  
  6355.                 if (trans_edp_pipe == crtc->pipe)
  6356.                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
  6357.         }
  6358.  
  6359.         if (!intel_display_power_enabled(dev,
  6360.                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
  6361.                 return false;
  6362.  
  6363.         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
  6364.         if (!(tmp & PIPECONF_ENABLE))
  6365.                 return false;
  6366.  
  6367.         /*
  6368.          * Haswell has only FDI/PCH transcoder A. It is which is connected to
  6369.          * DDI E. So just check whether this pipe is wired to DDI E and whether
  6370.          * the PCH transcoder is on.
  6371.          */
  6372.         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
  6373.         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
  6374.             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
  6375.                 pipe_config->has_pch_encoder = true;
  6376.  
  6377.                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
  6378.                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  6379.                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
  6380.  
  6381.                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
  6382.         }
  6383.  
  6384.         intel_get_pipe_timings(crtc, pipe_config);
  6385.  
  6386.         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
  6387.         if (intel_display_power_enabled(dev, pfit_domain))
  6388.                 ironlake_get_pfit_config(crtc, pipe_config);
  6389.  
  6390.         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
  6391.                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
  6392.  
  6393.         pipe_config->pixel_multiplier = 1;
  6394.  
  6395.         return true;
  6396. }
  6397.  
  6398. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  6399.                                int x, int y,
  6400.                                struct drm_framebuffer *fb)
  6401. {
  6402.         struct drm_device *dev = crtc->dev;
  6403.         struct drm_i915_private *dev_priv = dev->dev_private;
  6404.         struct intel_encoder *encoder;
  6405.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6406.         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  6407.         int pipe = intel_crtc->pipe;
  6408.         int ret;
  6409.  
  6410.         drm_vblank_pre_modeset(dev, pipe);
  6411.  
  6412.         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
  6413.  
  6414.         drm_vblank_post_modeset(dev, pipe);
  6415.  
  6416.         if (ret != 0)
  6417.         return ret;
  6418.  
  6419.         for_each_encoder_on_crtc(dev, crtc, encoder) {
  6420.                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
  6421.                         encoder->base.base.id,
  6422.                         drm_get_encoder_name(&encoder->base),
  6423.                         mode->base.id, mode->name);
  6424.                         encoder->mode_set(encoder);
  6425.         }
  6426.  
  6427.         return 0;
  6428. }
  6429.  
  6430. static bool intel_eld_uptodate(struct drm_connector *connector,
  6431.                                int reg_eldv, uint32_t bits_eldv,
  6432.                                int reg_elda, uint32_t bits_elda,
  6433.                                int reg_edid)
  6434. {
  6435.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  6436.         uint8_t *eld = connector->eld;
  6437.         uint32_t i;
  6438.  
  6439.         i = I915_READ(reg_eldv);
  6440.         i &= bits_eldv;
  6441.  
  6442.         if (!eld[0])
  6443.                 return !i;
  6444.  
  6445.         if (!i)
  6446.                 return false;
  6447.  
  6448.         i = I915_READ(reg_elda);
  6449.         i &= ~bits_elda;
  6450.         I915_WRITE(reg_elda, i);
  6451.  
  6452.         for (i = 0; i < eld[2]; i++)
  6453.                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  6454.                         return false;
  6455.  
  6456.         return true;
  6457. }
  6458.  
  6459. static void g4x_write_eld(struct drm_connector *connector,
  6460.                           struct drm_crtc *crtc)
  6461. {
  6462.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  6463.         uint8_t *eld = connector->eld;
  6464.         uint32_t eldv;
  6465.         uint32_t len;
  6466.         uint32_t i;
  6467.  
  6468.         i = I915_READ(G4X_AUD_VID_DID);
  6469.  
  6470.         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
  6471.                 eldv = G4X_ELDV_DEVCL_DEVBLC;
  6472.         else
  6473.                 eldv = G4X_ELDV_DEVCTG;
  6474.  
  6475.         if (intel_eld_uptodate(connector,
  6476.                                G4X_AUD_CNTL_ST, eldv,
  6477.                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
  6478.                                G4X_HDMIW_HDMIEDID))
  6479.                 return;
  6480.  
  6481.         i = I915_READ(G4X_AUD_CNTL_ST);
  6482.         i &= ~(eldv | G4X_ELD_ADDR);
  6483.         len = (i >> 9) & 0x1f;          /* ELD buffer size */
  6484.         I915_WRITE(G4X_AUD_CNTL_ST, i);
  6485.  
  6486.         if (!eld[0])
  6487.                 return;
  6488.  
  6489.         len = min_t(uint8_t, eld[2], len);
  6490.         DRM_DEBUG_DRIVER("ELD size %d\n", len);
  6491.         for (i = 0; i < len; i++)
  6492.                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
  6493.  
  6494.         i = I915_READ(G4X_AUD_CNTL_ST);
  6495.         i |= eldv;
  6496.         I915_WRITE(G4X_AUD_CNTL_ST, i);
  6497. }
  6498.  
  6499. static void haswell_write_eld(struct drm_connector *connector,
  6500.                                      struct drm_crtc *crtc)
  6501. {
  6502.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  6503.         uint8_t *eld = connector->eld;
  6504.         struct drm_device *dev = crtc->dev;
  6505.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6506.         uint32_t eldv;
  6507.         uint32_t i;
  6508.         int len;
  6509.         int pipe = to_intel_crtc(crtc)->pipe;
  6510.         int tmp;
  6511.  
  6512.         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
  6513.         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
  6514.         int aud_config = HSW_AUD_CFG(pipe);
  6515.         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
  6516.  
  6517.  
  6518.         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
  6519.  
  6520.         /* Audio output enable */
  6521.         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
  6522.         tmp = I915_READ(aud_cntrl_st2);
  6523.         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
  6524.         I915_WRITE(aud_cntrl_st2, tmp);
  6525.  
  6526.         /* Wait for 1 vertical blank */
  6527.         intel_wait_for_vblank(dev, pipe);
  6528.  
  6529.         /* Set ELD valid state */
  6530.         tmp = I915_READ(aud_cntrl_st2);
  6531.         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
  6532.         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
  6533.         I915_WRITE(aud_cntrl_st2, tmp);
  6534.         tmp = I915_READ(aud_cntrl_st2);
  6535.         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
  6536.  
  6537.         /* Enable HDMI mode */
  6538.         tmp = I915_READ(aud_config);
  6539.         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
  6540.         /* clear N_programing_enable and N_value_index */
  6541.         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
  6542.         I915_WRITE(aud_config, tmp);
  6543.  
  6544.         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  6545.  
  6546.         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
  6547.         intel_crtc->eld_vld = true;
  6548.  
  6549.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  6550.                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  6551.                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
  6552.                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  6553.         } else
  6554.                 I915_WRITE(aud_config, 0);
  6555.  
  6556.         if (intel_eld_uptodate(connector,
  6557.                                aud_cntrl_st2, eldv,
  6558.                                aud_cntl_st, IBX_ELD_ADDRESS,
  6559.                                hdmiw_hdmiedid))
  6560.                 return;
  6561.  
  6562.         i = I915_READ(aud_cntrl_st2);
  6563.         i &= ~eldv;
  6564.         I915_WRITE(aud_cntrl_st2, i);
  6565.  
  6566.         if (!eld[0])
  6567.                 return;
  6568.  
  6569.         i = I915_READ(aud_cntl_st);
  6570.         i &= ~IBX_ELD_ADDRESS;
  6571.         I915_WRITE(aud_cntl_st, i);
  6572.         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
  6573.         DRM_DEBUG_DRIVER("port num:%d\n", i);
  6574.  
  6575.         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
  6576.         DRM_DEBUG_DRIVER("ELD size %d\n", len);
  6577.         for (i = 0; i < len; i++)
  6578.                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  6579.  
  6580.         i = I915_READ(aud_cntrl_st2);
  6581.         i |= eldv;
  6582.         I915_WRITE(aud_cntrl_st2, i);
  6583.  
  6584. }
  6585.  
  6586. static void ironlake_write_eld(struct drm_connector *connector,
  6587.                                      struct drm_crtc *crtc)
  6588. {
  6589.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  6590.         uint8_t *eld = connector->eld;
  6591.         uint32_t eldv;
  6592.         uint32_t i;
  6593.         int len;
  6594.         int hdmiw_hdmiedid;
  6595.         int aud_config;
  6596.         int aud_cntl_st;
  6597.         int aud_cntrl_st2;
  6598.         int pipe = to_intel_crtc(crtc)->pipe;
  6599.  
  6600.         if (HAS_PCH_IBX(connector->dev)) {
  6601.                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
  6602.                 aud_config = IBX_AUD_CFG(pipe);
  6603.                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
  6604.                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
  6605.         } else {
  6606.                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
  6607.                 aud_config = CPT_AUD_CFG(pipe);
  6608.                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
  6609.                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
  6610.         }
  6611.  
  6612.         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  6613.  
  6614.         i = I915_READ(aud_cntl_st);
  6615.         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
  6616.         if (!i) {
  6617.                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
  6618.                 /* operate blindly on all ports */
  6619.                 eldv = IBX_ELD_VALIDB;
  6620.                 eldv |= IBX_ELD_VALIDB << 4;
  6621.                 eldv |= IBX_ELD_VALIDB << 8;
  6622.         } else {
  6623.                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
  6624.                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
  6625.         }
  6626.  
  6627.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  6628.                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  6629.                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
  6630.                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  6631.         } else
  6632.                 I915_WRITE(aud_config, 0);
  6633.  
  6634.         if (intel_eld_uptodate(connector,
  6635.                                aud_cntrl_st2, eldv,
  6636.                                aud_cntl_st, IBX_ELD_ADDRESS,
  6637.                                hdmiw_hdmiedid))
  6638.                 return;
  6639.  
  6640.         i = I915_READ(aud_cntrl_st2);
  6641.         i &= ~eldv;
  6642.         I915_WRITE(aud_cntrl_st2, i);
  6643.  
  6644.         if (!eld[0])
  6645.                 return;
  6646.  
  6647.         i = I915_READ(aud_cntl_st);
  6648.         i &= ~IBX_ELD_ADDRESS;
  6649.         I915_WRITE(aud_cntl_st, i);
  6650.  
  6651.         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
  6652.         DRM_DEBUG_DRIVER("ELD size %d\n", len);
  6653.         for (i = 0; i < len; i++)
  6654.                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  6655.  
  6656.         i = I915_READ(aud_cntrl_st2);
  6657.         i |= eldv;
  6658.         I915_WRITE(aud_cntrl_st2, i);
  6659. }
  6660.  
  6661. void intel_write_eld(struct drm_encoder *encoder,
  6662.                      struct drm_display_mode *mode)
  6663. {
  6664.         struct drm_crtc *crtc = encoder->crtc;
  6665.         struct drm_connector *connector;
  6666.         struct drm_device *dev = encoder->dev;
  6667.         struct drm_i915_private *dev_priv = dev->dev_private;
  6668.  
  6669.         connector = drm_select_eld(encoder, mode);
  6670.         if (!connector)
  6671.                 return;
  6672.  
  6673.         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  6674.                          connector->base.id,
  6675.                          drm_get_connector_name(connector),
  6676.                          connector->encoder->base.id,
  6677.                          drm_get_encoder_name(connector->encoder));
  6678.  
  6679.         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
  6680.  
  6681.         if (dev_priv->display.write_eld)
  6682.                 dev_priv->display.write_eld(connector, crtc);
  6683. }
  6684.  
  6685. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  6686. void intel_crtc_load_lut(struct drm_crtc *crtc)
  6687. {
  6688.         struct drm_device *dev = crtc->dev;
  6689.         struct drm_i915_private *dev_priv = dev->dev_private;
  6690.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6691.         enum pipe pipe = intel_crtc->pipe;
  6692.         int palreg = PALETTE(pipe);
  6693.         int i;
  6694.         bool reenable_ips = false;
  6695.  
  6696.         /* The clocks have to be on to load the palette. */
  6697.         if (!crtc->enabled || !intel_crtc->active)
  6698.                 return;
  6699.  
  6700.         if (!HAS_PCH_SPLIT(dev_priv->dev))
  6701.                 assert_pll_enabled(dev_priv, pipe);
  6702.  
  6703.         /* use legacy palette for Ironlake */
  6704.         if (HAS_PCH_SPLIT(dev))
  6705.                 palreg = LGC_PALETTE(pipe);
  6706.  
  6707.         /* Workaround : Do not read or write the pipe palette/gamma data while
  6708.          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
  6709.          */
  6710.         if (intel_crtc->config.ips_enabled &&
  6711.             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
  6712.              GAMMA_MODE_MODE_SPLIT)) {
  6713.                 hsw_disable_ips(intel_crtc);
  6714.                 reenable_ips = true;
  6715.         }
  6716.  
  6717.         for (i = 0; i < 256; i++) {
  6718.                 I915_WRITE(palreg + 4 * i,
  6719.                            (intel_crtc->lut_r[i] << 16) |
  6720.                            (intel_crtc->lut_g[i] << 8) |
  6721.                            intel_crtc->lut_b[i]);
  6722.         }
  6723.  
  6724.         if (reenable_ips)
  6725.                 hsw_enable_ips(intel_crtc);
  6726. }
  6727.  
  6728. #if 0
  6729. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  6730. {
  6731.         struct drm_device *dev = crtc->dev;
  6732.         struct drm_i915_private *dev_priv = dev->dev_private;
  6733.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6734.         bool visible = base != 0;
  6735.         u32 cntl;
  6736.  
  6737.         if (intel_crtc->cursor_visible == visible)
  6738.                 return;
  6739.  
  6740.         cntl = I915_READ(_CURACNTR);
  6741.         if (visible) {
  6742.                 /* On these chipsets we can only modify the base whilst
  6743.                  * the cursor is disabled.
  6744.                  */
  6745.                 I915_WRITE(_CURABASE, base);
  6746.  
  6747.                 cntl &= ~(CURSOR_FORMAT_MASK);
  6748.                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
  6749.                 cntl |= CURSOR_ENABLE |
  6750.                         CURSOR_GAMMA_ENABLE |
  6751.                         CURSOR_FORMAT_ARGB;
  6752.         } else
  6753.                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  6754.         I915_WRITE(_CURACNTR, cntl);
  6755.  
  6756.         intel_crtc->cursor_visible = visible;
  6757. }
  6758.  
  6759. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  6760. {
  6761.         struct drm_device *dev = crtc->dev;
  6762.         struct drm_i915_private *dev_priv = dev->dev_private;
  6763.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6764.         int pipe = intel_crtc->pipe;
  6765.         bool visible = base != 0;
  6766.  
  6767.         if (intel_crtc->cursor_visible != visible) {
  6768.                 uint32_t cntl = I915_READ(CURCNTR(pipe));
  6769.                 if (base) {
  6770.                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  6771.                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  6772.                         cntl |= pipe << 28; /* Connect to correct pipe */
  6773.                 } else {
  6774.                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  6775.                         cntl |= CURSOR_MODE_DISABLE;
  6776.                 }
  6777.                 I915_WRITE(CURCNTR(pipe), cntl);
  6778.  
  6779.                 intel_crtc->cursor_visible = visible;
  6780.         }
  6781.         /* and commit changes on next vblank */
  6782.         POSTING_READ(CURCNTR(pipe));
  6783.         I915_WRITE(CURBASE(pipe), base);
  6784.         POSTING_READ(CURBASE(pipe));
  6785. }
  6786.  
  6787. static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
  6788. {
  6789.         struct drm_device *dev = crtc->dev;
  6790.         struct drm_i915_private *dev_priv = dev->dev_private;
  6791.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6792.         int pipe = intel_crtc->pipe;
  6793.         bool visible = base != 0;
  6794.  
  6795.         if (intel_crtc->cursor_visible != visible) {
  6796.                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
  6797.                 if (base) {
  6798.                         cntl &= ~CURSOR_MODE;
  6799.                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  6800.                 } else {
  6801.                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  6802.                         cntl |= CURSOR_MODE_DISABLE;
  6803.                 }
  6804.                 if (IS_HASWELL(dev)) {
  6805.                         cntl |= CURSOR_PIPE_CSC_ENABLE;
  6806.                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
  6807.                 }
  6808.                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
  6809.  
  6810.                 intel_crtc->cursor_visible = visible;
  6811.         }
  6812.         /* and commit changes on next vblank */
  6813.         POSTING_READ(CURCNTR_IVB(pipe));
  6814.         I915_WRITE(CURBASE_IVB(pipe), base);
  6815.         POSTING_READ(CURBASE_IVB(pipe));
  6816. }
  6817.  
  6818. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  6819. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  6820.                                      bool on)
  6821. {
  6822.         struct drm_device *dev = crtc->dev;
  6823.         struct drm_i915_private *dev_priv = dev->dev_private;
  6824.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6825.         int pipe = intel_crtc->pipe;
  6826.         int x = intel_crtc->cursor_x;
  6827.         int y = intel_crtc->cursor_y;
  6828.         u32 base, pos;
  6829.         bool visible;
  6830.  
  6831.         pos = 0;
  6832.  
  6833.         if (on && crtc->enabled && crtc->fb) {
  6834.                 base = intel_crtc->cursor_addr;
  6835.                 if (x > (int) crtc->fb->width)
  6836.                         base = 0;
  6837.  
  6838.                 if (y > (int) crtc->fb->height)
  6839.                         base = 0;
  6840.         } else
  6841.                 base = 0;
  6842.  
  6843.         if (x < 0) {
  6844.                 if (x + intel_crtc->cursor_width < 0)
  6845.                         base = 0;
  6846.  
  6847.                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  6848.                 x = -x;
  6849.         }
  6850.         pos |= x << CURSOR_X_SHIFT;
  6851.  
  6852.         if (y < 0) {
  6853.                 if (y + intel_crtc->cursor_height < 0)
  6854.                         base = 0;
  6855.  
  6856.                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  6857.                 y = -y;
  6858.         }
  6859.         pos |= y << CURSOR_Y_SHIFT;
  6860.  
  6861.         visible = base != 0;
  6862.         if (!visible && !intel_crtc->cursor_visible)
  6863.                 return;
  6864.  
  6865.         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  6866.                 I915_WRITE(CURPOS_IVB(pipe), pos);
  6867.                 ivb_update_cursor(crtc, base);
  6868.         } else {
  6869.                 I915_WRITE(CURPOS(pipe), pos);
  6870.                 if (IS_845G(dev) || IS_I865G(dev))
  6871.                         i845_update_cursor(crtc, base);
  6872.                 else
  6873.                         i9xx_update_cursor(crtc, base);
  6874.         }
  6875. }
  6876.  
  6877. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  6878.                                  struct drm_file *file,
  6879.                                  uint32_t handle,
  6880.                                  uint32_t width, uint32_t height)
  6881. {
  6882.         struct drm_device *dev = crtc->dev;
  6883.         struct drm_i915_private *dev_priv = dev->dev_private;
  6884.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6885.         struct drm_i915_gem_object *obj;
  6886.         uint32_t addr;
  6887.         int ret;
  6888.  
  6889.         /* if we want to turn off the cursor ignore width and height */
  6890.         if (!handle) {
  6891.                 DRM_DEBUG_KMS("cursor off\n");
  6892.                 addr = 0;
  6893.                 obj = NULL;
  6894.                 mutex_lock(&dev->struct_mutex);
  6895.                 goto finish;
  6896.         }
  6897.  
  6898.         /* Currently we only support 64x64 cursors */
  6899.         if (width != 64 || height != 64) {
  6900.                 DRM_ERROR("we currently only support 64x64 cursors\n");
  6901.                 return -EINVAL;
  6902.         }
  6903.  
  6904.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  6905.         if (&obj->base == NULL)
  6906.                 return -ENOENT;
  6907.  
  6908.         if (obj->base.size < width * height * 4) {
  6909.                 DRM_ERROR("buffer is to small\n");
  6910.                 ret = -ENOMEM;
  6911.                 goto fail;
  6912.         }
  6913.  
  6914.         /* we only need to pin inside GTT if cursor is non-phy */
  6915.         mutex_lock(&dev->struct_mutex);
  6916.         if (!dev_priv->info->cursor_needs_physical) {
  6917.                 unsigned alignment;
  6918.  
  6919.                 if (obj->tiling_mode) {
  6920.                         DRM_ERROR("cursor cannot be tiled\n");
  6921.                         ret = -EINVAL;
  6922.                         goto fail_locked;
  6923.                 }
  6924.  
  6925.                 /* Note that the w/a also requires 2 PTE of padding following
  6926.                  * the bo. We currently fill all unused PTE with the shadow
  6927.                  * page and so we should always have valid PTE following the
  6928.                  * cursor preventing the VT-d warning.
  6929.                  */
  6930.                 alignment = 0;
  6931.                 if (need_vtd_wa(dev))
  6932.                         alignment = 64*1024;
  6933.  
  6934.                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
  6935.                 if (ret) {
  6936.                         DRM_ERROR("failed to move cursor bo into the GTT\n");
  6937.                         goto fail_locked;
  6938.                 }
  6939.  
  6940.                 ret = i915_gem_object_put_fence(obj);
  6941.                 if (ret) {
  6942.                         DRM_ERROR("failed to release fence for cursor");
  6943.                         goto fail_unpin;
  6944.                 }
  6945.  
  6946.                 addr = i915_gem_obj_ggtt_offset(obj);
  6947.         } else {
  6948.                 int align = IS_I830(dev) ? 16 * 1024 : 256;
  6949.                 ret = i915_gem_attach_phys_object(dev, obj,
  6950.                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  6951.                                                   align);
  6952.                 if (ret) {
  6953.                         DRM_ERROR("failed to attach phys object\n");
  6954.                         goto fail_locked;
  6955.                 }
  6956.                 addr = obj->phys_obj->handle->busaddr;
  6957.         }
  6958.  
  6959.         if (IS_GEN2(dev))
  6960.                 I915_WRITE(CURSIZE, (height << 12) | width);
  6961.  
  6962.  finish:
  6963.         if (intel_crtc->cursor_bo) {
  6964.                 if (dev_priv->info->cursor_needs_physical) {
  6965.                         if (intel_crtc->cursor_bo != obj)
  6966.                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  6967.                 } else
  6968.                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
  6969.                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  6970.         }
  6971.  
  6972.         mutex_unlock(&dev->struct_mutex);
  6973.  
  6974.         intel_crtc->cursor_addr = addr;
  6975.         intel_crtc->cursor_bo = obj;
  6976.         intel_crtc->cursor_width = width;
  6977.         intel_crtc->cursor_height = height;
  6978.  
  6979.         if (intel_crtc->active)
  6980.                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
  6981.  
  6982.         return 0;
  6983. fail_unpin:
  6984.         i915_gem_object_unpin_from_display_plane(obj);
  6985. fail_locked:
  6986.         mutex_unlock(&dev->struct_mutex);
  6987. fail:
  6988.         drm_gem_object_unreference_unlocked(&obj->base);
  6989.         return ret;
  6990. }
  6991.  
  6992. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  6993. {
  6994.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6995.  
  6996.         intel_crtc->cursor_x = x;
  6997.         intel_crtc->cursor_y = y;
  6998.  
  6999.         if (intel_crtc->active)
  7000.                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
  7001.  
  7002.         return 0;
  7003. }
  7004. #endif
  7005.  
  7006. /** Sets the color ramps on behalf of RandR */
  7007. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  7008.                                  u16 blue, int regno)
  7009. {
  7010.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7011.  
  7012.         intel_crtc->lut_r[regno] = red >> 8;
  7013.         intel_crtc->lut_g[regno] = green >> 8;
  7014.         intel_crtc->lut_b[regno] = blue >> 8;
  7015. }
  7016.  
  7017. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  7018.                              u16 *blue, int regno)
  7019. {
  7020.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7021.  
  7022.         *red = intel_crtc->lut_r[regno] << 8;
  7023.         *green = intel_crtc->lut_g[regno] << 8;
  7024.         *blue = intel_crtc->lut_b[regno] << 8;
  7025. }
  7026.  
  7027. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  7028.                                  u16 *blue, uint32_t start, uint32_t size)
  7029. {
  7030.         int end = (start + size > 256) ? 256 : start + size, i;
  7031.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7032.  
  7033.         for (i = start; i < end; i++) {
  7034.                 intel_crtc->lut_r[i] = red[i] >> 8;
  7035.                 intel_crtc->lut_g[i] = green[i] >> 8;
  7036.                 intel_crtc->lut_b[i] = blue[i] >> 8;
  7037.         }
  7038.  
  7039.         intel_crtc_load_lut(crtc);
  7040. }
  7041.  
  7042. /* VESA 640x480x72Hz mode to set on the pipe */
  7043. static struct drm_display_mode load_detect_mode = {
  7044.         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  7045.                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  7046. };
  7047.  
  7048. static struct drm_framebuffer *
  7049. intel_framebuffer_create(struct drm_device *dev,
  7050.                          struct drm_mode_fb_cmd2 *mode_cmd,
  7051.                          struct drm_i915_gem_object *obj)
  7052. {
  7053.         struct intel_framebuffer *intel_fb;
  7054.         int ret;
  7055.  
  7056.         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  7057.         if (!intel_fb) {
  7058.                 drm_gem_object_unreference_unlocked(&obj->base);
  7059.                 return ERR_PTR(-ENOMEM);
  7060.         }
  7061.  
  7062.         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  7063.         if (ret) {
  7064.                 drm_gem_object_unreference_unlocked(&obj->base);
  7065.                 kfree(intel_fb);
  7066.                 return ERR_PTR(ret);
  7067.         }
  7068.  
  7069.         return &intel_fb->base;
  7070. }
  7071.  
  7072. static u32
  7073. intel_framebuffer_pitch_for_width(int width, int bpp)
  7074. {
  7075.         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  7076.         return ALIGN(pitch, 64);
  7077. }
  7078.  
  7079. static u32
  7080. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  7081. {
  7082.         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  7083.         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  7084. }
  7085.  
  7086. static struct drm_framebuffer *
  7087. intel_framebuffer_create_for_mode(struct drm_device *dev,
  7088.                                   struct drm_display_mode *mode,
  7089.                                   int depth, int bpp)
  7090. {
  7091.         struct drm_i915_gem_object *obj;
  7092.         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
  7093.  
  7094.         return NULL;
  7095. }
  7096.  
  7097. static struct drm_framebuffer *
  7098. mode_fits_in_fbdev(struct drm_device *dev,
  7099.                    struct drm_display_mode *mode)
  7100. {
  7101.         struct drm_i915_private *dev_priv = dev->dev_private;
  7102.         struct drm_i915_gem_object *obj;
  7103.         struct drm_framebuffer *fb;
  7104.  
  7105.         if (dev_priv->fbdev == NULL)
  7106.                 return NULL;
  7107.  
  7108.         obj = dev_priv->fbdev->ifb.obj;
  7109.         if (obj == NULL)
  7110.                 return NULL;
  7111.  
  7112.         fb = &dev_priv->fbdev->ifb.base;
  7113.         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  7114.                                                                fb->bits_per_pixel))
  7115.                 return NULL;
  7116.  
  7117.         if (obj->base.size < mode->vdisplay * fb->pitches[0])
  7118.                 return NULL;
  7119.  
  7120.         return fb;
  7121. }
  7122.  
  7123. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  7124.                                 struct drm_display_mode *mode,
  7125.                                 struct intel_load_detect_pipe *old)
  7126. {
  7127.         struct intel_crtc *intel_crtc;
  7128.         struct intel_encoder *intel_encoder =
  7129.                 intel_attached_encoder(connector);
  7130.         struct drm_crtc *possible_crtc;
  7131.         struct drm_encoder *encoder = &intel_encoder->base;
  7132.         struct drm_crtc *crtc = NULL;
  7133.         struct drm_device *dev = encoder->dev;
  7134.         struct drm_framebuffer *fb;
  7135.         int i = -1;
  7136.  
  7137.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  7138.                       connector->base.id, drm_get_connector_name(connector),
  7139.                       encoder->base.id, drm_get_encoder_name(encoder));
  7140.  
  7141.         /*
  7142.          * Algorithm gets a little messy:
  7143.          *
  7144.          *   - if the connector already has an assigned crtc, use it (but make
  7145.          *     sure it's on first)
  7146.          *
  7147.          *   - try to find the first unused crtc that can drive this connector,
  7148.          *     and use that if we find one
  7149.          */
  7150.  
  7151.         /* See if we already have a CRTC for this connector */
  7152.         if (encoder->crtc) {
  7153.                 crtc = encoder->crtc;
  7154.  
  7155.                 mutex_lock(&crtc->mutex);
  7156.  
  7157.                 old->dpms_mode = connector->dpms;
  7158.                 old->load_detect_temp = false;
  7159.  
  7160.                 /* Make sure the crtc and connector are running */
  7161.                 if (connector->dpms != DRM_MODE_DPMS_ON)
  7162.                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  7163.  
  7164.                 return true;
  7165.         }
  7166.  
  7167.         /* Find an unused one (if possible) */
  7168.         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  7169.                 i++;
  7170.                 if (!(encoder->possible_crtcs & (1 << i)))
  7171.                         continue;
  7172.                 if (!possible_crtc->enabled) {
  7173.                         crtc = possible_crtc;
  7174.                         break;
  7175.                 }
  7176.         }
  7177.  
  7178.         /*
  7179.          * If we didn't find an unused CRTC, don't use any.
  7180.          */
  7181.         if (!crtc) {
  7182.                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
  7183.                 return false;
  7184.         }
  7185.  
  7186.         mutex_lock(&crtc->mutex);
  7187.         intel_encoder->new_crtc = to_intel_crtc(crtc);
  7188.         to_intel_connector(connector)->new_encoder = intel_encoder;
  7189.  
  7190.         intel_crtc = to_intel_crtc(crtc);
  7191.         old->dpms_mode = connector->dpms;
  7192.         old->load_detect_temp = true;
  7193.         old->release_fb = NULL;
  7194.  
  7195.         if (!mode)
  7196.                 mode = &load_detect_mode;
  7197.  
  7198.         /* We need a framebuffer large enough to accommodate all accesses
  7199.          * that the plane may generate whilst we perform load detection.
  7200.          * We can not rely on the fbcon either being present (we get called
  7201.          * during its initialisation to detect all boot displays, or it may
  7202.          * not even exist) or that it is large enough to satisfy the
  7203.          * requested mode.
  7204.          */
  7205.         fb = mode_fits_in_fbdev(dev, mode);
  7206.         if (fb == NULL) {
  7207.                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  7208.                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  7209.                 old->release_fb = fb;
  7210.         } else
  7211.                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  7212.         if (IS_ERR(fb)) {
  7213.                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  7214.                 mutex_unlock(&crtc->mutex);
  7215.                 return false;
  7216.         }
  7217.  
  7218.         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
  7219.                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  7220.                 if (old->release_fb)
  7221.                         old->release_fb->funcs->destroy(old->release_fb);
  7222.                 mutex_unlock(&crtc->mutex);
  7223.                 return false;
  7224.         }
  7225.  
  7226.         /* let the connector get through one full cycle before testing */
  7227.         intel_wait_for_vblank(dev, intel_crtc->pipe);
  7228.         return true;
  7229. }
  7230.  
  7231. void intel_release_load_detect_pipe(struct drm_connector *connector,
  7232.                                     struct intel_load_detect_pipe *old)
  7233. {
  7234.         struct intel_encoder *intel_encoder =
  7235.                 intel_attached_encoder(connector);
  7236.         struct drm_encoder *encoder = &intel_encoder->base;
  7237.         struct drm_crtc *crtc = encoder->crtc;
  7238.  
  7239.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  7240.                       connector->base.id, drm_get_connector_name(connector),
  7241.                       encoder->base.id, drm_get_encoder_name(encoder));
  7242.  
  7243.         if (old->load_detect_temp) {
  7244.                 to_intel_connector(connector)->new_encoder = NULL;
  7245.                 intel_encoder->new_crtc = NULL;
  7246.                 intel_set_mode(crtc, NULL, 0, 0, NULL);
  7247.  
  7248.                 if (old->release_fb) {
  7249.                         drm_framebuffer_unregister_private(old->release_fb);
  7250.                         drm_framebuffer_unreference(old->release_fb);
  7251.                 }
  7252.  
  7253.                 mutex_unlock(&crtc->mutex);
  7254.                 return;
  7255.         }
  7256.  
  7257.         /* Switch crtc and encoder back off if necessary */
  7258.         if (old->dpms_mode != DRM_MODE_DPMS_ON)
  7259.                 connector->funcs->dpms(connector, old->dpms_mode);
  7260.  
  7261.         mutex_unlock(&crtc->mutex);
  7262. }
  7263.  
  7264. /* Returns the clock of the currently programmed mode of the given pipe. */
  7265. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  7266.                                 struct intel_crtc_config *pipe_config)
  7267. {
  7268.         struct drm_device *dev = crtc->base.dev;
  7269.         struct drm_i915_private *dev_priv = dev->dev_private;
  7270.         int pipe = pipe_config->cpu_transcoder;
  7271.         u32 dpll = I915_READ(DPLL(pipe));
  7272.         u32 fp;
  7273.         intel_clock_t clock;
  7274.  
  7275.         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  7276.                 fp = I915_READ(FP0(pipe));
  7277.         else
  7278.                 fp = I915_READ(FP1(pipe));
  7279.  
  7280.         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  7281.         if (IS_PINEVIEW(dev)) {
  7282.                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  7283.                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  7284.         } else {
  7285.                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  7286.                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  7287.         }
  7288.  
  7289.         if (!IS_GEN2(dev)) {
  7290.                 if (IS_PINEVIEW(dev))
  7291.                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  7292.                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  7293.                 else
  7294.                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  7295.                                DPLL_FPA01_P1_POST_DIV_SHIFT);
  7296.  
  7297.                 switch (dpll & DPLL_MODE_MASK) {
  7298.                 case DPLLB_MODE_DAC_SERIAL:
  7299.                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  7300.                                 5 : 10;
  7301.                         break;
  7302.                 case DPLLB_MODE_LVDS:
  7303.                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  7304.                                 7 : 14;
  7305.                         break;
  7306.                 default:
  7307.                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  7308.                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
  7309.                         pipe_config->adjusted_mode.clock = 0;
  7310.                         return;
  7311.                 }
  7312.  
  7313.                 if (IS_PINEVIEW(dev))
  7314.                         pineview_clock(96000, &clock);
  7315.                 else
  7316.                         i9xx_clock(96000, &clock);
  7317.         } else {
  7318.                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  7319.  
  7320.                 if (is_lvds) {
  7321.                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  7322.                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
  7323.                         clock.p2 = 14;
  7324.  
  7325.                         if ((dpll & PLL_REF_INPUT_MASK) ==
  7326.                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  7327.                                 /* XXX: might not be 66MHz */
  7328.                                 i9xx_clock(66000, &clock);
  7329.                         } else
  7330.                                 i9xx_clock(48000, &clock);
  7331.                 } else {
  7332.                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
  7333.                                 clock.p1 = 2;
  7334.                         else {
  7335.                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  7336.                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  7337.                         }
  7338.                         if (dpll & PLL_P2_DIVIDE_BY_4)
  7339.                                 clock.p2 = 4;
  7340.                         else
  7341.                                 clock.p2 = 2;
  7342.  
  7343.                         i9xx_clock(48000, &clock);
  7344.                 }
  7345.         }
  7346.  
  7347.         pipe_config->adjusted_mode.clock = clock.dot;
  7348. }
  7349.  
  7350. static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  7351.                                     struct intel_crtc_config *pipe_config)
  7352. {
  7353.         struct drm_device *dev = crtc->base.dev;
  7354.         struct drm_i915_private *dev_priv = dev->dev_private;
  7355.         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
  7356.         int link_freq, repeat;
  7357.         u64 clock;
  7358.         u32 link_m, link_n;
  7359.  
  7360.         repeat = pipe_config->pixel_multiplier;
  7361.  
  7362.         /*
  7363.          * The calculation for the data clock is:
  7364.          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
  7365.          * But we want to avoid losing precison if possible, so:
  7366.          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
  7367.          *
  7368.          * and the link clock is simpler:
  7369.          * link_clock = (m * link_clock * repeat) / n
  7370.          */
  7371.  
  7372.         /*
  7373.          * We need to get the FDI or DP link clock here to derive
  7374.          * the M/N dividers.
  7375.          *
  7376.          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
  7377.          * For DP, it's either 1.62GHz or 2.7GHz.
  7378.          * We do our calculations in 10*MHz since we don't need much precison.
  7379.          */
  7380.         if (pipe_config->has_pch_encoder)
  7381.                 link_freq = intel_fdi_link_freq(dev) * 10000;
  7382.         else
  7383.                 link_freq = pipe_config->port_clock;
  7384.  
  7385.         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
  7386.         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
  7387.  
  7388.         if (!link_m || !link_n)
  7389.                 return;
  7390.  
  7391.         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
  7392.         do_div(clock, link_n);
  7393.  
  7394.         pipe_config->adjusted_mode.clock = clock;
  7395. }
  7396.  
  7397. /** Returns the currently programmed mode of the given pipe. */
  7398. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  7399.                                              struct drm_crtc *crtc)
  7400. {
  7401.         struct drm_i915_private *dev_priv = dev->dev_private;
  7402.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7403.         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  7404.         struct drm_display_mode *mode;
  7405.         struct intel_crtc_config pipe_config;
  7406.         int htot = I915_READ(HTOTAL(cpu_transcoder));
  7407.         int hsync = I915_READ(HSYNC(cpu_transcoder));
  7408.         int vtot = I915_READ(VTOTAL(cpu_transcoder));
  7409.         int vsync = I915_READ(VSYNC(cpu_transcoder));
  7410.  
  7411.         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  7412.         if (!mode)
  7413.                 return NULL;
  7414.  
  7415.         /*
  7416.          * Construct a pipe_config sufficient for getting the clock info
  7417.          * back out of crtc_clock_get.
  7418.          *
  7419.          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
  7420.          * to use a real value here instead.
  7421.          */
  7422.         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
  7423.         pipe_config.pixel_multiplier = 1;
  7424.         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
  7425.  
  7426.         mode->clock = pipe_config.adjusted_mode.clock;
  7427.         mode->hdisplay = (htot & 0xffff) + 1;
  7428.         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  7429.         mode->hsync_start = (hsync & 0xffff) + 1;
  7430.         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  7431.         mode->vdisplay = (vtot & 0xffff) + 1;
  7432.         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  7433.         mode->vsync_start = (vsync & 0xffff) + 1;
  7434.         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  7435.  
  7436.         drm_mode_set_name(mode);
  7437.  
  7438.         return mode;
  7439. }
  7440.  
  7441. static void intel_increase_pllclock(struct drm_crtc *crtc)
  7442. {
  7443.         struct drm_device *dev = crtc->dev;
  7444.         drm_i915_private_t *dev_priv = dev->dev_private;
  7445.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7446.         int pipe = intel_crtc->pipe;
  7447.         int dpll_reg = DPLL(pipe);
  7448.         int dpll;
  7449.  
  7450.         if (HAS_PCH_SPLIT(dev))
  7451.                 return;
  7452.  
  7453.         if (!dev_priv->lvds_downclock_avail)
  7454.                 return;
  7455.  
  7456.         dpll = I915_READ(dpll_reg);
  7457.         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  7458.                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
  7459.  
  7460.                 assert_panel_unlocked(dev_priv, pipe);
  7461.  
  7462.                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  7463.                 I915_WRITE(dpll_reg, dpll);
  7464.                 intel_wait_for_vblank(dev, pipe);
  7465.  
  7466.                 dpll = I915_READ(dpll_reg);
  7467.                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
  7468.                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  7469.         }
  7470. }
  7471.  
  7472. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  7473. {
  7474.         struct drm_device *dev = crtc->dev;
  7475.         drm_i915_private_t *dev_priv = dev->dev_private;
  7476.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7477.  
  7478.         if (HAS_PCH_SPLIT(dev))
  7479.                 return;
  7480.  
  7481.         if (!dev_priv->lvds_downclock_avail)
  7482.                 return;
  7483.  
  7484.         /*
  7485.          * Since this is called by a timer, we should never get here in
  7486.          * the manual case.
  7487.          */
  7488.         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  7489.                 int pipe = intel_crtc->pipe;
  7490.                 int dpll_reg = DPLL(pipe);
  7491.                 int dpll;
  7492.  
  7493.                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
  7494.  
  7495.                 assert_panel_unlocked(dev_priv, pipe);
  7496.  
  7497.                 dpll = I915_READ(dpll_reg);
  7498.                 dpll |= DISPLAY_RATE_SELECT_FPA1;
  7499.                 I915_WRITE(dpll_reg, dpll);
  7500.                 intel_wait_for_vblank(dev, pipe);
  7501.                 dpll = I915_READ(dpll_reg);
  7502.                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  7503.                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  7504.         }
  7505.  
  7506. }
  7507.  
  7508. void intel_mark_busy(struct drm_device *dev)
  7509. {
  7510.         struct drm_i915_private *dev_priv = dev->dev_private;
  7511.  
  7512.         hsw_package_c8_gpu_busy(dev_priv);
  7513.         i915_update_gfx_val(dev_priv);
  7514. }
  7515.  
  7516. void intel_mark_idle(struct drm_device *dev)
  7517. {
  7518.         struct drm_i915_private *dev_priv = dev->dev_private;
  7519.         struct drm_crtc *crtc;
  7520.  
  7521.         hsw_package_c8_gpu_idle(dev_priv);
  7522.  
  7523.         if (!i915_powersave)
  7524.                 return;
  7525.  
  7526.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  7527.                 if (!crtc->fb)
  7528.                         continue;
  7529.  
  7530.                 intel_decrease_pllclock(crtc);
  7531.         }
  7532. }
  7533.  
  7534. void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
  7535.                         struct intel_ring_buffer *ring)
  7536. {
  7537.         struct drm_device *dev = obj->base.dev;
  7538.         struct drm_crtc *crtc;
  7539.  
  7540.         if (!i915_powersave)
  7541.                 return;
  7542.  
  7543.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  7544.                 if (!crtc->fb)
  7545.                         continue;
  7546.  
  7547.                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
  7548.                         continue;
  7549.  
  7550.                         intel_increase_pllclock(crtc);
  7551.                 if (ring && intel_fbc_enabled(dev))
  7552.                         ring->fbc_dirty = true;
  7553.         }
  7554. }
  7555.  
  7556. static void intel_crtc_destroy(struct drm_crtc *crtc)
  7557. {
  7558.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7559.         struct drm_device *dev = crtc->dev;
  7560.         struct intel_unpin_work *work;
  7561.         unsigned long flags;
  7562.  
  7563.         spin_lock_irqsave(&dev->event_lock, flags);
  7564.         work = intel_crtc->unpin_work;
  7565.         intel_crtc->unpin_work = NULL;
  7566.         spin_unlock_irqrestore(&dev->event_lock, flags);
  7567.  
  7568.         if (work) {
  7569.                 cancel_work_sync(&work->work);
  7570.                 kfree(work);
  7571.         }
  7572.  
  7573.         drm_crtc_cleanup(crtc);
  7574.  
  7575.         kfree(intel_crtc);
  7576. }
  7577.  
  7578. #if 0
  7579. static void intel_unpin_work_fn(struct work_struct *__work)
  7580. {
  7581.         struct intel_unpin_work *work =
  7582.                 container_of(__work, struct intel_unpin_work, work);
  7583.         struct drm_device *dev = work->crtc->dev;
  7584.  
  7585.         mutex_lock(&dev->struct_mutex);
  7586.         intel_unpin_fb_obj(work->old_fb_obj);
  7587.         drm_gem_object_unreference(&work->pending_flip_obj->base);
  7588.         drm_gem_object_unreference(&work->old_fb_obj->base);
  7589.  
  7590.         intel_update_fbc(dev);
  7591.         mutex_unlock(&dev->struct_mutex);
  7592.  
  7593.         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
  7594.         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
  7595.  
  7596.         kfree(work);
  7597. }
  7598.  
  7599. static void do_intel_finish_page_flip(struct drm_device *dev,
  7600.                                       struct drm_crtc *crtc)
  7601. {
  7602.         drm_i915_private_t *dev_priv = dev->dev_private;
  7603.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7604.         struct intel_unpin_work *work;
  7605.         unsigned long flags;
  7606.  
  7607.         /* Ignore early vblank irqs */
  7608.         if (intel_crtc == NULL)
  7609.                 return;
  7610.  
  7611.         spin_lock_irqsave(&dev->event_lock, flags);
  7612.         work = intel_crtc->unpin_work;
  7613.  
  7614.         /* Ensure we don't miss a work->pending update ... */
  7615.         smp_rmb();
  7616.  
  7617.         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
  7618.                 spin_unlock_irqrestore(&dev->event_lock, flags);
  7619.                 return;
  7620.         }
  7621.  
  7622.         /* and that the unpin work is consistent wrt ->pending. */
  7623.         smp_rmb();
  7624.  
  7625.         intel_crtc->unpin_work = NULL;
  7626.  
  7627.         if (work->event)
  7628.                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
  7629.  
  7630.         drm_vblank_put(dev, intel_crtc->pipe);
  7631.  
  7632.         spin_unlock_irqrestore(&dev->event_lock, flags);
  7633.  
  7634.         wake_up_all(&dev_priv->pending_flip_queue);
  7635.  
  7636.         queue_work(dev_priv->wq, &work->work);
  7637.  
  7638.         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  7639. }
  7640.  
  7641. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  7642. {
  7643.         drm_i915_private_t *dev_priv = dev->dev_private;
  7644.         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  7645.  
  7646.         do_intel_finish_page_flip(dev, crtc);
  7647. }
  7648.  
  7649. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  7650. {
  7651.         drm_i915_private_t *dev_priv = dev->dev_private;
  7652.         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  7653.  
  7654.         do_intel_finish_page_flip(dev, crtc);
  7655. }
  7656.  
  7657. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  7658. {
  7659.         drm_i915_private_t *dev_priv = dev->dev_private;
  7660.         struct intel_crtc *intel_crtc =
  7661.                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  7662.         unsigned long flags;
  7663.  
  7664.         /* NB: An MMIO update of the plane base pointer will also
  7665.          * generate a page-flip completion irq, i.e. every modeset
  7666.          * is also accompanied by a spurious intel_prepare_page_flip().
  7667.          */
  7668.         spin_lock_irqsave(&dev->event_lock, flags);
  7669.         if (intel_crtc->unpin_work)
  7670.                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
  7671.         spin_unlock_irqrestore(&dev->event_lock, flags);
  7672. }
  7673.  
  7674. inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
  7675. {
  7676.         /* Ensure that the work item is consistent when activating it ... */
  7677.         smp_wmb();
  7678.         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
  7679.         /* and that it is marked active as soon as the irq could fire. */
  7680.         smp_wmb();
  7681. }
  7682.  
  7683. static int intel_gen2_queue_flip(struct drm_device *dev,
  7684.                                  struct drm_crtc *crtc,
  7685.                                  struct drm_framebuffer *fb,
  7686.                                  struct drm_i915_gem_object *obj,
  7687.                                  uint32_t flags)
  7688. {
  7689.         struct drm_i915_private *dev_priv = dev->dev_private;
  7690.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7691.         u32 flip_mask;
  7692.         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  7693.         int ret;
  7694.  
  7695.         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  7696.         if (ret)
  7697.                 goto err;
  7698.  
  7699.         ret = intel_ring_begin(ring, 6);
  7700.         if (ret)
  7701.                 goto err_unpin;
  7702.  
  7703.         /* Can't queue multiple flips, so wait for the previous
  7704.          * one to finish before executing the next.
  7705.          */
  7706.         if (intel_crtc->plane)
  7707.                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  7708.         else
  7709.                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  7710.         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  7711.         intel_ring_emit(ring, MI_NOOP);
  7712.         intel_ring_emit(ring, MI_DISPLAY_FLIP |
  7713.                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  7714.         intel_ring_emit(ring, fb->pitches[0]);
  7715.         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  7716.         intel_ring_emit(ring, 0); /* aux display base address, unused */
  7717.  
  7718.         intel_mark_page_flip_active(intel_crtc);
  7719.         intel_ring_advance(ring);
  7720.         return 0;
  7721.  
  7722. err_unpin:
  7723.         intel_unpin_fb_obj(obj);
  7724. err:
  7725.         return ret;
  7726. }
  7727.  
  7728. static int intel_gen3_queue_flip(struct drm_device *dev,
  7729.                                  struct drm_crtc *crtc,
  7730.                                  struct drm_framebuffer *fb,
  7731.                                  struct drm_i915_gem_object *obj,
  7732.                                  uint32_t flags)
  7733. {
  7734.         struct drm_i915_private *dev_priv = dev->dev_private;
  7735.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7736.         u32 flip_mask;
  7737.         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  7738.         int ret;
  7739.  
  7740.         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  7741.         if (ret)
  7742.                 goto err;
  7743.  
  7744.         ret = intel_ring_begin(ring, 6);
  7745.         if (ret)
  7746.                 goto err_unpin;
  7747.  
  7748.         if (intel_crtc->plane)
  7749.                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  7750.         else
  7751.                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  7752.         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  7753.         intel_ring_emit(ring, MI_NOOP);
  7754.         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
  7755.                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  7756.         intel_ring_emit(ring, fb->pitches[0]);
  7757.         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  7758.         intel_ring_emit(ring, MI_NOOP);
  7759.  
  7760.         intel_mark_page_flip_active(intel_crtc);
  7761.         intel_ring_advance(ring);
  7762.         return 0;
  7763.  
  7764. err_unpin:
  7765.         intel_unpin_fb_obj(obj);
  7766. err:
  7767.         return ret;
  7768. }
  7769.  
  7770. static int intel_gen4_queue_flip(struct drm_device *dev,
  7771.                                  struct drm_crtc *crtc,
  7772.                                  struct drm_framebuffer *fb,
  7773.                                  struct drm_i915_gem_object *obj,
  7774.                                  uint32_t flags)
  7775. {
  7776.         struct drm_i915_private *dev_priv = dev->dev_private;
  7777.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7778.         uint32_t pf, pipesrc;
  7779.         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  7780.         int ret;
  7781.  
  7782.         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  7783.         if (ret)
  7784.                 goto err;
  7785.  
  7786.         ret = intel_ring_begin(ring, 4);
  7787.         if (ret)
  7788.                 goto err_unpin;
  7789.  
  7790.         /* i965+ uses the linear or tiled offsets from the
  7791.          * Display Registers (which do not change across a page-flip)
  7792.          * so we need only reprogram the base address.
  7793.          */
  7794.         intel_ring_emit(ring, MI_DISPLAY_FLIP |
  7795.                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  7796.         intel_ring_emit(ring, fb->pitches[0]);
  7797.         intel_ring_emit(ring,
  7798.                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
  7799.                         obj->tiling_mode);
  7800.  
  7801.         /* XXX Enabling the panel-fitter across page-flip is so far
  7802.          * untested on non-native modes, so ignore it for now.
  7803.          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  7804.          */
  7805.         pf = 0;
  7806.         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  7807.         intel_ring_emit(ring, pf | pipesrc);
  7808.  
  7809.         intel_mark_page_flip_active(intel_crtc);
  7810.         intel_ring_advance(ring);
  7811.         return 0;
  7812.  
  7813. err_unpin:
  7814.         intel_unpin_fb_obj(obj);
  7815. err:
  7816.         return ret;
  7817. }
  7818.  
  7819. static int intel_gen6_queue_flip(struct drm_device *dev,
  7820.                                  struct drm_crtc *crtc,
  7821.                                  struct drm_framebuffer *fb,
  7822.                                  struct drm_i915_gem_object *obj,
  7823.                                  uint32_t flags)
  7824. {
  7825.         struct drm_i915_private *dev_priv = dev->dev_private;
  7826.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7827.         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  7828.         uint32_t pf, pipesrc;
  7829.         int ret;
  7830.  
  7831.         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  7832.         if (ret)
  7833.                 goto err;
  7834.  
  7835.         ret = intel_ring_begin(ring, 4);
  7836.         if (ret)
  7837.                 goto err_unpin;
  7838.  
  7839.         intel_ring_emit(ring, MI_DISPLAY_FLIP |
  7840.                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  7841.         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
  7842.         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  7843.  
  7844.         /* Contrary to the suggestions in the documentation,
  7845.          * "Enable Panel Fitter" does not seem to be required when page
  7846.          * flipping with a non-native mode, and worse causes a normal
  7847.          * modeset to fail.
  7848.          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  7849.          */
  7850.         pf = 0;
  7851.         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  7852.         intel_ring_emit(ring, pf | pipesrc);
  7853.  
  7854.         intel_mark_page_flip_active(intel_crtc);
  7855.         intel_ring_advance(ring);
  7856.         return 0;
  7857.  
  7858. err_unpin:
  7859.         intel_unpin_fb_obj(obj);
  7860. err:
  7861.         return ret;
  7862. }
  7863.  
  7864. static int intel_gen7_queue_flip(struct drm_device *dev,
  7865.                                  struct drm_crtc *crtc,
  7866.                                  struct drm_framebuffer *fb,
  7867.                                  struct drm_i915_gem_object *obj,
  7868.                                  uint32_t flags)
  7869. {
  7870.         struct drm_i915_private *dev_priv = dev->dev_private;
  7871.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7872.         struct intel_ring_buffer *ring;
  7873.         uint32_t plane_bit = 0;
  7874.         int len, ret;
  7875.  
  7876.         ring = obj->ring;
  7877.         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
  7878.                 ring = &dev_priv->ring[BCS];
  7879.  
  7880.         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  7881.         if (ret)
  7882.                 goto err;
  7883.  
  7884.         switch(intel_crtc->plane) {
  7885.         case PLANE_A:
  7886.                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
  7887.                 break;
  7888.         case PLANE_B:
  7889.                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
  7890.                 break;
  7891.         case PLANE_C:
  7892.                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
  7893.                 break;
  7894.         default:
  7895.                 WARN_ONCE(1, "unknown plane in flip command\n");
  7896.                 ret = -ENODEV;
  7897.                 goto err_unpin;
  7898.         }
  7899.  
  7900.         len = 4;
  7901.         if (ring->id == RCS)
  7902.                 len += 6;
  7903.  
  7904.         ret = intel_ring_begin(ring, len);
  7905.         if (ret)
  7906.                 goto err_unpin;
  7907.  
  7908.         /* Unmask the flip-done completion message. Note that the bspec says that
  7909.          * we should do this for both the BCS and RCS, and that we must not unmask
  7910.          * more than one flip event at any time (or ensure that one flip message
  7911.          * can be sent by waiting for flip-done prior to queueing new flips).
  7912.          * Experimentation says that BCS works despite DERRMR masking all
  7913.          * flip-done completion events and that unmasking all planes at once
  7914.          * for the RCS also doesn't appear to drop events. Setting the DERRMR
  7915.          * to zero does lead to lockups within MI_DISPLAY_FLIP.
  7916.          */
  7917.         if (ring->id == RCS) {
  7918.                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  7919.                 intel_ring_emit(ring, DERRMR);
  7920.                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
  7921.                                         DERRMR_PIPEB_PRI_FLIP_DONE |
  7922.                                         DERRMR_PIPEC_PRI_FLIP_DONE));
  7923.                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
  7924.                 intel_ring_emit(ring, DERRMR);
  7925.                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
  7926.         }
  7927.  
  7928.         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
  7929.         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
  7930.         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  7931.         intel_ring_emit(ring, (MI_NOOP));
  7932.  
  7933.         intel_mark_page_flip_active(intel_crtc);
  7934.         intel_ring_advance(ring);
  7935.         return 0;
  7936.  
  7937. err_unpin:
  7938.         intel_unpin_fb_obj(obj);
  7939. err:
  7940.         return ret;
  7941. }
  7942.  
  7943. static int intel_default_queue_flip(struct drm_device *dev,
  7944.                                     struct drm_crtc *crtc,
  7945.                                     struct drm_framebuffer *fb,
  7946.                                     struct drm_i915_gem_object *obj,
  7947.                                     uint32_t flags)
  7948. {
  7949.         return -ENODEV;
  7950. }
  7951.  
  7952. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  7953.                                 struct drm_framebuffer *fb,
  7954.                                 struct drm_pending_vblank_event *event,
  7955.                                 uint32_t page_flip_flags)
  7956. {
  7957.         struct drm_device *dev = crtc->dev;
  7958.         struct drm_i915_private *dev_priv = dev->dev_private;
  7959.         struct drm_framebuffer *old_fb = crtc->fb;
  7960.         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
  7961.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7962.         struct intel_unpin_work *work;
  7963.         unsigned long flags;
  7964.         int ret;
  7965.  
  7966.         /* Can't change pixel format via MI display flips. */
  7967.         if (fb->pixel_format != crtc->fb->pixel_format)
  7968.                 return -EINVAL;
  7969.  
  7970.         /*
  7971.          * TILEOFF/LINOFF registers can't be changed via MI display flips.
  7972.          * Note that pitch changes could also affect these register.
  7973.          */
  7974.         if (INTEL_INFO(dev)->gen > 3 &&
  7975.             (fb->offsets[0] != crtc->fb->offsets[0] ||
  7976.              fb->pitches[0] != crtc->fb->pitches[0]))
  7977.                 return -EINVAL;
  7978.  
  7979.         work = kzalloc(sizeof *work, GFP_KERNEL);
  7980.         if (work == NULL)
  7981.                 return -ENOMEM;
  7982.  
  7983.         work->event = event;
  7984.         work->crtc = crtc;
  7985.         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
  7986.         INIT_WORK(&work->work, intel_unpin_work_fn);
  7987.  
  7988.         ret = drm_vblank_get(dev, intel_crtc->pipe);
  7989.         if (ret)
  7990.                 goto free_work;
  7991.  
  7992.         /* We borrow the event spin lock for protecting unpin_work */
  7993.         spin_lock_irqsave(&dev->event_lock, flags);
  7994.         if (intel_crtc->unpin_work) {
  7995.                 spin_unlock_irqrestore(&dev->event_lock, flags);
  7996.                 kfree(work);
  7997.                 drm_vblank_put(dev, intel_crtc->pipe);
  7998.  
  7999.                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  8000.                 return -EBUSY;
  8001.         }
  8002.         intel_crtc->unpin_work = work;
  8003.         spin_unlock_irqrestore(&dev->event_lock, flags);
  8004.  
  8005.         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
  8006.                 flush_workqueue(dev_priv->wq);
  8007.  
  8008.         ret = i915_mutex_lock_interruptible(dev);
  8009.         if (ret)
  8010.                 goto cleanup;
  8011.  
  8012.         /* Reference the objects for the scheduled work. */
  8013.         drm_gem_object_reference(&work->old_fb_obj->base);
  8014.         drm_gem_object_reference(&obj->base);
  8015.  
  8016.         crtc->fb = fb;
  8017.  
  8018.         work->pending_flip_obj = obj;
  8019.  
  8020.         work->enable_stall_check = true;
  8021.  
  8022.         atomic_inc(&intel_crtc->unpin_work_count);
  8023.         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  8024.  
  8025.         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
  8026.         if (ret)
  8027.                 goto cleanup_pending;
  8028.  
  8029.         intel_disable_fbc(dev);
  8030.         intel_mark_fb_busy(obj, NULL);
  8031.         mutex_unlock(&dev->struct_mutex);
  8032.  
  8033.         trace_i915_flip_request(intel_crtc->plane, obj);
  8034.  
  8035.         return 0;
  8036.  
  8037. cleanup_pending:
  8038.         atomic_dec(&intel_crtc->unpin_work_count);
  8039.         crtc->fb = old_fb;
  8040.         drm_gem_object_unreference(&work->old_fb_obj->base);
  8041.         drm_gem_object_unreference(&obj->base);
  8042.         mutex_unlock(&dev->struct_mutex);
  8043.  
  8044. cleanup:
  8045.         spin_lock_irqsave(&dev->event_lock, flags);
  8046.         intel_crtc->unpin_work = NULL;
  8047.         spin_unlock_irqrestore(&dev->event_lock, flags);
  8048.  
  8049.         drm_vblank_put(dev, intel_crtc->pipe);
  8050. free_work:
  8051.         kfree(work);
  8052.  
  8053.         return ret;
  8054. }
  8055. #endif
  8056.  
  8057. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  8058.         .mode_set_base_atomic = intel_pipe_set_base_atomic,
  8059.         .load_lut = intel_crtc_load_lut,
  8060. };
  8061.  
  8062. static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
  8063.                                   struct drm_crtc *crtc)
  8064. {
  8065.         struct drm_device *dev;
  8066.         struct drm_crtc *tmp;
  8067.         int crtc_mask = 1;
  8068.  
  8069.         WARN(!crtc, "checking null crtc?\n");
  8070.  
  8071.         dev = crtc->dev;
  8072.  
  8073.         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
  8074.                 if (tmp == crtc)
  8075.                         break;
  8076.                 crtc_mask <<= 1;
  8077.         }
  8078.  
  8079.         if (encoder->possible_crtcs & crtc_mask)
  8080.                 return true;
  8081.         return false;
  8082. }
  8083.  
  8084. /**
  8085.  * intel_modeset_update_staged_output_state
  8086.  *
  8087.  * Updates the staged output configuration state, e.g. after we've read out the
  8088.  * current hw state.
  8089.  */
  8090. static void intel_modeset_update_staged_output_state(struct drm_device *dev)
  8091. {
  8092.         struct intel_encoder *encoder;
  8093.         struct intel_connector *connector;
  8094.  
  8095.         list_for_each_entry(connector, &dev->mode_config.connector_list,
  8096.                             base.head) {
  8097.                 connector->new_encoder =
  8098.                         to_intel_encoder(connector->base.encoder);
  8099.         }
  8100.  
  8101.         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8102.                             base.head) {
  8103.                 encoder->new_crtc =
  8104.                         to_intel_crtc(encoder->base.crtc);
  8105.         }
  8106. }
  8107.  
  8108. /**
  8109.  * intel_modeset_commit_output_state
  8110.  *
  8111.  * This function copies the stage display pipe configuration to the real one.
  8112.  */
  8113. static void intel_modeset_commit_output_state(struct drm_device *dev)
  8114. {
  8115.         struct intel_encoder *encoder;
  8116.         struct intel_connector *connector;
  8117.  
  8118.         list_for_each_entry(connector, &dev->mode_config.connector_list,
  8119.                             base.head) {
  8120.                 connector->base.encoder = &connector->new_encoder->base;
  8121.         }
  8122.  
  8123.         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8124.                             base.head) {
  8125.                 encoder->base.crtc = &encoder->new_crtc->base;
  8126.         }
  8127. }
  8128.  
  8129. static void
  8130. connected_sink_compute_bpp(struct intel_connector * connector,
  8131.                            struct intel_crtc_config *pipe_config)
  8132. {
  8133.         int bpp = pipe_config->pipe_bpp;
  8134.  
  8135.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
  8136.                 connector->base.base.id,
  8137.                 drm_get_connector_name(&connector->base));
  8138.  
  8139.         /* Don't use an invalid EDID bpc value */
  8140.         if (connector->base.display_info.bpc &&
  8141.             connector->base.display_info.bpc * 3 < bpp) {
  8142.                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
  8143.                               bpp, connector->base.display_info.bpc*3);
  8144.                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
  8145.         }
  8146.  
  8147.         /* Clamp bpp to 8 on screens without EDID 1.4 */
  8148.         if (connector->base.display_info.bpc == 0 && bpp > 24) {
  8149.                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
  8150.                               bpp);
  8151.                 pipe_config->pipe_bpp = 24;
  8152.         }
  8153. }
  8154.  
  8155. static int
  8156. compute_baseline_pipe_bpp(struct intel_crtc *crtc,
  8157.                     struct drm_framebuffer *fb,
  8158.                     struct intel_crtc_config *pipe_config)
  8159. {
  8160.         struct drm_device *dev = crtc->base.dev;
  8161.         struct intel_connector *connector;
  8162.         int bpp;
  8163.  
  8164.         switch (fb->pixel_format) {
  8165.         case DRM_FORMAT_C8:
  8166.                 bpp = 8*3; /* since we go through a colormap */
  8167.                 break;
  8168.         case DRM_FORMAT_XRGB1555:
  8169.         case DRM_FORMAT_ARGB1555:
  8170.                 /* checked in intel_framebuffer_init already */
  8171.                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
  8172.                         return -EINVAL;
  8173.         case DRM_FORMAT_RGB565:
  8174.                 bpp = 6*3; /* min is 18bpp */
  8175.                 break;
  8176.         case DRM_FORMAT_XBGR8888:
  8177.         case DRM_FORMAT_ABGR8888:
  8178.                 /* checked in intel_framebuffer_init already */
  8179.                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  8180.                         return -EINVAL;
  8181.         case DRM_FORMAT_XRGB8888:
  8182.         case DRM_FORMAT_ARGB8888:
  8183.                 bpp = 8*3;
  8184.                 break;
  8185.         case DRM_FORMAT_XRGB2101010:
  8186.         case DRM_FORMAT_ARGB2101010:
  8187.         case DRM_FORMAT_XBGR2101010:
  8188.         case DRM_FORMAT_ABGR2101010:
  8189.                 /* checked in intel_framebuffer_init already */
  8190.                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  8191.                         return -EINVAL;
  8192.                 bpp = 10*3;
  8193.                 break;
  8194.         /* TODO: gen4+ supports 16 bpc floating point, too. */
  8195.         default:
  8196.                 DRM_DEBUG_KMS("unsupported depth\n");
  8197.                 return -EINVAL;
  8198.         }
  8199.  
  8200.         pipe_config->pipe_bpp = bpp;
  8201.  
  8202.         /* Clamp display bpp to EDID value */
  8203.         list_for_each_entry(connector, &dev->mode_config.connector_list,
  8204.                             base.head) {
  8205.                 if (!connector->new_encoder ||
  8206.                     connector->new_encoder->new_crtc != crtc)
  8207.                         continue;
  8208.  
  8209.                 connected_sink_compute_bpp(connector, pipe_config);
  8210.         }
  8211.  
  8212.         return bpp;
  8213. }
  8214.  
  8215. static void intel_dump_pipe_config(struct intel_crtc *crtc,
  8216.                                    struct intel_crtc_config *pipe_config,
  8217.                                    const char *context)
  8218. {
  8219.         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
  8220.                       context, pipe_name(crtc->pipe));
  8221.  
  8222.         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
  8223.         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
  8224.                       pipe_config->pipe_bpp, pipe_config->dither);
  8225.         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  8226.                       pipe_config->has_pch_encoder,
  8227.                       pipe_config->fdi_lanes,
  8228.                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
  8229.                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
  8230.                       pipe_config->fdi_m_n.tu);
  8231.         DRM_DEBUG_KMS("requested mode:\n");
  8232.         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
  8233.         DRM_DEBUG_KMS("adjusted mode:\n");
  8234.         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
  8235.         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
  8236.                       pipe_config->gmch_pfit.control,
  8237.                       pipe_config->gmch_pfit.pgm_ratios,
  8238.                       pipe_config->gmch_pfit.lvds_border_bits);
  8239.         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
  8240.                       pipe_config->pch_pfit.pos,
  8241.                       pipe_config->pch_pfit.size,
  8242.                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
  8243.         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
  8244. }
  8245.  
  8246. static bool check_encoder_cloning(struct drm_crtc *crtc)
  8247. {
  8248.         int num_encoders = 0;
  8249.         bool uncloneable_encoders = false;
  8250.         struct intel_encoder *encoder;
  8251.  
  8252.         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
  8253.                             base.head) {
  8254.                 if (&encoder->new_crtc->base != crtc)
  8255.                         continue;
  8256.  
  8257.                 num_encoders++;
  8258.                 if (!encoder->cloneable)
  8259.                         uncloneable_encoders = true;
  8260.         }
  8261.  
  8262.         return !(num_encoders > 1 && uncloneable_encoders);
  8263. }
  8264.  
  8265. static struct intel_crtc_config *
  8266. intel_modeset_pipe_config(struct drm_crtc *crtc,
  8267.                           struct drm_framebuffer *fb,
  8268.                             struct drm_display_mode *mode)
  8269. {
  8270.         struct drm_device *dev = crtc->dev;
  8271.         struct intel_encoder *encoder;
  8272.         struct intel_crtc_config *pipe_config;
  8273.         int plane_bpp, ret = -EINVAL;
  8274.         bool retry = true;
  8275.  
  8276.         if (!check_encoder_cloning(crtc)) {
  8277.                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
  8278.                 return ERR_PTR(-EINVAL);
  8279.         }
  8280.  
  8281.         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
  8282.         if (!pipe_config)
  8283.                 return ERR_PTR(-ENOMEM);
  8284.  
  8285.         drm_mode_copy(&pipe_config->adjusted_mode, mode);
  8286.         drm_mode_copy(&pipe_config->requested_mode, mode);
  8287.         pipe_config->cpu_transcoder =
  8288.                 (enum transcoder) to_intel_crtc(crtc)->pipe;
  8289.         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  8290.  
  8291.         /*
  8292.          * Sanitize sync polarity flags based on requested ones. If neither
  8293.          * positive or negative polarity is requested, treat this as meaning
  8294.          * negative polarity.
  8295.          */
  8296.         if (!(pipe_config->adjusted_mode.flags &
  8297.               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
  8298.                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
  8299.  
  8300.         if (!(pipe_config->adjusted_mode.flags &
  8301.               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
  8302.                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
  8303.  
  8304.         /* Compute a starting value for pipe_config->pipe_bpp taking the source
  8305.          * plane pixel format and any sink constraints into account. Returns the
  8306.          * source plane bpp so that dithering can be selected on mismatches
  8307.          * after encoders and crtc also have had their say. */
  8308.         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
  8309.                                               fb, pipe_config);
  8310.         if (plane_bpp < 0)
  8311.                 goto fail;
  8312.  
  8313. encoder_retry:
  8314.         /* Ensure the port clock defaults are reset when retrying. */
  8315.         pipe_config->port_clock = 0;
  8316.         pipe_config->pixel_multiplier = 1;
  8317.  
  8318.         /* Fill in default crtc timings, allow encoders to overwrite them. */
  8319.         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
  8320.  
  8321.         /* Pass our mode to the connectors and the CRTC to give them a chance to
  8322.          * adjust it according to limitations or connector properties, and also
  8323.          * a chance to reject the mode entirely.
  8324.          */
  8325.         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8326.                             base.head) {
  8327.  
  8328.                 if (&encoder->new_crtc->base != crtc)
  8329.                         continue;
  8330.  
  8331.                         if (!(encoder->compute_config(encoder, pipe_config))) {
  8332.                                 DRM_DEBUG_KMS("Encoder config failure\n");
  8333.                                 goto fail;
  8334.                         }
  8335.                 }
  8336.  
  8337.         /* Set default port clock if not overwritten by the encoder. Needs to be
  8338.          * done afterwards in case the encoder adjusts the mode. */
  8339.         if (!pipe_config->port_clock)
  8340.                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
  8341.  
  8342.         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
  8343.         if (ret < 0) {
  8344.                 DRM_DEBUG_KMS("CRTC fixup failed\n");
  8345.                 goto fail;
  8346.         }
  8347.  
  8348.         if (ret == RETRY) {
  8349.                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
  8350.                         ret = -EINVAL;
  8351.                         goto fail;
  8352.                 }
  8353.  
  8354.                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
  8355.                 retry = false;
  8356.                 goto encoder_retry;
  8357.         }
  8358.  
  8359.         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
  8360.         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
  8361.                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
  8362.  
  8363.         return pipe_config;
  8364. fail:
  8365.         kfree(pipe_config);
  8366.         return ERR_PTR(ret);
  8367. }
  8368.  
  8369. /* Computes which crtcs are affected and sets the relevant bits in the mask. For
  8370.  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
  8371. static void
  8372. intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
  8373.                              unsigned *prepare_pipes, unsigned *disable_pipes)
  8374. {
  8375.         struct intel_crtc *intel_crtc;
  8376.         struct drm_device *dev = crtc->dev;
  8377.         struct intel_encoder *encoder;
  8378.         struct intel_connector *connector;
  8379.         struct drm_crtc *tmp_crtc;
  8380.  
  8381.         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
  8382.  
  8383.         /* Check which crtcs have changed outputs connected to them, these need
  8384.          * to be part of the prepare_pipes mask. We don't (yet) support global
  8385.          * modeset across multiple crtcs, so modeset_pipes will only have one
  8386.          * bit set at most. */
  8387.         list_for_each_entry(connector, &dev->mode_config.connector_list,
  8388.                             base.head) {
  8389.                 if (connector->base.encoder == &connector->new_encoder->base)
  8390.                         continue;
  8391.  
  8392.                 if (connector->base.encoder) {
  8393.                         tmp_crtc = connector->base.encoder->crtc;
  8394.  
  8395.                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  8396.                 }
  8397.  
  8398.                 if (connector->new_encoder)
  8399.                         *prepare_pipes |=
  8400.                                 1 << connector->new_encoder->new_crtc->pipe;
  8401.         }
  8402.  
  8403.         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8404.                             base.head) {
  8405.                 if (encoder->base.crtc == &encoder->new_crtc->base)
  8406.                         continue;
  8407.  
  8408.                 if (encoder->base.crtc) {
  8409.                         tmp_crtc = encoder->base.crtc;
  8410.  
  8411.                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  8412.                 }
  8413.  
  8414.                 if (encoder->new_crtc)
  8415.                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
  8416.         }
  8417.  
  8418.         /* Check for any pipes that will be fully disabled ... */
  8419.         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  8420.                             base.head) {
  8421.                 bool used = false;
  8422.  
  8423.                 /* Don't try to disable disabled crtcs. */
  8424.                 if (!intel_crtc->base.enabled)
  8425.                         continue;
  8426.  
  8427.                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8428.                                     base.head) {
  8429.                         if (encoder->new_crtc == intel_crtc)
  8430.                                 used = true;
  8431.                 }
  8432.  
  8433.                 if (!used)
  8434.                         *disable_pipes |= 1 << intel_crtc->pipe;
  8435.         }
  8436.  
  8437.  
  8438.         /* set_mode is also used to update properties on life display pipes. */
  8439.         intel_crtc = to_intel_crtc(crtc);
  8440.         if (crtc->enabled)
  8441.                 *prepare_pipes |= 1 << intel_crtc->pipe;
  8442.  
  8443.         /*
  8444.          * For simplicity do a full modeset on any pipe where the output routing
  8445.          * changed. We could be more clever, but that would require us to be
  8446.          * more careful with calling the relevant encoder->mode_set functions.
  8447.          */
  8448.         if (*prepare_pipes)
  8449.                 *modeset_pipes = *prepare_pipes;
  8450.  
  8451.         /* ... and mask these out. */
  8452.         *modeset_pipes &= ~(*disable_pipes);
  8453.         *prepare_pipes &= ~(*disable_pipes);
  8454.  
  8455.         /*
  8456.          * HACK: We don't (yet) fully support global modesets. intel_set_config
  8457.          * obies this rule, but the modeset restore mode of
  8458.          * intel_modeset_setup_hw_state does not.
  8459.          */
  8460.         *modeset_pipes &= 1 << intel_crtc->pipe;
  8461.         *prepare_pipes &= 1 << intel_crtc->pipe;
  8462.  
  8463.         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
  8464.                       *modeset_pipes, *prepare_pipes, *disable_pipes);
  8465. }
  8466.  
  8467. static bool intel_crtc_in_use(struct drm_crtc *crtc)
  8468. {
  8469.         struct drm_encoder *encoder;
  8470.         struct drm_device *dev = crtc->dev;
  8471.  
  8472.         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
  8473.                 if (encoder->crtc == crtc)
  8474.                         return true;
  8475.  
  8476.         return false;
  8477. }
  8478.  
  8479. static void
  8480. intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
  8481. {
  8482.         struct intel_encoder *intel_encoder;
  8483.         struct intel_crtc *intel_crtc;
  8484.         struct drm_connector *connector;
  8485.  
  8486.         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
  8487.                             base.head) {
  8488.                 if (!intel_encoder->base.crtc)
  8489.                         continue;
  8490.  
  8491.                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
  8492.  
  8493.                 if (prepare_pipes & (1 << intel_crtc->pipe))
  8494.                         intel_encoder->connectors_active = false;
  8495.         }
  8496.  
  8497.         intel_modeset_commit_output_state(dev);
  8498.  
  8499.         /* Update computed state. */
  8500.         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  8501.                             base.head) {
  8502.                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
  8503.         }
  8504.  
  8505.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  8506.                 if (!connector->encoder || !connector->encoder->crtc)
  8507.                         continue;
  8508.  
  8509.                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
  8510.  
  8511.                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
  8512.                         struct drm_property *dpms_property =
  8513.                                 dev->mode_config.dpms_property;
  8514.  
  8515.                         connector->dpms = DRM_MODE_DPMS_ON;
  8516.                         drm_object_property_set_value(&connector->base,
  8517.                                                          dpms_property,
  8518.                                                          DRM_MODE_DPMS_ON);
  8519.  
  8520.                         intel_encoder = to_intel_encoder(connector->encoder);
  8521.                         intel_encoder->connectors_active = true;
  8522.                 }
  8523.         }
  8524.  
  8525. }
  8526.  
  8527. static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
  8528.                                     struct intel_crtc_config *new)
  8529. {
  8530.         int clock1, clock2, diff;
  8531.  
  8532.         clock1 = cur->adjusted_mode.clock;
  8533.         clock2 = new->adjusted_mode.clock;
  8534.  
  8535.         if (clock1 == clock2)
  8536.                 return true;
  8537.  
  8538.         if (!clock1 || !clock2)
  8539.                 return false;
  8540.  
  8541.         diff = abs(clock1 - clock2);
  8542.  
  8543.         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
  8544.                 return true;
  8545.  
  8546.         return false;
  8547. }
  8548.  
  8549. #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
  8550.         list_for_each_entry((intel_crtc), \
  8551.                             &(dev)->mode_config.crtc_list, \
  8552.                             base.head) \
  8553.                 if (mask & (1 <<(intel_crtc)->pipe))
  8554.  
  8555. static bool
  8556. intel_pipe_config_compare(struct drm_device *dev,
  8557.                           struct intel_crtc_config *current_config,
  8558.                           struct intel_crtc_config *pipe_config)
  8559. {
  8560. #define PIPE_CONF_CHECK_X(name) \
  8561.         if (current_config->name != pipe_config->name) { \
  8562.                 DRM_ERROR("mismatch in " #name " " \
  8563.                           "(expected 0x%08x, found 0x%08x)\n", \
  8564.                           current_config->name, \
  8565.                           pipe_config->name); \
  8566.                 return false; \
  8567.         }
  8568.  
  8569. #define PIPE_CONF_CHECK_I(name) \
  8570.         if (current_config->name != pipe_config->name) { \
  8571.                 DRM_ERROR("mismatch in " #name " " \
  8572.                           "(expected %i, found %i)\n", \
  8573.                           current_config->name, \
  8574.                           pipe_config->name); \
  8575.                 return false; \
  8576.         }
  8577.  
  8578. #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
  8579.         if ((current_config->name ^ pipe_config->name) & (mask)) { \
  8580.                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
  8581.                           "(expected %i, found %i)\n", \
  8582.                           current_config->name & (mask), \
  8583.                           pipe_config->name & (mask)); \
  8584.                 return false; \
  8585.         }
  8586.  
  8587. #define PIPE_CONF_QUIRK(quirk)  \
  8588.         ((current_config->quirks | pipe_config->quirks) & (quirk))
  8589.  
  8590.         PIPE_CONF_CHECK_I(cpu_transcoder);
  8591.  
  8592.         PIPE_CONF_CHECK_I(has_pch_encoder);
  8593.         PIPE_CONF_CHECK_I(fdi_lanes);
  8594.         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
  8595.         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
  8596.         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
  8597.         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
  8598.         PIPE_CONF_CHECK_I(fdi_m_n.tu);
  8599.  
  8600.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
  8601.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
  8602.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
  8603.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
  8604.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
  8605.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
  8606.  
  8607.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
  8608.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
  8609.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
  8610.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
  8611.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
  8612.         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
  8613.  
  8614.                 PIPE_CONF_CHECK_I(pixel_multiplier);
  8615.  
  8616.         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  8617.                               DRM_MODE_FLAG_INTERLACE);
  8618.  
  8619.         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
  8620.                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  8621.                                       DRM_MODE_FLAG_PHSYNC);
  8622.                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  8623.                                       DRM_MODE_FLAG_NHSYNC);
  8624.                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  8625.                                       DRM_MODE_FLAG_PVSYNC);
  8626.                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  8627.                                       DRM_MODE_FLAG_NVSYNC);
  8628.         }
  8629.  
  8630.         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
  8631.         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
  8632.  
  8633.         PIPE_CONF_CHECK_I(gmch_pfit.control);
  8634.         /* pfit ratios are autocomputed by the hw on gen4+ */
  8635.         if (INTEL_INFO(dev)->gen < 4)
  8636.                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
  8637.         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
  8638.         PIPE_CONF_CHECK_I(pch_pfit.enabled);
  8639.         if (current_config->pch_pfit.enabled) {
  8640.         PIPE_CONF_CHECK_I(pch_pfit.pos);
  8641.         PIPE_CONF_CHECK_I(pch_pfit.size);
  8642.         }
  8643.  
  8644.         PIPE_CONF_CHECK_I(ips_enabled);
  8645.  
  8646.         PIPE_CONF_CHECK_I(shared_dpll);
  8647.         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
  8648.         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
  8649.         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
  8650.         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
  8651.  
  8652.         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
  8653.                 PIPE_CONF_CHECK_I(pipe_bpp);
  8654.  
  8655. #undef PIPE_CONF_CHECK_X
  8656. #undef PIPE_CONF_CHECK_I
  8657. #undef PIPE_CONF_CHECK_FLAGS
  8658. #undef PIPE_CONF_QUIRK
  8659.  
  8660.         if (!IS_HASWELL(dev)) {
  8661.                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
  8662.                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
  8663.                                   current_config->adjusted_mode.clock,
  8664.                                   pipe_config->adjusted_mode.clock);
  8665.                         return false;
  8666.                 }
  8667.         }
  8668.  
  8669.         return true;
  8670. }
  8671.  
  8672. static void
  8673. check_connector_state(struct drm_device *dev)
  8674. {
  8675.         struct intel_connector *connector;
  8676.  
  8677.         list_for_each_entry(connector, &dev->mode_config.connector_list,
  8678.                             base.head) {
  8679.                 /* This also checks the encoder/connector hw state with the
  8680.                  * ->get_hw_state callbacks. */
  8681.                 intel_connector_check_state(connector);
  8682.  
  8683.                 WARN(&connector->new_encoder->base != connector->base.encoder,
  8684.                      "connector's staged encoder doesn't match current encoder\n");
  8685.         }
  8686. }
  8687.  
  8688. static void
  8689. check_encoder_state(struct drm_device *dev)
  8690. {
  8691.         struct intel_encoder *encoder;
  8692.         struct intel_connector *connector;
  8693.  
  8694.         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8695.                             base.head) {
  8696.                 bool enabled = false;
  8697.                 bool active = false;
  8698.                 enum pipe pipe, tracked_pipe;
  8699.  
  8700.                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
  8701.                               encoder->base.base.id,
  8702.                               drm_get_encoder_name(&encoder->base));
  8703.  
  8704.                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
  8705.                      "encoder's stage crtc doesn't match current crtc\n");
  8706.                 WARN(encoder->connectors_active && !encoder->base.crtc,
  8707.                      "encoder's active_connectors set, but no crtc\n");
  8708.  
  8709.                 list_for_each_entry(connector, &dev->mode_config.connector_list,
  8710.                                     base.head) {
  8711.                         if (connector->base.encoder != &encoder->base)
  8712.                                 continue;
  8713.                         enabled = true;
  8714.                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
  8715.                                 active = true;
  8716.                 }
  8717.                 WARN(!!encoder->base.crtc != enabled,
  8718.                      "encoder's enabled state mismatch "
  8719.                      "(expected %i, found %i)\n",
  8720.                      !!encoder->base.crtc, enabled);
  8721.                 WARN(active && !encoder->base.crtc,
  8722.                      "active encoder with no crtc\n");
  8723.  
  8724.                 WARN(encoder->connectors_active != active,
  8725.                      "encoder's computed active state doesn't match tracked active state "
  8726.                      "(expected %i, found %i)\n", active, encoder->connectors_active);
  8727.  
  8728.                 active = encoder->get_hw_state(encoder, &pipe);
  8729.                 WARN(active != encoder->connectors_active,
  8730.                      "encoder's hw state doesn't match sw tracking "
  8731.                      "(expected %i, found %i)\n",
  8732.                      encoder->connectors_active, active);
  8733.  
  8734.                 if (!encoder->base.crtc)
  8735.                         continue;
  8736.  
  8737.                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
  8738.                 WARN(active && pipe != tracked_pipe,
  8739.                      "active encoder's pipe doesn't match"
  8740.                      "(expected %i, found %i)\n",
  8741.                      tracked_pipe, pipe);
  8742.  
  8743.         }
  8744. }
  8745.  
  8746. static void
  8747. check_crtc_state(struct drm_device *dev)
  8748. {
  8749.         drm_i915_private_t *dev_priv = dev->dev_private;
  8750.         struct intel_crtc *crtc;
  8751.         struct intel_encoder *encoder;
  8752.         struct intel_crtc_config pipe_config;
  8753.  
  8754.         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8755.                             base.head) {
  8756.                 bool enabled = false;
  8757.                 bool active = false;
  8758.  
  8759.                 memset(&pipe_config, 0, sizeof(pipe_config));
  8760.  
  8761.                 DRM_DEBUG_KMS("[CRTC:%d]\n",
  8762.                               crtc->base.base.id);
  8763.  
  8764.                 WARN(crtc->active && !crtc->base.enabled,
  8765.                      "active crtc, but not enabled in sw tracking\n");
  8766.  
  8767.                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8768.                                     base.head) {
  8769.                         if (encoder->base.crtc != &crtc->base)
  8770.                                 continue;
  8771.                         enabled = true;
  8772.                         if (encoder->connectors_active)
  8773.                                 active = true;
  8774.                 }
  8775.  
  8776.                 WARN(active != crtc->active,
  8777.                      "crtc's computed active state doesn't match tracked active state "
  8778.                      "(expected %i, found %i)\n", active, crtc->active);
  8779.                 WARN(enabled != crtc->base.enabled,
  8780.                      "crtc's computed enabled state doesn't match tracked enabled state "
  8781.                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
  8782.  
  8783.                 active = dev_priv->display.get_pipe_config(crtc,
  8784.                                                            &pipe_config);
  8785.  
  8786.                 /* hw state is inconsistent with the pipe A quirk */
  8787.                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  8788.                         active = crtc->active;
  8789.  
  8790.                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8791.                                     base.head) {
  8792.                         enum pipe pipe;
  8793.                         if (encoder->base.crtc != &crtc->base)
  8794.                                 continue;
  8795.                         if (encoder->get_config &&
  8796.                             encoder->get_hw_state(encoder, &pipe))
  8797.                                 encoder->get_config(encoder, &pipe_config);
  8798.                 }
  8799.  
  8800.                 if (dev_priv->display.get_clock)
  8801.                         dev_priv->display.get_clock(crtc, &pipe_config);
  8802.  
  8803.                 WARN(crtc->active != active,
  8804.                      "crtc active state doesn't match with hw state "
  8805.                      "(expected %i, found %i)\n", crtc->active, active);
  8806.  
  8807.                 if (active &&
  8808.                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
  8809.                         WARN(1, "pipe state doesn't match!\n");
  8810.                         intel_dump_pipe_config(crtc, &pipe_config,
  8811.                                                "[hw state]");
  8812.                         intel_dump_pipe_config(crtc, &crtc->config,
  8813.                                                "[sw state]");
  8814.                 }
  8815.         }
  8816. }
  8817.  
  8818. static void
  8819. check_shared_dpll_state(struct drm_device *dev)
  8820. {
  8821.         drm_i915_private_t *dev_priv = dev->dev_private;
  8822.         struct intel_crtc *crtc;
  8823.         struct intel_dpll_hw_state dpll_hw_state;
  8824.         int i;
  8825.  
  8826.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  8827.                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  8828.                 int enabled_crtcs = 0, active_crtcs = 0;
  8829.                 bool active;
  8830.  
  8831.                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
  8832.  
  8833.                 DRM_DEBUG_KMS("%s\n", pll->name);
  8834.  
  8835.                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
  8836.  
  8837.                 WARN(pll->active > pll->refcount,
  8838.                      "more active pll users than references: %i vs %i\n",
  8839.                      pll->active, pll->refcount);
  8840.                 WARN(pll->active && !pll->on,
  8841.                      "pll in active use but not on in sw tracking\n");
  8842.                 WARN(pll->on && !pll->active,
  8843.                      "pll in on but not on in use in sw tracking\n");
  8844.                 WARN(pll->on != active,
  8845.                      "pll on state mismatch (expected %i, found %i)\n",
  8846.                      pll->on, active);
  8847.  
  8848.                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8849.                                     base.head) {
  8850.                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
  8851.                                 enabled_crtcs++;
  8852.                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
  8853.                                 active_crtcs++;
  8854.                 }
  8855.                 WARN(pll->active != active_crtcs,
  8856.                      "pll active crtcs mismatch (expected %i, found %i)\n",
  8857.                      pll->active, active_crtcs);
  8858.                 WARN(pll->refcount != enabled_crtcs,
  8859.                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
  8860.                      pll->refcount, enabled_crtcs);
  8861.  
  8862.                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
  8863.                                        sizeof(dpll_hw_state)),
  8864.                      "pll hw state mismatch\n");
  8865.         }
  8866. }
  8867.  
  8868. void
  8869. intel_modeset_check_state(struct drm_device *dev)
  8870. {
  8871.         check_connector_state(dev);
  8872.         check_encoder_state(dev);
  8873.         check_crtc_state(dev);
  8874.         check_shared_dpll_state(dev);
  8875. }
  8876.  
  8877. static int __intel_set_mode(struct drm_crtc *crtc,
  8878.                     struct drm_display_mode *mode,
  8879.                     int x, int y, struct drm_framebuffer *fb)
  8880. {
  8881.         struct drm_device *dev = crtc->dev;
  8882.         drm_i915_private_t *dev_priv = dev->dev_private;
  8883.         struct drm_display_mode *saved_mode, *saved_hwmode;
  8884.         struct intel_crtc_config *pipe_config = NULL;
  8885.         struct intel_crtc *intel_crtc;
  8886.         unsigned disable_pipes, prepare_pipes, modeset_pipes;
  8887.         int ret = 0;
  8888.  
  8889.         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
  8890.         if (!saved_mode)
  8891.                 return -ENOMEM;
  8892.         saved_hwmode = saved_mode + 1;
  8893.  
  8894.         intel_modeset_affected_pipes(crtc, &modeset_pipes,
  8895.                                      &prepare_pipes, &disable_pipes);
  8896.  
  8897.         *saved_hwmode = crtc->hwmode;
  8898.         *saved_mode = crtc->mode;
  8899.  
  8900.         /* Hack: Because we don't (yet) support global modeset on multiple
  8901.          * crtcs, we don't keep track of the new mode for more than one crtc.
  8902.          * Hence simply check whether any bit is set in modeset_pipes in all the
  8903.          * pieces of code that are not yet converted to deal with mutliple crtcs
  8904.          * changing their mode at the same time. */
  8905.         if (modeset_pipes) {
  8906.                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
  8907.                 if (IS_ERR(pipe_config)) {
  8908.                         ret = PTR_ERR(pipe_config);
  8909.                         pipe_config = NULL;
  8910.  
  8911.                         goto out;
  8912.                 }
  8913.                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
  8914.                                        "[modeset]");
  8915.         }
  8916.  
  8917.         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
  8918.                 intel_crtc_disable(&intel_crtc->base);
  8919.  
  8920.         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
  8921.                 if (intel_crtc->base.enabled)
  8922.                         dev_priv->display.crtc_disable(&intel_crtc->base);
  8923.         }
  8924.  
  8925.         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
  8926.          * to set it here already despite that we pass it down the callchain.
  8927.          */
  8928.         if (modeset_pipes) {
  8929.                 crtc->mode = *mode;
  8930.                 /* mode_set/enable/disable functions rely on a correct pipe
  8931.                  * config. */
  8932.                 to_intel_crtc(crtc)->config = *pipe_config;
  8933.         }
  8934.  
  8935.         /* Only after disabling all output pipelines that will be changed can we
  8936.          * update the the output configuration. */
  8937.         intel_modeset_update_state(dev, prepare_pipes);
  8938.  
  8939.         if (dev_priv->display.modeset_global_resources)
  8940.                 dev_priv->display.modeset_global_resources(dev);
  8941.  
  8942.         /* Set up the DPLL and any encoders state that needs to adjust or depend
  8943.          * on the DPLL.
  8944.          */
  8945.         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
  8946.                 ret = intel_crtc_mode_set(&intel_crtc->base,
  8947.                                            x, y, fb);
  8948.                 if (ret)
  8949.                     goto done;
  8950.         }
  8951.  
  8952.         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
  8953.         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
  8954.                 dev_priv->display.crtc_enable(&intel_crtc->base);
  8955.  
  8956.         if (modeset_pipes) {
  8957.                 /* Store real post-adjustment hardware mode. */
  8958.                 crtc->hwmode = pipe_config->adjusted_mode;
  8959.  
  8960.                 /* Calculate and store various constants which
  8961.                  * are later needed by vblank and swap-completion
  8962.                  * timestamping. They are derived from true hwmode.
  8963.                  */
  8964.                 drm_calc_timestamping_constants(crtc);
  8965.         }
  8966.  
  8967.         /* FIXME: add subpixel order */
  8968. done:
  8969.         if (ret && crtc->enabled) {
  8970.                 crtc->hwmode = *saved_hwmode;
  8971.                 crtc->mode = *saved_mode;
  8972.         }
  8973.  
  8974. out:
  8975.         kfree(pipe_config);
  8976.         kfree(saved_mode);
  8977.         return ret;
  8978. }
  8979.  
  8980. static int intel_set_mode(struct drm_crtc *crtc,
  8981.                      struct drm_display_mode *mode,
  8982.                      int x, int y, struct drm_framebuffer *fb)
  8983. {
  8984.         int ret;
  8985.  
  8986.         ret = __intel_set_mode(crtc, mode, x, y, fb);
  8987.  
  8988.         if (ret == 0)
  8989.                 intel_modeset_check_state(crtc->dev);
  8990.  
  8991.         return ret;
  8992. }
  8993.  
  8994. void intel_crtc_restore_mode(struct drm_crtc *crtc)
  8995. {
  8996.         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
  8997. }
  8998.  
  8999. #undef for_each_intel_crtc_masked
  9000.  
  9001. static void intel_set_config_free(struct intel_set_config *config)
  9002. {
  9003.         if (!config)
  9004.                 return;
  9005.  
  9006.         kfree(config->save_connector_encoders);
  9007.         kfree(config->save_encoder_crtcs);
  9008.         kfree(config);
  9009. }
  9010.  
  9011. static int intel_set_config_save_state(struct drm_device *dev,
  9012.                                        struct intel_set_config *config)
  9013. {
  9014.         struct drm_encoder *encoder;
  9015.         struct drm_connector *connector;
  9016.         int count;
  9017.  
  9018.         config->save_encoder_crtcs =
  9019.                 kcalloc(dev->mode_config.num_encoder,
  9020.                         sizeof(struct drm_crtc *), GFP_KERNEL);
  9021.         if (!config->save_encoder_crtcs)
  9022.                 return -ENOMEM;
  9023.  
  9024.         config->save_connector_encoders =
  9025.                 kcalloc(dev->mode_config.num_connector,
  9026.                         sizeof(struct drm_encoder *), GFP_KERNEL);
  9027.         if (!config->save_connector_encoders)
  9028.                 return -ENOMEM;
  9029.  
  9030.         /* Copy data. Note that driver private data is not affected.
  9031.          * Should anything bad happen only the expected state is
  9032.          * restored, not the drivers personal bookkeeping.
  9033.          */
  9034.         count = 0;
  9035.         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  9036.                 config->save_encoder_crtcs[count++] = encoder->crtc;
  9037.         }
  9038.  
  9039.         count = 0;
  9040.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  9041.                 config->save_connector_encoders[count++] = connector->encoder;
  9042.         }
  9043.  
  9044.         return 0;
  9045. }
  9046.  
  9047. static void intel_set_config_restore_state(struct drm_device *dev,
  9048.                                            struct intel_set_config *config)
  9049. {
  9050.         struct intel_encoder *encoder;
  9051.         struct intel_connector *connector;
  9052.         int count;
  9053.  
  9054.         count = 0;
  9055.         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  9056.                 encoder->new_crtc =
  9057.                         to_intel_crtc(config->save_encoder_crtcs[count++]);
  9058.         }
  9059.  
  9060.         count = 0;
  9061.         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
  9062.                 connector->new_encoder =
  9063.                         to_intel_encoder(config->save_connector_encoders[count++]);
  9064.         }
  9065. }
  9066.  
  9067. static bool
  9068. is_crtc_connector_off(struct drm_mode_set *set)
  9069. {
  9070.         int i;
  9071.  
  9072.         if (set->num_connectors == 0)
  9073.                 return false;
  9074.  
  9075.         if (WARN_ON(set->connectors == NULL))
  9076.                 return false;
  9077.  
  9078.         for (i = 0; i < set->num_connectors; i++)
  9079.                 if (set->connectors[i]->encoder &&
  9080.                     set->connectors[i]->encoder->crtc == set->crtc &&
  9081.                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
  9082.                         return true;
  9083.  
  9084.         return false;
  9085. }
  9086.  
  9087. static void
  9088. intel_set_config_compute_mode_changes(struct drm_mode_set *set,
  9089.                                       struct intel_set_config *config)
  9090. {
  9091.  
  9092.         /* We should be able to check here if the fb has the same properties
  9093.          * and then just flip_or_move it */
  9094.         if (is_crtc_connector_off(set)) {
  9095.                         config->mode_changed = true;
  9096.         } else if (set->crtc->fb != set->fb) {
  9097.                 /* If we have no fb then treat it as a full mode set */
  9098.                 if (set->crtc->fb == NULL) {
  9099.                         struct intel_crtc *intel_crtc =
  9100.                                 to_intel_crtc(set->crtc);
  9101.  
  9102.                         if (intel_crtc->active && i915_fastboot) {
  9103.                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
  9104.                                 config->fb_changed = true;
  9105.                         } else {
  9106.                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
  9107.                         config->mode_changed = true;
  9108.                         }
  9109.                 } else if (set->fb == NULL) {
  9110.                         config->mode_changed = true;
  9111.                 } else if (set->fb->pixel_format !=
  9112.                            set->crtc->fb->pixel_format) {
  9113.                         config->mode_changed = true;
  9114.                 } else {
  9115.                         config->fb_changed = true;
  9116.         }
  9117.         }
  9118.  
  9119.         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
  9120.                 config->fb_changed = true;
  9121.  
  9122.         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
  9123.                 DRM_DEBUG_KMS("modes are different, full mode set\n");
  9124.                 drm_mode_debug_printmodeline(&set->crtc->mode);
  9125.                 drm_mode_debug_printmodeline(set->mode);
  9126.                 config->mode_changed = true;
  9127.         }
  9128.  
  9129.         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
  9130.                         set->crtc->base.id, config->mode_changed, config->fb_changed);
  9131. }
  9132.  
  9133. static int
  9134. intel_modeset_stage_output_state(struct drm_device *dev,
  9135.                                  struct drm_mode_set *set,
  9136.                                  struct intel_set_config *config)
  9137. {
  9138.         struct drm_crtc *new_crtc;
  9139.         struct intel_connector *connector;
  9140.         struct intel_encoder *encoder;
  9141.         int ro;
  9142.  
  9143.         /* The upper layers ensure that we either disable a crtc or have a list
  9144.          * of connectors. For paranoia, double-check this. */
  9145.         WARN_ON(!set->fb && (set->num_connectors != 0));
  9146.         WARN_ON(set->fb && (set->num_connectors == 0));
  9147.  
  9148.         list_for_each_entry(connector, &dev->mode_config.connector_list,
  9149.                             base.head) {
  9150.                 /* Otherwise traverse passed in connector list and get encoders
  9151.                  * for them. */
  9152.                 for (ro = 0; ro < set->num_connectors; ro++) {
  9153.                         if (set->connectors[ro] == &connector->base) {
  9154.                                 connector->new_encoder = connector->encoder;
  9155.                                 break;
  9156.                         }
  9157.                 }
  9158.  
  9159.                 /* If we disable the crtc, disable all its connectors. Also, if
  9160.                  * the connector is on the changing crtc but not on the new
  9161.                  * connector list, disable it. */
  9162.                 if ((!set->fb || ro == set->num_connectors) &&
  9163.                     connector->base.encoder &&
  9164.                     connector->base.encoder->crtc == set->crtc) {
  9165.                         connector->new_encoder = NULL;
  9166.  
  9167.                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
  9168.                                 connector->base.base.id,
  9169.                                 drm_get_connector_name(&connector->base));
  9170.                 }
  9171.  
  9172.  
  9173.                 if (&connector->new_encoder->base != connector->base.encoder) {
  9174.                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
  9175.                         config->mode_changed = true;
  9176.                 }
  9177.         }
  9178.         /* connector->new_encoder is now updated for all connectors. */
  9179.  
  9180.         /* Update crtc of enabled connectors. */
  9181.         list_for_each_entry(connector, &dev->mode_config.connector_list,
  9182.                             base.head) {
  9183.                 if (!connector->new_encoder)
  9184.                         continue;
  9185.  
  9186.                 new_crtc = connector->new_encoder->base.crtc;
  9187.  
  9188.                 for (ro = 0; ro < set->num_connectors; ro++) {
  9189.                         if (set->connectors[ro] == &connector->base)
  9190.                                 new_crtc = set->crtc;
  9191.                 }
  9192.  
  9193.                 /* Make sure the new CRTC will work with the encoder */
  9194.                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
  9195.                                            new_crtc)) {
  9196.                         return -EINVAL;
  9197.                 }
  9198.                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
  9199.  
  9200.                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
  9201.                         connector->base.base.id,
  9202.                         drm_get_connector_name(&connector->base),
  9203.                         new_crtc->base.id);
  9204.         }
  9205.  
  9206.         /* Check for any encoders that needs to be disabled. */
  9207.         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  9208.                             base.head) {
  9209.                 list_for_each_entry(connector,
  9210.                                     &dev->mode_config.connector_list,
  9211.                                     base.head) {
  9212.                         if (connector->new_encoder == encoder) {
  9213.                                 WARN_ON(!connector->new_encoder->new_crtc);
  9214.  
  9215.                                 goto next_encoder;
  9216.                         }
  9217.                 }
  9218.                 encoder->new_crtc = NULL;
  9219. next_encoder:
  9220.                 /* Only now check for crtc changes so we don't miss encoders
  9221.                  * that will be disabled. */
  9222.                 if (&encoder->new_crtc->base != encoder->base.crtc) {
  9223.                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
  9224.                         config->mode_changed = true;
  9225.                 }
  9226.         }
  9227.         /* Now we've also updated encoder->new_crtc for all encoders. */
  9228.  
  9229.         return 0;
  9230. }
  9231.  
  9232. static int intel_crtc_set_config(struct drm_mode_set *set)
  9233. {
  9234.         struct drm_device *dev;
  9235.         struct drm_mode_set save_set;
  9236.         struct intel_set_config *config;
  9237.         int ret;
  9238.  
  9239.         BUG_ON(!set);
  9240.         BUG_ON(!set->crtc);
  9241.         BUG_ON(!set->crtc->helper_private);
  9242.  
  9243.         /* Enforce sane interface api - has been abused by the fb helper. */
  9244.         BUG_ON(!set->mode && set->fb);
  9245.         BUG_ON(set->fb && set->num_connectors == 0);
  9246.  
  9247.         if (set->fb) {
  9248.                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
  9249.                                 set->crtc->base.id, set->fb->base.id,
  9250.                                 (int)set->num_connectors, set->x, set->y);
  9251.         } else {
  9252.                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
  9253.         }
  9254.  
  9255.         dev = set->crtc->dev;
  9256.  
  9257.         ret = -ENOMEM;
  9258.         config = kzalloc(sizeof(*config), GFP_KERNEL);
  9259.         if (!config)
  9260.                 goto out_config;
  9261.  
  9262.         ret = intel_set_config_save_state(dev, config);
  9263.         if (ret)
  9264.                 goto out_config;
  9265.  
  9266.         save_set.crtc = set->crtc;
  9267.         save_set.mode = &set->crtc->mode;
  9268.         save_set.x = set->crtc->x;
  9269.         save_set.y = set->crtc->y;
  9270.         save_set.fb = set->crtc->fb;
  9271.  
  9272.         /* Compute whether we need a full modeset, only an fb base update or no
  9273.          * change at all. In the future we might also check whether only the
  9274.          * mode changed, e.g. for LVDS where we only change the panel fitter in
  9275.          * such cases. */
  9276.         intel_set_config_compute_mode_changes(set, config);
  9277.  
  9278.         ret = intel_modeset_stage_output_state(dev, set, config);
  9279.         if (ret)
  9280.                 goto fail;
  9281.  
  9282.         if (config->mode_changed) {
  9283.                 ret = intel_set_mode(set->crtc, set->mode,
  9284.                                      set->x, set->y, set->fb);
  9285.         } else if (config->fb_changed) {
  9286. //       intel_crtc_wait_for_pending_flips(set->crtc);
  9287.  
  9288.                 ret = intel_pipe_set_base(set->crtc,
  9289.                                           set->x, set->y, set->fb);
  9290.         }
  9291.  
  9292.         if (ret) {
  9293.                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
  9294.                           set->crtc->base.id, ret);
  9295. fail:
  9296.         intel_set_config_restore_state(dev, config);
  9297.  
  9298.         /* Try to restore the config */
  9299.         if (config->mode_changed &&
  9300.             intel_set_mode(save_set.crtc, save_set.mode,
  9301.                             save_set.x, save_set.y, save_set.fb))
  9302.                 DRM_ERROR("failed to restore config after modeset failure\n");
  9303.         }
  9304.  
  9305. out_config:
  9306.         intel_set_config_free(config);
  9307.         return ret;
  9308. }
  9309.  
  9310. static const struct drm_crtc_funcs intel_crtc_funcs = {
  9311. //      .cursor_set = intel_crtc_cursor_set,
  9312. //      .cursor_move = intel_crtc_cursor_move,
  9313.         .gamma_set = intel_crtc_gamma_set,
  9314.         .set_config = intel_crtc_set_config,
  9315.         .destroy = intel_crtc_destroy,
  9316. //      .page_flip = intel_crtc_page_flip,
  9317. };
  9318.  
  9319. static void intel_cpu_pll_init(struct drm_device *dev)
  9320. {
  9321.         if (HAS_DDI(dev))
  9322.                 intel_ddi_pll_init(dev);
  9323. }
  9324.  
  9325. static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
  9326.                                       struct intel_shared_dpll *pll,
  9327.                                       struct intel_dpll_hw_state *hw_state)
  9328. {
  9329.         uint32_t val;
  9330.  
  9331.         val = I915_READ(PCH_DPLL(pll->id));
  9332.         hw_state->dpll = val;
  9333.         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
  9334.         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
  9335.  
  9336.         return val & DPLL_VCO_ENABLE;
  9337. }
  9338.  
  9339. static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
  9340.                                   struct intel_shared_dpll *pll)
  9341. {
  9342.         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
  9343.         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
  9344. }
  9345.  
  9346. static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
  9347.                                 struct intel_shared_dpll *pll)
  9348. {
  9349.         /* PCH refclock must be enabled first */
  9350.         assert_pch_refclk_enabled(dev_priv);
  9351.  
  9352.         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
  9353.  
  9354.         /* Wait for the clocks to stabilize. */
  9355.         POSTING_READ(PCH_DPLL(pll->id));
  9356.         udelay(150);
  9357.  
  9358.         /* The pixel multiplier can only be updated once the
  9359.          * DPLL is enabled and the clocks are stable.
  9360.          *
  9361.          * So write it again.
  9362.          */
  9363.         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
  9364.         POSTING_READ(PCH_DPLL(pll->id));
  9365.         udelay(200);
  9366. }
  9367.  
  9368. static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
  9369.                                  struct intel_shared_dpll *pll)
  9370. {
  9371.         struct drm_device *dev = dev_priv->dev;
  9372.         struct intel_crtc *crtc;
  9373.  
  9374.         /* Make sure no transcoder isn't still depending on us. */
  9375.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  9376.                 if (intel_crtc_to_shared_dpll(crtc) == pll)
  9377.                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
  9378.         }
  9379.  
  9380.         I915_WRITE(PCH_DPLL(pll->id), 0);
  9381.         POSTING_READ(PCH_DPLL(pll->id));
  9382.         udelay(200);
  9383. }
  9384.  
  9385. static char *ibx_pch_dpll_names[] = {
  9386.         "PCH DPLL A",
  9387.         "PCH DPLL B",
  9388. };
  9389.  
  9390. static void ibx_pch_dpll_init(struct drm_device *dev)
  9391. {
  9392.         struct drm_i915_private *dev_priv = dev->dev_private;
  9393.         int i;
  9394.  
  9395.         dev_priv->num_shared_dpll = 2;
  9396.  
  9397.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  9398.                 dev_priv->shared_dplls[i].id = i;
  9399.                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
  9400.                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
  9401.                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
  9402.                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
  9403.                 dev_priv->shared_dplls[i].get_hw_state =
  9404.                         ibx_pch_dpll_get_hw_state;
  9405.         }
  9406. }
  9407.  
  9408. static void intel_shared_dpll_init(struct drm_device *dev)
  9409. {
  9410.         struct drm_i915_private *dev_priv = dev->dev_private;
  9411.  
  9412.         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  9413.                 ibx_pch_dpll_init(dev);
  9414.         else
  9415.                 dev_priv->num_shared_dpll = 0;
  9416.  
  9417.         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
  9418.         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
  9419.                       dev_priv->num_shared_dpll);
  9420. }
  9421.  
  9422. static void intel_crtc_init(struct drm_device *dev, int pipe)
  9423. {
  9424.         drm_i915_private_t *dev_priv = dev->dev_private;
  9425.         struct intel_crtc *intel_crtc;
  9426.         int i;
  9427.  
  9428.         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  9429.         if (intel_crtc == NULL)
  9430.                 return;
  9431.  
  9432.         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  9433.  
  9434.         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  9435.         for (i = 0; i < 256; i++) {
  9436.                 intel_crtc->lut_r[i] = i;
  9437.                 intel_crtc->lut_g[i] = i;
  9438.                 intel_crtc->lut_b[i] = i;
  9439.         }
  9440.  
  9441.         /* Swap pipes & planes for FBC on pre-965 */
  9442.         intel_crtc->pipe = pipe;
  9443.         intel_crtc->plane = pipe;
  9444.         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  9445.                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  9446.                 intel_crtc->plane = !pipe;
  9447.         }
  9448.  
  9449.         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  9450.                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  9451.         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  9452.         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  9453.  
  9454.         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  9455. }
  9456.  
  9457. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  9458.                                 struct drm_file *file)
  9459. {
  9460.         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  9461.         struct drm_mode_object *drmmode_obj;
  9462.         struct intel_crtc *crtc;
  9463.  
  9464.         if (!drm_core_check_feature(dev, DRIVER_MODESET))
  9465.                 return -ENODEV;
  9466.  
  9467.         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  9468.                         DRM_MODE_OBJECT_CRTC);
  9469.  
  9470.         if (!drmmode_obj) {
  9471.                 DRM_ERROR("no such CRTC id\n");
  9472.                 return -EINVAL;
  9473.         }
  9474.  
  9475.         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  9476.         pipe_from_crtc_id->pipe = crtc->pipe;
  9477.  
  9478.         return 0;
  9479. }
  9480.  
  9481. static int intel_encoder_clones(struct intel_encoder *encoder)
  9482. {
  9483.         struct drm_device *dev = encoder->base.dev;
  9484.         struct intel_encoder *source_encoder;
  9485.         int index_mask = 0;
  9486.         int entry = 0;
  9487.  
  9488.         list_for_each_entry(source_encoder,
  9489.                             &dev->mode_config.encoder_list, base.head) {
  9490.  
  9491.                 if (encoder == source_encoder)
  9492.                         index_mask |= (1 << entry);
  9493.  
  9494.                 /* Intel hw has only one MUX where enocoders could be cloned. */
  9495.                 if (encoder->cloneable && source_encoder->cloneable)
  9496.                         index_mask |= (1 << entry);
  9497.  
  9498.                 entry++;
  9499.         }
  9500.  
  9501.         return index_mask;
  9502. }
  9503.  
  9504. static bool has_edp_a(struct drm_device *dev)
  9505. {
  9506.         struct drm_i915_private *dev_priv = dev->dev_private;
  9507.  
  9508.         if (!IS_MOBILE(dev))
  9509.                 return false;
  9510.  
  9511.         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  9512.                 return false;
  9513.  
  9514.         if (IS_GEN5(dev) &&
  9515.             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  9516.                 return false;
  9517.  
  9518.         return true;
  9519. }
  9520.  
  9521. static void intel_setup_outputs(struct drm_device *dev)
  9522. {
  9523.         struct drm_i915_private *dev_priv = dev->dev_private;
  9524.         struct intel_encoder *encoder;
  9525.         bool dpd_is_edp = false;
  9526.  
  9527.         intel_lvds_init(dev);
  9528.  
  9529.         if (!IS_ULT(dev))
  9530.         intel_crt_init(dev);
  9531.  
  9532.         if (HAS_DDI(dev)) {
  9533.                 int found;
  9534.  
  9535.                 /* Haswell uses DDI functions to detect digital outputs */
  9536.                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
  9537.                 /* DDI A only supports eDP */
  9538.                 if (found)
  9539.                         intel_ddi_init(dev, PORT_A);
  9540.  
  9541.                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
  9542.                  * register */
  9543.                 found = I915_READ(SFUSE_STRAP);
  9544.  
  9545.                 if (found & SFUSE_STRAP_DDIB_DETECTED)
  9546.                         intel_ddi_init(dev, PORT_B);
  9547.                 if (found & SFUSE_STRAP_DDIC_DETECTED)
  9548.                         intel_ddi_init(dev, PORT_C);
  9549.                 if (found & SFUSE_STRAP_DDID_DETECTED)
  9550.                         intel_ddi_init(dev, PORT_D);
  9551.         } else if (HAS_PCH_SPLIT(dev)) {
  9552.                 int found;
  9553.                 dpd_is_edp = intel_dpd_is_edp(dev);
  9554.  
  9555.                 if (has_edp_a(dev))
  9556.                         intel_dp_init(dev, DP_A, PORT_A);
  9557.  
  9558.                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
  9559.                         /* PCH SDVOB multiplex with HDMIB */
  9560.                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
  9561.                         if (!found)
  9562.                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
  9563.                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  9564.                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
  9565.                 }
  9566.  
  9567.                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
  9568.                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
  9569.  
  9570.                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
  9571.                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
  9572.  
  9573.                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
  9574.                         intel_dp_init(dev, PCH_DP_C, PORT_C);
  9575.  
  9576.                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
  9577.                         intel_dp_init(dev, PCH_DP_D, PORT_D);
  9578.         } else if (IS_VALLEYVIEW(dev)) {
  9579.                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
  9580.                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
  9581.                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
  9582.                                         PORT_C);
  9583.                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
  9584.                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
  9585.                                               PORT_C);
  9586.                 }
  9587.  
  9588.                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
  9589.                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
  9590.                                         PORT_B);
  9591.                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
  9592.                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
  9593.                 }
  9594.         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  9595.                 bool found = false;
  9596.  
  9597.                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  9598.                         DRM_DEBUG_KMS("probing SDVOB\n");
  9599.                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
  9600.                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  9601.                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  9602.                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
  9603.                         }
  9604.  
  9605.                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
  9606.                                 intel_dp_init(dev, DP_B, PORT_B);
  9607.                         }
  9608.  
  9609.                 /* Before G4X SDVOC doesn't have its own detect register */
  9610.  
  9611.                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  9612.                         DRM_DEBUG_KMS("probing SDVOC\n");
  9613.                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
  9614.                 }
  9615.  
  9616.                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
  9617.  
  9618.                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  9619.                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  9620.                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
  9621.                         }
  9622.                         if (SUPPORTS_INTEGRATED_DP(dev))
  9623.                                 intel_dp_init(dev, DP_C, PORT_C);
  9624.                         }
  9625.  
  9626.                 if (SUPPORTS_INTEGRATED_DP(dev) &&
  9627.                     (I915_READ(DP_D) & DP_DETECTED))
  9628.                         intel_dp_init(dev, DP_D, PORT_D);
  9629.         } else if (IS_GEN2(dev))
  9630.                 intel_dvo_init(dev);
  9631.  
  9632. //   if (SUPPORTS_TV(dev))
  9633. //       intel_tv_init(dev);
  9634.  
  9635.         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  9636.                 encoder->base.possible_crtcs = encoder->crtc_mask;
  9637.                 encoder->base.possible_clones =
  9638.                         intel_encoder_clones(encoder);
  9639.         }
  9640.  
  9641.         intel_init_pch_refclk(dev);
  9642.  
  9643.         drm_helper_move_panel_connectors_to_head(dev);
  9644. }
  9645.  
  9646.  
  9647.  
  9648. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  9649. //      .destroy = intel_user_framebuffer_destroy,
  9650. //      .create_handle = intel_user_framebuffer_create_handle,
  9651. };
  9652.  
  9653. int intel_framebuffer_init(struct drm_device *dev,
  9654.                            struct intel_framebuffer *intel_fb,
  9655.                            struct drm_mode_fb_cmd2 *mode_cmd,
  9656.                            struct drm_i915_gem_object *obj)
  9657. {
  9658.         int pitch_limit;
  9659.         int ret;
  9660.  
  9661.         if (obj->tiling_mode == I915_TILING_Y) {
  9662.                 DRM_DEBUG("hardware does not support tiling Y\n");
  9663.                 return -EINVAL;
  9664.         }
  9665.  
  9666.         if (mode_cmd->pitches[0] & 63) {
  9667.                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
  9668.                           mode_cmd->pitches[0]);
  9669.                 return -EINVAL;
  9670.         }
  9671.  
  9672.         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
  9673.                 pitch_limit = 32*1024;
  9674.         } else if (INTEL_INFO(dev)->gen >= 4) {
  9675.                 if (obj->tiling_mode)
  9676.                         pitch_limit = 16*1024;
  9677.                 else
  9678.                         pitch_limit = 32*1024;
  9679.         } else if (INTEL_INFO(dev)->gen >= 3) {
  9680.                 if (obj->tiling_mode)
  9681.                         pitch_limit = 8*1024;
  9682.                 else
  9683.                         pitch_limit = 16*1024;
  9684.         } else
  9685.                 /* XXX DSPC is limited to 4k tiled */
  9686.                 pitch_limit = 8*1024;
  9687.  
  9688.         if (mode_cmd->pitches[0] > pitch_limit) {
  9689.                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
  9690.                           obj->tiling_mode ? "tiled" : "linear",
  9691.                           mode_cmd->pitches[0], pitch_limit);
  9692.                 return -EINVAL;
  9693.         }
  9694.  
  9695.         if (obj->tiling_mode != I915_TILING_NONE &&
  9696.             mode_cmd->pitches[0] != obj->stride) {
  9697.                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
  9698.                           mode_cmd->pitches[0], obj->stride);
  9699.                         return -EINVAL;
  9700.         }
  9701.  
  9702.         /* Reject formats not supported by any plane early. */
  9703.         switch (mode_cmd->pixel_format) {
  9704.         case DRM_FORMAT_C8:
  9705.         case DRM_FORMAT_RGB565:
  9706.         case DRM_FORMAT_XRGB8888:
  9707.         case DRM_FORMAT_ARGB8888:
  9708.                 break;
  9709.         case DRM_FORMAT_XRGB1555:
  9710.         case DRM_FORMAT_ARGB1555:
  9711.                 if (INTEL_INFO(dev)->gen > 3) {
  9712.                         DRM_DEBUG("unsupported pixel format: %s\n",
  9713.                                   drm_get_format_name(mode_cmd->pixel_format));
  9714.                         return -EINVAL;
  9715.                 }
  9716.                 break;
  9717.         case DRM_FORMAT_XBGR8888:
  9718.         case DRM_FORMAT_ABGR8888:
  9719.         case DRM_FORMAT_XRGB2101010:
  9720.         case DRM_FORMAT_ARGB2101010:
  9721.         case DRM_FORMAT_XBGR2101010:
  9722.         case DRM_FORMAT_ABGR2101010:
  9723.                 if (INTEL_INFO(dev)->gen < 4) {
  9724.                         DRM_DEBUG("unsupported pixel format: %s\n",
  9725.                                   drm_get_format_name(mode_cmd->pixel_format));
  9726.                         return -EINVAL;
  9727.                 }
  9728.                 break;
  9729.         case DRM_FORMAT_YUYV:
  9730.         case DRM_FORMAT_UYVY:
  9731.         case DRM_FORMAT_YVYU:
  9732.         case DRM_FORMAT_VYUY:
  9733.                 if (INTEL_INFO(dev)->gen < 5) {
  9734.                         DRM_DEBUG("unsupported pixel format: %s\n",
  9735.                                   drm_get_format_name(mode_cmd->pixel_format));
  9736.                         return -EINVAL;
  9737.                 }
  9738.                 break;
  9739.         default:
  9740.                 DRM_DEBUG("unsupported pixel format: %s\n",
  9741.                           drm_get_format_name(mode_cmd->pixel_format));
  9742.                 return -EINVAL;
  9743.         }
  9744.  
  9745.         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
  9746.         if (mode_cmd->offsets[0] != 0)
  9747.                 return -EINVAL;
  9748.  
  9749.         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  9750.         intel_fb->obj = obj;
  9751.  
  9752.         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  9753.         if (ret) {
  9754.                 DRM_ERROR("framebuffer init failed %d\n", ret);
  9755.                 return ret;
  9756.         }
  9757.  
  9758.         return 0;
  9759. }
  9760.  
  9761.  
  9762. static const struct drm_mode_config_funcs intel_mode_funcs = {
  9763.         .fb_create = NULL /*intel_user_framebuffer_create*/,
  9764.         .output_poll_changed = intel_fb_output_poll_changed,
  9765. };
  9766.  
  9767. /* Set up chip specific display functions */
  9768. static void intel_init_display(struct drm_device *dev)
  9769. {
  9770.         struct drm_i915_private *dev_priv = dev->dev_private;
  9771.  
  9772.         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
  9773.                 dev_priv->display.find_dpll = g4x_find_best_dpll;
  9774.         else if (IS_VALLEYVIEW(dev))
  9775.                 dev_priv->display.find_dpll = vlv_find_best_dpll;
  9776.         else if (IS_PINEVIEW(dev))
  9777.                 dev_priv->display.find_dpll = pnv_find_best_dpll;
  9778.         else
  9779.                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
  9780.  
  9781.         if (HAS_DDI(dev)) {
  9782.                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
  9783.                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
  9784.                 dev_priv->display.crtc_enable = haswell_crtc_enable;
  9785.                 dev_priv->display.crtc_disable = haswell_crtc_disable;
  9786.                 dev_priv->display.off = haswell_crtc_off;
  9787.                 dev_priv->display.update_plane = ironlake_update_plane;
  9788.         } else if (HAS_PCH_SPLIT(dev)) {
  9789.                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
  9790.                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
  9791.                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  9792.                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
  9793.                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
  9794.                 dev_priv->display.off = ironlake_crtc_off;
  9795.                 dev_priv->display.update_plane = ironlake_update_plane;
  9796.         } else if (IS_VALLEYVIEW(dev)) {
  9797.                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  9798.                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
  9799.                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  9800.                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
  9801.                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
  9802.                 dev_priv->display.off = i9xx_crtc_off;
  9803.                 dev_priv->display.update_plane = i9xx_update_plane;
  9804.         } else {
  9805.                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  9806.                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
  9807.                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  9808.                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
  9809.                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
  9810.                 dev_priv->display.off = i9xx_crtc_off;
  9811.                 dev_priv->display.update_plane = i9xx_update_plane;
  9812.         }
  9813.  
  9814.         /* Returns the core display clock speed */
  9815.         if (IS_VALLEYVIEW(dev))
  9816.                 dev_priv->display.get_display_clock_speed =
  9817.                         valleyview_get_display_clock_speed;
  9818.         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
  9819.                 dev_priv->display.get_display_clock_speed =
  9820.                         i945_get_display_clock_speed;
  9821.         else if (IS_I915G(dev))
  9822.                 dev_priv->display.get_display_clock_speed =
  9823.                         i915_get_display_clock_speed;
  9824.         else if (IS_I945GM(dev) || IS_845G(dev))
  9825.                 dev_priv->display.get_display_clock_speed =
  9826.                         i9xx_misc_get_display_clock_speed;
  9827.         else if (IS_PINEVIEW(dev))
  9828.                 dev_priv->display.get_display_clock_speed =
  9829.                         pnv_get_display_clock_speed;
  9830.         else if (IS_I915GM(dev))
  9831.                 dev_priv->display.get_display_clock_speed =
  9832.                         i915gm_get_display_clock_speed;
  9833.         else if (IS_I865G(dev))
  9834.                 dev_priv->display.get_display_clock_speed =
  9835.                         i865_get_display_clock_speed;
  9836.         else if (IS_I85X(dev))
  9837.                 dev_priv->display.get_display_clock_speed =
  9838.                         i855_get_display_clock_speed;
  9839.         else /* 852, 830 */
  9840.                 dev_priv->display.get_display_clock_speed =
  9841.                         i830_get_display_clock_speed;
  9842.  
  9843.         if (HAS_PCH_SPLIT(dev)) {
  9844.                 if (IS_GEN5(dev)) {
  9845.                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  9846.                         dev_priv->display.write_eld = ironlake_write_eld;
  9847.                 } else if (IS_GEN6(dev)) {
  9848.                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  9849.                         dev_priv->display.write_eld = ironlake_write_eld;
  9850.                 } else if (IS_IVYBRIDGE(dev)) {
  9851.                         /* FIXME: detect B0+ stepping and use auto training */
  9852.                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  9853.                         dev_priv->display.write_eld = ironlake_write_eld;
  9854.                         dev_priv->display.modeset_global_resources =
  9855.                                 ivb_modeset_global_resources;
  9856.                 } else if (IS_HASWELL(dev)) {
  9857.                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
  9858.                         dev_priv->display.write_eld = haswell_write_eld;
  9859.                         dev_priv->display.modeset_global_resources =
  9860.                                 haswell_modeset_global_resources;
  9861.                 }
  9862.         } else if (IS_G4X(dev)) {
  9863.                 dev_priv->display.write_eld = g4x_write_eld;
  9864.         }
  9865.  
  9866.         /* Default just returns -ENODEV to indicate unsupported */
  9867. //      dev_priv->display.queue_flip = intel_default_queue_flip;
  9868.  
  9869.  
  9870.  
  9871.  
  9872. }
  9873.  
  9874. /*
  9875.  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  9876.  * resume, or other times.  This quirk makes sure that's the case for
  9877.  * affected systems.
  9878.  */
  9879. static void quirk_pipea_force(struct drm_device *dev)
  9880. {
  9881.         struct drm_i915_private *dev_priv = dev->dev_private;
  9882.  
  9883.         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  9884.         DRM_INFO("applying pipe a force quirk\n");
  9885. }
  9886.  
  9887. /*
  9888.  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  9889.  */
  9890. static void quirk_ssc_force_disable(struct drm_device *dev)
  9891. {
  9892.         struct drm_i915_private *dev_priv = dev->dev_private;
  9893.         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  9894.         DRM_INFO("applying lvds SSC disable quirk\n");
  9895. }
  9896.  
  9897. /*
  9898.  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  9899.  * brightness value
  9900.  */
  9901. static void quirk_invert_brightness(struct drm_device *dev)
  9902. {
  9903.         struct drm_i915_private *dev_priv = dev->dev_private;
  9904.         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
  9905.         DRM_INFO("applying inverted panel brightness quirk\n");
  9906. }
  9907.  
  9908. /*
  9909.  * Some machines (Dell XPS13) suffer broken backlight controls if
  9910.  * BLM_PCH_PWM_ENABLE is set.
  9911.  */
  9912. static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
  9913. {
  9914.         struct drm_i915_private *dev_priv = dev->dev_private;
  9915.         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
  9916.         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
  9917. }
  9918.  
  9919. struct intel_quirk {
  9920.         int device;
  9921.         int subsystem_vendor;
  9922.         int subsystem_device;
  9923.         void (*hook)(struct drm_device *dev);
  9924. };
  9925.  
  9926. /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
  9927. struct intel_dmi_quirk {
  9928.         void (*hook)(struct drm_device *dev);
  9929.         const struct dmi_system_id (*dmi_id_list)[];
  9930. };
  9931.  
  9932. static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
  9933. {
  9934.         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
  9935.         return 1;
  9936. }
  9937.  
  9938. static const struct intel_dmi_quirk intel_dmi_quirks[] = {
  9939.         {
  9940.                 .dmi_id_list = &(const struct dmi_system_id[]) {
  9941.                         {
  9942.                                 .callback = intel_dmi_reverse_brightness,
  9943.                                 .ident = "NCR Corporation",
  9944.                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
  9945.                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
  9946.                                 },
  9947.                         },
  9948.                         { }  /* terminating entry */
  9949.                 },
  9950.                 .hook = quirk_invert_brightness,
  9951.         },
  9952. };
  9953.  
  9954. static struct intel_quirk intel_quirks[] = {
  9955.         /* HP Mini needs pipe A force quirk (LP: #322104) */
  9956.         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
  9957.  
  9958.         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  9959.         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  9960.  
  9961.         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  9962.         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  9963.  
  9964.         /* 830/845 need to leave pipe A & dpll A up */
  9965.         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  9966.         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  9967.  
  9968.         /* Lenovo U160 cannot use SSC on LVDS */
  9969.         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  9970.  
  9971.         /* Sony Vaio Y cannot use SSC on LVDS */
  9972.         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  9973.  
  9974.         /* Acer Aspire 5734Z must invert backlight brightness */
  9975.         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
  9976.  
  9977.         /* Acer/eMachines G725 */
  9978.         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
  9979.  
  9980.         /* Acer/eMachines e725 */
  9981.         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
  9982.  
  9983.         /* Acer/Packard Bell NCL20 */
  9984.         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
  9985.  
  9986.         /* Acer Aspire 4736Z */
  9987.         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
  9988.  
  9989.         /* Dell XPS13 HD Sandy Bridge */
  9990.         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
  9991.         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
  9992.         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
  9993. };
  9994.  
  9995. static void intel_init_quirks(struct drm_device *dev)
  9996. {
  9997.         struct pci_dev *d = dev->pdev;
  9998.         int i;
  9999.  
  10000.         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  10001.                 struct intel_quirk *q = &intel_quirks[i];
  10002.  
  10003.                 if (d->device == q->device &&
  10004.                     (d->subsystem_vendor == q->subsystem_vendor ||
  10005.                      q->subsystem_vendor == PCI_ANY_ID) &&
  10006.                     (d->subsystem_device == q->subsystem_device ||
  10007.                      q->subsystem_device == PCI_ANY_ID))
  10008.                         q->hook(dev);
  10009.         }
  10010. }
  10011.  
  10012. /* Disable the VGA plane that we never use */
  10013. static void i915_disable_vga(struct drm_device *dev)
  10014. {
  10015.         struct drm_i915_private *dev_priv = dev->dev_private;
  10016.         u8 sr1;
  10017.         u32 vga_reg = i915_vgacntrl_reg(dev);
  10018.  
  10019. //   vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  10020.     out8(SR01, VGA_SR_INDEX);
  10021.     sr1 = in8(VGA_SR_DATA);
  10022.     out8(sr1 | 1<<5, VGA_SR_DATA);
  10023. //   vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  10024.         udelay(300);
  10025.  
  10026.         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  10027.         POSTING_READ(vga_reg);
  10028. }
  10029.  
  10030. void intel_modeset_init_hw(struct drm_device *dev)
  10031. {
  10032.         intel_init_power_well(dev);
  10033.  
  10034.         intel_prepare_ddi(dev);
  10035.  
  10036.         intel_init_clock_gating(dev);
  10037.  
  10038.     mutex_lock(&dev->struct_mutex);
  10039.     intel_enable_gt_powersave(dev);
  10040.     mutex_unlock(&dev->struct_mutex);
  10041. }
  10042.  
  10043. void intel_modeset_init(struct drm_device *dev)
  10044. {
  10045.         struct drm_i915_private *dev_priv = dev->dev_private;
  10046.         int i, j, ret;
  10047.  
  10048.         drm_mode_config_init(dev);
  10049.  
  10050.         dev->mode_config.min_width = 0;
  10051.         dev->mode_config.min_height = 0;
  10052.  
  10053.         dev->mode_config.preferred_depth = 24;
  10054.         dev->mode_config.prefer_shadow = 1;
  10055.  
  10056.         dev->mode_config.funcs = &intel_mode_funcs;
  10057.  
  10058.         intel_init_quirks(dev);
  10059.  
  10060.         intel_init_pm(dev);
  10061.  
  10062.         if (INTEL_INFO(dev)->num_pipes == 0)
  10063.                 return;
  10064.  
  10065.         intel_init_display(dev);
  10066.  
  10067.         if (IS_GEN2(dev)) {
  10068.                 dev->mode_config.max_width = 2048;
  10069.                 dev->mode_config.max_height = 2048;
  10070.         } else if (IS_GEN3(dev)) {
  10071.                 dev->mode_config.max_width = 4096;
  10072.                 dev->mode_config.max_height = 4096;
  10073.         } else {
  10074.                 dev->mode_config.max_width = 8192;
  10075.                 dev->mode_config.max_height = 8192;
  10076.         }
  10077.         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
  10078.  
  10079.         DRM_DEBUG_KMS("%d display pipe%s available.\n",
  10080.                       INTEL_INFO(dev)->num_pipes,
  10081.                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
  10082.  
  10083.         for_each_pipe(i) {
  10084.                 intel_crtc_init(dev, i);
  10085.                 for (j = 0; j < dev_priv->num_plane; j++) {
  10086.                         ret = intel_plane_init(dev, i, j);
  10087.                 if (ret)
  10088.                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
  10089.                                               pipe_name(i), sprite_name(i, j), ret);
  10090.                 }
  10091.         }
  10092.  
  10093.         intel_cpu_pll_init(dev);
  10094.         intel_shared_dpll_init(dev);
  10095.  
  10096.         /* Just disable it once at startup */
  10097.         i915_disable_vga(dev);
  10098.         intel_setup_outputs(dev);
  10099.  
  10100.         /* Just in case the BIOS is doing something questionable. */
  10101.         intel_disable_fbc(dev);
  10102. }
  10103.  
  10104. static void
  10105. intel_connector_break_all_links(struct intel_connector *connector)
  10106. {
  10107.         connector->base.dpms = DRM_MODE_DPMS_OFF;
  10108.         connector->base.encoder = NULL;
  10109.         connector->encoder->connectors_active = false;
  10110.         connector->encoder->base.crtc = NULL;
  10111. }
  10112.  
  10113. static void intel_enable_pipe_a(struct drm_device *dev)
  10114. {
  10115.         struct intel_connector *connector;
  10116.         struct drm_connector *crt = NULL;
  10117.         struct intel_load_detect_pipe load_detect_temp;
  10118.  
  10119.         /* We can't just switch on the pipe A, we need to set things up with a
  10120.          * proper mode and output configuration. As a gross hack, enable pipe A
  10121.          * by enabling the load detect pipe once. */
  10122.         list_for_each_entry(connector,
  10123.                             &dev->mode_config.connector_list,
  10124.                             base.head) {
  10125.                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
  10126.                         crt = &connector->base;
  10127.                         break;
  10128.                 }
  10129.         }
  10130.  
  10131.         if (!crt)
  10132.                 return;
  10133.  
  10134.         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
  10135.                 intel_release_load_detect_pipe(crt, &load_detect_temp);
  10136.  
  10137.  
  10138. }
  10139.  
  10140. static bool
  10141. intel_check_plane_mapping(struct intel_crtc *crtc)
  10142. {
  10143.         struct drm_device *dev = crtc->base.dev;
  10144.         struct drm_i915_private *dev_priv = dev->dev_private;
  10145.         u32 reg, val;
  10146.  
  10147.         if (INTEL_INFO(dev)->num_pipes == 1)
  10148.                 return true;
  10149.  
  10150.         reg = DSPCNTR(!crtc->plane);
  10151.         val = I915_READ(reg);
  10152.  
  10153.         if ((val & DISPLAY_PLANE_ENABLE) &&
  10154.             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
  10155.                 return false;
  10156.  
  10157.         return true;
  10158. }
  10159.  
  10160. static void intel_sanitize_crtc(struct intel_crtc *crtc)
  10161. {
  10162.         struct drm_device *dev = crtc->base.dev;
  10163.         struct drm_i915_private *dev_priv = dev->dev_private;
  10164.         u32 reg;
  10165.  
  10166.         /* Clear any frame start delays used for debugging left by the BIOS */
  10167.         reg = PIPECONF(crtc->config.cpu_transcoder);
  10168.         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
  10169.  
  10170.         /* We need to sanitize the plane -> pipe mapping first because this will
  10171.          * disable the crtc (and hence change the state) if it is wrong. Note
  10172.          * that gen4+ has a fixed plane -> pipe mapping.  */
  10173.         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
  10174.                 struct intel_connector *connector;
  10175.                 bool plane;
  10176.  
  10177.                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
  10178.                               crtc->base.base.id);
  10179.  
  10180.                 /* Pipe has the wrong plane attached and the plane is active.
  10181.                  * Temporarily change the plane mapping and disable everything
  10182.                  * ...  */
  10183.                 plane = crtc->plane;
  10184.                 crtc->plane = !plane;
  10185.                 dev_priv->display.crtc_disable(&crtc->base);
  10186.                 crtc->plane = plane;
  10187.  
  10188.                 /* ... and break all links. */
  10189.                 list_for_each_entry(connector, &dev->mode_config.connector_list,
  10190.                                     base.head) {
  10191.                         if (connector->encoder->base.crtc != &crtc->base)
  10192.                                 continue;
  10193.  
  10194.                         intel_connector_break_all_links(connector);
  10195.                 }
  10196.  
  10197.                 WARN_ON(crtc->active);
  10198.                 crtc->base.enabled = false;
  10199.         }
  10200.  
  10201.         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  10202.             crtc->pipe == PIPE_A && !crtc->active) {
  10203.                 /* BIOS forgot to enable pipe A, this mostly happens after
  10204.                  * resume. Force-enable the pipe to fix this, the update_dpms
  10205.                  * call below we restore the pipe to the right state, but leave
  10206.                  * the required bits on. */
  10207.                 intel_enable_pipe_a(dev);
  10208.         }
  10209.  
  10210.         /* Adjust the state of the output pipe according to whether we
  10211.          * have active connectors/encoders. */
  10212.         intel_crtc_update_dpms(&crtc->base);
  10213.  
  10214.         if (crtc->active != crtc->base.enabled) {
  10215.                 struct intel_encoder *encoder;
  10216.  
  10217.                 /* This can happen either due to bugs in the get_hw_state
  10218.                  * functions or because the pipe is force-enabled due to the
  10219.                  * pipe A quirk. */
  10220.                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
  10221.                               crtc->base.base.id,
  10222.                               crtc->base.enabled ? "enabled" : "disabled",
  10223.                               crtc->active ? "enabled" : "disabled");
  10224.  
  10225.                 crtc->base.enabled = crtc->active;
  10226.  
  10227.                 /* Because we only establish the connector -> encoder ->
  10228.                  * crtc links if something is active, this means the
  10229.                  * crtc is now deactivated. Break the links. connector
  10230.                  * -> encoder links are only establish when things are
  10231.                  *  actually up, hence no need to break them. */
  10232.                 WARN_ON(crtc->active);
  10233.  
  10234.                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
  10235.                         WARN_ON(encoder->connectors_active);
  10236.                         encoder->base.crtc = NULL;
  10237.                 }
  10238.         }
  10239. }
  10240.  
  10241. static void intel_sanitize_encoder(struct intel_encoder *encoder)
  10242. {
  10243.         struct intel_connector *connector;
  10244.         struct drm_device *dev = encoder->base.dev;
  10245.  
  10246.         /* We need to check both for a crtc link (meaning that the
  10247.          * encoder is active and trying to read from a pipe) and the
  10248.          * pipe itself being active. */
  10249.         bool has_active_crtc = encoder->base.crtc &&
  10250.                 to_intel_crtc(encoder->base.crtc)->active;
  10251.  
  10252.         if (encoder->connectors_active && !has_active_crtc) {
  10253.                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
  10254.                               encoder->base.base.id,
  10255.                               drm_get_encoder_name(&encoder->base));
  10256.  
  10257.                 /* Connector is active, but has no active pipe. This is
  10258.                  * fallout from our resume register restoring. Disable
  10259.                  * the encoder manually again. */
  10260.                 if (encoder->base.crtc) {
  10261.                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
  10262.                                       encoder->base.base.id,
  10263.                                       drm_get_encoder_name(&encoder->base));
  10264.                         encoder->disable(encoder);
  10265.                 }
  10266.  
  10267.                 /* Inconsistent output/port/pipe state happens presumably due to
  10268.                  * a bug in one of the get_hw_state functions. Or someplace else
  10269.                  * in our code, like the register restore mess on resume. Clamp
  10270.                  * things to off as a safer default. */
  10271.                 list_for_each_entry(connector,
  10272.                                     &dev->mode_config.connector_list,
  10273.                                     base.head) {
  10274.                         if (connector->encoder != encoder)
  10275.                                 continue;
  10276.  
  10277.                         intel_connector_break_all_links(connector);
  10278.                 }
  10279.         }
  10280.         /* Enabled encoders without active connectors will be fixed in
  10281.          * the crtc fixup. */
  10282. }
  10283.  
  10284. void i915_redisable_vga(struct drm_device *dev)
  10285. {
  10286.         struct drm_i915_private *dev_priv = dev->dev_private;
  10287.         u32 vga_reg = i915_vgacntrl_reg(dev);
  10288.  
  10289.         /* This function can be called both from intel_modeset_setup_hw_state or
  10290.          * at a very early point in our resume sequence, where the power well
  10291.          * structures are not yet restored. Since this function is at a very
  10292.          * paranoid "someone might have enabled VGA while we were not looking"
  10293.          * level, just check if the power well is enabled instead of trying to
  10294.          * follow the "don't touch the power well if we don't need it" policy
  10295.          * the rest of the driver uses. */
  10296.         if (HAS_POWER_WELL(dev) &&
  10297.             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
  10298.                 return;
  10299.  
  10300.         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
  10301.                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
  10302.                 i915_disable_vga(dev);
  10303.         }
  10304. }
  10305.  
  10306. static void intel_modeset_readout_hw_state(struct drm_device *dev)
  10307. {
  10308.         struct drm_i915_private *dev_priv = dev->dev_private;
  10309.         enum pipe pipe;
  10310.         struct intel_crtc *crtc;
  10311.         struct intel_encoder *encoder;
  10312.         struct intel_connector *connector;
  10313.         int i;
  10314.  
  10315.         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  10316.                             base.head) {
  10317.                 memset(&crtc->config, 0, sizeof(crtc->config));
  10318.  
  10319.                 crtc->active = dev_priv->display.get_pipe_config(crtc,
  10320.                                                                  &crtc->config);
  10321.  
  10322.                 crtc->base.enabled = crtc->active;
  10323.  
  10324.                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
  10325.                               crtc->base.base.id,
  10326.                               crtc->active ? "enabled" : "disabled");
  10327.         }
  10328.  
  10329.         /* FIXME: Smash this into the new shared dpll infrastructure. */
  10330.         if (HAS_DDI(dev))
  10331.                 intel_ddi_setup_hw_pll_state(dev);
  10332.  
  10333.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  10334.                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  10335.  
  10336.                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
  10337.                 pll->active = 0;
  10338.                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  10339.                                     base.head) {
  10340.                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
  10341.                                 pll->active++;
  10342.                 }
  10343.                 pll->refcount = pll->active;
  10344.  
  10345.                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
  10346.                               pll->name, pll->refcount, pll->on);
  10347.         }
  10348.  
  10349.         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  10350.                             base.head) {
  10351.                 pipe = 0;
  10352.  
  10353.                 if (encoder->get_hw_state(encoder, &pipe)) {
  10354.                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  10355.                         encoder->base.crtc = &crtc->base;
  10356.                         if (encoder->get_config)
  10357.                                 encoder->get_config(encoder, &crtc->config);
  10358.                 } else {
  10359.                         encoder->base.crtc = NULL;
  10360.                 }
  10361.  
  10362.                 encoder->connectors_active = false;
  10363.                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
  10364.                               encoder->base.base.id,
  10365.                               drm_get_encoder_name(&encoder->base),
  10366.                               encoder->base.crtc ? "enabled" : "disabled",
  10367.                               pipe);
  10368.         }
  10369.  
  10370.         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  10371.                             base.head) {
  10372.                 if (!crtc->active)
  10373.                         continue;
  10374.                 if (dev_priv->display.get_clock)
  10375.                         dev_priv->display.get_clock(crtc,
  10376.                                                     &crtc->config);
  10377.         }
  10378.  
  10379.         list_for_each_entry(connector, &dev->mode_config.connector_list,
  10380.                             base.head) {
  10381.                 if (connector->get_hw_state(connector)) {
  10382.                         connector->base.dpms = DRM_MODE_DPMS_ON;
  10383.                         connector->encoder->connectors_active = true;
  10384.                         connector->base.encoder = &connector->encoder->base;
  10385.                 } else {
  10386.                         connector->base.dpms = DRM_MODE_DPMS_OFF;
  10387.                         connector->base.encoder = NULL;
  10388.                 }
  10389.                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
  10390.                               connector->base.base.id,
  10391.                               drm_get_connector_name(&connector->base),
  10392.                               connector->base.encoder ? "enabled" : "disabled");
  10393.         }
  10394. }
  10395.  
  10396. /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
  10397.  * and i915 state tracking structures. */
  10398. void intel_modeset_setup_hw_state(struct drm_device *dev,
  10399.                                   bool force_restore)
  10400. {
  10401.         struct drm_i915_private *dev_priv = dev->dev_private;
  10402.         enum pipe pipe;
  10403.         struct drm_plane *plane;
  10404.         struct intel_crtc *crtc;
  10405.         struct intel_encoder *encoder;
  10406.         int i;
  10407.  
  10408.         intel_modeset_readout_hw_state(dev);
  10409.  
  10410.         /*
  10411.          * Now that we have the config, copy it to each CRTC struct
  10412.          * Note that this could go away if we move to using crtc_config
  10413.          * checking everywhere.
  10414.          */
  10415.         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  10416.                             base.head) {
  10417.                 if (crtc->active && i915_fastboot) {
  10418.                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
  10419.  
  10420.                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
  10421.                                       crtc->base.base.id);
  10422.                         drm_mode_debug_printmodeline(&crtc->base.mode);
  10423.                 }
  10424.         }
  10425.  
  10426.         /* HW state is read out, now we need to sanitize this mess. */
  10427.         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  10428.                             base.head) {
  10429.                 intel_sanitize_encoder(encoder);
  10430.         }
  10431.  
  10432.         for_each_pipe(pipe) {
  10433.                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  10434.                 intel_sanitize_crtc(crtc);
  10435.                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
  10436.         }
  10437.  
  10438.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  10439.                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  10440.  
  10441.                 if (!pll->on || pll->active)
  10442.                         continue;
  10443.  
  10444.                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
  10445.  
  10446.                 pll->disable(dev_priv, pll);
  10447.                 pll->on = false;
  10448.         }
  10449.  
  10450.         if (force_restore) {
  10451.                 /*
  10452.                  * We need to use raw interfaces for restoring state to avoid
  10453.                  * checking (bogus) intermediate states.
  10454.                  */
  10455.                 for_each_pipe(pipe) {
  10456.                         struct drm_crtc *crtc =
  10457.                                 dev_priv->pipe_to_crtc_mapping[pipe];
  10458.  
  10459.                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
  10460.                                          crtc->fb);
  10461.                 }
  10462.                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
  10463.                         intel_plane_restore(plane);
  10464.  
  10465.                 i915_redisable_vga(dev);
  10466.         } else {
  10467.         intel_modeset_update_staged_output_state(dev);
  10468.         }
  10469.  
  10470.         intel_modeset_check_state(dev);
  10471.  
  10472.         drm_mode_config_reset(dev);
  10473. }
  10474.  
  10475. void intel_modeset_gem_init(struct drm_device *dev)
  10476. {
  10477.         intel_modeset_init_hw(dev);
  10478.  
  10479. //   intel_setup_overlay(dev);
  10480.  
  10481.         intel_modeset_setup_hw_state(dev, false);
  10482. }
  10483.  
  10484. void intel_modeset_cleanup(struct drm_device *dev)
  10485. {
  10486. #if 0
  10487.         struct drm_i915_private *dev_priv = dev->dev_private;
  10488.         struct drm_crtc *crtc;
  10489.  
  10490.         /*
  10491.          * Interrupts and polling as the first thing to avoid creating havoc.
  10492.          * Too much stuff here (turning of rps, connectors, ...) would
  10493.          * experience fancy races otherwise.
  10494.          */
  10495.         drm_irq_uninstall(dev);
  10496.         cancel_work_sync(&dev_priv->hotplug_work);
  10497.         /*
  10498.          * Due to the hpd irq storm handling the hotplug work can re-arm the
  10499.          * poll handlers. Hence disable polling after hpd handling is shut down.
  10500.          */
  10501. //   drm_kms_helper_poll_fini(dev);
  10502.  
  10503.         mutex_lock(&dev->struct_mutex);
  10504.  
  10505. //   intel_unregister_dsm_handler();
  10506.  
  10507.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  10508.                 /* Skip inactive CRTCs */
  10509.                 if (!crtc->fb)
  10510.                         continue;
  10511.  
  10512.                 intel_increase_pllclock(crtc);
  10513.         }
  10514.  
  10515.         intel_disable_fbc(dev);
  10516.  
  10517.         intel_disable_gt_powersave(dev);
  10518.  
  10519.         ironlake_teardown_rc6(dev);
  10520.  
  10521.         mutex_unlock(&dev->struct_mutex);
  10522.  
  10523.         /* flush any delayed tasks or pending work */
  10524.         flush_scheduled_work();
  10525.  
  10526.         /* destroy backlight, if any, before the connectors */
  10527.         intel_panel_destroy_backlight(dev);
  10528.  
  10529.         drm_mode_config_cleanup(dev);
  10530. #endif
  10531. }
  10532.  
  10533. /*
  10534.  * Return which encoder is currently attached for connector.
  10535.  */
  10536. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  10537. {
  10538.         return &intel_attached_encoder(connector)->base;
  10539. }
  10540.  
  10541. void intel_connector_attach_encoder(struct intel_connector *connector,
  10542.                                     struct intel_encoder *encoder)
  10543. {
  10544.         connector->encoder = encoder;
  10545.         drm_mode_connector_attach_encoder(&connector->base,
  10546.                                           &encoder->base);
  10547. }
  10548.  
  10549. /*
  10550.  * set vga decode state - true == enable VGA decode
  10551.  */
  10552. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  10553. {
  10554.         struct drm_i915_private *dev_priv = dev->dev_private;
  10555.         u16 gmch_ctrl;
  10556.  
  10557.         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  10558.         if (state)
  10559.                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  10560.         else
  10561.                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  10562.         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  10563.         return 0;
  10564. }
  10565.  
  10566. #ifdef CONFIG_DEBUG_FS
  10567. #include <linux/seq_file.h>
  10568.  
  10569. struct intel_display_error_state {
  10570.  
  10571.         u32 power_well_driver;
  10572.  
  10573.         int num_transcoders;
  10574.  
  10575.         struct intel_cursor_error_state {
  10576.                 u32 control;
  10577.                 u32 position;
  10578.                 u32 base;
  10579.                 u32 size;
  10580.         } cursor[I915_MAX_PIPES];
  10581.  
  10582.         struct intel_pipe_error_state {
  10583.                 u32 source;
  10584.         } pipe[I915_MAX_PIPES];
  10585.  
  10586.         struct intel_plane_error_state {
  10587.                 u32 control;
  10588.                 u32 stride;
  10589.                 u32 size;
  10590.                 u32 pos;
  10591.                 u32 addr;
  10592.                 u32 surface;
  10593.                 u32 tile_offset;
  10594.         } plane[I915_MAX_PIPES];
  10595.  
  10596.         struct intel_transcoder_error_state {
  10597.                 enum transcoder cpu_transcoder;
  10598.  
  10599.                 u32 conf;
  10600.  
  10601.                 u32 htotal;
  10602.                 u32 hblank;
  10603.                 u32 hsync;
  10604.                 u32 vtotal;
  10605.                 u32 vblank;
  10606.                 u32 vsync;
  10607.         } transcoder[4];
  10608. };
  10609.  
  10610. struct intel_display_error_state *
  10611. intel_display_capture_error_state(struct drm_device *dev)
  10612. {
  10613.         drm_i915_private_t *dev_priv = dev->dev_private;
  10614.         struct intel_display_error_state *error;
  10615.         int transcoders[] = {
  10616.                 TRANSCODER_A,
  10617.                 TRANSCODER_B,
  10618.                 TRANSCODER_C,
  10619.                 TRANSCODER_EDP,
  10620.         };
  10621.         int i;
  10622.  
  10623.         if (INTEL_INFO(dev)->num_pipes == 0)
  10624.                 return NULL;
  10625.  
  10626.         error = kmalloc(sizeof(*error), GFP_ATOMIC);
  10627.         if (error == NULL)
  10628.                 return NULL;
  10629.  
  10630.         if (HAS_POWER_WELL(dev))
  10631.                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
  10632.  
  10633.         for_each_pipe(i) {
  10634.                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
  10635.                 error->cursor[i].control = I915_READ(CURCNTR(i));
  10636.                 error->cursor[i].position = I915_READ(CURPOS(i));
  10637.                 error->cursor[i].base = I915_READ(CURBASE(i));
  10638.                 } else {
  10639.                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
  10640.                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
  10641.                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
  10642.                 }
  10643.  
  10644.                 error->plane[i].control = I915_READ(DSPCNTR(i));
  10645.                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  10646.                 if (INTEL_INFO(dev)->gen <= 3) {
  10647.                 error->plane[i].size = I915_READ(DSPSIZE(i));
  10648.                 error->plane[i].pos = I915_READ(DSPPOS(i));
  10649.                 }
  10650.                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  10651.                 error->plane[i].addr = I915_READ(DSPADDR(i));
  10652.                 if (INTEL_INFO(dev)->gen >= 4) {
  10653.                         error->plane[i].surface = I915_READ(DSPSURF(i));
  10654.                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  10655.                 }
  10656.  
  10657.                 error->pipe[i].source = I915_READ(PIPESRC(i));
  10658.         }
  10659.  
  10660.         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
  10661.         if (HAS_DDI(dev_priv->dev))
  10662.                 error->num_transcoders++; /* Account for eDP. */
  10663.  
  10664.         for (i = 0; i < error->num_transcoders; i++) {
  10665.                 enum transcoder cpu_transcoder = transcoders[i];
  10666.  
  10667.                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
  10668.  
  10669.                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
  10670.                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
  10671.                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
  10672.                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
  10673.                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
  10674.                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
  10675.                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
  10676.         }
  10677.  
  10678.         /* In the code above we read the registers without checking if the power
  10679.          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
  10680.          * prevent the next I915_WRITE from detecting it and printing an error
  10681.          * message. */
  10682.         intel_uncore_clear_errors(dev);
  10683.  
  10684.         return error;
  10685. }
  10686.  
  10687. #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
  10688.  
  10689. void
  10690. intel_display_print_error_state(struct drm_i915_error_state_buf *m,
  10691.                                 struct drm_device *dev,
  10692.                                 struct intel_display_error_state *error)
  10693. {
  10694.         int i;
  10695.  
  10696.         if (!error)
  10697.                 return;
  10698.  
  10699.         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
  10700.         if (HAS_POWER_WELL(dev))
  10701.                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
  10702.                            error->power_well_driver);
  10703.         for_each_pipe(i) {
  10704.                 err_printf(m, "Pipe [%d]:\n", i);
  10705.                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
  10706.  
  10707.                 err_printf(m, "Plane [%d]:\n", i);
  10708.                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
  10709.                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
  10710.                 if (INTEL_INFO(dev)->gen <= 3) {
  10711.                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
  10712.                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
  10713.                 }
  10714.                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  10715.                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
  10716.                 if (INTEL_INFO(dev)->gen >= 4) {
  10717.                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
  10718.                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
  10719.                 }
  10720.  
  10721.                 err_printf(m, "Cursor [%d]:\n", i);
  10722.                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
  10723.                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
  10724.                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
  10725.         }
  10726.  
  10727.         for (i = 0; i < error->num_transcoders; i++) {
  10728.                 err_printf(m, "  CPU transcoder: %c\n",
  10729.                            transcoder_name(error->transcoder[i].cpu_transcoder));
  10730.                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
  10731.                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
  10732.                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
  10733.                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
  10734.                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
  10735.                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
  10736.                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
  10737.         }
  10738. }
  10739. #endif
  10740.