Subversion Repositories Kolibri OS

Rev

Rev 6660 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright © 2014 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  */
  24. #include <linux/firmware.h>
  25. #include "i915_drv.h"
  26. #include "i915_reg.h"
  27.  
  28. /**
  29.  * DOC: csr support for dmc
  30.  *
  31.  * Display Context Save and Restore (CSR) firmware support added from gen9
  32.  * onwards to drive newly added DMC (Display microcontroller) in display
  33.  * engine to save and restore the state of display engine when it enter into
  34.  * low-power state and comes back to normal.
  35.  *
  36.  * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
  37.  * FW_LOADED, FW_FAILED.
  38.  *
  39.  * Once the firmware is written into the registers status will be moved from
  40.  * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
  41.  * be moved to FW_FAILED.
  42.  */
  43.  
  44. #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
  45. #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
  46.  
  47. MODULE_FIRMWARE(I915_CSR_SKL);
  48. MODULE_FIRMWARE(I915_CSR_BXT);
  49.  
  50. #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 23)
  51.  
  52. #define CSR_MAX_FW_SIZE                 0x2FFF
  53. #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  54.  
  55. struct intel_css_header {
  56.         /* 0x09 for DMC */
  57.         uint32_t module_type;
  58.  
  59.         /* Includes the DMC specific header in dwords */
  60.         uint32_t header_len;
  61.  
  62.         /* always value would be 0x10000 */
  63.         uint32_t header_ver;
  64.  
  65.         /* Not used */
  66.         uint32_t module_id;
  67.  
  68.         /* Not used */
  69.         uint32_t module_vendor;
  70.  
  71.         /* in YYYYMMDD format */
  72.         uint32_t date;
  73.  
  74.         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  75.         uint32_t size;
  76.  
  77.         /* Not used */
  78.         uint32_t key_size;
  79.  
  80.         /* Not used */
  81.         uint32_t modulus_size;
  82.  
  83.         /* Not used */
  84.         uint32_t exponent_size;
  85.  
  86.         /* Not used */
  87.         uint32_t reserved1[12];
  88.  
  89.         /* Major Minor */
  90.         uint32_t version;
  91.  
  92.         /* Not used */
  93.         uint32_t reserved2[8];
  94.  
  95.         /* Not used */
  96.         uint32_t kernel_header_info;
  97. } __packed;
  98.  
  99. struct intel_fw_info {
  100.         uint16_t reserved1;
  101.  
  102.         /* Stepping (A, B, C, ..., *). * is a wildcard */
  103.         char stepping;
  104.  
  105.         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
  106.         char substepping;
  107.  
  108.         uint32_t offset;
  109.         uint32_t reserved2;
  110. } __packed;
  111.  
  112. struct intel_package_header {
  113.         /* DMC container header length in dwords */
  114.         unsigned char header_len;
  115.  
  116.         /* always value would be 0x01 */
  117.         unsigned char header_ver;
  118.  
  119.         unsigned char reserved[10];
  120.  
  121.         /* Number of valid entries in the FWInfo array below */
  122.         uint32_t num_entries;
  123.  
  124.         struct intel_fw_info fw_info[20];
  125. } __packed;
  126.  
  127. struct intel_dmc_header {
  128.         /* always value would be 0x40403E3E */
  129.         uint32_t signature;
  130.  
  131.         /* DMC binary header length */
  132.         unsigned char header_len;
  133.  
  134.         /* 0x01 */
  135.         unsigned char header_ver;
  136.  
  137.         /* Reserved */
  138.         uint16_t dmcc_ver;
  139.  
  140.         /* Major, Minor */
  141.         uint32_t        project;
  142.  
  143.         /* Firmware program size (excluding header) in dwords */
  144.         uint32_t        fw_size;
  145.  
  146.         /* Major Minor version */
  147.         uint32_t fw_version;
  148.  
  149.         /* Number of valid MMIO cycles present. */
  150.         uint32_t mmio_count;
  151.  
  152.         /* MMIO address */
  153.         uint32_t mmioaddr[8];
  154.  
  155.         /* MMIO data */
  156.         uint32_t mmiodata[8];
  157.  
  158.         /* FW filename  */
  159.         unsigned char dfile[32];
  160.  
  161.         uint32_t reserved1[2];
  162. } __packed;
  163.  
  164. struct stepping_info {
  165.         char stepping;
  166.         char substepping;
  167. };
  168.  
  169. /*
  170.  * Kabylake derivated from Skylake H0, so SKL H0
  171.  * is the right firmware for KBL A0 (revid 0).
  172.  */
  173. static const struct stepping_info kbl_stepping_info[] = {
  174.         {'H', '0'}, {'I', '0'}
  175. };
  176.  
  177. static const struct stepping_info skl_stepping_info[] = {
  178.                 {'A', '0'}, {'B', '0'}, {'C', '0'},
  179.                 {'D', '0'}, {'E', '0'}, {'F', '0'},
  180.                 {'G', '0'}, {'H', '0'}, {'I', '0'},
  181.                 {'J', '0'}, {'K', '0'}
  182. };
  183.  
  184. static const struct stepping_info bxt_stepping_info[] = {
  185.         {'A', '0'}, {'A', '1'}, {'A', '2'},
  186.         {'B', '0'}, {'B', '1'}, {'B', '2'}
  187. };
  188.  
  189. static const struct stepping_info *intel_get_stepping_info(struct drm_device *dev)
  190. {
  191.         const struct stepping_info *si;
  192.         unsigned int size;
  193.  
  194.         if (IS_KABYLAKE(dev)) {
  195.                 size = ARRAY_SIZE(kbl_stepping_info);
  196.                 si = kbl_stepping_info;
  197.         } else if (IS_SKYLAKE(dev)) {
  198.                 size = ARRAY_SIZE(skl_stepping_info);
  199.                 si = skl_stepping_info;
  200.         } else if (IS_BROXTON(dev)) {
  201.                 size = ARRAY_SIZE(bxt_stepping_info);
  202.                 si = bxt_stepping_info;
  203.         } else {
  204.                 return NULL;
  205.         }
  206.  
  207.         if (INTEL_REVID(dev) < size)
  208.                 return si + INTEL_REVID(dev);
  209.  
  210.         return NULL;
  211. }
  212.  
  213. /**
  214.  * intel_csr_load_program() - write the firmware from memory to register.
  215.  * @dev_priv: i915 drm device.
  216.  *
  217.  * CSR firmware is read from a .bin file and kept in internal memory one time.
  218.  * Everytime display comes back from low power state this function is called to
  219.  * copy the firmware from internal memory to registers.
  220.  */
  221. void intel_csr_load_program(struct drm_i915_private *dev_priv)
  222. {
  223.         u32 *payload = dev_priv->csr.dmc_payload;
  224.         uint32_t i, fw_size;
  225.  
  226.         if (!IS_GEN9(dev_priv)) {
  227.                 DRM_ERROR("No CSR support available for this platform\n");
  228.                 return;
  229.         }
  230.  
  231.         if (!dev_priv->csr.dmc_payload) {
  232.                 DRM_ERROR("Tried to program CSR with empty payload\n");
  233.                 return;
  234.         }
  235.  
  236.         fw_size = dev_priv->csr.dmc_fw_size;
  237.         for (i = 0; i < fw_size; i++)
  238.                 I915_WRITE(CSR_PROGRAM(i), payload[i]);
  239.  
  240.         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
  241.                 I915_WRITE(dev_priv->csr.mmioaddr[i],
  242.                         dev_priv->csr.mmiodata[i]);
  243.         }
  244.  
  245.         dev_priv->csr.dc_state = 0;
  246. }
  247.  
  248. static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
  249.                               const struct firmware *fw)
  250. {
  251.         struct drm_device *dev = dev_priv->dev;
  252.         struct intel_css_header *css_header;
  253.         struct intel_package_header *package_header;
  254.         struct intel_dmc_header *dmc_header;
  255.         struct intel_csr *csr = &dev_priv->csr;
  256.         const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
  257.         char stepping, substepping;
  258.         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
  259.         uint32_t i;
  260.         uint32_t *dmc_payload;
  261.  
  262.         if (!fw)
  263.                 return NULL;
  264.  
  265.         if (!stepping_info) {
  266.                 DRM_ERROR("Unknown stepping info, firmware loading failed\n");
  267.                 return NULL;
  268.         }
  269.  
  270.         stepping = stepping_info->stepping;
  271.         substepping = stepping_info->substepping;
  272.  
  273.         /* Extract CSS Header information*/
  274.         css_header = (struct intel_css_header *)fw->data;
  275.         if (sizeof(struct intel_css_header) !=
  276.                 (css_header->header_len * 4)) {
  277.                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
  278.                         (css_header->header_len * 4));
  279.                 return NULL;
  280.         }
  281.  
  282.         csr->version = css_header->version;
  283.  
  284.         if (IS_SKYLAKE(dev) && csr->version < SKL_CSR_VERSION_REQUIRED) {
  285.                 DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
  286.                          " please upgrade to v%u.%u or later"
  287.                          " [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n",
  288.                          CSR_VERSION_MAJOR(csr->version),
  289.                          CSR_VERSION_MINOR(csr->version),
  290.                          CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
  291.                          CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
  292.                 return NULL;
  293.         }
  294.  
  295.         readcount += sizeof(struct intel_css_header);
  296.  
  297.         /* Extract Package Header information*/
  298.         package_header = (struct intel_package_header *)
  299.                                         &fw->data[readcount];
  300.         if (sizeof(struct intel_package_header) !=
  301.                 (package_header->header_len * 4)) {
  302.                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
  303.                         (package_header->header_len * 4));
  304.                 return NULL;
  305.         }
  306.         readcount += sizeof(struct intel_package_header);
  307.  
  308.         /* Search for dmc_offset to find firware binary. */
  309.         for (i = 0; i < package_header->num_entries; i++) {
  310.                 if (package_header->fw_info[i].substepping == '*' &&
  311.                         stepping == package_header->fw_info[i].stepping) {
  312.                         dmc_offset = package_header->fw_info[i].offset;
  313.                         break;
  314.                 } else if (stepping == package_header->fw_info[i].stepping &&
  315.                         substepping == package_header->fw_info[i].substepping) {
  316.                         dmc_offset = package_header->fw_info[i].offset;
  317.                         break;
  318.                 } else if (package_header->fw_info[i].stepping == '*' &&
  319.                         package_header->fw_info[i].substepping == '*')
  320.                         dmc_offset = package_header->fw_info[i].offset;
  321.         }
  322.         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
  323.                 DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
  324.                 return NULL;
  325.         }
  326.         readcount += dmc_offset;
  327.  
  328.         /* Extract dmc_header information. */
  329.         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
  330.         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
  331.                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
  332.                                 (dmc_header->header_len));
  333.                 return NULL;
  334.         }
  335.         readcount += sizeof(struct intel_dmc_header);
  336.  
  337.         /* Cache the dmc header info. */
  338.         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
  339.                 DRM_ERROR("Firmware has wrong mmio count %u\n",
  340.                                                 dmc_header->mmio_count);
  341.                 return NULL;
  342.         }
  343.         csr->mmio_count = dmc_header->mmio_count;
  344.         for (i = 0; i < dmc_header->mmio_count; i++) {
  345.                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
  346.                         dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
  347.                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
  348.                                                 dmc_header->mmioaddr[i]);
  349.                         return NULL;
  350.                 }
  351.                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
  352.                 csr->mmiodata[i] = dmc_header->mmiodata[i];
  353.         }
  354.  
  355.         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
  356.         nbytes = dmc_header->fw_size * 4;
  357.         if (nbytes > CSR_MAX_FW_SIZE) {
  358.                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
  359.                 return NULL;
  360.         }
  361.         csr->dmc_fw_size = dmc_header->fw_size;
  362.  
  363.         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
  364.         if (!dmc_payload) {
  365.                 DRM_ERROR("Memory allocation failed for dmc payload\n");
  366.                 return NULL;
  367.         }
  368.  
  369.         memcpy(dmc_payload, &fw->data[readcount], nbytes);
  370.  
  371.         return dmc_payload;
  372. }
  373.  
  374. static void csr_load_work_fn(struct drm_i915_private *dev_priv)
  375. {
  376.         struct intel_csr *csr;
  377.         const struct firmware *fw;
  378.         int ret;
  379.  
  380.         csr = &dev_priv->csr;
  381.  
  382.         ret = request_firmware(&fw, dev_priv->csr.fw_path,
  383.                                &dev_priv->dev->pdev->dev);
  384.         if (!fw)
  385.                 goto out;
  386.  
  387.         dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
  388.         if (!dev_priv->csr.dmc_payload)
  389.                 goto out;
  390.  
  391.         /* load csr program during system boot, as needed for DC states */
  392.         intel_csr_load_program(dev_priv);
  393.  
  394. out:
  395.         if (dev_priv->csr.dmc_payload) {
  396.                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
  397.  
  398.                 DRM_INFO("Finished loading %s (v%u.%u)\n",
  399.                          dev_priv->csr.fw_path,
  400.                          CSR_VERSION_MAJOR(csr->version),
  401.                          CSR_VERSION_MINOR(csr->version));
  402.         } else {
  403.                 DRM_ERROR("Failed to load DMC firmware, disabling rpm\n");
  404.     }
  405.  
  406.         release_firmware(fw);
  407. }
  408.  
  409. /**
  410.  * intel_csr_ucode_init() - initialize the firmware loading.
  411.  * @dev_priv: i915 drm device.
  412.  *
  413.  * This function is called at the time of loading the display driver to read
  414.  * firmware from a .bin file and copied into a internal memory.
  415.  */
  416. void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
  417. {
  418.         struct intel_csr *csr = &dev_priv->csr;
  419.  
  420.         if (!HAS_CSR(dev_priv))
  421.                 return;
  422.  
  423.         if (IS_SKYLAKE(dev_priv))
  424.                 csr->fw_path = I915_CSR_SKL;
  425.         else if (IS_BROXTON(dev_priv))
  426.                 csr->fw_path = I915_CSR_BXT;
  427.         else {
  428.                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
  429.                 return;
  430.         }
  431.  
  432.         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
  433.  
  434.         /*
  435.          * Obtain a runtime pm reference, until CSR is loaded,
  436.          * to avoid entering runtime-suspend.
  437.          */
  438.         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
  439.  
  440.         csr_load_work_fn(dev_priv);
  441. }
  442.  
  443. /**
  444.  * intel_csr_ucode_fini() - unload the CSR firmware.
  445.  * @dev_priv: i915 drm device.
  446.  *
  447.  * Firmmware unloading includes freeing the internal momory and reset the
  448.  * firmware loading status.
  449.  */
  450. void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
  451. {
  452.         if (!HAS_CSR(dev_priv))
  453.                 return;
  454.  
  455.  
  456.         kfree(dev_priv->csr.dmc_payload);
  457. }
  458.